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Fixed MTP to work with TWRP

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30
Documentation/devicetree/bindings/clock/altr_socfpga.txt Normal file
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Device Tree Clock bindings for Altera's SoCFPGA platform
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of the following:
"altr,socfpga-pll-clock" - for a PLL clock
"altr,socfpga-perip-clock" - The peripheral clock divided from the
PLL clock.
"altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
can get gated.
- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
- clocks : shall be the input parent clock phandle for the clock. This is
either an oscillator or a pll output.
- #clock-cells : from common clock binding, shall be set to 0.
Optional properties:
- fixed-divider : If clocks have a fixed divider value, use this property.
- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
and the bit index.
- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
the divider register, bit shift, and width.
- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
hold/delay times that is needed for the SD/MMC CIU clock. The values of both
can be 0-315 degrees, in 45 degree increments.

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Clock bindings for ARM Integrator and Versatile Core Module clocks
Auxiliary Oscillator Clock
This is a configurable clock fed from a 24 MHz chrystal,
used for generating e.g. video clocks. It is located on the
core module and there is only one of these.
This clock node *must* be a subnode of the core module, since
it obtains the base address for it's address range from its
parent node.
Required properties:
- compatible: must be "arm,integrator-cm-auxosc" or "arm,versatile-cm-auxosc"
- #clock-cells: must be <0>
Optional properties:
- clocks: parent clock(s)
Example:
core-module@10000000 {
xtal24mhz: xtal24mhz@24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
auxosc: cm_aux_osc@25M {
#clock-cells = <0>;
compatible = "arm,integrator-cm-auxosc";
clocks = <&xtal24mhz>;
};
};

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Device Tree Clock bindings for arch-at91
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of the following:
"atmel,at91sam9x5-sckc":
at91 SCKC (Slow Clock Controller)
This node contains the slow clock definitions.
"atmel,at91sam9x5-clk-slow-osc":
at91 slow oscillator
"atmel,at91sam9x5-clk-slow-rc-osc":
at91 internal slow RC oscillator
"atmel,at91rm9200-pmc" or
"atmel,at91sam9g45-pmc" or
"atmel,at91sam9n12-pmc" or
"atmel,at91sam9x5-pmc" or
"atmel,sama5d3-pmc":
at91 PMC (Power Management Controller)
All at91 specific clocks (clocks defined below) must be child
node of the PMC node.
"atmel,at91sam9x5-clk-slow" (under sckc node)
or
"atmel,at91sam9260-clk-slow" (under pmc node):
at91 slow clk
"atmel,at91rm9200-clk-main-osc"
"atmel,at91sam9x5-clk-main-rc-osc"
at91 main clk sources
"atmel,at91sam9x5-clk-main"
"atmel,at91rm9200-clk-main":
at91 main clock
"atmel,at91rm9200-clk-master" or
"atmel,at91sam9x5-clk-master":
at91 master clock
"atmel,at91sam9x5-clk-peripheral" or
"atmel,at91rm9200-clk-peripheral":
at91 peripheral clocks
"atmel,at91rm9200-clk-pll" or
"atmel,at91sam9g45-clk-pll" or
"atmel,at91sam9g20-clk-pllb" or
"atmel,sama5d3-clk-pll":
at91 pll clocks
"atmel,at91sam9x5-clk-plldiv":
at91 plla divisor
"atmel,at91rm9200-clk-programmable" or
"atmel,at91sam9g45-clk-programmable" or
"atmel,at91sam9x5-clk-programmable":
at91 programmable clocks
"atmel,at91sam9x5-clk-smd":
at91 SMD (Soft Modem) clock
"atmel,at91rm9200-clk-system":
at91 system clocks
"atmel,at91rm9200-clk-usb" or
"atmel,at91sam9x5-clk-usb" or
"atmel,at91sam9n12-clk-usb":
at91 usb clock
"atmel,at91sam9x5-clk-utmi":
at91 utmi clock
"atmel,sama5d4-clk-h32mx":
at91 h32mx clock
Required properties for SCKC node:
- reg : defines the IO memory reserved for the SCKC.
- #size-cells : shall be 0 (reg is used to encode clk id).
- #address-cells : shall be 1 (reg is used to encode clk id).
For example:
sckc: sckc@fffffe50 {
compatible = "atmel,sama5d3-pmc";
reg = <0xfffffe50 0x4>
#size-cells = <0>;
#address-cells = <1>;
/* put at91 slow clocks here */
};
Required properties for internal slow RC oscillator:
- #clock-cells : from common clock binding; shall be set to 0.
- clock-frequency : define the internal RC oscillator frequency.
Optional properties:
- clock-accuracy : define the internal RC oscillator accuracy.
For example:
slow_rc_osc: slow_rc_osc {
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
clock-frequency = <32768>;
clock-accuracy = <50000000>;
};
Required properties for slow oscillator:
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall encode the main osc source clk sources (see atmel datasheet).
Optional properties:
- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
provided on XIN.
For example:
slow_osc: slow_osc {
compatible = "atmel,at91rm9200-clk-slow-osc";
#clock-cells = <0>;
clocks = <&slow_xtal>;
};
Required properties for slow clock:
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall encode the slow clk sources (see atmel datasheet).
For example:
clk32k: slck {
compatible = "atmel,at91sam9x5-clk-slow";
#clock-cells = <0>;
clocks = <&slow_rc_osc &slow_osc>;
};
Required properties for PMC node:
- reg : defines the IO memory reserved for the PMC.
- #size-cells : shall be 0 (reg is used to encode clk id).
- #address-cells : shall be 1 (reg is used to encode clk id).
- interrupts : shall be set to PMC interrupt line.
- interrupt-controller : tell that the PMC is an interrupt controller.
- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
and reflect the bit position in the PMC_ER/DR/SR registers.
You can use the dt macros defined in dt-bindings/clock/at91.h.
0 (AT91_PMC_MOSCS) -> main oscillator ready
1 (AT91_PMC_LOCKA) -> PLL A ready
2 (AT91_PMC_LOCKB) -> PLL B ready
3 (AT91_PMC_MCKRDY) -> master clock ready
6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready
8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready
16 (AT91_PMC_MOSCSELS) -> main oscillator selected
17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized
18 (AT91_PMC_CFDEV) -> clock failure detected
For example:
pmc: pmc@fffffc00 {
compatible = "atmel,sama5d3-pmc";
interrupts = <1 4 7>;
interrupt-controller;
#interrupt-cells = <2>;
#size-cells = <0>;
#address-cells = <1>;
/* put at91 clocks here */
};
Required properties for main clock internal RC oscillator:
- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<0>".
- clock-frequency : define the internal RC oscillator frequency.
Optional properties:
- clock-accuracy : define the internal RC oscillator accuracy.
For example:
main_rc_osc: main_rc_osc {
compatible = "atmel,at91sam9x5-clk-main-rc-osc";
interrupt-parent = <&pmc>;
interrupts = <0>;
clock-frequency = <12000000>;
clock-accuracy = <50000000>;
};
Required properties for main clock oscillator:
- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<0>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall encode the main osc source clk sources (see atmel datasheet).
Optional properties:
- atmel,osc-bypass : boolean property. Specified if a clock signal is provided
on XIN.
clock signal is directly provided on XIN pin.
For example:
main_osc: main_osc {
compatible = "atmel,at91rm9200-clk-main-osc";
interrupt-parent = <&pmc>;
interrupts = <0>;
#clock-cells = <0>;
clocks = <&main_xtal>;
};
Required properties for main clock:
- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<0>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall encode the main clk sources (see atmel datasheet).
For example:
main: mainck {
compatible = "atmel,at91sam9x5-clk-main";
interrupt-parent = <&pmc>;
interrupts = <0>;
#clock-cells = <0>;
clocks = <&main_rc_osc &main_osc>;
};
Required properties for master clock:
- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<3>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the master clock sources (see atmel datasheet) phandles.
e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>".
- atmel,clk-output-range : minimum and maximum clock frequency (two u32
fields).
e.g. output = <0 133000000>; <=> 0 to 133MHz.
- atmel,clk-divisors : master clock divisors table (four u32 fields).
0 <=> reserved value.
e.g. divisors = <1 2 4 6>;
- atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the
PRES field as CLOCK_DIV3 (e.g sam9x5).
For example:
mck: mck {
compatible = "atmel,at91rm9200-clk-master";
interrupt-parent = <&pmc>;
interrupts = <3>;
#clock-cells = <0>;
atmel,clk-output-range = <0 133000000>;
atmel,clk-divisors = <1 2 4 0>;
};
Required properties for peripheral clocks:
- #size-cells : shall be 0 (reg is used to encode clk id).
- #address-cells : shall be 1 (reg is used to encode clk id).
- clocks : shall be the master clock phandle.
e.g. clocks = <&mck>;
- name: device tree node describing a specific system clock.
* #clock-cells : from common clock binding; shall be set to 0.
* reg: peripheral id. See Atmel's datasheets to get a full
list of peripheral ids.
* atmel,clk-output-range : minimum and maximum clock frequency
(two u32 fields). Only valid on at91sam9x5-clk-peripheral
compatible IPs.
For example:
periph: periphck {
compatible = "atmel,at91sam9x5-clk-peripheral";
#size-cells = <0>;
#address-cells = <1>;
clocks = <&mck>;
ssc0_clk {
#clock-cells = <0>;
reg = <2>;
atmel,clk-output-range = <0 133000000>;
};
usart0_clk {
#clock-cells = <0>;
reg = <3>;
atmel,clk-output-range = <0 66000000>;
};
};
Required properties for pll clocks:
- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<1>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the main clock phandle.
- reg : pll id.
0 -> PLL A
1 -> PLL B
- atmel,clk-input-range : minimum and maximum source clock frequency (two u32
fields).
e.g. input = <1 32000000>; <=> 1 to 32MHz.
- #atmel,pll-clk-output-range-cells : number of cells reserved for pll output
range description. Sould be set to 2, 3
or 4.
* 1st and 2nd cells represent the frequency range (min-max).
* 3rd cell is optional and represents the OUT field value for the given
range.
* 4th cell is optional and represents the ICPLL field (PLLICPR
register)
- atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter
depending on #atmel,pll-output-range-cells
property value.
For example:
plla: pllack {
compatible = "atmel,at91sam9g45-clk-pll";
interrupt-parent = <&pmc>;
interrupts = <1>;
#clock-cells = <0>;
clocks = <&main>;
reg = <0>;
atmel,clk-input-range = <2000000 32000000>;
#atmel,pll-clk-output-range-cells = <4>;
atmel,pll-clk-output-ranges = <74500000 800000000 0 0
69500000 750000000 1 0
64500000 700000000 2 0
59500000 650000000 3 0
54500000 600000000 0 1
49500000 550000000 1 1
44500000 500000000 2 1
40000000 450000000 3 1>;
};
Required properties for plldiv clocks (plldiv = pll / 2):
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the plla clock phandle.
The pll divisor is equal to 2 and cannot be changed.
For example:
plladiv: plladivck {
compatible = "atmel,at91sam9x5-clk-plldiv";
#clock-cells = <0>;
clocks = <&plla>;
};
Required properties for programmable clocks:
- interrupt-parent : must reference the PMC node.
- #size-cells : shall be 0 (reg is used to encode clk id).
- #address-cells : shall be 1 (reg is used to encode clk id).
- clocks : shall be the programmable clock source phandles.
e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
- name: device tree node describing a specific prog clock.
* #clock-cells : from common clock binding; shall be set to 0.
* reg : programmable clock id (register offset from PCKx
register).
* interrupts : shall be set to "<(8 + id)>".
For example:
prog: progck {
compatible = "atmel,at91sam9g45-clk-programmable";
#size-cells = <0>;
#address-cells = <1>;
interrupt-parent = <&pmc>;
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
prog0 {
#clock-cells = <0>;
reg = <0>;
interrupts = <8>;
};
prog1 {
#clock-cells = <0>;
reg = <1>;
interrupts = <9>;
};
};
Required properties for smd clock:
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the smd clock source phandles.
e.g. clocks = <&plladiv>, <&utmi>;
For example:
smd: smdck {
compatible = "atmel,at91sam9x5-clk-smd";
#clock-cells = <0>;
clocks = <&plladiv>, <&utmi>;
};
Required properties for system clocks:
- #size-cells : shall be 0 (reg is used to encode clk id).
- #address-cells : shall be 1 (reg is used to encode clk id).
- name: device tree node describing a specific system clock.
* #clock-cells : from common clock binding; shall be set to 0.
* reg: system clock id (bit position in SCER/SCDR/SCSR registers).
See Atmel's datasheet to get a full list of system clock ids.
For example:
system: systemck {
compatible = "atmel,at91rm9200-clk-system";
#address-cells = <1>;
#size-cells = <0>;
ddrck {
#clock-cells = <0>;
reg = <2>;
clocks = <&mck>;
};
uhpck {
#clock-cells = <0>;
reg = <6>;
clocks = <&usb>;
};
udpck {
#clock-cells = <0>;
reg = <7>;
clocks = <&usb>;
};
};
Required properties for usb clock:
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the smd clock source phandles.
e.g. clocks = <&pllb>;
- atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"):
usb clock divisor table.
e.g. divisors = <1 2 4 0>;
For example:
usb: usbck {
compatible = "atmel,at91sam9x5-clk-usb";
#clock-cells = <0>;
clocks = <&plladiv>, <&utmi>;
};
usb: usbck {
compatible = "atmel,at91rm9200-clk-usb";
#clock-cells = <0>;
clocks = <&pllb>;
atmel,clk-divisors = <1 2 4 0>;
};
Required properties for utmi clock:
- interrupt-parent : must reference the PMC node.
- interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the main clock source phandle.
For example:
utmi: utmick {
compatible = "atmel,at91sam9x5-clk-utmi";
interrupt-parent = <&pmc>;
interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <0>;
clocks = <&main>;
};
Required properties for 32 bits bus Matrix clock (h32mx clock):
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the master clock source phandle.
For example:
h32ck: h32mxck {
#clock-cells = <0>;
compatible = "atmel,sama5d4-clk-h32mx";
clocks = <&mck>;
};

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Binding for the axi-clkgen clock generator
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
- #clock-cells : from common clock binding; Should always be set to 0.
- reg : Address and length of the axi-clkgen register set.
- clocks : Phandle and clock specifier for the parent clock.
Optional properties:
- clock-output-names : From common clock binding.
Example:
clock@0xff000000 {
compatible = "adi,axi-clkgen";
#clock-cells = <0>;
reg = <0xff000000 0x1000>;
clocks = <&osc 1>;
};

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Broadcom Kona Family Clocks
This binding is associated with Broadcom SoCs having "Kona" style
clock control units (CCUs). A CCU is a clock provider that manages
a set of clock signals. Each CCU is represented by a node in the
device tree.
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible
Shall have a value of the form "brcm,<model>-<which>-ccu",
where <model> is a Broadcom SoC model number and <which> is
the name of a defined CCU. For example:
"brcm,bcm11351-root-ccu"
The compatible strings used for each supported SoC family
are defined below.
- reg
Shall define the base and range of the address space
containing clock control registers
- #clock-cells
Shall have value <1>. The permitted clock-specifier values
are defined below.
- clock-output-names
Shall be an ordered list of strings defining the names of
the clocks provided by the CCU.
Device tree example:
slave_ccu: slave_ccu {
compatible = "brcm,bcm11351-slave-ccu";
reg = <0x3e011000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "uartb",
"uartb2",
"uartb3",
"uartb4";
};
ref_crystal_clk: ref_crystal {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <26000000>;
};
uart@3e002000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e002000 0x1000>;
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
BCM281XX family
---------------
CCU compatible string values for SoCs in the BCM281XX family are:
"brcm,bcm11351-root-ccu"
"brcm,bcm11351-aon-ccu"
"brcm,bcm11351-hub-ccu"
"brcm,bcm11351-master-ccu"
"brcm,bcm11351-slave-ccu"
The following table defines the set of CCUs and clock specifiers for
BCM281XX family clocks. When a clock consumer references a clocks,
its symbolic specifier (rather than its numeric index value) should
be used. These specifiers are defined in:
"include/dt-bindings/clock/bcm281xx.h"
CCU Clock Type Index Specifier
--- ----- ---- ----- ---------
root frac_1m peri 0 BCM281XX_ROOT_CCU_FRAC_1M
aon hub_timer peri 0 BCM281XX_AON_CCU_HUB_TIMER
aon pmu_bsc peri 1 BCM281XX_AON_CCU_PMU_BSC
aon pmu_bsc_var peri 2 BCM281XX_AON_CCU_PMU_BSC_VAR
hub tmon_1m peri 0 BCM281XX_HUB_CCU_TMON_1M
master sdio1 peri 0 BCM281XX_MASTER_CCU_SDIO1
master sdio2 peri 1 BCM281XX_MASTER_CCU_SDIO2
master sdio3 peri 2 BCM281XX_MASTER_CCU_SDIO3
master sdio4 peri 3 BCM281XX_MASTER_CCU_SDIO4
master dmac peri 4 BCM281XX_MASTER_CCU_DMAC
master usb_ic peri 5 BCM281XX_MASTER_CCU_USB_IC
master hsic2_48m peri 6 BCM281XX_MASTER_CCU_HSIC_48M
master hsic2_12m peri 7 BCM281XX_MASTER_CCU_HSIC_12M
slave uartb peri 0 BCM281XX_SLAVE_CCU_UARTB
slave uartb2 peri 1 BCM281XX_SLAVE_CCU_UARTB2
slave uartb3 peri 2 BCM281XX_SLAVE_CCU_UARTB3
slave uartb4 peri 3 BCM281XX_SLAVE_CCU_UARTB4
slave ssp0 peri 4 BCM281XX_SLAVE_CCU_SSP0
slave ssp2 peri 5 BCM281XX_SLAVE_CCU_SSP2
slave bsc1 peri 6 BCM281XX_SLAVE_CCU_BSC1
slave bsc2 peri 7 BCM281XX_SLAVE_CCU_BSC2
slave bsc3 peri 8 BCM281XX_SLAVE_CCU_BSC3
slave pwm peri 9 BCM281XX_SLAVE_CCU_PWM
BCM21664 family
---------------
CCU compatible string values for SoCs in the BCM21664 family are:
"brcm,bcm21664-root-ccu"
"brcm,bcm21664-aon-ccu"
"brcm,bcm21664-master-ccu"
"brcm,bcm21664-slave-ccu"
The following table defines the set of CCUs and clock specifiers for
BCM21664 family clocks. When a clock consumer references a clocks,
its symbolic specifier (rather than its numeric index value) should
be used. These specifiers are defined in:
"include/dt-bindings/clock/bcm21664.h"
CCU Clock Type Index Specifier
--- ----- ---- ----- ---------
root frac_1m peri 0 BCM21664_ROOT_CCU_FRAC_1M
aon hub_timer peri 0 BCM21664_AON_CCU_HUB_TIMER
master sdio1 peri 0 BCM21664_MASTER_CCU_SDIO1
master sdio2 peri 1 BCM21664_MASTER_CCU_SDIO2
master sdio3 peri 2 BCM21664_MASTER_CCU_SDIO3
master sdio4 peri 3 BCM21664_MASTER_CCU_SDIO4
master sdio1_sleep peri 4 BCM21664_MASTER_CCU_SDIO1_SLEEP
master sdio2_sleep peri 5 BCM21664_MASTER_CCU_SDIO2_SLEEP
master sdio3_sleep peri 6 BCM21664_MASTER_CCU_SDIO3_SLEEP
master sdio4_sleep peri 7 BCM21664_MASTER_CCU_SDIO4_SLEEP
slave uartb peri 0 BCM21664_SLAVE_CCU_UARTB
slave uartb2 peri 1 BCM21664_SLAVE_CCU_UARTB2
slave uartb3 peri 2 BCM21664_SLAVE_CCU_UARTB3
slave uartb4 peri 3 BCM21664_SLAVE_CCU_UARTB4
slave bsc1 peri 4 BCM21664_SLAVE_CCU_BSC1
slave bsc2 peri 5 BCM21664_SLAVE_CCU_BSC2
slave bsc3 peri 6 BCM21664_SLAVE_CCU_BSC3
slave bsc4 peri 7 BCM21664_SLAVE_CCU_BSC4

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Device Tree Clock bindings for Calxeda highbank platform
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of the following:
"calxeda,hb-pll-clock" - for a PLL clock
"calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the
A9 clock.
"calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock.
"calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller.
- reg : shall be the control register offset from SYSREGs base for the clock.
- clocks : shall be the input parent clock phandle for the clock. This is
either an oscillator or a pll output.
- #clock-cells : from common clock binding; shall be set to 0.

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* Samsung Audio Subsystem Clock Controller
The Samsung Audio Subsystem clock controller generates and supplies clocks
to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
binding described here is applicable to all SoCs in Exynos family.
Required Properties:
- compatible: should be one of the following:
- "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
- "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
SoCs.
- "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
SoCs.
- reg: physical base address and length of the controller's register set.
- #clock-cells: should be 1.
- clocks:
- pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
is used if not specified.
- pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
is used if not specified.
- cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
specified.
- sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
not specified.
- sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not
specified.
- clock-names: Aliases for the above clocks. They should be "pll_ref",
"pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume. Some of the clocks are available only on a particular
Exynos4 SoC and this is specified where applicable.
Provided clocks:
Clock ID SoC (if specific)
-----------------------------------------------
mout_audss 0
mout_i2s 1
dout_srp 2
dout_aud_bus 3
dout_i2s 4
srp_clk 5
i2s_bus 6
sclk_i2s 7
pcm_bus 8
sclk_pcm 9
adma 10 Exynos5420
Example 1: An example of a clock controller node using the default input
clock names is listed below.
clock_audss: audss-clock-controller@3810000 {
compatible = "samsung,exynos5250-audss-clock";
reg = <0x03810000 0x0C>;
#clock-cells = <1>;
};
Example 2: An example of a clock controller node with the input clocks
specified.
clock_audss: audss-clock-controller@3810000 {
compatible = "samsung,exynos5250-audss-clock";
reg = <0x03810000 0x0C>;
#clock-cells = <1>;
clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
<&ext_i2s_clk>;
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
};
Example 3: I2S controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
i2s0: i2s@03830000 {
compatible = "samsung,i2s-v5";
reg = <0x03830000 0x100>;
dmas = <&pdma0 10
&pdma0 9
&pdma0 8>;
dma-names = "tx", "rx", "tx-sec";
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_SCLK_I2S>,
<&clock_audss EXYNOS_MOUT_AUDSS>,
<&clock_audss EXYNOS_MOUT_I2S>;
clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
"mout_audss", "mout_i2s";
};

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* Palmas 32KHz clocks *
Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
This binding uses the common clock binding ./clock-bindings.txt.
Required properties:
- compatible : "ti,palmas-clk32kg" for clk32kg clock
"ti,palmas-clk32kgaudio" for clk32kgaudio clock
- #clock-cells : shall be set to 0.
Optional property:
- ti,external-sleep-control: The external enable input pins controlled the
enable/disable of clocks. The external enable input pins ENABLE1,
ENABLE2 and NSLEEP. The valid values for the external pins are:
PALMAS_EXT_CONTROL_PIN_ENABLE1 for ENABLE1 pin
PALMAS_EXT_CONTROL_PIN_ENABLE2 for ENABLE2 pin
PALMAS_EXT_CONTROL_PIN_NSLEEP for NSLEEP pin
Option 0 or missing this property means the clock is enabled/disabled
via register access and these pins do not have any control.
The macros of external control pins for DTS is defined at
dt-bindings/mfd/palmas.h
Example:
#include <dt-bindings/mfd/palmas.h>
...
palmas: tps65913@58 {
...
clk32kg: palmas_clk32k@0 {
compatible = "ti,palmas-clk32kg";
#clock-cells = <0>;
ti,external-sleep-control = <PALMAS_EXT_CONTROL_PIN_NSLEEP>;
};
...
};

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* Samsung Audio Subsystem Clock Controller
The Samsung Audio Subsystem clock controller generates and supplies clocks
to Audio Subsystem block available in the S5PV210 and compatible SoCs.
Required Properties:
- compatible: should be "samsung,s5pv210-audss-clock".
- reg: physical base address and length of the controller's register set.
- #clock-cells: should be 1.
- clocks:
- hclk: AHB bus clock of the Audio Subsystem.
- xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
not specified (i.e. xusbxti is used for PLL reference), it is fixed to
a clock named "xxti".
- fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
- iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not
specified, it is fixed to a clock named "iiscdclk0".
- sclk_audio0: Audio bus clock, parent of mout_i2s.
- clock-names: Aliases for the above clocks. They should be "hclk",
"xxti", "fout_epll", "iiscdclk0", and "sclk_audio0" respectively.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s5pv210-audss-clk.h header and can be used in device
tree sources.
Example: Clock controller node.
clk_audss: clock-controller@c0900000 {
compatible = "samsung,s5pv210-audss-clock";
reg = <0xc0900000 0x1000>;
#clock-cells = <1>;
clock-names = "hclk", "xxti",
"fout_epll", "sclk_audio0";
clocks = <&clocks DOUT_HCLKP>, <&xxti>,
<&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>;
};
Example: I2S controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
i2s0: i2s@03830000 {
/* ... */
clock-names = "iis", "i2s_opclk0",
"i2s_opclk1";
clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>,
<&clk_audss CLK_DOUT_AUD_BUS>;
/* ... */
};

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This binding is a work-in-progress, and are based on some experimental
work by benh[1].
Sources of clock signal can be represented by any node in the device
tree. Those nodes are designated as clock providers. Clock consumer
nodes use a phandle and clock specifier pair to connect clock provider
outputs to clock inputs. Similar to the gpio specifiers, a clock
specifier is an array of zero, one or more cells identifying the clock
output on a device. The length of a clock specifier is defined by the
value of a #clock-cells property in the clock provider node.
[1] http://patchwork.ozlabs.org/patch/31551/
==Clock providers==
Required properties:
#clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
with a single clock output and 1 for nodes with multiple
clock outputs.
Optional properties:
clock-output-names: Recommended to be a list of strings of clock output signal
names indexed by the first cell in the clock specifier.
However, the meaning of clock-output-names is domain
specific to the clock provider, and is only provided to
encourage using the same meaning for the majority of clock
providers. This format may not work for clock providers
using a complex clock specifier format. In those cases it
is recommended to omit this property and create a binding
specific names property.
Clock consumer nodes must never directly reference
the provider's clock-output-names property.
For example:
oscillator {
#clock-cells = <1>;
clock-output-names = "ckil", "ckih";
};
- this node defines a device with two clock outputs, the first named
"ckil" and the second named "ckih". Consumer nodes always reference
clocks by index. The names should reflect the clock output signal
names for the device.
clock-indices: If the identifying number for the clocks in the node
is not linear from zero, then this allows the mapping of
identifiers into the clock-output-names array.
For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
oscillator {
compatible = "myclocktype";
#clock-cells = <1>;
clock-indices = <1>, <3>;
clock-output-names = "clka", "clkb";
}
This ensures we do not have any empty strings in clock-output-names
==Clock consumers==
Required properties:
clocks: List of phandle and clock specifier pairs, one pair
for each clock input to the device. Note: if the
clock provider specifies '0' for #clock-cells, then
only the phandle portion of the pair will appear.
Optional properties:
clock-names: List of clock input name strings sorted in the same
order as the clocks property. Consumers drivers
will use clock-names to match clock input names
with clocks specifiers.
clock-ranges: Empty property indicating that child nodes can inherit named
clocks from this node. Useful for bus nodes to provide a
clock to their children.
For example:
device {
clocks = <&osc 1>, <&ref 0>;
clock-names = "baud", "register";
};
This represents a device with two clock inputs, named "baud" and "register".
The baud clock is connected to output 1 of the &osc device, and the register
clock is connected to output 0 of the &ref.
==Example==
/* external oscillator */
osc: oscillator {
compatible = "fixed-clock";
#clock-cells = <1>;
clock-frequency = <32678>;
clock-output-names = "osc";
};
/* phase-locked-loop device, generates a higher frequency clock
* from the external oscillator reference */
pll: pll@4c000 {
compatible = "vendor,some-pll-interface"
#clock-cells = <1>;
clocks = <&osc 0>;
clock-names = "ref";
reg = <0x4c000 0x1000>;
clock-output-names = "pll", "pll-switched";
};
/* UART, using the low frequency oscillator for the baud clock,
* and the high frequency switched PLL output for register
* clocking */
uart@a000 {
compatible = "fsl,imx-uart";
reg = <0xa000 0x1000>;
interrupts = <33>;
clocks = <&osc 0>, <&pll 1>;
clock-names = "baud", "register";
};
This DT fragment defines three devices: an external oscillator to provide a
low-frequency reference clock, a PLL device to generate a higher frequency
clock signal, and a UART.
* The oscillator is fixed-frequency, and provides one clock output, named "osc".
* The PLL is both a clock provider and a clock consumer. It uses the clock
signal generated by the external oscillator, and provides two output signals
("pll" and "pll-switched").
* The UART has its baud clock connected the external oscillator and its
register clock connected to the PLL clock (the "pll-switched" signal)
==Assigned clock parents and rates==
Some platforms may require initial configuration of default parent clocks
and clock frequencies. Such a configuration can be specified in a device tree
node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
properties. The assigned-clock-parents property should contain a list of parent
clocks in form of phandle and clock specifier pairs, the assigned-clock-parents
property the list of assigned clock frequency values - corresponding to clocks
listed in the assigned-clocks property.
To skip setting parent or rate of a clock its corresponding entry should be
set to 0, or can be omitted if it is not followed by any non-zero entry.
uart@a000 {
compatible = "fsl,imx-uart";
reg = <0xa000 0x1000>;
...
clocks = <&osc 0>, <&pll 1>;
clock-names = "baud", "register";
assigned-clocks = <&clkcon 0>, <&pll 2>;
assigned-clock-parents = <&pll 2>;
assigned-clock-rates = <0>, <460800>;
};
In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
the <&pll 2> clock is assigned a frequency value of 460800 Hz.
Configuring a clock's parent and rate through the device node that consumes
the clock can be done only for clocks that have a single user. Specifying
conflicting parent or rate configuration in multiple consumer nodes for
a shared clock is forbidden.
Configuration of common clocks, which affect multiple consumer devices can
be similarly specified in the clock provider node.

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* Clock bindings for the Cirrus Logic CLPS711X CPUs
Required properties:
- compatible : Shall contain "cirrus,clps711x-clk".
- reg : Address of the internal register set.
- startup-frequency: Factory set CPU startup frequency in HZ.
- #clock-cells : Should be <1>.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/clps711x-clock.h
for the full list of CLPS711X clock IDs.
Example:
clks: clks@80000000 {
#clock-cells = <1>;
compatible = "cirrus,ep7312-clk", "cirrus,clps711x-clk";
reg = <0x80000000 0xc000>;
startup-frequency = <73728000>;
};

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* Clock bindings for Energy Micro efm32 Giant Gecko's Clock Management Unit
Required properties:
- compatible: Should be "efm32gg,cmu"
- reg: Base address and length of the register set
- interrupts: Interrupt used by the CMU
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock ID in
its "clocks" phandle cell. The header efm32-clk.h contains a list of available
IDs.

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Device tree Clock bindings for Renesas EMMA Mobile EV2
This binding uses the common clock binding.
* SMU
System Management Unit described in user's manual R19UH0037EJ1000_SMU.
This is not a clock provider, but clocks under SMU depend on it.
Required properties:
- compatible: Should be "renesas,emev2-smu"
- reg: Address and Size of SMU registers
* SMU_CLKDIV
Function block with an input mux and a divider, which corresponds to
"Serial clock generator" in fig."Clock System Overview" of the manual,
and "xxx frequency division setting register" (XXXCLKDIV) registers.
This makes internal (neither input nor output) clock that is provided
to input of xxxGCLK block.
Required properties:
- compatible: Should be "renesas,emev2-smu-clkdiv"
- reg: Byte offset from SMU base and Bit position in the register
- clocks: Parent clocks. Input clocks as described in clock-bindings.txt
- #clock-cells: Should be <0>
* SMU_GCLK
Clock gating node shown as "Clock stop processing block" in the
fig."Clock System Overview" of the manual.
Registers are "xxx clock gate control register" (XXXGCLKCTRL).
Required properties:
- compatible: Should be "renesas,emev2-smu-gclk"
- reg: Byte offset from SMU base and Bit position in the register
- clocks: Input clock as described in clock-bindings.txt
- #clock-cells: Should be <0>
Example of provider:
usia_u0_sclkdiv: usia_u0_sclkdiv {
compatible = "renesas,emev2-smu-clkdiv";
reg = <0x610 0>;
clocks = <&pll3_fo>, <&pll4_fo>, <&pll1_fo>, <&osc1_fo>;
#clock-cells = <0>;
};
usia_u0_sclk: usia_u0_sclk {
compatible = "renesas,emev2-smu-gclk";
reg = <0x4a0 1>;
clocks = <&usia_u0_sclkdiv>;
#clock-cells = <0>;
};
Example of consumer:
uart@e1020000 {
compatible = "renesas,em-uart";
reg = <0xe1020000 0x38>;
interrupts = <0 8 0>;
clocks = <&usia_u0_sclk>;
clock-names = "sclk";
};
Example of clock-tree description:
This describes a clock path in the clock tree
c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
smu@e0110000 {
compatible = "renesas,emev2-smu";
reg = <0xe0110000 0x10000>;
#address-cells = <2>;
#size-cells = <0>;
c32ki: c32ki {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
pll3_fo: pll3_fo {
compatible = "fixed-factor-clock";
clocks = <&c32ki>;
clock-div = <1>;
clock-mult = <7000>;
#clock-cells = <0>;
};
usia_u0_sclkdiv: usia_u0_sclkdiv {
compatible = "renesas,emev2-smu-clkdiv";
reg = <0x610 0>;
clocks = <&pll3_fo>;
#clock-cells = <0>;
};
usia_u0_sclk: usia_u0_sclk {
compatible = "renesas,emev2-smu-gclk";
reg = <0x4a0 1>;
clocks = <&usia_u0_sclkdiv>;
#clock-cells = <0>;
};
};

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* Samsung Exynos3250 Clock Controller
The Exynos3250 clock controller generates and supplies clock to various
controllers within the Exynos3250 SoC.
Required Properties:
- compatible: should be one of the following.
- "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
- "samsung,exynos3250-cmu-dmc" - controller compatible with
Exynos3250 SoC for Dynamic Memory Controller domain.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos3250.h header and can be used in device
tree sources.
Example 1: Examples of clock controller nodes are listed below.
cmu: clock-controller@10030000 {
compatible = "samsung,exynos3250-cmu";
reg = <0x10030000 0x20000>;
#clock-cells = <1>;
};
cmu_dmc: clock-controller@105C0000 {
compatible = "samsung,exynos3250-cmu-dmc";
reg = <0x105C0000 0x2000>;
#clock-cells = <1>;
};
Example 2: UART controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
serial@13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>;
interrupts = <0 109 0>;
clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
};

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* Samsung Exynos4 Clock Controller
The Exynos4 clock controller generates and supplies clock to various controllers
within the Exynos4 SoC. The clock binding described here is applicable to all
SoC's in the Exynos4 family.
Required Properties:
- compatible: should be one of the following.
- "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
- "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos4.h header and can be used in device
tree sources.
Example 1: An example of a clock controller node is listed below.
clock: clock-controller@0x10030000 {
compatible = "samsung,exynos4210-clock";
reg = <0x10030000 0x20000>;
#clock-cells = <1>;
};
Example 2: UART controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
serial@13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
interrupts = <0 54 0>;
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
};

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* Samsung Exynos5250 Clock Controller
The Exynos5250 clock controller generates and supplies clock to various
controllers within the Exynos5250 SoC.
Required Properties:
- compatible: should be one of the following.
- "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos5250.h header and can be used in device
tree sources.
Example 1: An example of a clock controller node is listed below.
clock: clock-controller@0x10010000 {
compatible = "samsung,exynos5250-clock";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
};
Example 2: UART controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
serial@13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
interrupts = <0 54 0>;
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
};

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* Samsung Exynos5260 Clock Controller
Exynos5260 has 13 clock controllers which are instantiated
independently from the device-tree. These clock controllers
generate and supply clocks to various hardware blocks within
the SoC.
Each clock is assigned an identifier and client nodes can use
this identifier to specify the clock which they consume. All
available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos5260-clk.h header and can be used in
device tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It
is expected that they are defined using standard clock bindings
with following clock-output-names:
- "fin_pll" - PLL input clock from XXTI
- "xrtcxti" - input clock from XRTCXTI
- "ioclk_pcm_extclk" - pcm external operation clock
- "ioclk_spdif_extclk" - spdif external operation clock
- "ioclk_i2s_cdclk" - i2s0 codec clock
Phy clocks:
There are several clocks which are generated by specific PHYs.
These clocks are fed into the clock controller and then routed to
the hardware blocks. These clocks are defined as fixed clocks in the
driver with following names:
- "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
- "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
- "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
- "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
- "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
- "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
- "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
- "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
- "phyclk_dptx_phy_clk_div2"
- "phyclk_mipi_dphy_4l_m_rxclkesc0"
- "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
- "phyclk_usbhost20_phy_freeclk"
- "phyclk_usbhost20_phy_clk48mohci"
- "phyclk_usbdrd30_udrd30_pipe_pclk"
- "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
Required Properties for Clock Controller:
- compatible: should be one of the following.
1) "samsung,exynos5260-clock-top"
2) "samsung,exynos5260-clock-peri"
3) "samsung,exynos5260-clock-egl"
4) "samsung,exynos5260-clock-kfc"
5) "samsung,exynos5260-clock-g2d"
6) "samsung,exynos5260-clock-mif"
7) "samsung,exynos5260-clock-mfc"
8) "samsung,exynos5260-clock-g3d"
9) "samsung,exynos5260-clock-fsys"
10) "samsung,exynos5260-clock-aud"
11) "samsung,exynos5260-clock-isp"
12) "samsung,exynos5260-clock-gscl"
13) "samsung,exynos5260-clock-disp"
- reg: physical base address of the controller and the length of
memory mapped region.
- #clock-cells: should be 1.
- clocks: list of clock identifiers which are fed as the input to
the given clock controller. Please refer the next section to find
the input clocks for a given controller.
- clock-names: list of names of clocks which are fed as the input
to the given clock controller.
Input clocks for top clock controller:
- fin_pll
- dout_mem_pll
- dout_bus_pll
- dout_media_pll
Input clocks for peri clock controller:
- fin_pll
- ioclk_pcm_extclk
- ioclk_i2s_cdclk
- ioclk_spdif_extclk
- phyclk_hdmi_phy_ref_cko
- dout_aclk_peri_66
- dout_sclk_peri_uart0
- dout_sclk_peri_uart1
- dout_sclk_peri_uart2
- dout_sclk_peri_spi0_b
- dout_sclk_peri_spi1_b
- dout_sclk_peri_spi2_b
- dout_aclk_peri_aud
- dout_sclk_peri_spi0_b
Input clocks for egl clock controller:
- fin_pll
- dout_bus_pll
Input clocks for kfc clock controller:
- fin_pll
- dout_media_pll
Input clocks for g2d clock controller:
- fin_pll
- dout_aclk_g2d_333
Input clocks for mif clock controller:
- fin_pll
Input clocks for mfc clock controller:
- fin_pll
- dout_aclk_mfc_333
Input clocks for g3d clock controller:
- fin_pll
Input clocks for fsys clock controller:
- fin_pll
- phyclk_usbhost20_phy_phyclock
- phyclk_usbhost20_phy_freeclk
- phyclk_usbhost20_phy_clk48mohci
- phyclk_usbdrd30_udrd30_pipe_pclk
- phyclk_usbdrd30_udrd30_phyclock
- dout_aclk_fsys_200
Input clocks for aud clock controller:
- fin_pll
- fout_aud_pll
- ioclk_i2s_cdclk
- ioclk_pcm_extclk
Input clocks for isp clock controller:
- fin_pll
- dout_aclk_isp1_266
- dout_aclk_isp1_400
- mout_aclk_isp1_266
Input clocks for gscl clock controller:
- fin_pll
- dout_aclk_gscl_400
- dout_aclk_gscl_333
Input clocks for disp clock controller:
- fin_pll
- phyclk_dptx_phy_ch3_txd_clk
- phyclk_dptx_phy_ch2_txd_clk
- phyclk_dptx_phy_ch1_txd_clk
- phyclk_dptx_phy_ch0_txd_clk
- phyclk_hdmi_phy_tmds_clko
- phyclk_hdmi_phy_ref_clko
- phyclk_hdmi_phy_pixel_clko
- phyclk_hdmi_link_o_tmds_clkhi
- phyclk_mipi_dphy_4l_m_txbyte_clkhs
- phyclk_dptx_phy_o_ref_clk_24m
- phyclk_dptx_phy_clk_div2
- phyclk_mipi_dphy_4l_m_rxclkesc0
- phyclk_hdmi_phy_ref_cko
- ioclk_spdif_extclk
- dout_aclk_peri_aud
- dout_aclk_disp_222
- dout_sclk_disp_pixel
- dout_aclk_disp_333
Example 1: An example of a clock controller node is listed below.
clock_mfc: clock-controller@11090000 {
compatible = "samsung,exynos5260-clock-mfc";
clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>;
clock-names = "fin_pll", "dout_aclk_mfc_333";
reg = <0x11090000 0x10000>;
#clock-cells = <1>;
};
Example 2: UART controller node that consumes the clock generated by the
peri clock controller. Refer to the standard clock bindings for
information about 'clocks' and 'clock-names' property.
serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
interrupts = <0 146 0>;
clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
};

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* Samsung Exynos5410 Clock Controller
The Exynos5410 clock controller generates and supplies clock to various
controllers within the Exynos5410 SoC.
Required Properties:
- compatible: should be "samsung,exynos5410-clock"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos5410.h header and can be used in device
tree sources.
External clock:
There is clock that is generated outside the SoC. It
is expected that it is defined using standard clock bindings
with following clock-output-name:
- "fin_pll" - PLL input clock from XXTI
Example 1: An example of a clock controller node is listed below.
clock: clock-controller@0x10010000 {
compatible = "samsung,exynos5410-clock";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
};
Example 2: UART controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
serial@12C20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
interrupts = <0 51 0>;
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
};

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* Samsung Exynos5420 Clock Controller
The Exynos5420 clock controller generates and supplies clock to various
controllers within the Exynos5420 SoC and for the Exynos5800 SoC.
Required Properties:
- compatible: should be one of the following.
- "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
- "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos5420.h header and can be used in device
tree sources.
Example 1: An example of a clock controller node is listed below.
clock: clock-controller@0x10010000 {
compatible = "samsung,exynos5420-clock";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
};
Example 2: UART controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
serial@13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
interrupts = <0 54 0>;
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
};

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* Samsung Exynos5440 Clock Controller
The Exynos5440 clock controller generates and supplies clock to various
controllers within the Exynos5440 SoC.
Required Properties:
- compatible: should be "samsung,exynos5440-clock".
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos5440.h header and can be used in device
tree sources.
Example: An example of a clock controller node is listed below.
clock: clock-controller@0x10010000 {
compatible = "samsung,exynos5440-clock";
reg = <0x160000 0x10000>;
#clock-cells = <1>;
};

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Binding for simple fixed-rate clock sources.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "fixed-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- clock-frequency : frequency of clock in Hz. Should be a single cell.
Optional properties:
- clock-accuracy : accuracy of clock in ppb (parts per billion).
Should be a single cell.
- clock-output-names : From common clock binding.
Example:
clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000000>;
clock-accuracy = <100>;
};

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Binding for simple fixed factor rate clock sources.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "fixed-factor-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- clock-div: fixed divider.
- clock-mult: fixed multiplier.
- clocks: parent clock.
Optional properties:
- clock-output-names : From common clock binding.
Example:
clock {
compatible = "fixed-factor-clock";
clocks = <&parentclk>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
};

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Binding for simple gpio gated clock.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "gpio-gate-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- enable-gpios : GPIO reference for enabling and disabling the clock.
Optional properties:
- clocks: Maximum of one parent clock is supported.
Example:
clock {
compatible = "gpio-gate-clock";
clocks = <&parentclk>;
#clock-cells = <0>;
enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
};

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* Hisilicon Hi3620 Clock Controller
The Hi3620 clock controller generates and supplies clock to various
controllers within the Hi3620 SoC.
Required Properties:
- compatible: should be one of the following.
- "hisilicon,hi3620-clock" - controller compatible with Hi3620 SoC.
- "hisilicon,hi3620-mmc-clock" - controller specific for Hi3620 mmc.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifier could be found in <dt-bindings/clock/hi3620-clock.h>.

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* Hisilicon Hix5hd2 Clock Controller
The hix5hd2 clock controller generates and supplies clock to various
controllers within the hix5hd2 SoC.
Required Properties:
- compatible: should be "hisilicon,hix5hd2-clock"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifier could be found in <dt-bindings/clock/hix5hd2-clock.h>.
Examples:
clock: clock@f8a22000 {
compatible = "hisilicon,hix5hd2-clock";
reg = <0xf8a22000 0x1000>;
#clock-cells = <1>;
};
uart0: uart@f8b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xf8b00000 0x1000>;
interrupts = <0 49 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
status = "disabled";
};

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* Clock bindings for Freescale i.MX1 CPUs
Required properties:
- compatible: Should be "fsl,imx1-ccm".
- reg: Address and length of the register set.
- #clock-cells: Should be <1>.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
for the full list of i.MX1 clock IDs.
Examples:
clks: ccm@0021b000 {
#clock-cells = <1>;
compatible = "fsl,imx1-ccm";
reg = <0x0021b000 0x1000>;
};
pwm: pwm@00208000 {
#pwm-cells = <2>;
compatible = "fsl,imx1-pwm";
reg = <0x00208000 0x1000>;
interrupts = <34>;
clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
};

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* Clock bindings for Freescale i.MX21
Required properties:
- compatible : Should be "fsl,imx21-ccm".
- reg : Address and length of the register set.
- interrupts : Should contain CCM interrupt.
- #clock-cells: Should be <1>.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h
for the full list of i.MX21 clock IDs.
Examples:
clks: ccm@10027000{
compatible = "fsl,imx21-ccm";
reg = <0x10027000 0x800>;
#clock-cells = <1>;
};
uart1: serial@1000a000 {
compatible = "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
interrupts = <20>;
clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
<&clks IMX21_CLK_PER1>;
clock-names = "ipg", "per";
status = "disabled";
};

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* Clock bindings for Freescale i.MX23
Required properties:
- compatible: Should be "fsl,imx23-clkctrl"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX23
clocks and IDs.
Clock ID
------------------
ref_xtal 0
pll 1
ref_cpu 2
ref_emi 3
ref_pix 4
ref_io 5
saif_sel 6
lcdif_sel 7
gpmi_sel 8
ssp_sel 9
emi_sel 10
cpu 11
etm_sel 12
cpu_pll 13
cpu_xtal 14
hbus 15
xbus 16
lcdif_div 17
ssp_div 18
gpmi_div 19
emi_pll 20
emi_xtal 21
etm_div 22
saif_div 23
clk32k_div 24
rtc 25
adc 26
spdif_div 27
clk32k 28
dri 29
pwm 30
filt 31
uart 32
ssp 33
gpmi 34
spdif 35
emi 36
saif 37
lcdif 38
etm 39
usb 40
usb_phy 41
Examples:
clks: clkctrl@80040000 {
compatible = "fsl,imx23-clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};
auart0: serial@8006c000 {
compatible = "fsl,imx23-auart";
reg = <0x8006c000 0x2000>;
interrupts = <24 25 23>;
clocks = <&clks 32>;
status = "disabled";
};

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* Clock bindings for Freescale i.MX25
Required properties:
- compatible: Should be "fsl,imx25-ccm"
- reg: Address and length of the register set
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX25
clocks and IDs.
Clock ID
---------------------------
dummy 0
osc 1
mpll 2
upll 3
mpll_cpu_3_4 4
cpu_sel 5
cpu 6
ahb 7
usb_div 8
ipg 9
per0_sel 10
per1_sel 11
per2_sel 12
per3_sel 13
per4_sel 14
per5_sel 15
per6_sel 16
per7_sel 17
per8_sel 18
per9_sel 19
per10_sel 20
per11_sel 21
per12_sel 22
per13_sel 23
per14_sel 24
per15_sel 25
per0 26
per1 27
per2 28
per3 29
per4 30
per5 31
per6 32
per7 33
per8 34
per9 35
per10 36
per11 37
per12 38
per13 39
per14 40
per15 41
csi_ipg_per 42
epit_ipg_per 43
esai_ipg_per 44
esdhc1_ipg_per 45
esdhc2_ipg_per 46
gpt_ipg_per 47
i2c_ipg_per 48
lcdc_ipg_per 49
nfc_ipg_per 50
owire_ipg_per 51
pwm_ipg_per 52
sim1_ipg_per 53
sim2_ipg_per 54
ssi1_ipg_per 55
ssi2_ipg_per 56
uart_ipg_per 57
ata_ahb 58
reserved 59
csi_ahb 60
emi_ahb 61
esai_ahb 62
esdhc1_ahb 63
esdhc2_ahb 64
fec_ahb 65
lcdc_ahb 66
rtic_ahb 67
sdma_ahb 68
slcdc_ahb 69
usbotg_ahb 70
reserved 71
reserved 72
reserved 73
reserved 74
can1_ipg 75
can2_ipg 76
csi_ipg 77
cspi1_ipg 78
cspi2_ipg 79
cspi3_ipg 80
dryice_ipg 81
ect_ipg 82
epit1_ipg 83
epit2_ipg 84
reserved 85
esdhc1_ipg 86
esdhc2_ipg 87
fec_ipg 88
reserved 89
reserved 90
reserved 91
gpt1_ipg 92
gpt2_ipg 93
gpt3_ipg 94
gpt4_ipg 95
reserved 96
reserved 97
reserved 98
iim_ipg 99
reserved 100
reserved 101
kpp_ipg 102
lcdc_ipg 103
reserved 104
pwm1_ipg 105
pwm2_ipg 106
pwm3_ipg 107
pwm4_ipg 108
rngb_ipg 109
reserved 110
scc_ipg 111
sdma_ipg 112
sim1_ipg 113
sim2_ipg 114
slcdc_ipg 115
spba_ipg 116
ssi1_ipg 117
ssi2_ipg 118
tsc_ipg 119
uart1_ipg 120
uart2_ipg 121
uart3_ipg 122
uart4_ipg 123
uart5_ipg 124
reserved 125
wdt_ipg 126
cko_div 127
cko_sel 128
cko 129
Examples:
clks: ccm@53f80000 {
compatible = "fsl,imx25-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <31>;
};
uart1: serial@43f90000 {
compatible = "fsl,imx25-uart", "fsl,imx21-uart";
reg = <0x43f90000 0x4000>;
interrupts = <45>;
clocks = <&clks 79>, <&clks 50>;
clock-names = "ipg", "per";
status = "disabled";
};

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* Clock bindings for Freescale i.MX27
Required properties:
- compatible: Should be "fsl,imx27-ccm"
- reg: Address and length of the register set
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
for the full list of i.MX27 clock IDs.
Examples:
clks: ccm@10027000{
compatible = "fsl,imx27-ccm";
reg = <0x10027000 0x1000>;
#clock-cells = <1>;
};
uart1: serial@1000a000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
interrupts = <20>;
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
<&clks IMX27_CLK_PER1_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};

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* Clock bindings for Freescale i.MX28
Required properties:
- compatible: Should be "fsl,imx28-clkctrl"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX28
clocks and IDs.
Clock ID
------------------
ref_xtal 0
pll0 1
pll1 2
pll2 3
ref_cpu 4
ref_emi 5
ref_io0 6
ref_io1 7
ref_pix 8
ref_hsadc 9
ref_gpmi 10
saif0_sel 11
saif1_sel 12
gpmi_sel 13
ssp0_sel 14
ssp1_sel 15
ssp2_sel 16
ssp3_sel 17
emi_sel 18
etm_sel 19
lcdif_sel 20
cpu 21
ptp_sel 22
cpu_pll 23
cpu_xtal 24
hbus 25
xbus 26
ssp0_div 27
ssp1_div 28
ssp2_div 29
ssp3_div 30
gpmi_div 31
emi_pll 32
emi_xtal 33
lcdif_div 34
etm_div 35
ptp 36
saif0_div 37
saif1_div 38
clk32k_div 39
rtc 40
lradc 41
spdif_div 42
clk32k 43
pwm 44
uart 45
ssp0 46
ssp1 47
ssp2 48
ssp3 49
gpmi 50
spdif 51
emi 52
saif0 53
saif1 54
lcdif 55
etm 56
fec 57
can0 58
can1 59
usb0 60
usb1 61
usb0_phy 62
usb1_phy 63
enet_out 64
Examples:
clks: clkctrl@80040000 {
compatible = "fsl,imx28-clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};
auart0: serial@8006a000 {
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006a000 0x2000>;
interrupts = <112 70 71>;
clocks = <&clks 45>;
status = "disabled";
};

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* Clock bindings for Freescale i.MX31
Required properties:
- compatible: Should be "fsl,imx31-ccm"
- reg: Address and length of the register set
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX31
clocks and IDs.
Clock ID
-----------------------
dummy 0
ckih 1
ckil 2
mpll 3
spll 4
upll 5
mcu_main 6
hsp 7
ahb 8
nfc 9
ipg 10
per_div 11
per 12
csi_sel 13
fir_sel 14
csi_div 15
usb_div_pre 16
usb_div_post 17
fir_div_pre 18
fir_div_post 19
sdhc1_gate 20
sdhc2_gate 21
gpt_gate 22
epit1_gate 23
epit2_gate 24
iim_gate 25
ata_gate 26
sdma_gate 27
cspi3_gate 28
rng_gate 29
uart1_gate 30
uart2_gate 31
ssi1_gate 32
i2c1_gate 33
i2c2_gate 34
i2c3_gate 35
hantro_gate 36
mstick1_gate 37
mstick2_gate 38
csi_gate 39
rtc_gate 40
wdog_gate 41
pwm_gate 42
sim_gate 43
ect_gate 44
usb_gate 45
kpp_gate 46
ipu_gate 47
uart3_gate 48
uart4_gate 49
uart5_gate 50
owire_gate 51
ssi2_gate 52
cspi1_gate 53
cspi2_gate 54
gacc_gate 55
emi_gate 56
rtic_gate 57
firi_gate 58
Examples:
clks: ccm@53f80000{
compatible = "fsl,imx31-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <0 31 0x04 0 53 0x04>;
#clock-cells = <1>;
};
uart1: serial@43f90000 {
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
reg = <0x43f90000 0x4000>;
interrupts = <45>;
clocks = <&clks 10>, <&clks 30>;
clock-names = "ipg", "per";
status = "disabled";
};

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* Clock bindings for Freescale i.MX35
Required properties:
- compatible: Should be "fsl,imx35-ccm"
- reg: Address and length of the register set
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX35
clocks and IDs.
Clock ID
---------------------------
ckih 0
mpll 1
ppll 2
mpll_075 3
arm 4
hsp 5
hsp_div 6
hsp_sel 7
ahb 8
ipg 9
arm_per_div 10
ahb_per_div 11
ipg_per 12
uart_sel 13
uart_div 14
esdhc_sel 15
esdhc1_div 16
esdhc2_div 17
esdhc3_div 18
spdif_sel 19
spdif_div_pre 20
spdif_div_post 21
ssi_sel 22
ssi1_div_pre 23
ssi1_div_post 24
ssi2_div_pre 25
ssi2_div_post 26
usb_sel 27
usb_div 28
nfc_div 29
asrc_gate 30
pata_gate 31
audmux_gate 32
can1_gate 33
can2_gate 34
cspi1_gate 35
cspi2_gate 36
ect_gate 37
edio_gate 38
emi_gate 39
epit1_gate 40
epit2_gate 41
esai_gate 42
esdhc1_gate 43
esdhc2_gate 44
esdhc3_gate 45
fec_gate 46
gpio1_gate 47
gpio2_gate 48
gpio3_gate 49
gpt_gate 50
i2c1_gate 51
i2c2_gate 52
i2c3_gate 53
iomuxc_gate 54
ipu_gate 55
kpp_gate 56
mlb_gate 57
mshc_gate 58
owire_gate 59
pwm_gate 60
rngc_gate 61
rtc_gate 62
rtic_gate 63
scc_gate 64
sdma_gate 65
spba_gate 66
spdif_gate 67
ssi1_gate 68
ssi2_gate 69
uart1_gate 70
uart2_gate 71
uart3_gate 72
usbotg_gate 73
wdog_gate 74
max_gate 75
admux_gate 76
csi_gate 77
csi_div 78
csi_sel 79
iim_gate 80
gpu2d_gate 81
Examples:
clks: ccm@53f80000 {
compatible = "fsl,imx35-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <31>;
#clock-cells = <1>;
};
esdhc1: esdhc@53fb4000 {
compatible = "fsl,imx35-esdhc";
reg = <0x53fb4000 0x4000>;
interrupts = <7>;
clocks = <&clks 9>, <&clks 8>, <&clks 43>;
clock-names = "ipg", "ahb", "per";
};

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* Clock bindings for Freescale i.MX5
Required properties:
- compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53
- reg: Address and length of the register set
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h
for the full list of i.MX5 clock IDs.
Examples (for mx53):
clks: ccm@53fd4000{
compatible = "fsl,imx53-ccm";
reg = <0x53fd4000 0x4000>;
interrupts = <0 71 0x04 0 72 0x04>;
#clock-cells = <1>;
};
can1: can@53fc8000 {
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
reg = <0x53fc8000 0x4000>;
interrupts = <82>;
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};

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* Clock bindings for Freescale i.MX6 Quad
Required properties:
- compatible: Should be "fsl,imx6q-ccm"
- reg: Address and length of the register set
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
for the full list of i.MX6 Quad and DualLite clock IDs.
Examples:
#include <dt-bindings/clock/imx6qdl-clock.h>
clks: ccm@020c4000 {
compatible = "fsl,imx6q-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 0x04 0 88 0x04>;
#clock-cells = <1>;
};
uart1: serial@02020000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
status = "disabled";
};

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* Clock bindings for Freescale i.MX6 SoloLite
Required properties:
- compatible: Should be "fsl,imx6sl-ccm"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sl-clock.h
for the full list of i.MX6 SoloLite clock IDs.

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* Clock bindings for Freescale i.MX6 SoloX
Required properties:
- compatible: Should be "fsl,imx6sx-ccm"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
- clocks: list of clock specifiers, must contain an entry for each required
entry in clock-names
- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sx-clock.h
for the full list of i.MX6 SoloX clock IDs.

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Status: Unstable - ABI compatibility may be broken in the future
Binding for Keystone gate control driver which uses PSC controller IP.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "ti,keystone,psc-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : parent clock phandle
- reg : psc control and domain address address space
- reg-names : psc control and domain registers
- domain-id : psc domain id needed to check the transition state register
Optional properties:
- clock-output-names : From common clock binding to override the
default output clock name
Example:
clkusb: clkusb {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk16>;
clock-output-names = "usb";
reg = <0x02350008 0xb00>, <0x02350000 0x400>;
reg-names = "control", "domain";
domain-id = <0>;
};

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Status: Unstable - ABI compatibility may be broken in the future
Binding for keystone PLLs. The main PLL IP typically has a multiplier,
a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
and PAPLL are controlled by the memory mapped register where as the Main
PLL is controlled by a PLL controller registers along with memory mapped
registers.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- #clock-cells : from common clock binding; shall be set to 0.
- compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
- clocks : parent clock phandle
- reg - pll control0 and pll multipler registers
- reg-names : control and multiplier. The multiplier is applicable only for
main pll clock
- fixed-postdiv : fixed post divider value. If absent, use clkod register bits
for postdiv
Example:
mainpllclk: mainpllclk@2310110 {
#clock-cells = <0>;
compatible = "ti,keystone,main-pll-clock";
clocks = <&refclksys>;
reg = <0x02620350 4>, <0x02310110 4>;
reg-names = "control", "multiplier";
fixed-postdiv = <2>;
};
papllclk: papllclk@2620358 {
#clock-cells = <0>;
compatible = "ti,keystone,pll-clock";
clocks = <&refclkpass>;
clock-output-names = "pa-pll-clk";
reg = <0x02620358 4>;
reg-names = "control";
};
Required properties:
- #clock-cells : from common clock binding; shall be set to 0.
- compatible : shall be "ti,keystone,pll-mux-clock"
- clocks : link phandles of parent clocks
- reg - pll mux register
- bit-shift : number of bits to shift the bit-mask
- bit-mask : arbitrary bitmask for programming the mux
Optional properties:
- clock-output-names : From common clock binding.
Example:
mainmuxclk: mainmuxclk@2310108 {
#clock-cells = <0>;
compatible = "ti,keystone,pll-mux-clock";
clocks = <&mainpllclk>, <&refclkmain>;
reg = <0x02310108 4>;
bit-shift = <23>;
bit-mask = <1>;
clock-output-names = "mainmuxclk";
};
Required properties:
- #clock-cells : from common clock binding; shall be set to 0.
- compatible : shall be "ti,keystone,pll-divider-clock"
- clocks : parent clock phandle
- reg - pll mux register
- bit-shift : number of bits to shift the bit-mask
- bit-mask : arbitrary bitmask for programming the divider
Optional properties:
- clock-output-names : From common clock binding.
Example:
gemtraceclk: gemtraceclk@2310120 {
#clock-cells = <0>;
compatible = "ti,keystone,pll-divider-clock";
clocks = <&mainmuxclk>;
reg = <0x02310120 4>;
bit-shift = <0>;
bit-mask = <8>;
clock-output-names = "gemtraceclk";
};

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AXM5516 clock driver bindings
-----------------------------
Required properties :
- compatible : shall contain "lsi,axm5516-clks"
- reg : shall contain base register location and length
- #clock-cells : shall contain 1
The consumer specifies the desired clock by having the clock ID in its "clocks"
phandle cell. See <dt-bindings/clock/lsi,axxia-clock.h> for the list of
supported clock IDs.
Example:
clks: clock-controller@2010020000 {
compatible = "lsi,axm5516-clks";
#clock-cells = <1>;
reg = <0x20 0x10020000 0 0x20000>;
};
serial0: uart@2010080000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x20 0x10080000 0 0x1000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks AXXIA_CLK_PER>;
clock-names = "apb_pclk";
};
};

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Binding for Maxim MAX77686 32k clock generator block
This is a part of device tree bindings of MAX77686 multi-function device.
More information can be found in bindings/mfd/max77686.txt file.
The MAX77686 contains three 32.768khz clock outputs that can be controlled
(gated/ungated) over I2C.
Following properties should be presend in main device node of the MFD chip.
Required properties:
- #clock-cells: from common clock binding; shall be set to 1.
Optional properties:
- clock-output-names: From common clock binding.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Following indices are allowed:
- 0: 32khz_ap clock,
- 1: 32khz_cp clock,
- 2: 32khz_pmic clock.
Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77686.h
header and can be used in device tree sources.
Example: Node of the MFD chip
max77686: max77686@09 {
compatible = "maxim,max77686";
interrupt-parent = <&wakeup_eint>;
interrupts = <26 0>;
reg = <0x09>;
#clock-cells = <1>;
/* ... */
};
Example: Clock consumer node
foo@0 {
compatible = "bar,foo";
/* ... */
clock-names = "my-clock";
clocks = <&max77686 MAX77686_CLK_PMIC>;
};

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Binding for Maxim MAX77802 32k clock generator block
This is a part of device tree bindings of MAX77802 multi-function device.
More information can be found in bindings/mfd/max77802.txt file.
The MAX77802 contains two 32.768khz clock outputs that can be controlled
(gated/ungated) over I2C.
Following properties should be present in main device node of the MFD chip.
Required properties:
- #clock-cells: From common clock binding; shall be set to 1.
Optional properties:
- clock-output-names: From common clock binding.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Following indices are allowed:
- 0: 32khz_ap clock,
- 1: 32khz_cp clock.
Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77802.h
header and can be used in device tree sources.
Example: Node of the MFD chip
max77802: max77802@09 {
compatible = "maxim,max77802";
interrupt-parent = <&wakeup_eint>;
interrupts = <26 0>;
reg = <0x09>;
#clock-cells = <1>;
/* ... */
};
Example: Clock consumer node
foo@0 {
compatible = "bar,foo";
/* ... */
clock-names = "my-clock";
clocks = <&max77802 MAX77802_CLK_32K_AP>;
};

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Device Tree Clock bindings for arch-moxart
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
MOXA ART SoCs allow to determine PLL output and APB frequencies
by reading registers holding multiplier and divisor information.
PLL:
Required properties:
- compatible : Must be "moxa,moxart-pll-clock"
- #clock-cells : Should be 0
- reg : Should contain registers location and length
- clocks : Should contain phandle + clock-specifier for the parent clock
Optional properties:
- clock-output-names : Should contain clock name
APB:
Required properties:
- compatible : Must be "moxa,moxart-apb-clock"
- #clock-cells : Should be 0
- reg : Should contain registers location and length
- clocks : Should contain phandle + clock-specifier for the parent clock
Optional properties:
- clock-output-names : Should contain clock name
For example:
clk_pll: clk_pll@98100000 {
compatible = "moxa,moxart-pll-clock";
#clock-cells = <0>;
reg = <0x98100000 0x34>;
};
clk_apb: clk_apb@98100000 {
compatible = "moxa,moxart-apb-clock";
#clock-cells = <0>;
reg = <0x98100000 0x34>;
clocks = <&clk_pll>;
};

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* Core Clock bindings for Marvell MVEBU SoCs
Marvell MVEBU SoCs usually allow to determine core clock frequencies by
reading the Sample-At-Reset (SAR) register. The core clock consumer should
specify the desired clock by having the clock ID in its "clocks" phandle cell.
The following is a list of provided IDs and clock names on Armada 370/XP:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = nbclk (L2 Cache clock)
3 = hclk (DRAM control clock)
4 = dramclk (DDR clock)
The following is a list of provided IDs and clock names on Armada 375:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = l2clk (L2 Cache clock)
3 = ddrclk (DDR clock)
The following is a list of provided IDs and clock names on Armada 380/385:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = l2clk (L2 Cache clock)
3 = ddrclk (DDR clock)
The following is a list of provided IDs and clock names on Kirkwood and Dove:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU0 clock)
2 = l2clk (L2 Cache clock derived from CPU0 clock)
3 = ddrclk (DDR controller clock derived from CPU0 clock)
The following is a list of provided IDs and clock names on Orion5x:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU0 clock)
2 = ddrclk (DDR controller clock derived from CPU0 clock)
Required properties:
- compatible : shall be one of the following:
"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
"marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
"marvell,dove-core-clock" - for Dove SoC core clocks
"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
- reg : shall be the register address of the Sample-At-Reset (SAR) register
- #clock-cells : from common clock binding; shall be set to 1
Optional properties:
- clock-output-names : from common clock binding; allows overwrite default clock
output names ("tclk", "cpuclk", "l2clk", "ddrclk")
Example:
core_clk: core-clocks@d0214 {
compatible = "marvell,dove-core-clock";
reg = <0xd0214 0x4>;
#clock-cells = <1>;
};
spi0: spi@10600 {
compatible = "marvell,orion-spi";
/* ... */
/* get tclk from core clock provider */
clocks = <&core_clk 0>;
};

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* Core Divider Clock bindings for Marvell MVEBU SoCs
The following is a list of provided IDs and clock names on Armada 370/XP:
0 = nand (NAND clock)
Required properties:
- compatible : must be "marvell,armada-370-corediv-clock",
"marvell,armada-375-corediv-clock",
"marvell,armada-380-corediv-clock",
- reg : must be the register address of Core Divider control register
- #clock-cells : from common clock binding; shall be set to 1
- clocks : must be set to the parent's phandle
Example:
corediv_clk: corediv-clocks@18740 {
compatible = "marvell,armada-370-corediv-clock";
reg = <0x18740 0xc>;
#clock-cells = <1>;
clocks = <&pll>;
};

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Device Tree Clock bindings for cpu clock of Marvell EBU platforms
Required properties:
- compatible : shall be one of the following:
"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
- reg : Address and length of the clock complex register set, followed
by address and length of the PMU DFS registers
- #clock-cells : should be set to 1.
- clocks : shall be the input parent clock phandle for the clock.
cpuclk: clock-complex@d0018700 {
#clock-cells = <1>;
compatible = "marvell,armada-xp-cpu-clock";
reg = <0xd0018700 0xA0>, <0x1c054 0x10>;
clocks = <&coreclk 1>;
}
cpu@0 {
compatible = "marvell,sheeva-v7";
reg = <0>;
clocks = <&cpuclk 0>;
};

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* Gated Clock bindings for Marvell EBU SoCs
Marvell Armada 370/375/380/385/XP, Dove and Kirkwood allow some
peripheral clocks to be gated to save some power. The clock consumer
should specify the desired clock by having the clock ID in its
"clocks" phandle cell. The clock ID is directly mapped to the
corresponding clock gating control bit in HW to ease manual clock
lookup in datasheet.
The following is a list of provided IDs for Armada 370:
ID Clock Peripheral
-----------------------------------
0 Audio AC97 Cntrl
1 pex0_en PCIe 0 Clock out
2 pex1_en PCIe 1 Clock out
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex0 PCIe Cntrl 0
9 pex1 PCIe Cntrl 1
15 sata0 SATA Host 0
17 sdio SDHCI Host
25 tdm Time Division Mplx
28 ddr DDR Cntrl
30 sata1 SATA Host 0
The following is a list of provided IDs for Armada 375:
ID Clock Peripheral
-----------------------------------
2 mu Management Unit
3 pp Packet Processor
4 ptp PTP
5 pex0 PCIe 0 Clock out
6 pex1 PCIe 1 Clock out
8 audio Audio Cntrl
11 nd_clk Nand Flash Cntrl
14 sata0_link SATA 0 Link
15 sata0_core SATA 0 Core
16 usb3 USB3 Host
17 sdio SDHCI Host
18 usb USB Host
19 gop Gigabit Ethernet MAC
20 sata1_link SATA 1 Link
21 sata1_core SATA 1 Core
22 xor0 XOR DMA 0
23 xor1 XOR DMA 0
24 copro Coprocessor
25 tdm Time Division Mplx
28 crypto0_enc Cryptographic Unit Port 0 Encryption
29 crypto0_core Cryptographic Unit Port 0 Core
30 crypto1_enc Cryptographic Unit Port 1 Encryption
31 crypto1_core Cryptographic Unit Port 1 Core
The following is a list of provided IDs for Armada 380/385:
ID Clock Peripheral
-----------------------------------
0 audio Audio
2 ge2 Gigabit Ethernet 2
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex1 PCIe 1
6 pex2 PCIe 2
7 pex3 PCIe 3
8 pex0 PCIe 0
9 usb3h0 USB3 Host 0
10 usb3h1 USB3 Host 1
11 usb3d USB3 Device
13 bm Buffer Management
14 crypto0z Cryptographic 0 Z
15 sata0 SATA 0
16 crypto1z Cryptographic 1 Z
17 sdio SDIO
18 usb2 USB 2
21 crypto1 Cryptographic 1
22 xor0 XOR 0
23 crypto0 Cryptographic 0
25 tdm Time Division Multiplexing
28 xor1 XOR 1
30 sata1 SATA 1
The following is a list of provided IDs for Armada XP:
ID Clock Peripheral
-----------------------------------
0 audio Audio Cntrl
1 ge3 Gigabit Ethernet 3
2 ge2 Gigabit Ethernet 2
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex0 PCIe Cntrl 0
6 pex1 PCIe Cntrl 1
7 pex2 PCIe Cntrl 2
8 pex3 PCIe Cntrl 3
13 bp
14 sata0lnk
15 sata0 SATA Host 0
16 lcd LCD Cntrl
17 sdio SDHCI Host
18 usb0 USB Host 0
19 usb1 USB Host 1
20 usb2 USB Host 2
22 xor0 XOR DMA 0
23 crypto CESA engine
25 tdm Time Division Mplx
28 xor1 XOR DMA 1
29 sata1lnk
30 sata1 SATA Host 0
The following is a list of provided IDs for Dove:
ID Clock Peripheral
-----------------------------------
0 usb0 USB Host 0
1 usb1 USB Host 1
2 ge Gigabit Ethernet
3 sata SATA Host
4 pex0 PCIe Cntrl 0
5 pex1 PCIe Cntrl 1
8 sdio0 SDHCI Host 0
9 sdio1 SDHCI Host 1
10 nand NAND Cntrl
11 camera Camera Cntrl
12 i2s0 I2S Cntrl 0
13 i2s1 I2S Cntrl 1
15 crypto CESA engine
21 ac97 AC97 Cntrl
22 pdma Peripheral DMA
23 xor0 XOR DMA 0
24 xor1 XOR DMA 1
30 gephy Gigabit Ethernel PHY
Note: gephy(30) is implemented as a parent clock of ge(2)
The following is a list of provided IDs for Kirkwood:
ID Clock Peripheral
-----------------------------------
0 ge0 Gigabit Ethernet 0
2 pex0 PCIe Cntrl 0
3 usb0 USB Host 0
4 sdio SDIO Cntrl
5 tsu Transp. Stream Unit
6 dunit SDRAM Cntrl
7 runit Runit
8 xor0 XOR DMA 0
9 audio I2S Cntrl 0
14 sata0 SATA Host 0
15 sata1 SATA Host 1
16 xor1 XOR DMA 1
17 crypto CESA engine
18 pex1 PCIe Cntrl 1
19 ge1 Gigabit Ethernet 1
20 tdm Time Division Mplx
Required properties:
- compatible : shall be one of the following:
"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
"marvell,dove-gating-clock" - for Dove SoC clock gating
"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
- reg : shall be the register address of the Clock Gating Control register
- #clock-cells : from common clock binding; shall be set to 1
Optional properties:
- clocks : default parent clock phandle (e.g. tclk)
Example:
gate_clk: clock-gating-control@d0038 {
compatible = "marvell,dove-gating-clock";
reg = <0xd0038 0x4>;
/* default parent clock is tclk */
clocks = <&core_clk 0>;
#clock-cells = <1>;
};
sdio0: sdio@92000 {
compatible = "marvell,dove-sdhci";
/* get clk gate bit 8 (sdio0) */
clocks = <&gate_clk 8>;
};

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TI-NSPIRE Clocks
Required properties:
- compatible: Valid compatible properties include:
"lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
"lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
"lsi,nspire-cx-clock" for the base clock in the CX model
"lsi,nspire-classic-clock" for the base clock in the older model
- reg: Physical base address of the controller and length of memory mapped
region.
Optional:
- clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
clock where it divides the rate from.
Example:
ahb_clk {
#clock-cells = <0>;
compatible = "lsi,nspire-cx-clock";
reg = <0x900B0000 0x4>;
clocks = <&base_clk>;
};

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NVIDIA Tegra114 Clock And Reset Controller
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
for muxing and gating Tegra's clocks, and setting their rates.
Required properties :
- compatible : Should be "nvidia,tegra114-car"
- reg : Should contain CAR registers location and length
- clocks : Should contain phandle and clock specifiers for two clocks:
the 32 KHz "32k_in", and the board-specific oscillator "osc".
- #clock-cells : Should be 1.
In clock consumers, this cell represents the clock ID exposed by the
CAR. The assignments may be found in header file
<dt-bindings/clock/tegra114-car.h>.
- #reset-cells : Should be 1.
In clock consumers, this cell represents the bit number in the CAR's
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
Example SoC include file:
/ {
tegra_car: clock {
compatible = "nvidia,tegra114-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
usb@c5004000 {
clocks = <&tegra_car TEGRA114_CLK_USB2>;
};
};
Example board file:
/ {
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
osc: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <12000000>;
};
clk_32k: clock@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
&tegra_car {
clocks = <&clk_32k> <&osc>;
};
};

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NVIDIA Tegra124 Clock And Reset Controller
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
for muxing and gating Tegra's clocks, and setting their rates.
Required properties :
- compatible : Should be "nvidia,tegra124-car"
- reg : Should contain CAR registers location and length
- clocks : Should contain phandle and clock specifiers for two clocks:
the 32 KHz "32k_in", and the board-specific oscillator "osc".
- #clock-cells : Should be 1.
In clock consumers, this cell represents the clock ID exposed by the
CAR. The assignments may be found in header file
<dt-bindings/clock/tegra124-car.h>.
- #reset-cells : Should be 1.
In clock consumers, this cell represents the bit number in the CAR's
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
Example SoC include file:
/ {
tegra_car: clock {
compatible = "nvidia,tegra124-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
usb@c5004000 {
clocks = <&tegra_car TEGRA124_CLK_USB2>;
};
};
Example board file:
/ {
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
osc: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <112400000>;
};
clk_32k: clock@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
&tegra_car {
clocks = <&clk_32k> <&osc>;
};
};

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NVIDIA Tegra20 Clock And Reset Controller
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
for muxing and gating Tegra's clocks, and setting their rates.
Required properties :
- compatible : Should be "nvidia,tegra20-car"
- reg : Should contain CAR registers location and length
- clocks : Should contain phandle and clock specifiers for two clocks:
the 32 KHz "32k_in", and the board-specific oscillator "osc".
- #clock-cells : Should be 1.
In clock consumers, this cell represents the clock ID exposed by the
CAR. The assignments may be found in header file
<dt-bindings/clock/tegra20-car.h>.
- #reset-cells : Should be 1.
In clock consumers, this cell represents the bit number in the CAR's
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
Example SoC include file:
/ {
tegra_car: clock {
compatible = "nvidia,tegra20-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
usb@c5004000 {
clocks = <&tegra_car TEGRA20_CLK_USB2>;
};
};
Example board file:
/ {
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
osc: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <12000000>;
};
clk_32k: clock@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
&tegra_car {
clocks = <&clk_32k> <&osc>;
};
};

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NVIDIA Tegra30 Clock And Reset Controller
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
for muxing and gating Tegra's clocks, and setting their rates.
Required properties :
- compatible : Should be "nvidia,tegra30-car"
- reg : Should contain CAR registers location and length
- clocks : Should contain phandle and clock specifiers for two clocks:
the 32 KHz "32k_in", and the board-specific oscillator "osc".
- #clock-cells : Should be 1.
In clock consumers, this cell represents the clock ID exposed by the
CAR. The assignments may be found in header file
<dt-bindings/clock/tegra30-car.h>.
- #reset-cells : Should be 1.
In clock consumers, this cell represents the bit number in the CAR's
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
Example SoC include file:
/ {
tegra_car: clock {
compatible = "nvidia,tegra30-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
usb@c5004000 {
clocks = <&tegra_car TEGRA30_CLK_USB2>;
};
};
Example board file:
/ {
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
osc: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <12000000>;
};
clk_32k: clock@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
&tegra_car {
clocks = <&clk_32k> <&osc>;
};
};

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* Clock bindings for CSR SiRFprimaII
Required properties:
- compatible: Should be "sirf,prima2-clkc"
- reg: Address and length of the register set
- interrupts: Should contain clock controller interrupt
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of prima2
clocks and IDs.
Clock ID
---------------------------
rtc 0
osc 1
pll1 2
pll2 3
pll3 4
mem 5
sys 6
security 7
dsp 8
gps 9
mf 10
io 11
cpu 12
uart0 13
uart1 14
uart2 15
tsc 16
i2c0 17
i2c1 18
spi0 19
spi1 20
pwmc 21
efuse 22
pulse 23
dmac0 24
dmac1 25
nand 26
audio 27
usp0 28
usp1 29
usp2 30
vip 31
gfx 32
mm 33
lcd 34
vpp 35
mmc01 36
mmc23 37
mmc45 38
usbpll 39
usb0 40
usb1 41
Examples:
clks: clock-controller@88000000 {
compatible = "sirf,prima2-clkc";
reg = <0x88000000 0x1000>;
interrupts = <3>;
#clock-cells = <1>;
};
i2c0: i2c@b00e0000 {
cell-index = <0>;
compatible = "sirf,prima2-i2c";
reg = <0xb00e0000 0x10000>;
interrupts = <24>;
clocks = <&clks 17>;
};

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* Clock bindings for Marvell PXA chips
Required properties:
- compatible: Should be "marvell,pxa-clocks"
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell (see include/.../pxa-clock.h).
Examples:
pxa2xx_clks: pxa2xx_clks@41300004 {
compatible = "marvell,pxa-clocks";
#clock-cells = <1>;
status = "okay";
};

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Qualcomm Global Clock & Reset Controller Binding
------------------------------------------------
Required properties :
- compatible : shall contain only one of the following:
"qcom,gcc-apq8064"
"qcom,gcc-apq8084"
"qcom,gcc-ipq8064"
"qcom,gcc-msm8660"
"qcom,gcc-msm8960"
"qcom,gcc-msm8974"
"qcom,gcc-msm8974pro"
"qcom,gcc-msm8974pro-ac"
- reg : shall contain base register location and length
- #clock-cells : shall contain 1
- #reset-cells : shall contain 1
Example:
clock-controller@900000 {
compatible = "qcom,gcc-msm8960";
reg = <0x900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

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Qualcomm Multimedia Clock & Reset Controller Binding
----------------------------------------------------
Required properties :
- compatible : shall contain only one of the following:
"qcom,mmcc-apq8064"
"qcom,mmcc-apq8084"
"qcom,mmcc-msm8660"
"qcom,mmcc-msm8960"
"qcom,mmcc-msm8974"
- reg : shall contain base register location and length
- #clock-cells : shall contain 1
- #reset-cells : shall contain 1
Example:
clock-controller@4000000 {
compatible = "qcom,mmcc-msm8960";
reg = <0x4000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

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* Clock Block on Freescale CoreNet Platforms
Freescale CoreNet chips take primary clocking input from the external
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
multiple phase locked loops (PLL) to create a variety of frequencies
which can then be passed to a variety of internal logic, including
cores and peripheral IP blocks.
Please refer to the Reference Manual for details.
All references to "1.0" and "2.0" refer to the QorIQ chassis version to
which the chip complies.
Chassis Version Example Chips
--------------- -------------
1.0 p4080, p5020, p5040
2.0 t4240, b4860, t1040
1. Clock Block Binding
Required properties:
- compatible: Should contain a specific clock block compatible string
and a single chassis clock compatible string.
Clock block strings include, but not limited to, one of the:
* "fsl,p2041-clockgen"
* "fsl,p3041-clockgen"
* "fsl,p4080-clockgen"
* "fsl,p5020-clockgen"
* "fsl,p5040-clockgen"
* "fsl,t4240-clockgen"
* "fsl,b4420-clockgen"
* "fsl,b4860-clockgen"
Chassis clock strings include:
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
- reg: Describes the address of the device's resources within the
address space defined by its parent bus, and resource zero
represents the clock register set
- clock-frequency: Input system clock frequency
Recommended properties:
- ranges: Allows valid translation between child's address space and
parent's. Must be present if the device has sub-nodes.
- #address-cells: Specifies the number of cells used to represent
physical base addresses. Must be present if the device has
sub-nodes and set to 1 if present
- #size-cells: Specifies the number of cells used to represent
the size of an address. Must be present if the device has
sub-nodes and set to 1 if present
2. Clock Provider/Consumer Binding
Most of the bindings are from the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : Should include one of the following:
* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
It takes parent's clock-frequency as its clock.
* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
It takes parent's clock-frequency as its clock.
- #clock-cells: From common clock binding. The number of cells in a
clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
clock-specifier cell may take the following values:
* 0 - equal to the PLL frequency
* 1 - equal to the PLL frequency divided by 2
* 2 - equal to the PLL frequency divided by 4
Recommended properties:
- clocks: Should be the phandle of input parent clock
- clock-names: From common clock binding, indicates the clock name
- clock-output-names: From common clock binding, indicates the names of
output clocks
- reg: Should be the offset and length of clock block base address.
The length should be 4.
Example for clock block and clock provider:
/ {
clockgen: global-utilities@e1000 {
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
ranges = <0x0 0xe1000 0x1000>;
clock-frequency = <133333333>;
reg = <0xe1000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-1.0";
clock-output-names = "sysclk";
};
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2";
};
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux0";
};
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux1";
};
};
}
Example for clock consumer:
/ {
cpu0: PowerPC,e5500@0 {
...
clocks = <&mux0>;
...
};
}

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* Renesas CPG DIV6 Clock
The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
Generator (CPG). They clock input is divided by a configurable factor from 1
to 64.
Required Properties:
- compatible: Must be one of the following
- "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
- "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
- "renesas,cpg-div6-clock" for generic DIV6 clocks
- reg: Base address and length of the memory resource used by the DIV6 clock
- clocks: Reference to the parent clock
- #clock-cells: Must be 0
- clock-output-names: The name of the clock as a free-form string
Example
-------
sd2_clk: sd2_clk@e6150078 {
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150078 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "sd2";
};

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* Renesas CPG Module Stop (MSTP) Clocks
The CPG can gate SoC device clocks. The gates are organized in groups of up to
32 gates.
This device tree binding describes a single 32 gate clocks group per node.
Clocks are referenced by user nodes by the MSTP node phandle and the clock
index in the group, from 0 to 31.
Required Properties:
- compatible: Must be one of the following
- "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
- "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
- "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
- "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
- "renesas,cpg-mstp-clock" for generic MSTP gate clocks
- reg: Base address and length of the I/O mapped registers used by the MSTP
clocks. The first register is the clock control register and is mandatory.
The second register is the clock status register and is optional when not
implemented in hardware.
- clocks: Reference to the parent clocks, one per output clock. The parents
must appear in the same order as the output clocks.
- #clock-cells: Must be 1
- clock-output-names: The name of the clocks as free-form strings
- renesas,clock-indices: Indices of the gate clocks into the group (0 to 31)
The clocks, clock-output-names and renesas,clock-indices properties contain one
entry per gate clock. The MSTP groups are sparsely populated. Unimplemented
gate clocks must not be declared.
Example
-------
#include <dt-bindings/clock/r8a7790-clock.h>
mstp3_clks: mstp3_clks@e615013c {
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
<&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
<&mmc0_clk>;
#clock-cells = <1>;
clock-output-names =
"tpu0", "mmcif1", "sdhi3", "sdhi2",
"sdhi1", "sdhi0", "mmcif0";
clock-indices = <
R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
R8A7790_CLK_MMCIF0
>;
};

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These bindings should be considered EXPERIMENTAL for now.
* Renesas R8A7740 Clock Pulse Generator (CPG)
The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs
and several fixed ratio and variable ratio dividers.
Required Properties:
- compatible: Must be "renesas,r8a7740-cpg-clocks"
- reg: Base address and length of the memory resource used by the CPG
- clocks: Reference to the three parent clocks
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are
"system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b",
"m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp".
- renesas,mode: board-specific settings of the MD_CK* bits
Example
-------
cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7740-cpg-clocks";
reg = <0xe6150000 0x10000>;
clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
#clock-cells = <1>;
clock-output-names = "system", "pllc0", "pllc1",
"pllc2", "r",
"usb24s",
"i", "zg", "b", "m1", "hp",
"hpp", "usbp", "s", "zb", "m3",
"cp";
};
&cpg_clocks {
renesas,mode = <0x05>;
};

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* Renesas R8A7779 Clock Pulse Generator (CPG)
The CPG generates core clocks for the R8A7779. It includes one PLL and
several fixed ratio dividers
Required Properties:
- compatible: Must be "renesas,r8a7779-cpg-clocks"
- reg: Base address and length of the memory resource used by the CPG
- clocks: Reference to the parent clock
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are "plla",
"z", "zs", "s", "s1", "p", "b", "out".
Example
-------
cpg_clocks: cpg_clocks@ffc80000 {
compatible = "renesas,r8a7779-cpg-clocks";
reg = <0 0xffc80000 0 0x30>;
clocks = <&extal_clk>;
#clock-cells = <1>;
clock-output-names = "plla", "z", "zs", "s", "s1", "p",
"b", "out";
};

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* Renesas R-Car Gen2 Clock Pulse Generator (CPG)
The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
and several fixed ratio dividers.
Required Properties:
- compatible: Must be one of
- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
- "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
- "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
- reg: Base address and length of the memory resource used by the CPG
- clocks: Reference to the parent clock
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are "main",
"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1" and "z"
Example
-------
cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7790-cpg-clocks",
"renesas,rcar-gen2-cpg-clocks";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>;
#clock-cells = <1>;
clock-output-names = "main", "pll0, "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "sd1", "z";
};

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* Renesas RZ Clock Pulse Generator (CPG)
The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
CPU and GPU clocks, and several fixed ratio dividers.
Required Properties:
- compatible: Must be one of
- "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
- "renesas,rz-cpg-clocks" for the generic RZ CPG
- reg: Base address and length of the memory resource used by the CPG
- clocks: References to possible parent clocks. Order must match clock modes
in the datasheet. For the r7s72100, this is extal, usb_x1.
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are "pll",
"i", and "g"
Example
-------
cpg_clocks: cpg_clocks@fcfe0000 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-cpg-clocks",
"renesas,rz-cpg-clocks";
reg = <0xfcfe0000 0x18>;
clocks = <&extal_clk>, <&usb_x1_clk>;
clock-output-names = "pll", "i", "g";
};

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* Rockchip RK3188/RK3066 Clock and Reset Unit
The RK3188/RK3066 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.
Required Properties:
- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
"rockchip,rk3066a-cru"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
- #reset-cells: should be 1.
Optional Properties:
- rockchip,grf: phandle to the syscon managing the "general register files"
If missing pll rates are not changable, due to the missing pll lock status.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
Similar macros exist for the reset sources in these files.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xin24m" - crystal input - required,
- "xin32k" - rtc clock - optional,
- "xin27m" - 27mhz crystal input on rk3066 - optional,
- "ext_hsadc" - external HSADC clock - optional,
- "ext_cif0" - external camera clock - optional,
- "ext_rmii" - external RMII clock - optional,
- "ext_jtag" - externalJTAG clock - optional
Example: Clock controller node:
cru: cru@20000000 {
compatible = "rockchip,rk3188-cru";
reg = <0x20000000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller:
uart0: serial@10124000 {
compatible = "snps,dw-apb-uart";
reg = <0x10124000 0x400>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&cru SCLK_UART0>;
};

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* Rockchip RK3288 Clock and Reset Unit
The RK3288 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.
Required Properties:
- compatible: should be "rockchip,rk3288-cru"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
- #reset-cells: should be 1.
Optional Properties:
- rockchip,grf: phandle to the syscon managing the "general register files"
If missing pll rates are not changable, due to the missing pll lock status.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
used in device tree sources. Similar macros exist for the reset sources in
these files.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xin24m" - crystal input - required,
- "xin32k" - rtc clock - optional,
- "ext_i2s" - external I2S clock - optional,
- "ext_hsadc" - external HSADC clock - optional,
- "ext_edp_24m" - external display port clock - optional,
- "ext_vip" - external VIP clock - optional,
- "ext_isp" - external ISP clock - optional,
- "ext_jtag" - external JTAG clock - optional
Example: Clock controller node:
cru: cru@20000000 {
compatible = "rockchip,rk3188-cru";
reg = <0x20000000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller:
uart0: serial@10124000 {
compatible = "snps,dw-apb-uart";
reg = <0x10124000 0x400>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&cru SCLK_UART0>;
};

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Device Tree Clock bindings for arch-rockchip
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
== Gate clocks ==
These bindings are deprecated!
Please use the soc specific CRU bindings instead.
The gate registers form a continuos block which makes the dt node
structure a matter of taste, as either all gates can be put into
one gate clock spanning all registers or they can be divided into
the 10 individual gates containing 16 clocks each.
The code supports both approaches.
Required properties:
- compatible : "rockchip,rk2928-gate-clk"
- reg : shall be the control register address(es) for the clock.
- #clock-cells : from common clock binding; shall be set to 1
- clock-output-names : the corresponding gate names that the clock controls
- clocks : should contain the parent clock for each individual gate,
therefore the number of clocks elements should match the number of
clock-output-names
Example using multiple gate clocks:
clk_gates0: gate-clk@200000d0 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000d0 0x4>;
clocks = <&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"gate_core_periph", "gate_cpu_gpll",
"gate_ddrphy", "gate_aclk_cpu",
"gate_hclk_cpu", "gate_pclk_cpu",
"gate_atclk_cpu", "gate_i2s0",
"gate_i2s0_frac", "gate_i2s1",
"gate_i2s1_frac", "gate_i2s2",
"gate_i2s2_frac", "gate_spdif",
"gate_spdif_frac", "gate_testclk";
#clock-cells = <1>;
};
clk_gates1: gate-clk@200000d4 {
compatible = "rockchip,rk2928-gate-clk";
reg = <0x200000d4 0x4>;
clocks = <&xin24m>, <&xin24m>,
<&xin24m>, <&dummy>,
<&dummy>, <&xin24m>,
<&xin24m>, <&dummy>,
<&xin24m>, <&dummy>,
<&xin24m>, <&dummy>,
<&xin24m>, <&dummy>,
<&xin24m>, <&dummy>;
clock-output-names =
"gate_timer0", "gate_timer1",
"gate_timer2", "gate_jtag",
"gate_aclk_lcdc1_src", "gate_otgphy0",
"gate_otgphy1", "gate_ddr_gpll",
"gate_uart0", "gate_frac_uart0",
"gate_uart1", "gate_frac_uart1",
"gate_uart2", "gate_frac_uart2",
"gate_uart3", "gate_frac_uart3";
#clock-cells = <1>;
};

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* Samsung S3C2410 Clock Controller
The S3C2410 clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to the s3c2410,
s3c2440 and s3c2442 SoCs in the s3c24x family.
Required Properties:
- compatible: should be one of the following.
- "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC.
- "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC.
- "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular SoC.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s3c2410.h header and can be used in device
tree sources.
External clocks:
The xti clock used as input for the plls is generated outside the SoC. It is
expected that is are defined using standard clock bindings with a
clock-output-names value of "xti".
Example: Clock controller node:
clocks: clock-controller@4c000000 {
compatible = "samsung,s3c2410-clock";
reg = <0x4c000000 0x20>;
#clock-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
serial@50004000 {
compatible = "samsung,s3c2440-uart";
reg = <0x50004000 0x4000>;
interrupts = <1 23 3 4>, <1 23 4 4>;
clock-names = "uart", "clk_uart_baud2";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>;
status = "disabled";
};

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* Samsung S3C2412 Clock Controller
The S3C2412 clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to the s3c2412
and s3c2413 SoCs in the s3c24x family.
Required Properties:
- compatible: should be "samsung,s3c2412-clock"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular SoC.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s3c2412.h header and can be used in device
tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xti" - crystal input - required,
- "ext" - external clock source - optional,
Example: Clock controller node:
clocks: clock-controller@4c000000 {
compatible = "samsung,s3c2412-clock";
reg = <0x4c000000 0x20>;
#clock-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
serial@50004000 {
compatible = "samsung,s3c2412-uart";
reg = <0x50004000 0x4000>;
interrupts = <1 23 3 4>, <1 23 4 4>;
clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
status = "disabled";
};

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* Samsung S3C2443 Clock Controller
The S3C2443 clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to all SoCs in
the s3c24x family starting with the s3c2443.
Required Properties:
- compatible: should be one of the following.
- "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC.
- "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC.
- "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular SoC.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s3c2443.h header and can be used in device
tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xti" - crystal input - required,
- "ext" - external clock source - optional,
- "ext_i2s" - external I2S clock - optional,
- "ext_uart" - external uart clock - optional,
Example: Clock controller node:
clocks: clock-controller@4c000000 {
compatible = "samsung,s3c2416-clock";
reg = <0x4c000000 0x40>;
#clock-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
serial@50004000 {
compatible = "samsung,s3c2440-uart";
reg = <0x50004000 0x4000>;
interrupts = <1 23 3 4>, <1 23 4 4>;
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
status = "disabled";
};

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* Samsung S3C64xx Clock Controller
The S3C64xx clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to all SoCs in
the S3C64xx family.
Required Properties:
- compatible: should be one of the following.
- "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.
- "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular S3C64xx SoC and this is specified where applicable.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device
tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "fin_pll" - PLL input clock (xtal/extclk) - required,
- "xusbxti" - USB xtal - required,
- "iiscdclk0" - I2S0 codec clock - optional,
- "iiscdclk1" - I2S1 codec clock - optional,
- "iiscdclk2" - I2S2 codec clock - optional,
- "pcmcdclk0" - PCM0 codec clock - optional,
- "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.
Example: Clock controller node:
clock: clock-controller@7e00f000 {
compatible = "samsung,s3c6410-clock";
reg = <0x7e00f000 0x1000>;
#clock-cells = <1>;
};
Example: Required external clocks:
fin_pll: clock-fin-pll {
compatible = "fixed-clock";
clock-output-names = "fin_pll";
clock-frequency = <12000000>;
#clock-cells = <0>;
};
xusbxti: clock-xusbxti {
compatible = "fixed-clock";
clock-output-names = "xusbxti";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
uart0: serial@7f005000 {
compatible = "samsung,s3c6400-uart";
reg = <0x7f005000 0x100>;
interrupt-parent = <&vic1>;
interrupts = <5>;
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
<&clock SCLK_UART>;
status = "disabled";
};

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* Samsung S5P6442/S5PC110/S5PV210 Clock Controller
Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
controller, which generates and supplies clock to various controllers
within the SoC.
Required Properties:
- compatible: should be one of following:
- "samsung,s5pv210-clock" : for clock controller of Samsung
S5PC110/S5PV210 SoCs,
- "samsung,s5p6442-clock" : for clock controller of Samsung
S5P6442 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xxti": external crystal oscillator connected to XXTI and XXTO pins of
the SoC,
- "xusbxti": external crystal oscillator connected to XUSBXTI and XUSBXTO
pins of the SoC,
A subset of above clocks available on given board shall be specified in
board device tree, including the system base clock, as selected by XOM[0]
pin of the SoC. Refer to generic fixed rate clock bindings
documentation[1] for more information how to specify these clocks.
[1] Documentation/devicetree/bindings/clock/fixed-clock.txt
Example: Clock controller node:
clock: clock-controller@7e00f000 {
compatible = "samsung,s5pv210-clock";
reg = <0x7e00f000 0x1000>;
#clock-cells = <1>;
};
Example: Required external clocks:
xxti: clock-xxti {
compatible = "fixed-clock";
clock-output-names = "xxti";
clock-frequency = <24000000>;
#clock-cells = <0>;
};
xusbxti: clock-xusbxti {
compatible = "fixed-clock";
clock-output-names = "xusbxti";
clock-frequency = <24000000>;
#clock-cells = <0>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
uart0: serial@e2900000 {
compatible = "samsung,s5pv210-uart";
reg = <0xe2900000 0x400>;
interrupt-parent = <&vic1>;
interrupts = <10>;
clock-names = "uart", "clk_uart_baud0",
"clk_uart_baud1";
clocks = <&clocks UART0>, <&clocks UART0>,
<&clocks SCLK_UART0>;
status = "disabled";
};

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Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
Reference
[1] Si5351A/B/C Data Sheet
http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
The Si5351a/b/c are programmable i2c clock generators with up to 8 output
clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
3 output clocks are accessible. The internal structure of the clock
generators can be found in [1].
==I2C device node==
Required properties:
- compatible: shall be one of "silabs,si5351{a,a-msop,b,c}".
- reg: i2c device address, shall be 0x60 or 0x61.
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: from common clock binding; list of parent clock
handles, shall be xtal reference clock or xtal and clkin for
si5351c only.
- #address-cells: shall be set to 1.
- #size-cells: shall be set to 0.
Optional properties:
- silabs,pll-source: pair of (number, source) for each pll. Allows
to overwrite clock source of pll A (number=0) or B (number=1).
==Child nodes==
Each of the clock outputs can be overwritten individually by
using a child node to the I2C device node. If a child node for a clock
output is not set, the eeprom configuration is not overwritten.
Required child node properties:
- reg: number of clock output.
Optional child node properties:
- silabs,clock-source: source clock of the output divider stage N, shall be
0 = multisynth N
1 = multisynth 0 for output clocks 0-3, else multisynth4
2 = xtal
3 = clkin (si5351c only)
- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}.
- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
divider.
- silabs,pll-master: boolean, multisynth can change pll frequency.
- silabs,disable-state : clock output disable state, shall be
0 = clock output is driven LOW when disabled
1 = clock output is driven HIGH when disabled
2 = clock output is FLOATING (HIGH-Z) when disabled
3 = clock output is NEVER disabled
==Example==
/* 25MHz reference crystal */
ref25: ref25M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
i2c-master-node {
/* Si5351a msop10 i2c clock generator */
si5351a: clock-generator@60 {
compatible = "silabs,si5351a-msop";
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
/* connect xtal input to 25MHz reference */
clocks = <&ref25>;
/* connect xtal input as source of pll0 and pll1 */
silabs,pll-source = <0 0>, <1 0>;
/*
* overwrite clkout0 configuration with:
* - 8mA output drive strength
* - pll0 as clock source of multisynth0
* - multisynth0 as clock source of output divider
* - multisynth0 can change pll0
* - set initial clock frequency of 74.25MHz
*/
clkout0 {
reg = <0>;
silabs,drive-strength = <8>;
silabs,multisynth-source = <0>;
silabs,clock-source = <0>;
silabs,pll-master;
clock-frequency = <74250000>;
};
/*
* overwrite clkout1 configuration with:
* - 4mA output drive strength
* - pll1 as clock source of multisynth1
* - multisynth1 as clock source of output divider
* - multisynth1 can change pll1
*/
clkout1 {
reg = <1>;
silabs,drive-strength = <4>;
silabs,multisynth-source = <1>;
silabs,clock-source = <0>;
pll-master;
};
/*
* overwrite clkout2 configuration with:
* - xtal as clock source of output divider
*/
clkout2 {
reg = <2>;
silabs,clock-source = <2>;
};
};
};

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Binding for Silicon Labs 570, 571, 598 and 599 programmable
I2C clock generators.
Reference
This binding uses the common clock binding[1]. Details about the devices can be
found in the data sheets[2][3].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Si570/571 Data Sheet
http://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf
[3] Si598/599 Data Sheet
http://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf
Required properties:
- compatible: Shall be one of "silabs,si570", "silabs,si571",
"silabs,si598", "silabs,si599"
- reg: I2C device address.
- #clock-cells: From common clock bindings: Shall be 0.
- factory-fout: Factory set default frequency. This frequency is part specific.
The correct frequency for the part used has to be provided in
order to generate the correct output frequencies. For more
details, please refer to the data sheet.
- temperature-stability: Temperature stability of the device in PPM. Should be
one of: 7, 20, 50 or 100.
Optional properties:
- clock-output-names: From common clock bindings. Recommended to be "si570".
- clock-frequency: Output frequency to generate. This defines the output
frequency set during boot. It can be reprogrammed during
runtime through the common clock framework.
Example:
si570: clock-generator@5d {
#clock-cells = <0>;
compatible = "silabs,si570";
temperature-stability = <50>;
reg = <0x5d>;
factory-fout = <156250000>;
};

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ST Microelectronics Nomadik SRC System Reset and Control
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The Nomadik SRC controller is responsible of controlling chrystals,
PLLs and clock gates.
Required properties for the SRC node:
- compatible: must be "stericsson,nomadik-src"
- reg: must contain the SRC register base and size
Optional properties for the SRC node:
- disable-sxtalo: if present this will disable the SXTALO
i.e. the driver output for the slow 32kHz chrystal, if the
board has its own circuitry for providing this oscillator
- disable-mxtal: if present this will disable the MXTALO,
i.e. the driver output for the main (~19.2 MHz) chrystal,
if the board has its own circuitry for providing this
oscillator
PLL nodes: these nodes represent the two PLLs on the system,
which should both have the main chrystal, represented as a
fixed frequency clock, as parent.
Required properties for the two PLL nodes:
- compatible: must be "st,nomadik-pll-clock"
- clock-cells: must be 0
- clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
- clocks: this clock will have main chrystal as parent
HCLK nodes: these represent the clock gates on individual
lines from the HCLK clock tree and the gate for individual
lines from the PCLK clock tree.
Requires properties for the HCLK nodes:
- compatible: must be "st,nomadik-hclk-clock"
- clock-cells: must be 0
- clock-id: must be the clock ID from 0 to 63 according to
this table:
0: HCLKDMA0
1: HCLKSMC
2: HCLKSDRAM
3: HCLKDMA1
4: HCLKCLCD
5: PCLKIRDA
6: PCLKSSP
7: PCLKUART0
8: PCLKSDI
9: PCLKI2C0
10: PCLKI2C1
11: PCLKUART1
12: PCLMSP0
13: HCLKUSB
14: HCLKDIF
15: HCLKSAA
16: HCLKSVA
17: PCLKHSI
18: PCLKXTI
19: PCLKUART2
20: PCLKMSP1
21: PCLKMSP2
22: PCLKOWM
23: HCLKHPI
24: PCLKSKE
25: PCLKHSEM
26: HCLK3D
27: HCLKHASH
28: HCLKCRYP
29: PCLKMSHC
30: HCLKUSBM
31: HCLKRNG
(32, 33, 34, 35 RESERVED)
36: CLDCLK
37: IRDACLK
38: SSPICLK
39: UART0CLK
40: SDICLK
41: I2C0CLK
42: I2C1CLK
43: UART1CLK
44: MSPCLK0
45: USBCLK
46: DIFCLK
47: IPI2CCLK
48: IPBMCCLK
49: HSICLKRX
50: HSICLKTX
51: UART2CLK
52: MSPCLK1
53: MSPCLK2
54: OWMCLK
(55 RESERVED)
56: SKECLK
(57 RESERVED)
58: 3DCLK
59: PCLKMSP3
60: MSPCLK3
61: MSHCCLK
62: USBMCLK
63: RNGCCLK

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Binding for a ST divider and multiplexer clock driver.
This binding uses the common clock binding[1].
Base address is located to the parent node. See clock binding[2]
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
Required properties:
- compatible : shall be:
"st,clkgena-divmux-c65-hs", "st,clkgena-divmux"
"st,clkgena-divmux-c65-ls", "st,clkgena-divmux"
"st,clkgena-divmux-c32-odf0", "st,clkgena-divmux"
"st,clkgena-divmux-c32-odf1", "st,clkgena-divmux"
"st,clkgena-divmux-c32-odf2", "st,clkgena-divmux"
"st,clkgena-divmux-c32-odf3", "st,clkgena-divmux"
- #clock-cells : From common clock binding; shall be set to 1.
- clocks : From common clock binding
- clock-output-names : From common clock binding.
Example:
clockgen-a@fd345000 {
reg = <0xfd345000 0xb50>;
clk_m_a1_div1: clk-m-a1-div1 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf1",
"st,clkgena-divmux";
clocks = <&clk_m_a1_osc_prediv>,
<&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
<&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
clock-output-names = "clk-m-rx-icn-ts",
"clk-m-rx-icn-vdp-0",
"", /* unused */
"clk-m-prv-t1-bus",
"clk-m-icn-reg-12",
"clk-m-icn-reg-10",
"", /* unused */
"clk-m-icn-st231";
};
};

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Binding for a ST multiplexed clock driver.
This binding supports only simple indexed multiplexers, it does not
support table based parent index to hardware value translations.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be:
"st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"
"st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"
"st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"
"st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"
"st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
"st,stih415-clkgen-a9-mux", "st,clkgen-mux"
"st,stih416-clkgen-a9-mux", "st,clkgen-mux"
"st,stih407-clkgen-a9-mux", "st,clkgen-mux"
- #clock-cells : from common clock binding; shall be set to 0.
- reg : A Base address and length of the register set.
- clocks : from common clock binding
Example:
clk_m_hva: clk-m-hva@fd690868 {
#clock-cells = <0>;
compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
reg = <0xfd690868 4>;
clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
};

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Binding for a ST pll clock driver.
This binding uses the common clock binding[1].
Base address is located to the parent node. See clock binding[2]
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
Required properties:
- compatible : shall be:
"st,clkgena-prediv-c65", "st,clkgena-prediv"
"st,clkgena-prediv-c32", "st,clkgena-prediv"
"st,clkgena-plls-c65"
"st,plls-c32-a1x-0", "st,clkgen-plls-c32"
"st,plls-c32-a1x-1", "st,clkgen-plls-c32"
"st,stih415-plls-c32-a9", "st,clkgen-plls-c32"
"st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
"st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
- #clock-cells : From common clock binding; shall be set to 1.
- clocks : From common clock binding
- clock-output-names : From common clock binding.
Example:
clockgen-a@fee62000 {
reg = <0xfee62000 0xb48>;
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a0-pll0-hs",
"clk-s-a0-pll0-ls",
"clk-s-a0-pll1";
};
};

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Binding for a ST pre-divider clock driver.
This binding uses the common clock binding[1].
Base address is located to the parent node. See clock binding[2]
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
Required properties:
- compatible : shall be:
"st,clkgena-prediv-c65", "st,clkgena-prediv"
"st,clkgena-prediv-c32", "st,clkgena-prediv"
- #clock-cells : From common clock binding; shall be set to 0.
- clocks : From common clock binding
- clock-output-names : From common clock binding.
Example:
clockgen-a@fd345000 {
reg = <0xfd345000 0xb50>;
clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c32",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a2-osc-prediv";
};
};

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Binding for a type of STMicroelectronics clock crossbar (VCC).
The crossbar can take up to 4 input clocks and control up to 16
output clocks. Not all inputs or outputs have to be in use in a
particular instantiation. Each output can be individually enabled,
select any of the input clocks and apply a divide (by 1,2,4 or 8) to
that selected clock.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be:
"st,stih416-clkgenc", "st,vcc"
"st,stih416-clkgenf", "st,vcc"
- #clock-cells : from common clock binding; shall be set to 1.
- reg : A Base address and length of the register set.
- clocks : from common clock binding
- clock-output-names : From common clock binding. The block has 16
clock outputs but not all of them in a specific instance
have to be used in the SoC. If a clock name is left as
an empty string then no clock will be created for the
output associated with that string index. If fewer than
16 strings are provided then no clocks will be created
for the remaining outputs.
Example:
clockgen_c_vcc: clockgen-c-vcc@0xfe8308ac {
#clock-cells = <1>;
compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
reg = <0xfe8308ac 12>;
clocks = <&clk_s_vcc_hd>,
<&clockgen_c 1>,
<&clk_s_tmds_fromphy>,
<&clockgen_c 2>;
clock-output-names = "clk-s-pix-hdmi",
"clk-s-pix-dvo",
"clk-s-out-dvo",
"clk-s-pix-hd",
"clk-s-hddac",
"clk-s-denc",
"clk-s-sddac",
"clk-s-pix-main",
"clk-s-pix-aux",
"clk-s-stfe-frc-0",
"clk-s-ref-mcru",
"clk-s-slave-mcru",
"clk-s-tmds-hdmi",
"clk-s-hdmi-reject-pll",
"clk-s-thsens";
};

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Binding for a Clockgen hardware block found on
certain STMicroelectronics consumer electronics SoC devices.
A Clockgen node can contain pll, diviser or multiplexer nodes.
We will find only the base address of the Clockgen, this base
address is common of all subnode.
clockgen_node {
reg = <>;
pll_node {
...
};
prediv_node {
...
};
divmux_node {
...
};
quadfs_node {
...
};
mux_node {
...
};
vcc_node {
...
};
flexgen_node {
...
};
...
};
This binding uses the common clock binding[1].
Each subnode should use the binding discribe in [2]..[7]
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
[6] Documentation/devicetree/bindings/clock/st,vcc.txt
[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
Required properties:
- reg : A Base address and length of the register set.
Example:
clockgen-a@fee62000 {
reg = <0xfee62000 0xb48>;
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";
clocks = <&clk-sysin>;
clock-output-names = "clk-s-a0-pll0-hs",
"clk-s-a0-pll0-ls",
"clk-s-a0-pll1";
};
clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c65",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a0-osc-prediv";
};
clk_s_a0_hs: clk-s-a0-hs {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-hs",
"st,clkgena-divmux";
clocks = <&clk-s_a0_osc_prediv>,
<&clk-s_a0_pll 0>, /* pll0 hs */
<&clk-s_a0_pll 2>; /* pll1 */
clock-output-names = "clk-s-fdma-0",
"clk-s-fdma-1",
""; /* clk-s-jit-sense */
/* fourth output unused */
};
};

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Binding for a type of flexgen structure found on certain
STMicroelectronics consumer electronics SoC devices
This structure includes:
- a clock cross bar (represented by a mux element)
- a pre and final dividers (represented by a divider and gate elements)
Flexgen structure is a part of Clockgen[1].
Please find an example below:
Clockgen block diagram
-------------------------------------------------------------------
| Flexgen stucture |
| --------------------------------------------- |
| | ------- -------- -------- | |
clk_sysin | | | | | | | | |
---|-----------------|-->| | | | | | | |
| | | | | | | | | | |
| | ------- | | | |Pre | |Final | | |
| | |PLL0 | | | | |Dividers| |Dividers| | |
| |->| | | | | | x32 | | x32 | | |
| | | odf_0|----|-->| | | | | | | |
| | | | | | | | | | | | |
| | | | | | | | | | | | |
| | | | | | | | | | | | |
| | | | | | | | | | | | |
| | ------- | | | | | | | | |
| | | | | | | | | | |
| | ------- | | Clock | | | | | | |
| | |PLL1 | | | | | | | | | |
| |->| | | | Cross | | | | | | |
| | | odf_0|----|-->| | | | | | CLK_DIV[31:0]
| | | | | | Bar |====>| |====>| |===|=========>
| | | | | | | | | | | | |
| | | | | | | | | | | | |
| | | | | | | | | | | | |
| | ------- | | | | | | | | |
| | | | | | | | | | |
| | ------- | | | | | | | | |
| | |QUADFS | | | | | | | | | |
| |->| ch0|----|-->| | | | | | | |
| | | | | | | | | | | |
| | ch1|----|-->| | | | | | | |
| | | | | | | | | | | |
| | ch2|----|-->| | | DIV | | DIV | | |
| | | | | | | 1 to | | 1 to | | |
| | ch3|----|-->| | | 1024 | | 64 | | |
| ------- | | | | | | | | |
| | ------- -------- -------- | |
| -------------------------------------------- |
| |
-------------------------------------------------------------------
This binding uses the common clock binding[2].
[1] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be:
"st,flexgen"
- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
outputs).
- clocks : must be set to the parent's phandle. it's could be output clocks of
a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks)
- clock-output-names : List of strings used to name the clock outputs.
Example:
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen";
clocks = <&clk_s_c0_pll0 0>,
<&clk_s_c0_pll1 0>,
<&clk_s_c0_quadfs 0>,
<&clk_s_c0_quadfs 1>,
<&clk_s_c0_quadfs 2>,
<&clk_s_c0_quadfs 3>,
<&clk_sysin>;
clock-output-names = "clk-icn-gpu",
"clk-fdma",
"clk-nand",
"clk-hva",
"clk-proc-stfe",
"clk-proc-tp",
"clk-rx-icn-dmu",
"clk-rx-icn-hva",
"clk-icn-cpu",
"clk-tx-icn-dmu",
"clk-mmc-0",
"clk-mmc-1",
"clk-jpegdec",
"clk-ext2fa9",
"clk-ic-bdisp-0",
"clk-ic-bdisp-1",
"clk-pp-dmu",
"clk-vid-dmu",
"clk-dss-lpc",
"clk-st231-aud-0",
"clk-st231-gp-1",
"clk-st231-dmu",
"clk-icn-lmi",
"clk-tx-icn-disp-1",
"clk-icn-sbc",
"clk-stfe-frc2",
"clk-eth-phy",
"clk-eth-ref-phyclk",
"clk-flash-promip",
"clk-main-disp",
"clk-aux-disp",
"clk-compo-dvp";
};

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Binding for a type of quad channel digital frequency synthesizer found on
certain STMicroelectronics consumer electronics SoC devices.
This version contains a programmable PLL which can generate up to 216, 432
or 660MHz (from a 30MHz oscillator input) as the input to the digital
synthesizers.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be:
"st,stih416-quadfs216", "st,quadfs"
"st,stih416-quadfs432", "st,quadfs"
"st,stih416-quadfs660-E", "st,quadfs"
"st,stih416-quadfs660-F", "st,quadfs"
"st,stih407-quadfs660-C", "st,quadfs"
"st,stih407-quadfs660-D", "st,quadfs"
- #clock-cells : from common clock binding; shall be set to 1.
- reg : A Base address and length of the register set.
- clocks : from common clock binding
- clock-output-names : From common clock binding. The block has 4
clock outputs but not all of them in a specific instance
have to be used in the SoC. If a clock name is left as
an empty string then no clock will be created for the
output associated with that string index. If fewer than
4 strings are provided then no clocks will be created
for the remaining outputs.
Example:
clockgen_e: clockgen-e@fd3208bc {
#clock-cells = <1>;
compatible = "st,stih416-quadfs660-E", "st,quadfs";
reg = <0xfd3208bc 0xB0>;
clocks = <&clk_sysin>;
clock-output-names = "clk-m-pix-mdtp-0",
"clk-m-pix-mdtp-1",
"clk-m-pix-mdtp-2",
"clk-m-mpelpc";
};

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Clock bindings for ST-Ericsson U300 System Controller Clocks
Bindings for the gated system controller clocks:
Required properties:
- compatible: must be "stericsson,u300-syscon-clk"
- #clock-cells: must be <0>
- clock-type: specifies the type of clock:
0 = slow clock
1 = fast clock
2 = rest/remaining clock
- clock-id: specifies the clock in the type range
Optional properties:
- clocks: parent clock(s)
The available clocks per type are as follows:
Type: ID: Clock:
-------------------
0 0 Slow peripheral bridge clock
0 1 UART0 clock
0 4 GPIO clock
0 6 RTC clock
0 7 Application timer clock
0 8 Access timer clock
1 0 Fast peripheral bridge clock
1 1 I2C bus 0 clock
1 2 I2C bus 1 clock
1 5 MMC interface peripheral (silicon) clock
1 6 SPI clock
2 3 CPU clock
2 4 DMA controller clock
2 5 External Memory Interface (EMIF) clock
2 6 NAND flask interface clock
2 8 XGAM graphics engine clock
2 9 Shared External Memory Interface (SEMI) clock
2 10 AHB Subsystem Bridge clock
2 12 Interrupt controller clock
Example:
gpio_clk: gpio_clk@13M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <0>; /* Slow */
clock-id = <4>;
clocks = <&slow_clk>;
};
gpio: gpio@c0016000 {
compatible = "stericsson,gpio-coh901";
(...)
clocks = <&gpio_clk>;
};
Bindings for the MMC/SD card clock:
Required properties:
- compatible: must be "stericsson,u300-syscon-mclk"
- #clock-cells: must be <0>
Optional properties:
- clocks: parent clock(s)
mmc_mclk: mmc_mclk {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-mclk";
clocks = <&mmc_pclk>;
};
mmcsd: mmcsd@c0001000 {
compatible = "arm,pl18x", "arm,primecell";
clocks = <&mmc_pclk>, <&mmc_mclk>;
clock-names = "apb_pclk", "mclk";
(...)
};

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Device Tree Clock bindings for arch-sunxi
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of the following:
"allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
"allwinner,sun4i-a10-axi-clk" - for the AXI clock
"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
"allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
"allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10
"allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10
"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
"allwinner,sun7i-a20-out-clk" - for the external output clocks
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
Required properties for all clocks:
- reg : shall be the control register address for the clock.
- clocks : shall be the input parent clock(s) phandle for the clock. For
multiplexed clocks, the list order must match the hardware
programming order.
- #clock-cells : from common clock binding; shall be set to 0 except for
"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
"allwinner,sun4i-pll6-clk" where it shall be set to 1
- clock-output-names : shall be the corresponding names of the outputs.
If the clock module only has one output, the name shall be the
module name.
And "allwinner,*-usb-clk" clocks also require:
- reset-cells : shall be set to 1
For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
dummy clocks at 25 MHz and 125 MHz, respectively. See example.
Clock consumers should specify the desired clocks they use with a
"clocks" phandle cell. Consumers that are using a gated clock should
provide an additional ID in their clock property. This ID is the
offset of the bit controlling this particular gate in the register.
For example:
osc24M: clk@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-osc-clk";
reg = <0x01c20050 0x4>;
clocks = <&osc24M_fixed>;
clock-output-names = "osc24M";
};
pll1: clk@01c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll1";
};
pll5: clk@01c20020 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll5-clk";
reg = <0x01c20020 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll5_ddr", "pll5_other";
};
cpu: cpu@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-cpu-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>;
clock-output-names = "cpu";
};
mmc0_clk: clk@01c20088 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc0";
};
mii_phy_tx_clk: clk@2 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "mii_phy_tx";
};
gmac_int_tx_clk: clk@3 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_int_tx";
};
gmac_clk: clk@01c20164 {
#clock-cells = <0>;
compatible = "allwinner,sun7i-a20-gmac-clk";
reg = <0x01c20164 0x4>;
/*
* The first clock must be fixed at 25MHz;
* the second clock must be fixed at 125MHz
*/
clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
clock-output-names = "gmac";
};

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* Device tree bindings for Texas Instruments keystone pll controller
The main pll controller used to drive theC66x CorePacs, the switch fabric,
and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and
the NETCP modules) requires a PLL Controller to manage the various clock
divisions, gating, and synchronization.
Required properties:
- compatible: "ti,keystone-pllctrl", "syscon"
- reg: contains offset/length value for pll controller
registers space.
Example:
pllctrl: pll-controller@0x02310000 {
compatible = "ti,keystone-pllctrl", "syscon";
reg = <0x02310000 0x200>;
};

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Binding for Texas Instruments APLL clock.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1]. It assumes a
register-mapped APLL with usually two selectable input clocks
(reference clock and bypass clock), with analog phase locked
loop logic for multiplying the input clock to a desired output
clock. This clock also typically supports different operation
modes (locked, low power stop etc.) APLL mostly behaves like
a subtype of a DPLL [2], although a simplified one at that.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
Required properties:
- compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
- reg : address and length of the register set for controlling the APLL.
It contains the information of registers in the following order:
"control" - contains the control register offset
"idlest" - contains the idlest register offset
"autoidle" - contains the autoidle register offset (OMAP2 only)
- ti,clock-frequency : static clock frequency for the clock (OMAP2 only)
- ti,idlest-shift : bit-shift for the idlest field (OMAP2 only)
- ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only)
Examples:
apll_pcie_ck: apll_pcie_ck {
#clock-cells = <0>;
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
reg = <0x021c>, <0x0220>;
compatible = "ti,dra7-apll-clock";
};
apll96_ck: apll96_ck {
#clock-cells = <0>;
compatible = "ti,omap2-apll-clock";
clocks = <&sys_ck>;
ti,bit-shift = <2>;
ti,idlest-shift = <8>;
ti,clock-frequency = <96000000>;
reg = <0x0500>, <0x0530>, <0x0520>;
};

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Binding for Texas Instruments autoidle clock.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1]. It assumes a register mapped
clock which can be put to idle automatically by hardware based on the usage
and a configuration bit setting. Autoidle clock is never an individual
clock, it is always a derivative of some basic clock like a gate, divider,
or fixed-factor.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- reg : offset for the register controlling the autoidle
- ti,autoidle-shift : bit shift of the autoidle enable bit
- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0
Examples:
dpll_core_m4_ck: dpll_core_m4_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x2d38>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
clocks = <&dpll_usb_ck>;
ti,clock-div = <1>;
ti,autoidle-shift = <8>;
reg = <0x01b4>;
ti,clock-mult = <1>;
ti,invert-autoidle-bit;
};

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Binding for Texas Instruments clockdomain.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1] in consumer role.
Every clock on TI SoC belongs to one clockdomain, but software
only needs this information for specific clocks which require
their parent clockdomain to be controlled when the clock is
enabled/disabled. This binding doesn't define a new clock
binding type, it is used to group existing clock nodes under
hardware hierarchy.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "ti,clockdomain"
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of clocks within this domain
Examples:
dss_clkdm: dss_clkdm {
compatible = "ti,clockdomain";
clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
};

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Binding for TI composite clock.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1]. It assumes a
register-mapped composite clock with multiple different sub-types;
a multiplexer clock with multiple input clock signals or parents, one
of which can be selected as output, this behaves exactly as [2]
an adjustable clock rate divider, this behaves exactly as [3]
a gating function which can be used to enable and disable the output
clock, this behaves exactly as [4]
The binding must provide a list of the component clocks that shall be
merged to this clock. The component clocks shall be of one of the
"ti,*composite*-clock" types.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/ti/mux.txt
[3] Documentation/devicetree/bindings/clock/ti/divider.txt
[4] Documentation/devicetree/bindings/clock/ti/gate.txt
Required properties:
- compatible : shall be: "ti,composite-clock"
- clocks : link phandles of component clocks
- #clock-cells : from common clock binding; shall be set to 0.
Examples:
usb_l4_gate_ick: usb_l4_gate_ick {
#clock-cells = <0>;
compatible = "ti,composite-interface-clock";
clocks = <&l4_ick>;
ti,bit-shift = <5>;
reg = <0x0a10>;
};
usb_l4_div_ick: usb_l4_div_ick {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&l4_ick>;
ti,bit-shift = <4>;
ti,max-div = <1>;
reg = <0x0a40>;
ti,index-starts-at-one;
};
usb_l4_ick: usb_l4_ick {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
};

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Binding for TI divider clock
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1]. It assumes a
register-mapped adjustable clock rate divider that does not gate and has
only one input clock or parent. By default the value programmed into
the register is one less than the actual divisor value. E.g:
register value actual divisor value
0 1
1 2
2 3
This assumption may be modified by the following optional properties:
ti,index-starts-at-one - valid divisor values start at 1, not the default
of 0. E.g:
register value actual divisor value
1 1
2 2
3 3
ti,index-power-of-two - valid divisor values are powers of two. E.g:
register value actual divisor value
0 1
1 2
2 4
Additionally an array of valid dividers may be supplied like so:
ti,dividers = <4>, <8>, <0>, <16>;
Which will map the resulting values to a divisor table by their index:
register value actual divisor value
0 4
1 8
2 <invalid divisor, skipped>
3 16
Any zero value in this array means the corresponding bit-value is invalid
and must not be used.
The binding must also provide the register to control the divider and
unless the divider array is provided, min and max dividers. Optionally
the number of bits to shift that mask, if necessary. If the shift value
is missing it is the same as supplying a zero shift.
This binding can also optionally provide support to the hardware autoidle
feature, see [2].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
Required properties:
- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link to phandle of parent clock
- reg : offset for register controlling adjustable divider
Optional properties:
- clock-output-names : from common clock binding.
- ti,dividers : array of integers defining divisors
- ti,bit-shift : number of bits to shift the divider value, defaults to 0
- ti,min-div : min divisor for dividing the input clock rate, only
needed if the first divisor is offset from the default value (1)
- ti,max-div : max divisor for dividing the input clock rate, only needed
if ti,dividers is not defined.
- ti,index-starts-at-one : valid divisor programming starts at 1, not zero,
only valid if ti,dividers is not defined.
- ti,index-power-of-two : valid divisor programming must be a power of two,
only valid if ti,dividers is not defined.
- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
see [2]
- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
see [2]
- ti,set-rate-parent : clk_set_rate is propagated to parent
Examples:
dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_ck>;
ti,max-div = <127>;
reg = <0x190>;
ti,index-starts-at-one;
};
aess_fclk: aess_fclk@4a004528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&abe_clk>;
ti,bit-shift = <24>;
reg = <0x528>;
ti,max-div = <2>;
};
dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
reg = <0x0134>;
ti,index-starts-at-one;
};
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&corex2_fck>;
ti,bit-shift = <8>;
reg = <0x0a40>;
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
};

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Binding for Texas Instruments DPLL clock.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1]. It assumes a
register-mapped DPLL with usually two selectable input clocks
(reference clock and bypass clock), with digital phase locked
loop logic for multiplying the input clock to a desired output
clock. This clock also typically supports different operation
modes (locked, low power stop etc.) This binding has several
sub-types, which effectively result in slightly different setup
for the actual DPLL clock.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of:
"ti,omap3-dpll-clock",
"ti,omap3-dpll-core-clock",
"ti,omap3-dpll-per-clock",
"ti,omap3-dpll-per-j-type-clock",
"ti,omap4-dpll-clock",
"ti,omap4-dpll-x2-clock",
"ti,omap4-dpll-core-clock",
"ti,omap4-dpll-m4xen-clock",
"ti,omap4-dpll-j-type-clock",
"ti,omap5-mpu-dpll-clock",
"ti,am3-dpll-no-gate-clock",
"ti,am3-dpll-j-type-clock",
"ti,am3-dpll-no-gate-j-type-clock",
"ti,am3-dpll-clock",
"ti,am3-dpll-core-clock",
"ti,am3-dpll-x2-clock",
"ti,omap2-dpll-core-clock",
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of parent clocks, first entry lists reference clock
and second entry bypass clock
- reg : offsets for the register set for controlling the DPLL.
Registers are listed in following order:
"control" - contains the control register base address
"idlest" - contains the idle status register base address
"mult-div1" - contains the multiplier / divider register base address
"autoidle" - contains the autoidle register base address (optional)
ti,am3-* dpll types do not have autoidle register
ti,omap2-* dpll type does not support idlest / autoidle registers
Optional properties:
- DPLL mode setting - defining any one or more of the following overrides
default setting.
- ti,low-power-stop : DPLL supports low power stop mode, gating output
- ti,low-power-bypass : DPLL output matches rate of parent bypass clock
- ti,lock : DPLL locks in programmed rate
Examples:
dpll_core_ck: dpll_core_ck@44e00490 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x490>, <0x45c>, <0x488>, <0x468>;
};
dpll2_ck: dpll2_ck@48004004 {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-clock";
clocks = <&sys_ck>, <&dpll2_fck>;
ti,low-power-stop;
ti,low-power-bypass;
ti,lock;
reg = <0x4>, <0x24>, <0x34>, <0x40>;
};
dpll_core_ck: dpll_core_ck@44e00490 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x90>, <0x5c>, <0x68>;
};
dpll_ck: dpll_ck {
#clock-cells = <0>;
compatible = "ti,omap2-dpll-core-clock";
clocks = <&sys_ck>, <&sys_ck>;
reg = <0x0500>, <0x0540>;
};

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Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
The ATL IP is used to generate clock to be used to synchronize baseband and
audio codec. A single ATL IP provides four ATL clock instances sharing the same
functional clock but can be configured to provide different clocks.
ATL can maintain a clock averages to some desired frequency based on the bws/aws
signals - can compensate the drift between the two ws signal.
In order to provide the support for ATL and it's output clocks (which can be used
internally within the SoC or external components) two sets of bindings is needed:
Clock tree binding:
This binding uses the common clock binding[1].
To be able to integrate the ATL clocks with DT clock tree.
Provides ccf level representation of the ATL clocks to be used by drivers.
Since the clock instances are part of a single IP this binding is used as a node
for the DT clock tree, the IP driver is needed to handle the actual configuration
of the IP.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "ti,dra7-atl-clock"
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles to functional clock of ATL
Binding for the IP driver:
This binding is used to configure the IP driver which is going to handle the
configuration of the IP for the ATL clock instances.
Required properties:
- compatible : shall be "ti,dra7-atl"
- reg : base address for the ATL IP
- ti,provided-clocks : List of phandles to the clocks associated with the ATL
- clocks : link phandles to functional clock of ATL
- clock-names : Shall be set to "fck"
- ti,hwmods : Shall be set to "atl"
Optional properties:
Configuration of ATL instances:
- atl{0/1/2/3} {
- bws : Baseband word select signal selection
- aws : Audio word select signal selection
};
For valid word select signals, see the dt-bindings/clk/ti-dra7-atl.h include
file.
Examples:
/* clock bindings for atl provided clocks */
atl_clkin0_ck: atl_clkin0_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
};
atl_clkin1_ck: atl_clkin1_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
};
atl_clkin2_ck: atl_clkin2_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
};
atl_clkin3_ck: atl_clkin3_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
};
/* binding for the IP */
atl: atl@4843c000 {
compatible = "ti,dra7-atl";
reg = <0x4843c000 0x3ff>;
ti,hwmods = "atl";
ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
<&atl_clkin2_ck>, <&atl_clkin3_ck>;
clocks = <&atl_gfclk_mux>;
clock-names = "fck";
status = "disabled";
};
#include <dt-bindings/clk/ti-dra7-atl.h>
&atl {
status = "okay";
atl2 {
bws = <DRA7_ATL_WS_MCASP2_FSX>;
aws = <DRA7_ATL_WS_MCASP3_FSX>;
};
};

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Binding for TI fixed factor rate clock sources.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1], and also uses the autoidle
support from TI autoidle clock [2].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
Required properties:
- compatible : shall be "ti,fixed-factor-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- ti,clock-div: fixed divider.
- ti,clock-mult: fixed multiplier.
- clocks: parent clock.
Optional properties:
- ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
see [2]
- reg: offset for the autoidle register of this clock, see [2]
- ti,invert-autoidle-bit: autoidle is enabled by setting the bit to 0, see [2]
- ti,set-rate-parent: clk_set_rate is propagated to parent
Example:
clock {
compatible = "ti,fixed-factor-clock";
clocks = <&parentclk>;
#clock-cells = <0>;
ti,clock-div = <2>;
ti,clock-mult = <1>;
};
dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
clocks = <&dpll_usb_ck>;
ti,clock-div = <1>;
ti,autoidle-shift = <8>;
reg = <0x01b4>;
ti,clock-mult = <1>;
ti,invert-autoidle-bit;
};

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Binding for Texas Instruments gate clock.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1]. This clock is
quite much similar to the basic gate-clock [2], however,
it supports a number of additional features. If no register
is provided for this clock, the code assumes that a clockdomain
will be controlled instead and the corresponding hw-ops for
that is used.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/gate-clock.txt
[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
Required properties:
- compatible : shall be one of:
"ti,gate-clock" - basic gate clock
"ti,wait-gate-clock" - gate clock which waits until clock is active before
returning from clk_enable()
"ti,dss-gate-clock" - gate clock with DSS specific hardware handling
"ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
"ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
clock directly from a clockdomain, see [3] how
to map clockdomains properly
"ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
required for a hardware errata
"ti,composite-gate-clock" - composite gate clock, to be part of composite
clock
"ti,composite-no-wait-gate-clock" - composite gate clock that does not wait
for clock to be active before returning
from clk_enable()
- #clock-cells : from common clock binding; shall be set to 0
- clocks : link to phandle of parent clock
- reg : offset for register controlling adjustable gate, not needed for
ti,clkdm-gate-clock type
Optional properties:
- ti,bit-shift : bit shift for programming the clock gate, invalid for
ti,clkdm-gate-clock type
- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
gates the clock and clearing the bit ungates the clock.
Examples:
mmchs2_fck: mmchs2_fck@48004a00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&core_96m_fck>;
reg = <0x0a00>;
ti,bit-shift = <25>;
};
uart4_fck_am35xx: uart4_fck_am35xx {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_48m_fck>;
reg = <0x0a00>;
ti,bit-shift = <23>;
};
dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
#clock-cells = <0>;
compatible = "ti,dss-gate-clock";
clocks = <&dpll4_m4x2_ck>;
reg = <0x0e00>;
ti,bit-shift = <0>;
};
emac_ick: emac_ick@4800259c {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
reg = <0x059c>;
ti,bit-shift = <1>;
};
emu_src_ck: emu_src_ck {
#clock-cells = <0>;
compatible = "ti,clkdm-gate-clock";
clocks = <&emu_src_mux_ck>;
};
dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m2x2_mul_ck>;
ti,bit-shift = <0x1b>;
reg = <0x0d00>;
ti,set-bit-to-disable;
};
vlynq_gate_fck: vlynq_gate_fck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&core_ck>;
ti,bit-shift = <3>;
reg = <0x0200>;
};
sys_clkout2_src_gate: sys_clkout2_src_gate {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&core_ck>;
ti,bit-shift = <15>;
reg = <0x0070>;
};

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Binding for Texas Instruments interface clock.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1]. This clock is
quite much similar to the basic gate-clock [2], however,
it supports a number of additional features, including
companion clock finding (match corresponding functional gate
clock) and hardware autoidle enable / disable.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/gate-clock.txt
Required properties:
- compatible : shall be one of:
"ti,omap3-interface-clock" - basic OMAP3 interface clock
"ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
capability for waiting clock to be ready
"ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
handling
"ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
"ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
"ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
"ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW
handling
- #clock-cells : from common clock binding; shall be set to 0
- clocks : link to phandle of parent clock
- reg : base address for the control register
Optional properties:
- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)
Examples:
aes1_ick: aes1_ick@48004a14 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
reg = <0x48004a14 0x4>;
ti,bit-shift = <3>;
};
cam_ick: cam_ick@48004f10 {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&l4_ick>;
reg = <0x48004f10 0x4>;
ti,bit-shift = <0>;
};
ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
#clock-cells = <0>;
compatible = "ti,omap3-ssi-interface-clock";
clocks = <&ssi_l4_ick>;
reg = <0x48004a10 0x4>;
ti,bit-shift = <0>;
};

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Binding for TI mux clock.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1]. It assumes a
register-mapped multiplexer with multiple input clock signals or
parents, one of which can be selected as output. This clock does not
gate or adjust the parent rate via a divider or multiplier.
By default the "clocks" property lists the parents in the same order
as they are programmed into the regster. E.g:
clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
results in programming the register as follows:
register value selected parent clock
0 foo_clock
1 bar_clock
2 baz_clock
Some clock controller IPs do not allow a value of zero to be programmed
into the register, instead indexing begins at 1. The optional property
"index-starts-at-one" modified the scheme as follows:
register value selected clock parent
1 foo_clock
2 bar_clock
3 baz_clock
The binding must provide the register to control the mux. Optionally
the number of bits to shift the control field in the register can be
supplied. If the shift value is missing it is the same as supplying
a zero shift.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of parent clocks
- reg : register offset for register controlling adjustable mux
Optional properties:
- ti,bit-shift : number of bits to shift the bit-mask, defaults to
0 if not present
- ti,index-starts-at-one : valid input select programming starts at 1, not
zero
- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
not supported by the composite-mux-clock subtype
Examples:
sys_clkin_ck: sys_clkin_ck@4a306110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
reg = <0x0110>;
ti,index-starts-at-one;
};
abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
reg = <0x0108>;
};
mcbsp5_mux_fck: mcbsp5_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_96m_fck>, <&mcbsp_clks>;
ti,bit-shift = <4>;
reg = <0x02d8>;
};

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* Clock bindings for Freescale Vybrid VF610 SOC
Required properties:
- compatible: Should be "fsl,vf610-ccm"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
for the full list of VF610 clock IDs.
Examples:
clks: ccm@4006b000 {
compatible = "fsl,vf610-ccm";
reg = <0x4006b000 0x1000>;
#clock-cells = <1>;
};
uart1: serial@40028000 {
compatible = "fsl,vf610-uart";
reg = <0x40028000 0x1000>;
interrupts = <0 62 0x04>;
clocks = <&clks VF610_CLK_UART1>;
clock-names = "ipg";
};

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Device Tree Clock bindings for arch-vt8500
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of the following:
"via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
"wm,wm8650-pll-clock" - for a WM8650 PLL clock
"wm,wm8750-pll-clock" - for a WM8750 PLL clock
"wm,wm8850-pll-clock" - for a WM8850 PLL clock
"via,vt8500-device-clock" - for a VT/WM device clock
Required properties for PLL clocks:
- reg : shall be the control register offset from PMC base for the pll clock.
- clocks : shall be the input parent clock phandle for the clock. This should
be the reference clock.
- #clock-cells : from common clock binding; shall be set to 0.
Required properties for device clocks:
- clocks : shall be the input parent clock phandle for the clock. This should
be a pll output.
- #clock-cells : from common clock binding; shall be set to 0.
Device Clocks
Device clocks are required to have one or both of the following sets of
properties:
Gated device clocks:
Required properties:
- enable-reg : shall be the register offset from PMC base for the enable
register.
- enable-bit : shall be the bit within enable-reg to enable/disable the clock.
Divisor device clocks:
Required property:
- divisor-reg : shall be the register offset from PMC base for the divisor
register.
Optional property:
- divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
if not specified.
For example:
ref25: ref25M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
plla: plla {
#clock-cells = <0>;
compatible = "wm,wm8650-pll-clock";
clocks = <&ref25>;
reg = <0x200>;
};
sdhc: sdhc {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&pllb>;
divisor-reg = <0x328>;
divisor-mask = <0x3f>;
enable-reg = <0x254>;
enable-bit = <18>;
};

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Device Tree Clock bindings for APM X-Gene
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of the following:
"apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
"apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
"apm,xgene-device-clock" - for a X-Gene device clock
Required properties for SoC or PCP PLL clocks:
- reg : shall be the physical PLL register address for the pll clock.
- clocks : shall be the input parent clock phandle for the clock. This should
be the reference clock.
- #clock-cells : shall be set to 1.
- clock-output-names : shall be the name of the PLL referenced by derive
clock.
Optional properties for PLL clocks:
- clock-names : shall be the name of the PLL. If missing, use the device name.
Required properties for device clocks:
- reg : shall be a list of address and length pairs describing the CSR
reset and/or the divider. Either may be omitted, but at least
one must be present.
- reg-names : shall be a string list describing the reg resource. This
may include "csr-reg" and/or "div-reg". If this property
is not present, the reg property is assumed to describe
only "csr-reg".
- clocks : shall be the input parent clock phandle for the clock.
- #clock-cells : shall be set to 1.
- clock-output-names : shall be the name of the device referenced.
Optional properties for device clocks:
- clock-names : shall be the name of the device clock. If missing, use the
device name.
- csr-offset : Offset to the CSR reset register from the reset address base.
Default is 0.
- csr-mask : CSR reset mask bit. Default is 0xF.
- enable-offset : Offset to the enable register from the reset address base.
Default is 0x8.
- enable-mask : CSR enable mask bit. Default is 0xF.
- divider-offset : Offset to the divider CSR register from the divider base.
Default is 0x0.
- divider-width : Width of the divider register. Default is 0.
- divider-shift : Bit shift of the divider register. Default is 0.
For example:
pcppll: pcppll@17000100 {
compatible = "apm,xgene-pcppll-clock";
#clock-cells = <1>;
clocks = <&refclk 0>;
clock-names = "pcppll";
reg = <0x0 0x17000100 0x0 0x1000>;
clock-output-names = "pcppll";
type = <0>;
};
socpll: socpll@17000120 {
compatible = "apm,xgene-socpll-clock";
#clock-cells = <1>;
clocks = <&refclk 0>;
clock-names = "socpll";
reg = <0x0 0x17000120 0x0 0x1000>;
clock-output-names = "socpll";
type = <1>;
};
qmlclk: qmlclk {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
clock-names = "qmlclk";
reg = <0x0 0x1703C000 0x0 0x1000>;
reg-name = "csr-reg";
clock-output-names = "qmlclk";
};
ethclk: ethclk {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
clock-names = "ethclk";
reg = <0x0 0x17000000 0x0 0x1000>;
reg-names = "div-reg";
divider-offset = <0x238>;
divider-width = <0x9>;
divider-shift = <0x0>;
clock-output-names = "ethclk";
};
apbclk: apbclk {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&ahbclk 0>;
clock-names = "apbclk";
reg = <0x0 0x1F2AC000 0x0 0x1000
0x0 0x1F2AC000 0x0 0x1000>;
reg-names = "csr-reg", "div-reg";
csr-offset = <0x0>;
csr-mask = <0x200>;
enable-offset = <0x8>;
enable-mask = <0x200>;
divider-offset = <0x10>;
divider-width = <0x2>;
divider-shift = <0x0>;
flags = <0x8>;
clock-output-names = "apbclk";
};

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Device Tree Clock bindings for the Zynq 7000 EPP
The Zynq EPP has several different clk providers, each with there own bindings.
The purpose of this document is to document their usage.
See clock_bindings.txt for more information on the generic clock bindings.
See Chapter 25 of Zynq TRM for more information about Zynq clocks.
== Clock Controller ==
The clock controller is a logical abstraction of Zynq's clock tree. It reads
required input clock frequencies from the devicetree and acts as clock provider
for all clock consumers of PS clocks.
Required properties:
- #clock-cells : Must be 1
- compatible : "xlnx,ps7-clkc"
- reg : SLCR offset and size taken via syscon < 0x100 0x100 >
- ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
(usually 33 MHz oscillators are used for Zynq platforms)
- clock-output-names : List of strings used to name the clock outputs. Shall be
a list of the outputs given below.
Optional properties:
- clocks : as described in the clock bindings
- clock-names : as described in the clock bindings
- fclk-enable : Bit mask to enable FCLKs statically at boot time.
Bit [0..3] correspond to FCLK0..FCLK3. The corresponding
FCLK will only be enabled if it is actually running at
boot time.
Clock inputs:
The following strings are optional parameters to the 'clock-names' property in
order to provide an optional (E)MIO clock source.
- swdt_ext_clk
- gem0_emio_clk
- gem1_emio_clk
- mio_clk_XX # with XX = 00..53
...
Clock outputs:
0: armpll
1: ddrpll
2: iopll
3: cpu_6or4x
4: cpu_3or2x
5: cpu_2x
6: cpu_1x
7: ddr2x
8: ddr3x
9: dci
10: lqspi
11: smc
12: pcap
13: gem0
14: gem1
15: fclk0
16: fclk1
17: fclk2
18: fclk3
19: can0
20: can1
21: sdio0
22: sdio1
23: uart0
24: uart1
25: spi0
26: spi1
27: dma
28: usb0_aper
29: usb1_aper
30: gem0_aper
31: gem1_aper
32: sdio0_aper
33: sdio1_aper
34: spi0_aper
35: spi1_aper
36: can0_aper
37: can1_aper
38: i2c0_aper
39: i2c1_aper
40: uart0_aper
41: uart1_aper
42: gpio_aper
43: lqspi_aper
44: smc_aper
45: swdt
46: dbg_trc
47: dbg_apb
Example:
clkc: clkc@100 {
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
ps-clk-frequency = <33333333>;
reg = <0x100 0x100>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
"dma", "usb0_aper", "usb1_aper", "gem0_aper",
"gem1_aper", "sdio0_aper", "sdio1_aper",
"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
"dbg_trc", "dbg_apb";
# optional props
clocks = <&clkc 16>, <&clk_foo>;
clock-names = "gem1_emio_clk", "can_mio_clk_23";
};