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	Fixed MTP to work with TWRP
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								Documentation/devicetree/bindings/clock/imx31-clock.txt
									
										
									
									
									
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								Documentation/devicetree/bindings/clock/imx31-clock.txt
									
										
									
									
									
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* Clock bindings for Freescale i.MX31
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Required properties:
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- compatible: Should be "fsl,imx31-ccm"
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- reg: Address and length of the register set
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- interrupts: Should contain CCM interrupt
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- #clock-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell.  The following is a full list of i.MX31
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clocks and IDs.
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	Clock		    ID
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	-----------------------
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	dummy	             0
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	ckih                 1
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	ckil                 2
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	mpll                 3
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	spll                 4
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	upll                 5
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	mcu_main             6
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	hsp                  7
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	ahb                  8
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	nfc                  9
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	ipg                  10
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	per_div              11
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	per                  12
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	csi_sel              13
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	fir_sel              14
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	csi_div              15
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	usb_div_pre          16
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	usb_div_post         17
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	fir_div_pre          18
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	fir_div_post         19
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	sdhc1_gate           20
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	sdhc2_gate           21
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	gpt_gate             22
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	epit1_gate           23
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	epit2_gate           24
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	iim_gate             25
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	ata_gate             26
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	sdma_gate            27
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	cspi3_gate           28
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	rng_gate             29
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	uart1_gate           30
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	uart2_gate           31
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	ssi1_gate            32
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	i2c1_gate            33
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	i2c2_gate            34
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	i2c3_gate            35
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	hantro_gate          36
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	mstick1_gate         37
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	mstick2_gate         38
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	csi_gate             39
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	rtc_gate             40
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	wdog_gate            41
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	pwm_gate             42
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	sim_gate             43
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	ect_gate             44
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	usb_gate             45
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	kpp_gate             46
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	ipu_gate             47
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	uart3_gate           48
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	uart4_gate           49
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	uart5_gate           50
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	owire_gate           51
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	ssi2_gate            52
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	cspi1_gate           53
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	cspi2_gate           54
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	gacc_gate            55
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	emi_gate             56
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	rtic_gate            57
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	firi_gate            58
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Examples:
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clks: ccm@53f80000{
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	compatible = "fsl,imx31-ccm";
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	reg = <0x53f80000 0x4000>;
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	interrupts = <0 31 0x04 0 53 0x04>;
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	#clock-cells = <1>;
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};
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uart1: serial@43f90000 {
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	compatible = "fsl,imx31-uart", "fsl,imx21-uart";
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	reg = <0x43f90000 0x4000>;
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	interrupts = <45>;
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	clocks = <&clks 10>, <&clks 30>;
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	clock-names = "ipg", "per";
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	status = "disabled";
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};
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