mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-28 14:58:52 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
|
|
@ -0,0 +1,38 @@
|
|||
TB10x Top Level Interrupt Controller
|
||||
====================================
|
||||
|
||||
The Abilis TB10x SOC contains a custom interrupt controller. It performs
|
||||
one-to-one mapping of external interrupt sources to CPU interrupts and
|
||||
provides support for reconfigurable trigger modes.
|
||||
|
||||
Required properties
|
||||
-------------------
|
||||
|
||||
- compatible: Should be "abilis,tb10x-ictl"
|
||||
- reg: specifies physical base address and size of register range.
|
||||
- interrupt-congroller: Identifies the node as an interrupt controller.
|
||||
- #interrupt cells: Specifies the number of cells used to encode an interrupt
|
||||
source connected to this controller. The value shall be 2.
|
||||
- interrupt-parent: Specifies the parent interrupt controller.
|
||||
- interrupts: Specifies the list of interrupt lines which are handled by
|
||||
the interrupt controller in the parent controller's notation. Interrupts
|
||||
are mapped one-to-one to parent interrupts.
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
intc: interrupt-controller { /* Parent interrupt controller */
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>; /* For example below */
|
||||
/* ... */
|
||||
};
|
||||
|
||||
tb10x_ictl: pic@2000 { /* TB10x interrupt controller */
|
||||
compatible = "abilis,tb10x-ictl";
|
||||
reg = <0x2000 0x20>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
|
||||
20 21 22 23 24 25 26 27 28 29 30 31>;
|
||||
};
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
Allwinner Sunxi Interrupt Controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "allwinner,sun4i-a10-ic"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 1.
|
||||
|
||||
Example:
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "allwinner,sun4i-a10-ic";
|
||||
reg = <0x01c20400 0x400>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
Allwinner Sunxi NMI Controller
|
||||
==============================
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "allwinner,sun7i-a20-sc-nmi" or
|
||||
"allwinner,sun6i-a31-sc-nmi"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 2. The first cell is the IRQ number, the
|
||||
second cell the trigger type as defined in interrupt.txt in this directory.
|
||||
- interrupt-parent: Specifies the parent interrupt controller.
|
||||
- interrupts: Specifies the interrupt line (NMI) which is handled by
|
||||
the interrupt controller in the parent controller's notation. This value
|
||||
shall be the NMI.
|
||||
|
||||
Example:
|
||||
|
||||
sc-nmi-intc@01c00030 {
|
||||
compatible = "allwinner,sun7i-a20-sc-nmi";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x01c00030 0x0c>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 0 4>;
|
||||
};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
* Advanced Interrupt Controller (AIC)
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "atmel,<chip>-aic"
|
||||
<chip> can be "at91rm9200", "sama5d3" or "sama5d4"
|
||||
- interrupt-controller: Identifies the node as an interrupt controller.
|
||||
- interrupt-parent: For single AIC system, it is an empty property.
|
||||
- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
|
||||
The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
|
||||
The second cell is used to specify flags:
|
||||
bits[3:0] trigger type and level flags:
|
||||
1 = low-to-high edge triggered.
|
||||
2 = high-to-low edge triggered.
|
||||
4 = active high level-sensitive.
|
||||
8 = active low level-sensitive.
|
||||
Valid combinations are 1, 2, 3, 4, 8.
|
||||
Default flag for internal sources should be set to 4 (active high).
|
||||
The third cell is used to specify the irq priority from 0 (lowest) to 7
|
||||
(highest).
|
||||
- reg: Should contain AIC registers location and length
|
||||
- atmel,external-irqs: u32 array of external irqs.
|
||||
|
||||
Examples:
|
||||
/*
|
||||
* AIC
|
||||
*/
|
||||
aic: interrupt-controller@fffff000 {
|
||||
compatible = "atmel,at91rm9200-aic";
|
||||
interrupt-controller;
|
||||
interrupt-parent;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0xfffff000 0x200>;
|
||||
};
|
||||
|
||||
/*
|
||||
* An interrupt generating device that is wired to an AIC.
|
||||
*/
|
||||
dma: dma-controller@ffffec00 {
|
||||
compatible = "atmel,at91sam9g45-dma";
|
||||
reg = <0xffffec00 0x200>;
|
||||
interrupts = <21 4 5>;
|
||||
};
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
|
||||
|
||||
The BCM2835 contains a custom top-level interrupt controller, which supports
|
||||
72 interrupt sources using a 2-level register scheme. The interrupt
|
||||
controller, or the HW block containing it, is referred to occasionally
|
||||
as "armctrl" in the SoC documentation, hence naming of this binding.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "brcm,bcm2835-armctrl-ic"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 2.
|
||||
|
||||
The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
|
||||
pending" register, or 1/2 respectively for interrupts in the "IRQ pending
|
||||
1/2" register.
|
||||
|
||||
The 2nd cell contains the interrupt number within the bank. Valid values
|
||||
are 0..7 for bank 0, and 0..31 for bank 1.
|
||||
|
||||
The interrupt sources are as follows:
|
||||
|
||||
Bank 0:
|
||||
0: ARM_TIMER
|
||||
1: ARM_MAILBOX
|
||||
2: ARM_DOORBELL_0
|
||||
3: ARM_DOORBELL_1
|
||||
4: VPU0_HALTED
|
||||
5: VPU1_HALTED
|
||||
6: ILLEGAL_TYPE0
|
||||
7: ILLEGAL_TYPE1
|
||||
|
||||
Bank 1:
|
||||
0: TIMER0
|
||||
1: TIMER1
|
||||
2: TIMER2
|
||||
3: TIMER3
|
||||
4: CODEC0
|
||||
5: CODEC1
|
||||
6: CODEC2
|
||||
7: VC_JPEG
|
||||
8: ISP
|
||||
9: VC_USB
|
||||
10: VC_3D
|
||||
11: TRANSPOSER
|
||||
12: MULTICORESYNC0
|
||||
13: MULTICORESYNC1
|
||||
14: MULTICORESYNC2
|
||||
15: MULTICORESYNC3
|
||||
16: DMA0
|
||||
17: DMA1
|
||||
18: VC_DMA2
|
||||
19: VC_DMA3
|
||||
20: DMA4
|
||||
21: DMA5
|
||||
22: DMA6
|
||||
23: DMA7
|
||||
24: DMA8
|
||||
25: DMA9
|
||||
26: DMA10
|
||||
27: DMA11
|
||||
28: DMA12
|
||||
29: AUX
|
||||
30: ARM
|
||||
31: VPUDMA
|
||||
|
||||
Bank 2:
|
||||
0: HOSTPORT
|
||||
1: VIDEOSCALER
|
||||
2: CCP2TX
|
||||
3: SDC
|
||||
4: DSI0
|
||||
5: AVE
|
||||
6: CAM0
|
||||
7: CAM1
|
||||
8: HDMI0
|
||||
9: HDMI1
|
||||
10: PIXELVALVE1
|
||||
11: I2CSPISLV
|
||||
12: DSI1
|
||||
13: PWA0
|
||||
14: PWA1
|
||||
15: CPR
|
||||
16: SMI
|
||||
17: GPIO0
|
||||
18: GPIO1
|
||||
19: GPIO2
|
||||
20: GPIO3
|
||||
21: VC_I2C
|
||||
22: VC_SPI
|
||||
23: VC_I2SPCM
|
||||
24: VC_SDIO
|
||||
25: VC_UART
|
||||
26: SLIMBUS
|
||||
27: VEC
|
||||
28: CPG
|
||||
29: RNG
|
||||
30: VC_ARASANSDIO
|
||||
31: AVSPMON
|
||||
|
||||
Example:
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "brcm,bcm2835-armctrl-ic";
|
||||
reg = <0x7e00b200 0x200>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
Broadcom BCM7120-style Level 2 interrupt controller
|
||||
|
||||
This interrupt controller hardware is a second level interrupt controller that
|
||||
is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
|
||||
platforms. It can be found on BCM7xxx products starting with BCM7120.
|
||||
|
||||
Such an interrupt controller has the following hardware design:
|
||||
|
||||
- outputs multiple interrupts signals towards its interrupt controller parent
|
||||
|
||||
- controls how some of the interrupts will be flowing, whether they will
|
||||
directly output an interrupt signal towards the interrupt controller parent,
|
||||
or if they will output an interrupt signal at this 2nd level interrupt
|
||||
controller, in particular for UARTs
|
||||
|
||||
- not all 32-bits within the interrupt controller actually map to an interrupt
|
||||
|
||||
The typical hardware layout for this controller is represented below:
|
||||
|
||||
2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
|
||||
|
||||
0 -----[ MUX ] ------------|==========> GIC interrupt 75
|
||||
\-----------\
|
||||
|
|
||||
1 -----[ MUX ] --------)---|==========> GIC interrupt 76
|
||||
\------------|
|
||||
|
|
||||
2 -----[ MUX ] --------)---|==========> GIC interrupt 77
|
||||
\------------|
|
||||
|
|
||||
3 ---------------------|
|
||||
4 ---------------------|
|
||||
5 ---------------------|
|
||||
7 ---------------------|---|===========> GIC interrupt 66
|
||||
9 ---------------------|
|
||||
10 --------------------|
|
||||
11 --------------------/
|
||||
|
||||
6 ------------------------\
|
||||
|===========> GIC interrupt 64
|
||||
8 ------------------------/
|
||||
|
||||
12 ........................ X
|
||||
13 ........................ X (not connected)
|
||||
..
|
||||
31 ........................ X
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "brcm,bcm7120-l2-intc"
|
||||
- reg: specifies the base physical address and size of the registers
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
||||
source, should be 1.
|
||||
- interrupt-parent: specifies the phandle to the parent interrupt controller
|
||||
this one is cascaded from
|
||||
- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
|
||||
node, valid values depend on the type of parent interrupt controller
|
||||
- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
|
||||
are wired to this 2nd level interrupt controller, and how they match their
|
||||
respective interrupt parents. Should match exactly the number of interrupts
|
||||
specified in the 'interrupts' property.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
|
||||
wakeup source for system suspend/resume.
|
||||
|
||||
- brcm,int-fwd-mask: if present, a 32-bits bit mask to configure for the
|
||||
interrupts which have a mux gate, typically UARTs. Setting these bits will
|
||||
make their respective interrupts outputs bypass this 2nd level interrupt
|
||||
controller completely, it completely transparent for the interrupt controller
|
||||
parent
|
||||
|
||||
Example:
|
||||
|
||||
irq0_intc: interrupt-controller@f0406800 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
interrupt-parent = <&intc>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0xf0406800 0x8>;
|
||||
interrupt-controller;
|
||||
interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
|
||||
brcm,int-map-mask = <0xeb8>, <0x140>;
|
||||
brcm,int-fwd-mask = <0x7>;
|
||||
};
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
Broadcom Generic Level 2 Interrupt Controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "brcm,l2-intc"
|
||||
- reg: specifies the base physical address and size of the registers
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an
|
||||
interrupt source. Should be 1.
|
||||
- interrupt-parent: specifies the phandle to the parent interrupt controller
|
||||
this controller is cacaded from
|
||||
- interrupts: specifies the interrupt line in the interrupt-parent irq space
|
||||
to be used for cascading
|
||||
|
||||
Optional properties:
|
||||
|
||||
- brcm,irq-can-wake: If present, this means the L2 controller can be used as a
|
||||
wakeup source for system suspend/resume.
|
||||
|
||||
Example:
|
||||
|
||||
hif_intr2_intc: interrupt-controller@f0441000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0xf0441000 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0x0 0x20 0x0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
Cirrus Logic CLPS711X Interrupt Controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be "cirrus,clps711x-intc".
|
||||
- reg: Specifies base physical address of the registers set.
|
||||
- interrupt-controller: Identifies the node as an interrupt controller.
|
||||
- #interrupt-cells: Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 1.
|
||||
|
||||
The interrupt sources are as follows:
|
||||
ID Name Description
|
||||
---------------------------
|
||||
1: BLINT Battery low (FIQ)
|
||||
3: MCINT Media changed (FIQ)
|
||||
4: CSINT CODEC sound
|
||||
5: EINT1 External 1
|
||||
6: EINT2 External 2
|
||||
7: EINT3 External 3
|
||||
8: TC1OI TC1 under flow
|
||||
9: TC2OI TC2 under flow
|
||||
10: RTCMI RTC compare match
|
||||
11: TINT 64Hz tick
|
||||
12: UTXINT1 UART1 transmit FIFO half empty
|
||||
13: URXINT1 UART1 receive FIFO half full
|
||||
14: UMSINT UART1 modem status changed
|
||||
15: SSEOTI SSI1 end of transfer
|
||||
16: KBDINT Keyboard
|
||||
17: SS2RX SSI2 receive FIFO half or greater full
|
||||
18: SS2TX SSI2 transmit FIFO less than half empty
|
||||
28: UTXINT2 UART2 transmit FIFO half empty
|
||||
29: URXINT2 UART2 receive FIFO half full
|
||||
32: DAIINT DAI interface (FIQ)
|
||||
|
||||
Example:
|
||||
intc: interrupt-controller {
|
||||
compatible = "cirrus,clps711x-intc";
|
||||
reg = <0x80000000 0x4000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
Specifying interrupt information for devices
|
||||
============================================
|
||||
|
||||
1) Interrupt client nodes
|
||||
-------------------------
|
||||
|
||||
Nodes that describe devices which generate interrupts must contain an
|
||||
"interrupts" property, an "interrupts-extended" property, or both. If both are
|
||||
present, the latter should take precedence; the former may be provided simply
|
||||
for compatibility with software that does not recognize the latter. These
|
||||
properties contain a list of interrupt specifiers, one per output interrupt. The
|
||||
format of the interrupt specifier is determined by the interrupt controller to
|
||||
which the interrupts are routed; see section 2 below for details.
|
||||
|
||||
Example:
|
||||
interrupt-parent = <&intc1>;
|
||||
interrupts = <5 0>, <6 0>;
|
||||
|
||||
The "interrupt-parent" property is used to specify the controller to which
|
||||
interrupts are routed and contains a single phandle referring to the interrupt
|
||||
controller node. This property is inherited, so it may be specified in an
|
||||
interrupt client node or in any of its parent nodes. Interrupts listed in the
|
||||
"interrupts" property are always in reference to the node's interrupt parent.
|
||||
|
||||
The "interrupts-extended" property is a special form for use when a node needs
|
||||
to reference multiple interrupt parents. Each entry in this property contains
|
||||
both the parent phandle and the interrupt specifier. "interrupts-extended"
|
||||
should only be used when a device has multiple interrupt parents.
|
||||
|
||||
Example:
|
||||
interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
|
||||
|
||||
2) Interrupt controller nodes
|
||||
-----------------------------
|
||||
|
||||
A device is marked as an interrupt controller with the "interrupt-controller"
|
||||
property. This is a empty, boolean property. An additional "#interrupt-cells"
|
||||
property defines the number of cells needed to specify a single interrupt.
|
||||
|
||||
It is the responsibility of the interrupt controller's binding to define the
|
||||
length and format of the interrupt specifier. The following two variants are
|
||||
commonly used:
|
||||
|
||||
a) one cell
|
||||
-----------
|
||||
The #interrupt-cells property is set to 1 and the single cell defines the
|
||||
index of the interrupt within the controller.
|
||||
|
||||
Example:
|
||||
|
||||
vic: intc@10140000 {
|
||||
compatible = "arm,versatile-vic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x10140000 0x1000>;
|
||||
};
|
||||
|
||||
sic: intc@10003000 {
|
||||
compatible = "arm,versatile-sic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x10003000 0x1000>;
|
||||
interrupt-parent = <&vic>;
|
||||
interrupts = <31>; /* Cascaded to vic */
|
||||
};
|
||||
|
||||
b) two cells
|
||||
------------
|
||||
The #interrupt-cells property is set to 2 and the first cell defines the
|
||||
index of the interrupt within the controller, while the second cell is used
|
||||
to specify any of the following flags:
|
||||
- bits[3:0] trigger type and level flags
|
||||
1 = low-to-high edge triggered
|
||||
2 = high-to-low edge triggered
|
||||
4 = active high level-sensitive
|
||||
8 = active low level-sensitive
|
||||
|
||||
Example:
|
||||
|
||||
i2c@7000c000 {
|
||||
gpioext: gpio-adnp@41 {
|
||||
compatible = "ad,gpio-adnp";
|
||||
reg = <0x41>;
|
||||
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <160 1>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
nr-gpios = <64>;
|
||||
};
|
||||
|
||||
sx8634@2b {
|
||||
compatible = "smtc,sx8634";
|
||||
reg = <0x2b>;
|
||||
|
||||
interrupt-parent = <&gpioext>;
|
||||
interrupts = <3 0x8>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
threshold = <0x40>;
|
||||
sensitivity = <7>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
TI-NSPIRE interrupt controller
|
||||
|
||||
Required properties:
|
||||
- compatible: Compatible property value should be "lsi,zevio-intc".
|
||||
|
||||
- reg: Physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
|
||||
Example:
|
||||
|
||||
interrupt-controller {
|
||||
compatible = "lsi,zevio-intc";
|
||||
interrupt-controller;
|
||||
reg = <0xDC000000 0x1000>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
Marvell Armada 370, 375, 38x, XP Interrupt Controller
|
||||
-----------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "marvell,mpic"
|
||||
- interrupt-controller: Identifies the node as an interrupt controller.
|
||||
- msi-controller: Identifies the node as an PCI Message Signaled
|
||||
Interrupt controller.
|
||||
- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
|
||||
The cell is the IRQ number
|
||||
|
||||
- reg: Should contain PMIC registers location and length. First pair
|
||||
for the main interrupt registers, second pair for the per-CPU
|
||||
interrupt registers. For this last pair, to be compliant with SMP
|
||||
support, the "virtual" must be use (For the record, these registers
|
||||
automatically map to the interrupt controller registers of the
|
||||
current CPU)
|
||||
|
||||
Optional properties:
|
||||
|
||||
- interrupts: If defined, then it indicates that this MPIC is
|
||||
connected as a slave to another interrupt controller. This is
|
||||
typically the case on Armada 375 and Armada 38x, where the MPIC is
|
||||
connected as a slave to the Cortex-A9 GIC. The provided interrupt
|
||||
indicate to which GIC interrupt the MPIC output is connected.
|
||||
|
||||
Example:
|
||||
|
||||
mpic: interrupt-controller@d0020000 {
|
||||
compatible = "marvell,mpic";
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
reg = <0xd0020a00 0x1d0>,
|
||||
<0xd0021070 0x58>;
|
||||
};
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
Marvell Orion SoC interrupt controllers
|
||||
|
||||
* Main interrupt controller
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be "marvell,orion-intc"
|
||||
- reg: base address(es) of interrupt registers starting with CAUSE register
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
|
||||
|
||||
The interrupt sources map to the corresponding bits in the interrupt
|
||||
registers, i.e.
|
||||
- 0 maps to bit 0 of first base address,
|
||||
- 1 maps to bit 1 of first base address,
|
||||
- 32 maps to bit 0 of second base address, and so on.
|
||||
|
||||
Example:
|
||||
intc: interrupt-controller {
|
||||
compatible = "marvell,orion-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
/* Dove has 64 first level interrupts */
|
||||
reg = <0x20200 0x10>, <0x20210 0x10>;
|
||||
};
|
||||
|
||||
* Bridge interrupt controller
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be "marvell,orion-bridge-intc"
|
||||
- reg: base address of bridge interrupt registers starting with CAUSE register
|
||||
- interrupts: bridge interrupt of the main interrupt controller
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
|
||||
|
||||
Optional properties:
|
||||
- marvell,#interrupts: number of interrupts provided by bridge interrupt
|
||||
controller, defaults to 32 if not set
|
||||
|
||||
Example:
|
||||
bridge_intc: interrupt-controller {
|
||||
compatible = "marvell,orion-bridge-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x20110 0x8>;
|
||||
interrupts = <0>;
|
||||
/* Dove bridge provides 5 interrupts */
|
||||
marvell,#interrupts = <5>;
|
||||
};
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
OpenRISC 1000 Programmable Interrupt Controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "opencores,or1k-pic-level" for variants with
|
||||
level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
|
||||
edge triggered interrupt lines or "opencores,or1200-pic" for machines
|
||||
with the non-spec compliant or1200 type implementation.
|
||||
|
||||
"opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
|
||||
but this is only for backwards compatibility.
|
||||
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 1.
|
||||
|
||||
Example:
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "opencores,or1k-pic-level";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
DT bindings for the R-/SH-Mobile irqpin controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: has to be "renesas,intc-irqpin-<soctype>", "renesas,intc-irqpin"
|
||||
as fallback.
|
||||
Examples with soctypes are:
|
||||
- "renesas,intc-irqpin-r8a7740" (R-Mobile A1)
|
||||
- "renesas,intc-irqpin-r8a7778" (R-Car M1A)
|
||||
- "renesas,intc-irqpin-r8a7779" (R-Car H1)
|
||||
- "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5)
|
||||
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
|
||||
interrupts.txt in this directory
|
||||
|
||||
Optional properties:
|
||||
|
||||
- any properties, listed in interrupts.txt, and any standard resource allocation
|
||||
properties
|
||||
- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
|
||||
if different from the default 4 bits
|
||||
- control-parent: disable and enable interrupts on the parent interrupt
|
||||
controller, needed for some broken implementations
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
DT bindings for the R-Mobile/R-Car interrupt controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: has to be "renesas,irqc-<soctype>", "renesas,irqc" as fallback.
|
||||
Examples with soctypes are:
|
||||
- "renesas,irqc-r8a73a4" (R-Mobile AP6)
|
||||
- "renesas,irqc-r8a7790" (R-Car H2)
|
||||
- "renesas,irqc-r8a7791" (R-Car M2-W)
|
||||
- "renesas,irqc-r8a7792" (R-Car V2H)
|
||||
- "renesas,irqc-r8a7793" (R-Car M2-N)
|
||||
- "renesas,irqc-r8a7794" (R-Car E2)
|
||||
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
|
||||
interrupts.txt in this directory
|
||||
|
||||
Optional properties:
|
||||
|
||||
- any properties, listed in interrupts.txt, and any standard resource allocation
|
||||
properties
|
||||
|
||||
Example:
|
||||
|
||||
irqc0: interrupt-controller@e61c0000 {
|
||||
compatible = "renesas,irqc-r8a7790", "renesas,irqc";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xe61c0000 0 0x200>;
|
||||
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
Samsung S3C24XX Interrupt Controllers
|
||||
|
||||
The S3C24XX SoCs contain a custom set of interrupt controllers providing a
|
||||
varying number of interrupt sources. The set consists of a main- and sub-
|
||||
controller and on newer SoCs even a second main controller.
|
||||
|
||||
Required properties:
|
||||
- compatible: Compatible property value should be "samsung,s3c2410-irq"
|
||||
for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.
|
||||
|
||||
- reg: Physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 4 and interrupt descriptor shall
|
||||
have the following format:
|
||||
<ctrl_num parent_irq ctrl_irq type>
|
||||
|
||||
ctrl_num contains the controller to use:
|
||||
- 0 ... main controller
|
||||
- 1 ... sub controller
|
||||
- 2 ... second main controller on s3c2416 and s3c2450
|
||||
parent_irq contains the parent bit in the main controller and will be
|
||||
ignored in main controllers
|
||||
ctrl_irq contains the interrupt bit of the controller
|
||||
type contains the trigger type to use
|
||||
|
||||
Example:
|
||||
|
||||
interrupt-controller@4a000000 {
|
||||
compatible = "samsung,s3c2410-irq";
|
||||
reg = <0x4a000000 0x100>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells=<4>;
|
||||
};
|
||||
|
||||
[...]
|
||||
|
||||
serial@50000000 {
|
||||
compatible = "samsung,s3c2410-uart";
|
||||
reg = <0x50000000 0x4000>;
|
||||
interrupt-parent = <&subintc>;
|
||||
interrupts = <1 28 0 4>, <1 28 1 4>;
|
||||
};
|
||||
|
||||
rtc@57000000 {
|
||||
compatible = "samsung,s3c2410-rtc";
|
||||
reg = <0x57000000 0x100>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 30 0 3>, <0 8 0 3>;
|
||||
};
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
|
||||
|
||||
Synopsys DesignWare provides interrupt controller IP for APB known as
|
||||
dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
|
||||
APB bus, e.g. Marvell Armada 1500.
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be "snps,dw-apb-ictl"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region starting with ENABLE_LOW register
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
|
||||
- interrupts: interrupt reference to primary interrupt controller
|
||||
- interrupt-parent: (optional) reference specific primary interrupt controller
|
||||
|
||||
The interrupt sources map to the corresponding bits in the interrupt
|
||||
registers, i.e.
|
||||
- 0 maps to bit 0 of low interrupts,
|
||||
- 1 maps to bit 1 of low interrupts,
|
||||
- 32 maps to bit 0 of high interrupts,
|
||||
- 33 maps to bit 1 of high interrupts,
|
||||
- (optional) fast interrupts start at 64.
|
||||
|
||||
Example:
|
||||
aic: interrupt-controller@3000 {
|
||||
compatible = "snps,dw-apb-ictl";
|
||||
reg = <0x3000 0xc00>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
Keystone 2 IRQ controller IP
|
||||
|
||||
On Keystone SOCs, DSP cores can send interrupts to ARM
|
||||
host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
|
||||
The IRQ handler running on HOST OS can identify DSP signal source by
|
||||
analyzing SRCCx bits in IPCARx registers. This is one of the component
|
||||
used by the IPC mechanism used on Keystone SOCs.
|
||||
|
||||
Required Properties:
|
||||
- compatible: should be "ti,keystone-irq"
|
||||
- ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
|
||||
access device control registers and the offset inside
|
||||
device control registers range.
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
|
||||
source should be 1.
|
||||
- interrupts: interrupt reference to primary interrupt controller
|
||||
|
||||
Please refer to interrupts.txt in this directory for details of the common
|
||||
Interrupt Controllers bindings used by client devices.
|
||||
|
||||
Example:
|
||||
kirq0: keystone_irq0@026202a0 {
|
||||
compatible = "ti,keystone-irq";
|
||||
ti,syscon-dev = <&devctrl 0x2a0>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
dsp0: dsp0 {
|
||||
compatible = "linux,rproc-user";
|
||||
...
|
||||
interrupt-parent = <&kirq0>;
|
||||
interrupts = <10 2>;
|
||||
};
|
||||
Loading…
Add table
Add a link
Reference in a new issue