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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
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79
Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt Normal file
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Integrated Flash Controller
Properties:
- name : Should be ifc
- compatible : should contain "fsl,ifc". The version of the integrated
flash controller can be found in the IFC_REV register at
offset zero.
- #address-cells : Should be either two or three. The first cell is the
chipselect number, and the remaining cells are the
offset into the chipselect.
- #size-cells : Either one or two, depending on how large each chipselect
can be.
- reg : Offset and length of the register set for the device
- interrupts: IFC may have one or two interrupts. If two interrupt
specifiers are present, the first is the "common"
interrupt (CM_EVTER_STAT), and the second is the NAND
interrupt (NAND_EVTER_STAT). If there is only one,
that interrupt reports both types of event.
- ranges : Each range corresponds to a single chipselect, and covers
the entire access window as configured.
Child device nodes describe the devices connected to IFC such as NOR (e.g.
cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
like FPGAs, CPLDs, etc.
Example:
ifc@ffe1e000 {
compatible = "fsl,ifc", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x0 0xffe1e000 0 0x2000>;
interrupts = <16 2 19 2>;
/* NOR, NAND Flashes and CPLD on board */
ranges = <0x0 0x0 0x0 0xee000000 0x02000000
0x1 0x0 0x0 0xffa00000 0x00010000
0x3 0x0 0x0 0xffb00000 0x00020000>;
flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x2000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
/* 32MB for user data */
reg = <0x0 0x02000000>;
label = "NOR Data";
};
};
flash@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,ifc-nand";
reg = <0x1 0x0 0x10000>;
partition@0 {
/* This location must not be altered */
/* 1MB for u-boot Bootloader Image */
reg = <0x0 0x00100000>;
label = "NAND U-Boot Image";
read-only;
};
};
cpld@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p1010rdb-cpld";
reg = <0x3 0x0 0x000001f>;
};
};

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Device tree bindings for MVEBU Device Bus controllers
The Device Bus controller available in some Marvell's SoC allows to control
different types of standard memory and I/O devices such as NOR, NAND, and FPGA.
The actual devices are instantiated from the child nodes of a Device Bus node.
Required properties:
- compatible: Armada 370/XP SoC are supported using the
"marvell,mvebu-devbus" compatible string.
Orion5x SoC are supported using the
"marvell,orion-devbus" compatible string.
- reg: A resource specifier for the register space.
This is the base address of a chip select within
the controller's register space.
(see the example below)
- #address-cells: Must be set to 1
- #size-cells: Must be set to 1
- ranges: Must be set up to reflect the memory layout with four
integer values for each chip-select line in use:
0 <physical address of mapping> <size>
Optional properties:
- devbus,keep-config This property can optionally be used to keep
using the timing parameters set by the
bootloader. It makes all the timing properties
described below unused.
Timing properties for child nodes:
Read parameters:
- devbus,turn-off-ps: Defines the time during which the controller does not
drive the AD bus after the completion of a device read.
This prevents contentions on the Device Bus after a read
cycle from a slow device.
Mandatory, except if devbus,keep-config is used.
- devbus,bus-width: Defines the bus width, in bits (e.g. <16>).
Mandatory, except if devbus,keep-config is used.
- devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
to read data sample. This parameter is useful for
synchronous pipelined devices, where the address
precedes the read data by one or two cycles.
Mandatory, except if devbus,keep-config is used.
- devbus,acc-first-ps: Defines the time delay from the negation of
ALE[0] to the cycle that the first read data is sampled
by the controller.
Mandatory, except if devbus,keep-config is used.
- devbus,acc-next-ps: Defines the time delay between the cycle that
samples data N and the cycle that samples data N+1
(in burst accesses).
Mandatory, except if devbus,keep-config is used.
- devbus,rd-setup-ps: Defines the time delay between DEV_CSn assertion to
DEV_OEn assertion. If set to 0 (default),
DEV_OEn and DEV_CSn are asserted at the same cycle.
This parameter has no affect on <acc-first-ps> parameter
(no affect on first data sample). Set <rd-setup-ps>
to a value smaller than <acc-first-ps>.
Mandatory for "marvell,mvebu-devbus" compatible string,
except if devbus,keep-config is used.
- devbus,rd-hold-ps: Defines the time between the last data sample to the
de-assertion of DEV_CSn. If set to 0 (default),
DEV_OEn and DEV_CSn are de-asserted at the same cycle
(the cycle of the last data sample).
This parameter has no affect on DEV_OEn de-assertion.
DEV_OEn is always de-asserted the next cycle after
last data sampled. Also this parameter has no
affect on <turn-off-ps> parameter.
Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
Mandatory for "marvell,mvebu-devbus" compatible string,
except if devbus,keep-config is used.
Write parameters:
- devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
to the DEV_WEn assertion.
Mandatory.
- devbus,wr-low-ps: Defines the time during which DEV_WEn is active.
A[2:0] and Data are kept valid as long as DEV_WEn
is active. This parameter defines the setup time of
address and data to DEV_WEn rise.
Mandatory.
- devbus,wr-high-ps: Defines the time during which DEV_WEn is kept
inactive (high) between data beats of a burst write.
DEV_A[2:0] and Data are kept valid (do not toggle) for
<wr-high-ps> - <tick> ps.
This parameter defines the hold time of address and
data after DEV_WEn rise.
Mandatory.
- devbus,sync-enable: Synchronous device enable.
1: True
0: False
Mandatory for "marvell,mvebu-devbus" compatible string,
except if devbus,keep-config is used.
An example for an Armada XP GP board, with a 16 MiB NOR device as child
is showed below. Note that the Device Bus driver is in charge of allocating
the mbus address decoding window for each of its child devices.
The window is created using the chip select specified in the child
device node together with the base address and size specified in the ranges
property. For instance, in the example below the allocated decoding window
will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
for chip select 0 (a.k.a DEV_BOOTCS).
This address window handling is done in this mvebu-devbus only as a temporary
solution. It will be removed when the support for mbus device tree binding is
added.
The reg property implicitly specifies the chip select as this:
0x10400: DEV_BOOTCS
0x10408: DEV_CS0
0x10410: DEV_CS1
0x10418: DEV_CS2
0x10420: DEV_CS3
Example:
devbus-bootcs@d0010400 {
status = "okay";
ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */
#address-cells = <1>;
#size-cells = <1>;
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
flash@0 {
compatible = "cfi-flash";
/* 16 MiB */
reg = <0 0x1000000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
/*
* We split the 16 MiB in two partitions,
* just as an example.
*/
partition@0 {
label = "First";
reg = <0 0x800000>;
};
partition@800000 {
label = "Second";
reg = <0x800000 0x800000>;
};
};
};

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Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
Required properties:
- compatible: Should be 'xlnx,zynq-ddrc-a05'
- reg: Base address and size of the controllers memory area
Example:
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};

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* Device tree bindings for Texas instruments AEMIF controller
The Async External Memory Interface (EMIF16/AEMIF) controller is intended to
provide a glue-less interface to a variety of asynchronous memory devices like
ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories
can be accessed at any given time via four chip selects with 64M byte access
per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM
and Mobile SDR are not supported.
Documentation:
Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
Required properties:
- compatible: "ti,davinci-aemif"
"ti,keystone-aemif"
"ti,da850-aemif"
- reg: contains offset/length value for AEMIF control registers
space.
- #address-cells: Must be 2. The partition number has to be encoded in the
first address cell and it may accept values 0..N-1
(N - total number of partitions). It's recommended to
assign N-1 number for the control partition. The second
cell is the offset into the partition.
- #size-cells: Must be set to 1.
- ranges: Contains memory regions. There are two types of
ranges/partitions:
- CS-specific partition/range. If continuous, must be
set up to reflect the memory layout for 4 chipselects,
if not then additional range/partition can be added and
child device can select the proper one.
- control partition which is common for all CS
interfaces.
- clocks: the clock feeding the controller clock. Required only
if clock tree data present in device tree.
See clock-bindings.txt
- clock-names: clock name. It has to be "aemif". Required only if clock
tree data present in device tree, in another case don't
use it.
See clock-bindings.txt
- clock-ranges: Empty property indicating that child nodes can inherit
named clocks. Required only if clock tree data present
in device tree.
See clock-bindings.txt
Child chip-select (cs) nodes contain the memory devices nodes connected to
such as NOR (e.g. cfi-flash) and NAND (ti,davinci-nand, see davinci-nand.txt).
There might be board specific devices like FPGAs.
Required child cs node properties:
- #address-cells: Must be 2.
- #size-cells: Must be 1.
- ranges: Empty property indicating that child nodes can inherit
memory layout.
- clock-ranges: Empty property indicating that child nodes can inherit
named clocks. Required only if clock tree data present
in device tree.
- ti,cs-chipselect: number of chipselect. Indicates on the aemif driver
which chipselect is used for accessing the memory. For
compatibles "ti,davinci-aemif" and "ti,keystone-aemif"
it can be in range [0-3]. For compatible
"ti,da850-aemif" range is [2-5].
Optional child cs node properties:
- ti,cs-bus-width: width of the asynchronous device's data bus
8 or 16 if not preset 8
- ti,cs-select-strobe-mode: enable/disable select strobe mode
In select strobe mode chip select behaves as
the strobe and is active only during the strobe
period. If present then enable.
- ti,cs-extended-wait-mode: enable/disable extended wait mode
if set, the controller monitors the EMIFWAIT pin
mapped to that chip select to determine if the
device wants to extend the strobe period. If
present then enable.
- ti,cs-min-turnaround-ns: minimum turn around time, ns
Time between the end of one asynchronous memory
access and the start of another asynchronous
memory access. This delay is not incurred
between a read followed by read or a write
followed by a write to same chip select.
- ti,cs-read-setup-ns: read setup width, ns
Time between the beginning of a memory cycle
and the activation of read strobe.
Minimum value is 1 (0 treated as 1).
- ti,cs-read-strobe-ns: read strobe width, ns
Time between the activation and deactivation of
the read strobe.
Minimum value is 1 (0 treated as 1).
- ti,cs-read-hold-ns: read hold width, ns
Time between the deactivation of the read
strobe and the end of the cycle (which may be
either an address change or the deactivation of
the chip select signal.
Minimum value is 1 (0 treated as 1).
- ti,cs-write-setup-ns: write setup width, ns
Time between the beginning of a memory cycle
and the activation of write strobe.
Minimum value is 1 (0 treated as 1).
- ti,cs-write-strobe-ns: write strobe width, ns
Time between the activation and deactivation of
the write strobe.
Minimum value is 1 (0 treated as 1).
- ti,cs-write-hold-ns: write hold width, ns
Time between the deactivation of the write
strobe and the end of the cycle (which may be
either an address change or the deactivation of
the chip select signal.
Minimum value is 1 (0 treated as 1).
If any of the above parameters are absent, current parameter value will be taken
from the corresponding HW reg.
Example for aemif, davinci nand and nor flash chip select shown below.
memory-controller@21000A00 {
compatible = "ti,davinci-aemif";
#address-cells = <2>;
#size-cells = <1>;
clocks = <&clkaemif 0>;
clock-names = "aemif";
clock-ranges;
reg = <0x21000A00 0x00000100>;
ranges = <0 0 0x70000000 0x10000000
1 0 0x21000A00 0x00000100>;
/*
* Partition0: CS-specific memory range which is
* implemented as continuous physical memory region
* Partition1: control memory range
*/
nand:cs2 {
#address-cells = <2>;
#size-cells = <1>;
clock-ranges;
ranges;
ti,cs-chipselect = <2>;
/* all timings in nanoseconds */
ti,cs-min-turnaround-ns = <0>;
ti,cs-read-hold-ns = <7>;
ti,cs-read-strobe-ns = <42>;
ti,cs-read-setup-ns = <14>;
ti,cs-write-hold-ns = <7>;
ti,cs-write-strobe-ns = <42>;
ti,cs-write-setup-ns = <14>;
nand@0,0x8000000 {
compatible = "ti,davinci-nand";
reg = <0 0x8000000 0x4000000
1 0x0000000 0x0000100>;
/*
* Partition0, offset 0x8000000, size 0x4000000
* Partition1, offset 0x0000000, size 0x0000100
*/
.. see davinci-nand.txt
};
};
nor:cs0 {
#address-cells = <2>;
#size-cells = <1>;
clock-ranges;
ranges;
ti,cs-chipselect = <0>;
/* all timings in nanoseconds */
ti,cs-min-turnaround-ns = <0>;
ti,cs-read-hold-ns = <8>;
ti,cs-read-strobe-ns = <40>;
ti,cs-read-setup-ns = <14>;
ti,cs-write-hold-ns = <7>;
ti,cs-write-strobe-ns = <40>;
ti,cs-write-setup-ns = <14>;
ti,cs-bus-width = <16>;
flash@0,0x0000000 {
compatible = "cfi-flash";
reg = <0 0x0000000 0x4000000>;
...
};
};
};

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* EMIF family of TI SDRAM controllers
EMIF - External Memory Interface - is an SDRAM controller used in
TI SoCs. EMIF supports, based on the IP revision, one or more of
DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
of the EMIF IP and memory parts attached to it.
Required properties:
- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
is the IP revision of the specific EMIF instance.
- phy-type : <u32> indicating the DDR phy type. Following are the
allowed values
<1> : Attila PHY
<2> : Intelli PHY
- device-handle : phandle to a "lpddr2" node representing the memory part
- ti,hwmods : For TI hwmods processing and omap device creation
the value shall be "emif<n>" where <n> is the number of the EMIF
instance with base 1.
Optional properties:
- cs1-used : Have this property if CS1 of this EMIF
instance has a memory part attached to it. If there is a memory
part attached to CS1, it should be the same type as the one on CS0,
so there is no need to give the details of this memory part.
- cal-resistor-per-cs : Have this property if the board has one
calibration resistor per chip-select.
- hw-caps-read-idle-ctrl: Have this property if the controller
supports read idle window programming
- hw-caps-dll-calib-ctrl: Have this property if the controller
supports dll calibration control
- hw-caps-ll-interface : Have this property if the controller
has a low latency interface and corresponding interrupt events
- hw-caps-temp-alert : Have this property if the controller
has capability for generating SDRAM temperature alerts
Example:
emif1: emif@0x4c000000 {
compatible = "ti,emif-4d";
ti,hwmods = "emif2";
phy-type = <1>;
device-handle = <&elpida_ECB240ABACN>;
cs1-used;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
};