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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
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80
Documentation/devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt Normal file
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Abilis Systems TB10x pin controller
===================================
Required properties
-------------------
- compatible: should be "abilis,tb10x-iomux";
- reg: should contain the physical address and size of the pin controller's
register range.
Function definitions
--------------------
Functions are defined (and referenced) by sub-nodes of the pin controller.
Every sub-node defines exactly one function (implying a set of pins).
Every function is associated to one named pin group inside the pin controller
driver and these names are used to associate pin group predefinitions to pin
controller sub-nodes.
Required function definition subnode properties:
- abilis,function: should be set to the name of the function's pin group.
The following pin groups are available:
- GPIO ports: gpioa, gpiob, gpioc, gpiod, gpioe, gpiof, gpiog,
gpioh, gpioi, gpioj, gpiok, gpiol, gpiom, gpion
- Serial TS input ports: mis0, mis1, mis2, mis3, mis4, mis5, mis6, mis7
- Parallel TS input ports: mip1, mip3, mip5, mip7
- Serial TS output ports: mos0, mos1, mos2, mos3
- Parallel TS output port: mop
- CI+ port: ciplus
- CableCard (Mcard) port: mcard
- Smart card ports: stc0, stc1
- UART ports: uart0, uart1
- SPI ports: spi1, spi3
- JTAG: jtag
All other ports of the chip are not multiplexed and thus not managed by this
driver.
GPIO ranges definition
----------------------
The named pin groups of GPIO ports can be used to define GPIO ranges as
explained in Documentation/devicetree/bindings/gpio/gpio.txt.
Example
-------
iomux: iomux@FF10601c {
compatible = "abilis,tb10x-iomux";
reg = <0xFF10601c 0x4>;
pctl_gpio_a: pctl-gpio-a {
abilis,function = "gpioa";
};
pctl_uart0: pctl-uart0 {
abilis,function = "uart0";
};
};
uart@FF100000 {
compatible = "snps,dw-apb-uart";
reg = <0xFF100000 0x100>;
clock-frequency = <166666666>;
interrupts = <25 1>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pctl_uart0>;
};
gpioa: gpio@FF140000 {
compatible = "abilis,tb10x-gpio";
reg = <0xFF140000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
ngpio = <3>;
gpio-ranges = <&iomux 0 0>;
gpio-ranges-group-names = "gpioa";
};

67
Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt Normal file
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* Allwinner A1X Pin Controller
The pins controlled by sunXi pin controller are organized in banks,
each bank has 32 pins. Each pin has 7 multiplexing functions, with
the first two functions being GPIO in and out. The configuration on
the pins includes drive strength and pull-up.
Required properties:
- compatible: Should be one of the followings (depending on you SoC):
"allwinner,sun4i-a10-pinctrl"
"allwinner,sun5i-a10s-pinctrl"
"allwinner,sun5i-a13-pinctrl"
"allwinner,sun6i-a31-pinctrl"
"allwinner,sun6i-a31-r-pinctrl"
"allwinner,sun7i-a20-pinctrl"
"allwinner,sun8i-a23-pinctrl"
"allwinner,sun8i-a23-r-pinctrl"
- reg: Should contain the register physical address and length for the
pin controller.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, drive strength and pullups. If one of these options is
not set, its actual value will be unspecified.
Required subnode-properties:
- allwinner,pins: List of strings containing the pin name.
- allwinner,function: Function to mux the pins listed above to.
Optional subnode-properties:
- allwinner,drive: Integer. Represents the current sent to the pin
0: 10 mA
1: 20 mA
2: 30 mA
3: 40 mA
- allwinner,pull: Integer.
0: No resistor
1: Pull-up resistor
2: Pull-down resistor
Examples:
pinctrl@01c20800 {
compatible = "allwinner,sun5i-a13-pinctrl";
reg = <0x01c20800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
uart1_pins_a: uart1@0 {
allwinner,pins = "PE10", "PE11";
allwinner,function = "uart1";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
uart1_pins_b: uart1@1 {
allwinner,pins = "PG3", "PG4";
allwinner,function = "uart1";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
};

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Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt Normal file
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* Atmel AT91 Pinmux Controller
The AT91 Pinmux Controller, enables the IC
to share one PAD to several functional blocks. The sharing is done by
multiplexing the PAD input/output signals. For each PAD there are up to
8 muxing options (called periph modes). Since different modules require
different PAD settings (like pull up, keeper, etc) the contoller controls
also the PAD settings parameters.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Atmel AT91 pin configuration node is a node of a group of pins which can be
used for a specific device or function. This node represents both mux and config
of the pins in that group. The 'pins' selects the function mode(also named pin
mode) this pin can work on and the 'config' configures various pad settings
such as pull-up, multi drive, etc.
Required properties for iomux controller:
- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
or "atmel,sama5d3-pinctrl"
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
configured in this periph mode. All the periph and bank need to be describe.
How to create such array:
Each column will represent the possible peripheral of the pinctrl
Each line will represent a pio bank
Take an example on the 9260
Peripheral: 2 ( A and B)
Bank: 3 (A, B and C)
=>
/* A B */
0xffffffff 0xffc00c3b /* pioA */
0xffffffff 0x7fff3ccf /* pioB */
0xffffffff 0x007fffff /* pioC */
For each peripheral/bank we will descibe in a u32 if a pin can be
configured in it by putting 1 to the pin bit (1 << pin)
Let's take the pioA on peripheral B
From the datasheet Table 10-2.
Peripheral B
PA0 MCDB0
PA1 MCCDB
PA2
PA3 MCDB3
PA4 MCDB2
PA5 MCDB1
PA6
PA7
PA8
PA9
PA10 ETX2
PA11 ETX3
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22 ETXER
PA23 ETX2
PA24 ETX3
PA25 ERX2
PA26 ERX3
PA27 ERXCK
PA28 ECRS
PA29 ECOL
PA30 RXD4
PA31 TXD4
=> 0xffc00c3b
Required properties for pin configuration node:
- atmel,pins: 4 integers array, represents a group of pins mux and config
setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
Bits used for CONFIG:
PULL_UP (1 << 0): indicate this pin needs a pull up.
MULTIDRIVE (1 << 1): indicate this pin needs to be configured as multi-drive.
Multi-drive is equivalent to open-drain type output.
DEGLITCH (1 << 2): indicate this pin needs deglitch.
PULL_DOWN (1 << 3): indicate this pin needs a pull down.
DIS_SCHMIT (1 << 4): indicate this pin needs to the disable schmitt trigger.
DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the
following values:
00 - No change (reset state value kept)
01 - Low
10 - Medium
11 - High
DEBOUNCE (1 << 16): indicate this pin needs debounce.
DEBOUNCE_VAL (0x3fff << 17): debounce value.
NOTE:
Some requirements for using atmel,at91rm9200-pinctrl binding:
1. We have pin function node defined under at91 controller node to represent
what pinmux functions this SoC supports.
2. The driver can use the function node's name and pin configuration node's
name describe the pin function and group hierarchy.
For example, Linux at91 pinctrl driver takes the function node's name
as the function name and pin configuration node's name as group name to
create the map table.
3. Each pin configuration node should have a phandle, devices can set pins
configurations by referring to the phandle of that pin configuration node.
4. The gpio controller must be describe in the pinctrl simple-bus.
Examples:
pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
reg = <0xfffff400 0x600>;
atmel,mux-mask = <
/* A B */
0xffffffff 0xffc00c3b /* pioA */
0xffffffff 0x7fff3ccf /* pioB */
0xffffffff 0x007fffff /* pioC */
>;
/* shared pinctrl settings */
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<1 14 0x1 0x0 /* PB14 periph A */
1 15 0x1 0x1>; /* PB15 periph A with pullup */
};
};
};
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
interrupts = <1 4 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
status = "disabled";
};

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Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt Normal file
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Broadcom BCM281xx Pin Controller
This is a pin controller for the Broadcom BCM281xx SoC family, which includes
BCM11130, BCM11140, BCM11351, BCM28145, and BCM28155 SoCs.
=== Pin Controller Node ===
Required Properties:
- compatible: Must be "brcm,bcm11351-pinctrl"
- reg: Base address of the PAD Controller register block and the size
of the block.
For example, the following is the bare minimum node:
pinctrl@35004800 {
compatible = "brcm,bcm11351-pinctrl";
reg = <0x35004800 0x430>;
};
As a pin controller device, in addition to the required properties, this node
should also contain the pin configuration nodes that client devices reference,
if any.
=== Pin Configuration Node ===
Each pin configuration node is a sub-node of the pin controller node and is a
container of an arbitrary number of subnodes, called pin group nodes in this
document.
Please refer to the pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the definition of a
"pin configuration node".
=== Pin Group Node ===
A pin group node specifies the desired pin mux and/or pin configuration for an
arbitrary number of pins. The name of the pin group node is optional and not
used.
A pin group node only affects the properties specified in the node, and has no
effect on any properties that are omitted.
The pin group node accepts a subset of the generic pin config properties. For
details generic pin config properties, please refer to pinctrl-bindings.txt
and <include/linux/pinctrl/pinconfig-generic.h>.
Each pin controlled by this pin controller belong to one of three types:
Standard, I2C, and HDMI. Each type accepts a different set of pin config
properties. A list of pins and their types is provided below.
Required Properties (applicable to all pins):
- pins: Multiple strings. Specifies the name(s) of one or more pins to
be configured by this node.
Optional Properties (for standard pins):
- function: String. Specifies the pin mux selection. Values
must be one of: "alt1", "alt2", "alt3", "alt4"
- input-schmitt-enable: No arguments. Enable schmitt-trigger mode.
- input-schmitt-disable: No arguments. Disable schmitt-trigger mode.
- bias-pull-up: No arguments. Pull up on pin.
- bias-pull-down: No arguments. Pull down on pin.
- bias-disable: No arguments. Disable pin bias.
- slew-rate: Integer. Meaning depends on configured pin mux:
*_SCL or *_SDA:
0: Standard(100kbps)& Fast(400kbps) mode
1: Highspeed (3.4Mbps) mode
IC_DM or IC_DP:
0: normal slew rate
1: fast slew rate
Otherwise:
0: fast slew rate
1: normal slew rate
- input-enable: No arguments. Enable input (does not affect
output.)
- input-disable: No arguments. Disable input (does not affect
output.)
- drive-strength: Integer. Drive strength in mA. Valid values are
2, 4, 6, 8, 10, 12, 14, 16 mA.
Optional Properties (for I2C pins):
- function: String. Specifies the pin mux selection. Values
must be one of: "alt1", "alt2", "alt3", "alt4"
- bias-pull-up: Integer. Pull up strength in Ohm. There are 3
pull-up resisitors (1.2k, 1.8k, 2.7k) available
in parallel for I2C pins, so the valid values
are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm.
- bias-disable: No arguments. Disable pin bias.
- slew-rate: Integer. Meaning depends on configured pin mux:
*_SCL or *_SDA:
0: Standard(100kbps)& Fast(400kbps) mode
1: Highspeed (3.4Mbps) mode
IC_DM or IC_DP:
0: normal slew rate
1: fast slew rate
Otherwise:
0: fast slew rate
1: normal slew rate
- input-enable: No arguments. Enable input (does not affect
output.)
- input-disable: No arguments. Disable input (does not affect
output.)
Optional Properties (for HDMI pins):
- function: String. Specifies the pin mux selection. Values
must be one of: "alt1", "alt2", "alt3", "alt4"
- slew-rate: Integer. Controls slew rate.
0: Standard(100kbps)& Fast(400kbps) mode
1: Highspeed (3.4Mbps) mode
- input-enable: No arguments. Enable input (does not affect
output.)
- input-disable: No arguments. Disable input (does not affect
output.)
Example:
// pin controller node
pinctrl@35004800 {
compatible = "brcm,bcm11351-pinctrl";
reg = <0x35004800 0x430>;
// pin configuration node
dev_a_default: dev_a_active {
//group node defining 1 standard pin
grp_1 {
pins = "std_pin1";
function = "alt1";
input-schmitt-enable;
bias-disable;
slew-rate = <1>;
drive-strength = <4>;
};
// group node defining 2 I2C pins
grp_2 {
pins = "i2c_pin1", "i2c_pin2";
function = "alt2";
bias-pull-up = <720>;
input-enable;
};
// group node defining 2 HDMI pins
grp_3 {
pins = "hdmi_pin1", "hdmi_pin2";
function = "alt3";
slew-rate = <1>;
};
// other pin group nodes
...
};
// other pin configuration nodes
...
};
In the example above, "dev_a_active" is a pin configuration node with a number
of sub-nodes. In the pin group node "grp_1", one pin, "std_pin1", is defined in
the "pins" property. Thus, the remaining properties in the "grp_1" node applies
only to this pin, including the following settings:
- setting pinmux to "alt1"
- enabling schmitt-trigger (hystersis) mode
- disabling pin bias
- setting the slew-rate to 1
- setting the drive strength to 4 mA
Note that neither "input-enable" nor "input-disable" was specified - the pinctrl
subsystem will therefore leave this property unchanged from whatever state it
was in before applying these changes.
The "pins" property in the pin group node "grp_2" specifies two pins -
"i2c_pin1" and "i2c_pin2"; the remaining properties in this pin group node,
therefore, applies to both of these pins. The properties include:
- setting pinmux to "alt2"
- setting pull-up resistance to 720 Ohm (ie. enabling 1.2k and 1.8k resistors
in parallel)
- enabling both pins' input
"slew-rate" is not specified in this pin group node, so the slew-rate for these
pins are left as-is.
Finally, "grp_3" defines two HDMI pins. The following properties are applied to
both pins:
- setting pinmux to "alt3"
- setting slew-rate to 1; for HDMI pins, this corresponds to the 3.4 Mbps
Highspeed mode
The input is neither enabled or disabled, and is left untouched.
=== Pin Names and Type ===
The following are valid pin names and their pin types:
"adcsync", Standard
"bat_rm", Standard
"bsc1_scl", I2C
"bsc1_sda", I2C
"bsc2_scl", I2C
"bsc2_sda", I2C
"classgpwr", Standard
"clk_cx8", Standard
"clkout_0", Standard
"clkout_1", Standard
"clkout_2", Standard
"clkout_3", Standard
"clkreq_in_0", Standard
"clkreq_in_1", Standard
"cws_sys_req1", Standard
"cws_sys_req2", Standard
"cws_sys_req3", Standard
"digmic1_clk", Standard
"digmic1_dq", Standard
"digmic2_clk", Standard
"digmic2_dq", Standard
"gpen13", Standard
"gpen14", Standard
"gpen15", Standard
"gpio00", Standard
"gpio01", Standard
"gpio02", Standard
"gpio03", Standard
"gpio04", Standard
"gpio05", Standard
"gpio06", Standard
"gpio07", Standard
"gpio08", Standard
"gpio09", Standard
"gpio10", Standard
"gpio11", Standard
"gpio12", Standard
"gpio13", Standard
"gpio14", Standard
"gps_pablank", Standard
"gps_tmark", Standard
"hdmi_scl", HDMI
"hdmi_sda", HDMI
"ic_dm", Standard
"ic_dp", Standard
"kp_col_ip_0", Standard
"kp_col_ip_1", Standard
"kp_col_ip_2", Standard
"kp_col_ip_3", Standard
"kp_row_op_0", Standard
"kp_row_op_1", Standard
"kp_row_op_2", Standard
"kp_row_op_3", Standard
"lcd_b_0", Standard
"lcd_b_1", Standard
"lcd_b_2", Standard
"lcd_b_3", Standard
"lcd_b_4", Standard
"lcd_b_5", Standard
"lcd_b_6", Standard
"lcd_b_7", Standard
"lcd_g_0", Standard
"lcd_g_1", Standard
"lcd_g_2", Standard
"lcd_g_3", Standard
"lcd_g_4", Standard
"lcd_g_5", Standard
"lcd_g_6", Standard
"lcd_g_7", Standard
"lcd_hsync", Standard
"lcd_oe", Standard
"lcd_pclk", Standard
"lcd_r_0", Standard
"lcd_r_1", Standard
"lcd_r_2", Standard
"lcd_r_3", Standard
"lcd_r_4", Standard
"lcd_r_5", Standard
"lcd_r_6", Standard
"lcd_r_7", Standard
"lcd_vsync", Standard
"mdmgpio0", Standard
"mdmgpio1", Standard
"mdmgpio2", Standard
"mdmgpio3", Standard
"mdmgpio4", Standard
"mdmgpio5", Standard
"mdmgpio6", Standard
"mdmgpio7", Standard
"mdmgpio8", Standard
"mphi_data_0", Standard
"mphi_data_1", Standard
"mphi_data_2", Standard
"mphi_data_3", Standard
"mphi_data_4", Standard
"mphi_data_5", Standard
"mphi_data_6", Standard
"mphi_data_7", Standard
"mphi_data_8", Standard
"mphi_data_9", Standard
"mphi_data_10", Standard
"mphi_data_11", Standard
"mphi_data_12", Standard
"mphi_data_13", Standard
"mphi_data_14", Standard
"mphi_data_15", Standard
"mphi_ha0", Standard
"mphi_hat0", Standard
"mphi_hat1", Standard
"mphi_hce0_n", Standard
"mphi_hce1_n", Standard
"mphi_hrd_n", Standard
"mphi_hwr_n", Standard
"mphi_run0", Standard
"mphi_run1", Standard
"mtx_scan_clk", Standard
"mtx_scan_data", Standard
"nand_ad_0", Standard
"nand_ad_1", Standard
"nand_ad_2", Standard
"nand_ad_3", Standard
"nand_ad_4", Standard
"nand_ad_5", Standard
"nand_ad_6", Standard
"nand_ad_7", Standard
"nand_ale", Standard
"nand_cen_0", Standard
"nand_cen_1", Standard
"nand_cle", Standard
"nand_oen", Standard
"nand_rdy_0", Standard
"nand_rdy_1", Standard
"nand_wen", Standard
"nand_wp", Standard
"pc1", Standard
"pc2", Standard
"pmu_int", Standard
"pmu_scl", I2C
"pmu_sda", I2C
"rfst2g_mtsloten3g", Standard
"rgmii_0_rx_ctl", Standard
"rgmii_0_rxc", Standard
"rgmii_0_rxd_0", Standard
"rgmii_0_rxd_1", Standard
"rgmii_0_rxd_2", Standard
"rgmii_0_rxd_3", Standard
"rgmii_0_tx_ctl", Standard
"rgmii_0_txc", Standard
"rgmii_0_txd_0", Standard
"rgmii_0_txd_1", Standard
"rgmii_0_txd_2", Standard
"rgmii_0_txd_3", Standard
"rgmii_1_rx_ctl", Standard
"rgmii_1_rxc", Standard
"rgmii_1_rxd_0", Standard
"rgmii_1_rxd_1", Standard
"rgmii_1_rxd_2", Standard
"rgmii_1_rxd_3", Standard
"rgmii_1_tx_ctl", Standard
"rgmii_1_txc", Standard
"rgmii_1_txd_0", Standard
"rgmii_1_txd_1", Standard
"rgmii_1_txd_2", Standard
"rgmii_1_txd_3", Standard
"rgmii_gpio_0", Standard
"rgmii_gpio_1", Standard
"rgmii_gpio_2", Standard
"rgmii_gpio_3", Standard
"rtxdata2g_txdata3g1", Standard
"rtxen2g_txdata3g2", Standard
"rxdata3g0", Standard
"rxdata3g1", Standard
"rxdata3g2", Standard
"sdio1_clk", Standard
"sdio1_cmd", Standard
"sdio1_data_0", Standard
"sdio1_data_1", Standard
"sdio1_data_2", Standard
"sdio1_data_3", Standard
"sdio4_clk", Standard
"sdio4_cmd", Standard
"sdio4_data_0", Standard
"sdio4_data_1", Standard
"sdio4_data_2", Standard
"sdio4_data_3", Standard
"sim_clk", Standard
"sim_data", Standard
"sim_det", Standard
"sim_resetn", Standard
"sim2_clk", Standard
"sim2_data", Standard
"sim2_det", Standard
"sim2_resetn", Standard
"sri_c", Standard
"sri_d", Standard
"sri_e", Standard
"ssp_extclk", Standard
"ssp0_clk", Standard
"ssp0_fs", Standard
"ssp0_rxd", Standard
"ssp0_txd", Standard
"ssp2_clk", Standard
"ssp2_fs_0", Standard
"ssp2_fs_1", Standard
"ssp2_fs_2", Standard
"ssp2_fs_3", Standard
"ssp2_rxd_0", Standard
"ssp2_rxd_1", Standard
"ssp2_txd_0", Standard
"ssp2_txd_1", Standard
"ssp3_clk", Standard
"ssp3_fs", Standard
"ssp3_rxd", Standard
"ssp3_txd", Standard
"ssp4_clk", Standard
"ssp4_fs", Standard
"ssp4_rxd", Standard
"ssp4_txd", Standard
"ssp5_clk", Standard
"ssp5_fs", Standard
"ssp5_rxd", Standard
"ssp5_txd", Standard
"ssp6_clk", Standard
"ssp6_fs", Standard
"ssp6_rxd", Standard
"ssp6_txd", Standard
"stat_1", Standard
"stat_2", Standard
"sysclken", Standard
"traceclk", Standard
"tracedt00", Standard
"tracedt01", Standard
"tracedt02", Standard
"tracedt03", Standard
"tracedt04", Standard
"tracedt05", Standard
"tracedt06", Standard
"tracedt07", Standard
"tracedt08", Standard
"tracedt09", Standard
"tracedt10", Standard
"tracedt11", Standard
"tracedt12", Standard
"tracedt13", Standard
"tracedt14", Standard
"tracedt15", Standard
"txdata3g0", Standard
"txpwrind", Standard
"uartb1_ucts", Standard
"uartb1_urts", Standard
"uartb1_urxd", Standard
"uartb1_utxd", Standard
"uartb2_urxd", Standard
"uartb2_utxd", Standard
"uartb3_ucts", Standard
"uartb3_urts", Standard
"uartb3_urxd", Standard
"uartb3_utxd", Standard
"uartb4_ucts", Standard
"uartb4_urts", Standard
"uartb4_urxd", Standard
"uartb4_utxd", Standard
"vc_cam1_scl", I2C
"vc_cam1_sda", I2C
"vc_cam2_scl", I2C
"vc_cam2_sda", I2C
"vc_cam3_scl", I2C
"vc_cam3_sda", I2C

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Broadcom BCM2835 GPIO (and pinmux) controller
The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
controller, and pinmux/control device.
Required properties:
- compatible: "brcm,bcm2835-gpio"
- reg: Should contain the physical address of the GPIO module's registers.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters:
- bit 0 specifies polarity (0 for normal, 1 for inverted)
- interrupts : The interrupt outputs from the controller. One interrupt per
individual bank followed by the "all banks" interrupt.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells : Should be 2.
The first cell is the GPIO number.
The second cell is used to specify flags:
bits[3:0] trigger type and level flags:
1 = low-to-high edge triggered.
2 = high-to-low edge triggered.
4 = active high level-sensitive.
8 = active low level-sensitive.
Valid combinations are 1, 2, 3, 4, 8.
Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Each pin configuration node lists the pin(s) to which it applies, and one or
more of the mux function to select on those pin(s), and pull-up/down
configuration. Each subnode only affects those parameters that are explicitly
listed. In other words, a subnode that lists only a mux function implies no
information about any pull configuration. Similarly, a subnode that lists only
a pul parameter implies no information about the mux function.
Required subnode-properties:
- brcm,pins: An array of cells. Each cell contains the ID of a pin. Valid IDs
are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53.
Optional subnode-properties:
- brcm,function: Integer, containing the function to mux to the pin(s):
0: GPIO in
1: GPIO out
2: alt5
3: alt4
4: alt0
5: alt1
6: alt2
7: alt3
- brcm,pull: Integer, representing the pull-down/up to apply to the pin(s):
0: none
1: down
2: up
Each of brcm,function and brcm,pull may contain either a single value which
will be applied to all pins in brcm,pins, or 1 value for each entry in
brcm,pins.
Example:
gpio: gpio {
compatible = "brcm,bcm2835-gpio";
reg = <0x2200000 0xb4>;
interrupts = <2 17>, <2 19>, <2 18>, <2 20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

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* Freescale IOMUX Controller (IOMUXC) for i.MX
The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
to share one PAD to several functional blocks. The sharing is done by
multiplexing the PAD input/output signals. For each PAD there are up to
8 muxing options (called ALT modes). Since different modules require
different PAD settings (like pull up, keeper, etc) the IOMUXC controls
also the PAD settings parameters.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Freescale IMX pin configuration node is a node of a group of pins which can be
used for a specific device or function. This node represents both mux and config
of the pins in that group. The 'mux' selects the function mode(also named mux
mode) this pin can work on and the 'config' configures various pad settings
such as pull-up, open drain, drive strength, etc.
Required properties for iomux controller:
- compatible: "fsl,<soc>-iomuxc"
Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
Required properties for pin configuration node:
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
the pad setting value like pull-up on this pin. And that's why fsl,pins entry
looks like <PIN_FUNC_ID CONFIG> in the example below.
Bits used for CONFIG:
NO_PAD_CTL(1 << 31): indicate this pin does not need config.
SION(1 << 30): Software Input On Field.
Force the selected mux mode input path no matter of MUX_MODE functionality.
By default the input path is determined by functionality of the selected
mux mode (regular).
Other bits are used for PAD setting.
Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
of bits definitions.
NOTE:
Some requirements for using fsl,imx-pinctrl binding:
1. We have pin function node defined under iomux controller node to represent
what pinmux functions this SoC supports.
2. The pin configuration node intends to work on a specific function should
to be defined under that specific function node.
The function node's name should represent well about what function
this group of pins in this pin configuration node are working on.
3. The driver can use the function node's name and pin configuration node's
name describe the pin function and group hierarchy.
For example, Linux IMX pinctrl driver takes the function node's name
as the function name and pin configuration node's name as group name to
create the map table.
4. Each pin configuration node should have a phandle, devices can set pins
configurations by referring to the phandle of that pin configuration node.
Examples:
usdhc@0219c000 { /* uSDHC4 */
non-removable;
vmmc-supply = <&reg_3p3v>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4_1>;
};
iomuxc@020e0000 {
compatible = "fsl,imx6q-iomuxc";
reg = <0x020e0000 0x4000>;
/* shared pinctrl settings */
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
....
};
Refer to the IOMUXC controller chapter in imx6q datasheet,
0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,
80Ohm driver strength and Fast Slew Rate.
User should refer to each SoC spec to set the correct value.

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* Freescale IMX25 IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
CONFIG bits definition:
PAD_CTL_HYS (1 << 8)
PAD_CTL_PKE (1 << 7)
PAD_CTL_PUE (1 << 6)
PAD_CTL_PUS_100K_DOWN (0 << 4)
PAD_CTL_PUS_47K_UP (1 << 4)
PAD_CTL_PUS_100K_UP (2 << 4)
PAD_CTL_PUS_22K_UP (3 << 4)
PAD_CTL_ODE_CMOS (0 << 3)
PAD_CTL_ODE_OPENDRAIN (1 << 3)
PAD_CTL_DSE_NOMINAL (0 << 1)
PAD_CTL_DSE_HIGH (1 << 1)
PAD_CTL_DSE_MAX (2 << 1)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
Refer to imx25-pinfunc.h in device tree source folder for all available
imx25 PIN_FUNC_ID.

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* Freescale IMX27 IOMUX Controller
Required properties:
- compatible: "fsl,imx27-iomuxc"
The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
Required properties for pin configuration node:
- fsl,pins: three integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
number on the specific port (between 0 and 31).
MUX_ID is
function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
function value is used to select the pin function.
Possible values:
0 - Primary function
1 - Alternate function
2 - GPIO
Registers: GIUS (GPIO In Use), GPR (General Purpose Register)
direction defines the data direction of the pin.
Possible values:
0 - Input
1 - Output
Register: DDIR
gpio_oconf configures the gpio submodule output signal. This does not
have any effect unless GPIO function is selected. A/B/C_IN are output
signals of function blocks A,B and C. Specific function blocks are
described in the reference manual.
Possible values:
0 - A_IN
1 - B_IN
2 - C_IN
3 - Data Register
Registers: OCR1, OCR2
gpio_iconfa/b configures the gpio submodule input to functionblocks A and
B. GPIO function should be selected if this is configured.
Possible values:
0 - GPIO_IN
1 - Interrupt Status Register
2 - Pulldown
3 - Pullup
Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
CONFIG can be 0 or 1, meaning Pullup disable/enable.
The iomux controller has gpio child nodes which are embedded in the iomux
control registers. They have to be defined as child nodes of the iomux device
node. If gpio subnodes are defined "#address-cells", "#size-cells" and "ranges"
properties for the iomux device node are required.
Example:
iomuxc: iomuxc@10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio1: gpio@10015000 {
...
};
...
uart {
pinctrl_uart1: uart-1 {
fsl,pins = <
0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
>;
};
...
};
};
For convenience there are macros defined in imx27-pinfunc.h which provide PIN
and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
are defined in the i.MX27 reference manual.
The above example using macros:
iomuxc: iomuxc@10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio1: gpio@10015000 {
...
};
...
uart {
pinctrl_uart1: uart-1 {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
MX27_PAD_UART1_CTS__UART1_CTS 0x0
MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
...
};
};

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* Freescale IMX35 IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx35-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
pin working on a specific function, CONFIG is the pad setting value like
pull-up for this pin. Please refer to imx35 datasheet for the valid pad
config settings.
CONFIG bits definition:
PAD_CTL_DRIVE_VOLAGAGE_18 (1 << 13)
PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13)
PAD_CTL_HYS (1 << 8)
PAD_CTL_PKE (1 << 7)
PAD_CTL_PUE (1 << 6)
PAD_CTL_PUS_100K_DOWN (0 << 4)
PAD_CTL_PUS_47K_UP (1 << 4)
PAD_CTL_PUS_100K_UP (2 << 4)
PAD_CTL_PUS_22K_UP (3 << 4)
PAD_CTL_ODE_CMOS (0 << 3)
PAD_CTL_ODE_OPENDRAIN (1 << 3)
PAD_CTL_DSE_NOMINAL (0 << 1)
PAD_CTL_DSE_HIGH (1 << 1)
PAD_CTL_DSE_MAX (2 << 1)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
Refer to imx35-pinfunc.h in device tree source folder for all available
imx35 PIN_FUNC_ID.

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* Freescale IMX51 IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx51-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
pin working on a specific function, CONFIG is the pad setting value like
pull-up for this pin. Please refer to imx51 datasheet for the valid pad
config settings.
CONFIG bits definition:
PAD_CTL_HVE (1 << 13)
PAD_CTL_HYS (1 << 8)
PAD_CTL_PKE (1 << 7)
PAD_CTL_PUE (1 << 6)
PAD_CTL_PUS_100K_DOWN (0 << 4)
PAD_CTL_PUS_47K_UP (1 << 4)
PAD_CTL_PUS_100K_UP (2 << 4)
PAD_CTL_PUS_22K_UP (3 << 4)
PAD_CTL_ODE (1 << 3)
PAD_CTL_DSE_LOW (0 << 1)
PAD_CTL_DSE_MED (1 << 1)
PAD_CTL_DSE_HIGH (2 << 1)
PAD_CTL_DSE_MAX (3 << 1)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
Refer to imx51-pinfunc.h in device tree source folder for all available
imx51 PIN_FUNC_ID.

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* Freescale IMX53 IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx53-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
pin working on a specific function, CONFIG is the pad setting value like
pull-up for this pin. Please refer to imx53 datasheet for the valid pad
config settings.
CONFIG bits definition:
PAD_CTL_HVE (1 << 13)
PAD_CTL_HYS (1 << 8)
PAD_CTL_PKE (1 << 7)
PAD_CTL_PUE (1 << 6)
PAD_CTL_PUS_100K_DOWN (0 << 4)
PAD_CTL_PUS_47K_UP (1 << 4)
PAD_CTL_PUS_100K_UP (2 << 4)
PAD_CTL_PUS_22K_UP (3 << 4)
PAD_CTL_ODE (1 << 3)
PAD_CTL_DSE_LOW (0 << 1)
PAD_CTL_DSE_MED (1 << 1)
PAD_CTL_DSE_HIGH (2 << 1)
PAD_CTL_DSE_MAX (3 << 1)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
Refer to imx53-pinfunc.h in device tree source folder for all available
imx53 PIN_FUNC_ID.

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* Freescale IMX6 DualLite/Solo IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx6dl-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
pin working on a specific function, CONFIG is the pad setting value like
pull-up for this pin. Please refer to imx6dl datasheet for the valid pad
config settings.
CONFIG bits definition:
PAD_CTL_HYS (1 << 16)
PAD_CTL_PUS_100K_DOWN (0 << 14)
PAD_CTL_PUS_47K_UP (1 << 14)
PAD_CTL_PUS_100K_UP (2 << 14)
PAD_CTL_PUS_22K_UP (3 << 14)
PAD_CTL_PUE (1 << 13)
PAD_CTL_PKE (1 << 12)
PAD_CTL_ODE (1 << 11)
PAD_CTL_SPEED_LOW (1 << 6)
PAD_CTL_SPEED_MED (2 << 6)
PAD_CTL_SPEED_HIGH (3 << 6)
PAD_CTL_DSE_DISABLE (0 << 3)
PAD_CTL_DSE_240ohm (1 << 3)
PAD_CTL_DSE_120ohm (2 << 3)
PAD_CTL_DSE_80ohm (3 << 3)
PAD_CTL_DSE_60ohm (4 << 3)
PAD_CTL_DSE_48ohm (5 << 3)
PAD_CTL_DSE_40ohm (6 << 3)
PAD_CTL_DSE_34ohm (7 << 3)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
Refer to imx6dl-pinfunc.h in device tree source folder for all available
imx6dl PIN_FUNC_ID.

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* Freescale IMX6Q IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx6q-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
pin working on a specific function, CONFIG is the pad setting value like
pull-up for this pin. Please refer to imx6q datasheet for the valid pad
config settings.
CONFIG bits definition:
PAD_CTL_HYS (1 << 16)
PAD_CTL_PUS_100K_DOWN (0 << 14)
PAD_CTL_PUS_47K_UP (1 << 14)
PAD_CTL_PUS_100K_UP (2 << 14)
PAD_CTL_PUS_22K_UP (3 << 14)
PAD_CTL_PUE (1 << 13)
PAD_CTL_PKE (1 << 12)
PAD_CTL_ODE (1 << 11)
PAD_CTL_SPEED_LOW (1 << 6)
PAD_CTL_SPEED_MED (2 << 6)
PAD_CTL_SPEED_HIGH (3 << 6)
PAD_CTL_DSE_DISABLE (0 << 3)
PAD_CTL_DSE_240ohm (1 << 3)
PAD_CTL_DSE_120ohm (2 << 3)
PAD_CTL_DSE_80ohm (3 << 3)
PAD_CTL_DSE_60ohm (4 << 3)
PAD_CTL_DSE_48ohm (5 << 3)
PAD_CTL_DSE_40ohm (6 << 3)
PAD_CTL_DSE_34ohm (7 << 3)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
Refer to imx6q-pinfunc.h in device tree source folder for all available
imx6q PIN_FUNC_ID.

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* Freescale IMX6 SoloLite IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx6sl-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
pin working on a specific function, CONFIG is the pad setting value like
pull-up for this pin. Please refer to imx6sl datasheet for the valid pad
config settings.
CONFIG bits definition:
PAD_CTL_LVE (1 << 22)
PAD_CTL_HYS (1 << 16)
PAD_CTL_PUS_100K_DOWN (0 << 14)
PAD_CTL_PUS_47K_UP (1 << 14)
PAD_CTL_PUS_100K_UP (2 << 14)
PAD_CTL_PUS_22K_UP (3 << 14)
PAD_CTL_PUE (1 << 13)
PAD_CTL_PKE (1 << 12)
PAD_CTL_ODE (1 << 11)
PAD_CTL_SPEED_LOW (1 << 6)
PAD_CTL_SPEED_MED (2 << 6)
PAD_CTL_SPEED_HIGH (3 << 6)
PAD_CTL_DSE_DISABLE (0 << 3)
PAD_CTL_DSE_240ohm (1 << 3)
PAD_CTL_DSE_120ohm (2 << 3)
PAD_CTL_DSE_80ohm (3 << 3)
PAD_CTL_DSE_60ohm (4 << 3)
PAD_CTL_DSE_48ohm (5 << 3)
PAD_CTL_DSE_40ohm (6 << 3)
PAD_CTL_DSE_34ohm (7 << 3)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
Refer to imx6sl-pinfunc.h in device tree source folder for all available
imx6sl PIN_FUNC_ID.

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* Freescale i.MX6 SoloX IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx6sx-iomuxc"
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
imx6sx-pinfunc.h under device tree source folder. The last integer CONFIG is
the pad setting value like pull-up on this pin. Please refer to i.MX6 SoloX
Reference Manual for detailed CONFIG settings.
CONFIG bits definition:
PAD_CTL_HYS (1 << 16)
PAD_CTL_PUS_100K_DOWN (0 << 14)
PAD_CTL_PUS_47K_UP (1 << 14)
PAD_CTL_PUS_100K_UP (2 << 14)
PAD_CTL_PUS_22K_UP (3 << 14)
PAD_CTL_PUE (1 << 13)
PAD_CTL_PKE (1 << 12)
PAD_CTL_ODE (1 << 11)
PAD_CTL_SPEED_LOW (0 << 6)
PAD_CTL_SPEED_MED (1 << 6)
PAD_CTL_SPEED_HIGH (3 << 6)
PAD_CTL_DSE_DISABLE (0 << 3)
PAD_CTL_DSE_260ohm (1 << 3)
PAD_CTL_DSE_130ohm (2 << 3)
PAD_CTL_DSE_87ohm (3 << 3)
PAD_CTL_DSE_65ohm (4 << 3)
PAD_CTL_DSE_52ohm (5 << 3)
PAD_CTL_DSE_43ohm (6 << 3)
PAD_CTL_DSE_37ohm (7 << 3)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)

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* Freescale MXS Pin Controller
The pins controlled by mxs pin controller are organized in banks, each bank
has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
function is GPIO. The configuration on the pins includes drive strength,
voltage and pull-up.
Required properties:
- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
- reg: Should contain the register physical address and length for the
pin controller.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
The node of mxs pin controller acts as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for
a group of pins, and only affects those parameters that are explicitly listed.
In other words, a subnode that describes a drive strength parameter implies no
information about pull-up. For this reason, even seemingly boolean values are
actually tristates in this binding: unspecified, off, or on. Unspecified is
represented as an absent property, and off/on are represented as integer
values 0 and 1.
Those subnodes under mxs pin controller node will fall into two categories.
One is to set up a group of pins for a function, both mux selection and pin
configurations, and it's called group node in the binding document. The other
one is to adjust the pin configuration for some particular pins that need a
different configuration than what is defined in group node. The binding
document calls this type of node config node.
On mxs, there is no hardware pin group. The pin group in this binding only
means a group of pins put together for particular peripheral to work in
particular function, like SSP0 functioning as mmc0-8bit. That said, the
group node should include all the pins needed for one function rather than
having these pins defined in several group nodes. It also means each of
"pinctrl-*" phandle in client device node should only have one group node
pointed in there, while the phandle can have multiple config node referenced
there to adjust configurations for some pins in the group.
Required subnode-properties:
- fsl,pinmux-ids: An integer array. Each integer in the array specify a pin
with given mux function, with bank, pin and mux packed as below.
[15..12] : bank number
[11..4] : pin number
[3..0] : mux selection
This integer with mux selection packed is used as an entity by both group
and config nodes to identify a pin. The mux selection in the integer takes
effects only on group node, and will get ignored by driver with config node,
since config node is only meant to set up pin configurations.
Valid values for these integers are listed below.
- reg: Should be the index of the group nodes for same function. This property
is required only for group nodes, and should not be present in any config
nodes.
Optional subnode-properties:
- fsl,drive-strength: Integer.
0: MXS_DRIVE_4mA
1: MXS_DRIVE_8mA
2: MXS_DRIVE_12mA
3: MXS_DRIVE_16mA
- fsl,voltage: Integer.
0: MXS_VOLTAGE_LOW - 1.8 V
1: MXS_VOLTAGE_HIGH - 3.3 V
- fsl,pull-up: Integer.
0: MXS_PULL_DISABLE - Disable the internal pull-up
1: MXS_PULL_ENABLE - Enable the internal pull-up
Note that when enabling the pull-up, the internal pad keeper gets disabled.
Also, some pins doesn't have a pull up, in that case, setting the fsl,pull-up
will only disable the internal pad keeper.
Examples:
pinctrl@80018000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx28-pinctrl";
reg = <0x80018000 2000>;
mmc0_8bit_pins_a: mmc0-8bit@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SSP0_DATA0__SSP0_D0
MX28_PAD_SSP0_DATA1__SSP0_D1
MX28_PAD_SSP0_DATA2__SSP0_D2
MX28_PAD_SSP0_DATA3__SSP0_D3
MX28_PAD_SSP0_DATA4__SSP0_D4
MX28_PAD_SSP0_DATA5__SSP0_D5
MX28_PAD_SSP0_DATA6__SSP0_D6
MX28_PAD_SSP0_DATA7__SSP0_D7
MX28_PAD_SSP0_CMD__SSP0_CMD
MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
MX28_PAD_SSP0_SCK__SSP0_SCK
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
mmc_cd_cfg: mmc-cd-cfg {
fsl,pinmux-ids = <MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
mmc_sck_cfg: mmc-sck-cfg {
fsl,pinmux-ids = <MX28_PAD_SSP0_SCK__SSP0_SCK>;
fsl,drive-strength = <MXS_DRIVE_12mA>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
};
In this example, group node mmc0-8bit defines a group of pins for mxs SSP0
to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations
applied on all these pins. And config nodes mmc-cd-cfg and mmc-sck-cfg are
adjusting the configuration for pins card-detection and clock from what group
node mmc0-8bit defines. Only the configuration properties to be adjusted need
to be listed in the config nodes.
Valid values for i.MX28/i.MX23 pinmux-id are defined in
arch/arm/boot/dts/imx28-pinfunc.h and arch/arm/boot/dts/imx23-pinfunc.h.
The definitions for the padconfig properties can be found in
arch/arm/boot/dts/mxs-pinfunc.h.

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Freescale Vybrid VF610 IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,vf610-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is
a pin working on a specific function, CONFIG is the pad setting value
such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610
datasheet for the valid pad config settings.
CONFIG bits definition:
PAD_CTL_SPEED_LOW (1 << 12)
PAD_CTL_SPEED_MED (2 << 12)
PAD_CTL_SPEED_HIGH (3 << 12)
PAD_CTL_SRE_FAST (1 << 11)
PAD_CTL_SRE_SLOW (0 << 11)
PAD_CTL_ODE (1 << 10)
PAD_CTL_HYS (1 << 9)
PAD_CTL_DSE_DISABLE (0 << 6)
PAD_CTL_DSE_150ohm (1 << 6)
PAD_CTL_DSE_75ohm (2 << 6)
PAD_CTL_DSE_50ohm (3 << 6)
PAD_CTL_DSE_37ohm (4 << 6)
PAD_CTL_DSE_30ohm (5 << 6)
PAD_CTL_DSE_25ohm (6 << 6)
PAD_CTL_DSE_20ohm (7 << 6)
PAD_CTL_PUS_100K_DOWN (0 << 4)
PAD_CTL_PUS_47K_UP (1 << 4)
PAD_CTL_PUS_100K_UP (2 << 4)
PAD_CTL_PUS_22K_UP (3 << 4)
PAD_CTL_PKE (1 << 3)
PAD_CTL_PUE (1 << 2)
PAD_CTL_OBE_ENABLE (1 << 1)
PAD_CTL_IBE_ENABLE (1 << 0)
PAD_CTL_OBE_IBE_ENABLE (3 << 0)
Please refer to vf610-pinfunc.h in device tree source folder
for all available PIN_FUNC_ID for Vybrid VF610.

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ImgTec TZ1090 PDC pin controller
Required properties:
- compatible: "img,tz1090-pdc-pinctrl"
- reg: Should contain the register physical address and length of the
SOC_GPIO_CONTROL registers in the PDC register region.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
TZ1090-PDC's pin configuration nodes act as a container for an arbitrary number
of subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function. For this reason, even seemingly boolean
values are actually tristates in this binding: unspecified, off, or on.
Unspecified is represented as an absent property, and off/on are represented as
integer values 0 and 1.
Required subnode-properties:
- tz1090,pins : An array of strings. Each string contains the name of a pin or
group. Valid values for these names are listed below.
Optional subnode-properties:
- tz1090,function: A string containing the name of the function to mux to the
pin or group. Valid values for function names are listed below, including
which pingroups can be muxed to them.
- supported generic pinconfig properties (for further details see
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
- bias-disable
- bias-high-impedance
- bias-bus-hold
- bias-pull-up
- bias-pull-down
- input-schmitt-enable
- input-schmitt-disable
- drive-strength: Integer, control drive strength of pins in mA.
2: 2mA
4: 4mA
8: 8mA
12: 12mA
- low-power-enable: Flag, power-on-start weak pull-down for invalid power.
- low-power-disable: Flag, power-on-start weak pull-down disabled.
Note that many of these properties are only valid for certain specific pins
or groups. See the TZ1090 TRM for complete details regarding which groups
support which functionality. The Linux pinctrl driver may also be a useful
reference.
Valid values for pin and group names are:
pins:
These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
bias-bus-hold (which can also be provided to any of the groups below to set
it for all gpio pins in that group).
gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data, ext_power.
mux groups:
These all support function.
gpio0
pins: gpio0.
function: ir_mod_stable_out.
gpio1
pins: gpio1.
function: ir_mod_power_out.
drive groups:
These support input-schmitt-enable, input-schmitt-disable,
drive-strength, low-power-enable, and low-power-disable.
pdc
pins: gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data,
ext_power.
Example:
pinctrl_pdc: pinctrl@02006500 {
#gpio-range-cells = <3>;
compatible = "img,tz1090-pdc-pinctrl";
reg = <0x02006500 0x100>;
};
Example board file extracts:
&pinctrl_pdc {
pinctrl-names = "default";
pinctrl-0 = <&syswake_default>;
syswake_default: syswakes {
syswake_cfg {
tz1090,pins = "sys_wake0",
"sys_wake1",
"sys_wake2";
pull-up;
};
};
irmod_default: irmod {
gpio0_cfg {
tz1090,pins = "gpio0";
tz1090,function = "ir_mod_stable_out";
};
gpio1_cfg {
tz1090,pins = "gpio1";
tz1090,function = "ir_mod_power_out";
};
};
};
ir: ir@02006200 {
pinctrl-names = "default";
pinctrl-0 = <&irmod_default>;
};

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ImgTec TZ1090 pin controller
Required properties:
- compatible: "img,tz1090-pinctrl"
- reg: Should contain the register physical address and length of the pad
configuration registers (CR_PADS_* and CR_IF_CTL0).
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
TZ1090's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function. For this reason, even seemingly boolean
values are actually tristates in this binding: unspecified, off, or on.
Unspecified is represented as an absent property, and off/on are represented as
integer values 0 and 1.
Required subnode-properties:
- tz1090,pins : An array of strings. Each string contains the name of a pin or
group. Valid values for these names are listed below.
Optional subnode-properties:
- tz1090,function: A string containing the name of the function to mux to the
pin or group. Valid values for function names are listed below, including
which pingroups can be muxed to them.
- supported generic pinconfig properties (for further details see
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
- bias-disable
- bias-high-impedance
- bias-bus-hold
- bias-pull-up
- bias-pull-down
- input-schmitt-enable
- input-schmitt-disable
- drive-strength: Integer, control drive strength of pins in mA.
2: 2mA
4: 4mA
8: 8mA
12: 12mA
Note that many of these properties are only valid for certain specific pins
or groups. See the TZ1090 TRM for complete details regarding which groups
support which functionality. The Linux pinctrl driver may also be a useful
reference.
Valid values for pin and group names are:
gpio pins:
These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
bias-bus-hold (which can also be provided to any of the groups below to set
it for all pins in that group).
They also all support the some form of muxing. Any pins which are contained
in one of the mux groups (see below) can be muxed only to the functions
supported by the mux group. All other pins can be muxed to the "perip"
function which which enables them with their intended peripheral.
Different pins in the same mux group cannot be muxed to different functions,
however it is possible to mux only a subset of the pins in a mux group to a
particular function and leave the remaining pins unmuxed. This is useful if
the board connects certain pins in a group to other devices to be controlled
by GPIO, and you don't want the usual peripheral to have any control of the
pin.
ant_sel0, ant_sel1, gain0, gain1, gain2, gain3, gain4, gain5, gain6, gain7,
i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2, i2s_lrclk_out,
i2s_mclk, pa_on, pdm_a, pdm_b, pdm_c, pdm_d, pll_on, rx_hp, rx_on,
scb0_sclk, scb0_sdat, scb1_sclk, scb1_sdat, scb2_sclk, scb2_sdat, sdh_cd,
sdh_clk_in, sdh_wp, sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
spi0_cs0, spi0_cs1, spi0_cs2, spi0_din, spi0_dout, spi0_mclk, spi1_cs0,
spi1_cs1, spi1_cs2, spi1_din, spi1_dout, spi1_mclk, tft_blank_ls, tft_blue0,
tft_blue1, tft_blue2, tft_blue3, tft_blue4, tft_blue5, tft_blue6, tft_blue7,
tft_green0, tft_green1, tft_green2, tft_green3, tft_green4, tft_green5,
tft_green6, tft_green7, tft_hsync_nr, tft_panelclk, tft_pwrsave, tft_red0,
tft_red1, tft_red2, tft_red3, tft_red4, tft_red5, tft_red6, tft_red7,
tft_vd12acb, tft_vdden_gd, tft_vsync_ns, tx_on, uart0_cts, uart0_rts,
uart0_rxd, uart0_txd, uart1_rxd, uart1_txd.
bias-high-impediance: supported.
bias-pull-up: supported.
bias-pull-down: supported.
bias-bus-hold: supported.
function: perip or those supported by pin's mux group.
other pins:
These other pins are part of various pin groups below, but can't be
controlled as GPIOs. They do however support bias-high-impediance,
bias-pull-up, bias-pull-down, and bias-bus-hold (which can also be provided
to any of the groups below to set it for all pins in that group).
clk_out0, clk_out1, tck, tdi, tdo, tms, trst.
bias-high-impediance: supported.
bias-pull-up: supported.
bias-pull-down: supported.
bias-bus-hold: supported.
mux groups:
These all support function, and some support drive configs.
afe
pins: tx_on, rx_on, pll_on, pa_on, rx_hp, ant_sel0,
ant_sel1, gain0, gain1, gain2, gain3, gain4,
gain5, gain6, gain7.
function: afe, ts_out_0.
input-schmitt-enable: supported.
input-schmitt-disable: supported.
drive-strength: supported.
pdm_d
pins: pdm_d.
function: pdm_dac, usb_vbus.
sdh
pins: sdh_cd, sdh_wp, sdh_clk_in.
function: sdh, sdio.
sdio
pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2,
sdio_d3.
function: sdio, sdh.
spi1_cs2
pins: spi1_cs2.
function: spi1_cs2, usb_vbus.
tft
pins: tft_red0, tft_red1, tft_red2, tft_red3,
tft_red4, tft_red5, tft_red6, tft_red7,
tft_green0, tft_green1, tft_green2, tft_green3,
tft_green4, tft_green5, tft_green6, tft_green7,
tft_blue0, tft_blue1, tft_blue2, tft_blue3,
tft_blue4, tft_blue5, tft_blue6, tft_blue7,
tft_vdden_gd, tft_panelclk, tft_blank_ls,
tft_vsync_ns, tft_hsync_nr, tft_vd12acb,
tft_pwrsave.
function: tft, ext_dac, not_iqadc_stb, iqdac_stb, ts_out_1,
lcd_trace, phy_ringosc.
input-schmitt-enable: supported.
input-schmitt-disable: supported.
drive-strength: supported.
drive groups:
These all support input-schmitt-enable, input-schmitt-disable,
and drive-strength.
jtag
pins: tck, trst, tdi, tdo, tms.
scb1
pins: scb1_sdat, scb1_sclk.
scb2
pins: scb2_sdat, scb2_sclk.
spi0
pins: spi0_mclk, spi0_cs0, spi0_cs1, spi0_cs2, spi0_dout, spi0_din.
spi1
pins: spi1_mclk, spi1_cs0, spi1_cs1, spi1_cs2, spi1_dout, spi1_din.
uart
pins: uart0_txd, uart0_rxd, uart0_rts, uart0_cts,
uart1_txd, uart1_rxd.
drive_i2s
pins: clk_out1, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
i2s_lrclk_out, i2s_bclk_out, i2s_mclk.
drive_pdm
pins: clk_out0, pdm_b, pdm_a.
drive_scb0
pins: scb0_sclk, scb0_sdat, pdm_d, pdm_c.
drive_sdio
pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
sdh_wp, sdh_cd, sdh_clk_in.
convenience groups:
These are just convenient groupings of pins and don't support any drive
configs.
uart0
pins: uart0_cts, uart0_rts, uart0_rxd, uart0_txd.
uart1
pins: uart1_rxd, uart1_txd.
scb0
pins: scb0_sclk, scb0_sdat.
i2s
pins: i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
i2s_lrclk_out, i2s_mclk.
Example:
pinctrl: pinctrl@02005800 {
#gpio-range-cells = <3>;
compatible = "img,tz1090-pinctrl";
reg = <0x02005800 0xe4>;
};
Example board file extract:
&pinctrl {
uart0_default: uart0 {
uart0_cfg {
tz1090,pins = "uart0_rxd",
"uart0_txd";
tz1090,function = "perip";
};
};
tft_default: tft {
tft_cfg {
tz1090,pins = "tft";
tz1090,function = "tft";
};
};
};
uart@02004b00 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_default>;
};

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Lantiq FALCON pinmux controller
Required properties:
- compatible: "lantiq,pinctrl-falcon"
- reg: Should contain the physical address and length of the gpio/pinmux
register range
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Lantiq's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those group(s), and two pin configuration parameters:
pull-up and open-drain
The name of each subnode is not important as long as it is unique; all subnodes
should be enumerated and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
We support 2 types of nodes.
Definition of mux function groups:
Required subnode-properties:
- lantiq,groups : An array of strings. Each string contains the name of a group.
Valid values for these names are listed below.
- lantiq,function: A string containing the name of the function to mux to the
group. Valid values for function names are listed below.
Valid values for group and function names:
mux groups:
por, ntr, ntr8k, hrst, mdio, bootled, asc0, spi, spi cs0, spi cs1, i2c,
jtag, slic, pcm, asc1
functions:
rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm
Definition of pin configurations:
Required subnode-properties:
- lantiq,pins : An array of strings. Each string contains the name of a pin.
Valid values for these names are listed below.
Optional subnode-properties:
- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
0: none, 1: down
- lantiq,drive-current: Boolean, enables drive-current
- lantiq,slew-rate: Boolean, enables slew-rate
Example:
pinmux0 {
compatible = "lantiq,pinctrl-falcon";
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
asc0 {
lantiq,groups = "asc0";
lantiq,function = "asc";
};
ntr {
lantiq,groups = "ntr8k";
lantiq,function = "ntr";
};
i2c {
lantiq,groups = "i2c";
lantiq,function = "i2c";
};
hrst {
lantiq,groups = "hrst";
lantiq,function = "rst";
};
};
};

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Lantiq XWAY pinmux controller
Required properties:
- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9"
- reg: Should contain the physical address and length of the gpio/pinmux
register range
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Lantiq's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those group(s), and two pin configuration parameters:
pull-up and open-drain
The name of each subnode is not important as long as it is unique; all subnodes
should be enumerated and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
We support 2 types of nodes.
Definition of mux function groups:
Required subnode-properties:
- lantiq,groups : An array of strings. Each string contains the name of a group.
Valid values for these names are listed below.
- lantiq,function: A string containing the name of the function to mux to the
group. Valid values for function names are listed below.
Valid values for group and function names:
mux groups:
exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3,
spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2,
gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2,
req3
additional mux groups (XR9 only):
mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4
functions:
spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio
Definition of pin configurations:
Required subnode-properties:
- lantiq,pins : An array of strings. Each string contains the name of a pin.
Valid values for these names are listed below.
Optional subnode-properties:
- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
0: none, 1: down, 2: up.
- lantiq,open-drain: Boolean, enables open-drain on the defined pin.
Valid values for XWAY pin names:
Pinconf pins can be referenced via the names io0-io31.
Valid values for XR9 pin names:
Pinconf pins can be referenced via the names io0-io55.
Example:
gpio: pinmux@E100B10 {
compatible = "lantiq,pinctrl-xway";
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
#gpio-cells = <2>;
gpio-controller;
reg = <0xE100B10 0xA0>;
state_default: pinmux {
stp {
lantiq,groups = "stp";
lantiq,function = "stp";
};
pci {
lantiq,groups = "gnt1";
lantiq,function = "pci";
};
conf_out {
lantiq,pins = "io4", "io5", "io6"; /* stp */
lantiq,open-drain;
lantiq,pull = <0>;
};
};
};

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* Marvell Armada 370 SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,88f6710-pinctrl"
- reg: register specifier of MPP registers
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.
name pins functions
================================================================================
mpp0 0 gpio, uart0(rxd)
mpp1 1 gpo, uart0(txd)
mpp2 2 gpio, i2c0(sck), uart0(txd)
mpp3 3 gpio, i2c0(sda), uart0(rxd)
mpp4 4 gpio, cpu_pd(vdd)
mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
mpp7 7 gpo, ge0(txd1), tdm(tdx), audio(lrclk)
mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
sata1(prsnt), spi1(cs1)
mpp12 12 gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
audio(spdifi)
mpp13 13 gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
audio(rmclk)
mpp14 14 gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
spi0(cs2)
mpp15 15 gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
spi0(cs3)
mpp16 16 gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
mpp17 17 gpo, ge(mdc)
mpp18 18 gpio, ge(mdio)
mpp19 19 gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
mpp20 20 gpo, ge0(txd4), ge1(txd0)
mpp21 21 gpo, ge0(txd5), ge1(txd1), uart1(txd)
mpp22 22 gpo, ge0(txd6), ge1(txd2), uart0(rts)
mpp23 23 gpo, ge0(txd7), ge1(txd3), spi1(mosi)
mpp24 24 gpio, ge0(col), ge1(txctl), spi1(cs0)
mpp25 25 gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
mpp26 26 gpio, ge0(crs), ge1(rxd1), spi1(miso)
mpp27 27 gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
mpp28 28 gpio, ge0(rxd5), ge1(rxd3)
mpp29 29 gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
mpp31 31 gpio, tclk, ge0(txerr)
mpp32 32 gpio, spi0(cs0)
mpp33 33 gpio, dev(bootcs), spi0(cs0)
mpp34 34 gpo, dev(wen0), spi0(mosi)
mpp35 35 gpo, dev(oen), spi0(sck)
mpp36 36 gpo, dev(a1), spi0(miso)
mpp37 37 gpo, dev(a0), sata0(prsnt)
mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts)
mpp39 39 gpo, dev(ad0), audio(spdifo)
mpp40 40 gpio, dev(ad1), uart1(rts), uart0(rts)
mpp41 41 gpio, dev(ad2), uart1(rxd)
mpp42 42 gpo, dev(ad3), uart1(txd)
mpp43 43 gpo, dev(ad4), audio(bclk)
mpp44 44 gpo, dev(ad5), audio(mclk)
mpp45 45 gpo, dev(ad6), audio(lrclk)
mpp46 46 gpo, dev(ad7), audio(sdo)
mpp47 47 gpo, dev(ad8), sd0(clk), audio(spdifo)
mpp48 48 gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
spi0(cs1)
mpp49 49 gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
audio(spdifi)
mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
audio(rmclk)
mpp51 51 gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
mpp52 52 gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
mpp53 53 gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
pcie(clkreq1)
mpp54 54 gpo, dev(ad15), tdm(dtx)
mpp55 55 gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
sata0(prsnt)
mpp56 56 gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
pcie(clkreq0), spi1(cs1)
mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
audio(sdo)
mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
uart0(rts)
mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
audio(sdi)
mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk)
mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
audio(mclk), uart0(cts)
mpp63 63 gpo, spi0(sck), tclk
mpp64 64 gpio, spi0(miso), spi0-1(cs1)
mpp65 65 gpio, spi0(mosi), spi0-1(cs2)

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* Marvell Armada 375 SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,88f6720-pinctrl"
- reg: register specifier of MPP registers
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.
name pins functions
================================================================================
mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi)
mpp2 2 gpio, dev(ad4), ptp(eventreq), led(c0), audio(sdi)
mpp3 3 gpio, dev(ad5), ptp(triggen), led(p3), audio(mclk)
mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso)
mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2)
mpp6 6 gpio, dev(ad0), led(p1), audio(rclk)
mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk)
mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0)
mpp9 9 gpio, nf(wen), spi0(sck), spi1(sck)
mpp10 10 gpio, nf(ren), dram(vttctrl), led(c1)
mpp11 11 gpio, dev(a0), led(c2), audio(sdo)
mpp12 12 gpio, dev(a1), audio(bclk)
mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn)
mpp14 14 gpio, i2c0(sda), uart1(txd)
mpp15 15 gpio, i2c0(sck), uart1(rxd)
mpp16 16 gpio, uart0(txd)
mpp17 17 gpio, uart0(rxd)
mpp18 18 gpio, tdm(intn)
mpp19 19 gpio, tdm(rstn)
mpp20 20 gpio, tdm(pclk)
mpp21 21 gpio, tdm(fsync)
mpp22 22 gpio, tdm(drx)
mpp23 23 gpio, tdm(dtx)
mpp24 24 gpio, led(p0), ge1(rxd0), sd(cmd), uart0(rts)
mpp25 25 gpio, led(p2), ge1(rxd1), sd(d0), uart0(cts)
mpp26 26 gpio, pcie0(clkreq), ge1(rxd2), sd(d2), uart1(rts)
mpp27 27 gpio, pcie1(clkreq), ge1(rxd3), sd(d1), uart1(cts)
mpp28 28 gpio, led(p3), ge1(txctl), sd(clk)
mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3)
mpp30 30 gpio, ge1(txd0), spi1(cs0)
mpp31 31 gpio, ge1(txd1), spi1(mosi)
mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(triggen)
mpp33 33 gpio, ge1(txd3), spi1(miso)
mpp34 34 gpio, ge1(txclkout), spi1(sck)
mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2)
mpp36 36 gpio, pcie0(clkreq)
mpp37 37 gpio, pcie0(clkreq), tdm(intn), ge(mdc)
mpp38 38 gpio, pcie1(clkreq), ge(mdio)
mpp39 39 gpio, ref(clkout)
mpp40 40 gpio, uart1(txd)
mpp41 41 gpio, uart1(rxd)
mpp42 42 gpio, spi1(cs2), led(c0)
mpp43 43 gpio, sata0(prsnt), dram(vttctrl)
mpp44 44 gpio, sata0(prsnt)
mpp45 45 gpio, spi0(cs2), pcie0(rstoutn)
mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0)
mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1)
mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2)
mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3)
mpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0)
mpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1)
mpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2)
mpp53 53 gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3)
mpp54 54 gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl)
mpp55 55 gpio, ge0(rxclk), ge1(rxclk)
mpp56 56 gpio, ge0(txclkout), ge1(txclkout)
mpp57 57 gpio, ge0(txctl), ge1(txctl)
mpp58 58 gpio, led(c0)
mpp59 59 gpio, led(c1)
mpp60 60 gpio, uart1(txd), led(c2)
mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0)
mpp62 62 gpio, i2c1(sck), led(p1)
mpp63 63 gpio, ptp(triggen), led(p2)
mpp64 64 gpio, dram(vttctrl), led(p3)
mpp65 65 gpio, sata1(prsnt)
mpp66 66 gpio, ptp(eventreq), spi1(cs3)

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* Marvell Armada 380/385 SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or
"marvell,88f6828-pinctrl" depending on the specific variant of the
SoC being used.
- reg: register specifier of MPP registers
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.
name pins functions
================================================================================
mpp0 0 gpio, ua0(rxd)
mpp1 1 gpio, ua0(txd)
mpp2 2 gpio, i2c0(sck)
mpp3 3 gpio, i2c0(sda)
mpp4 4 gpio, ge(mdc), ua1(txd), ua0(rts)
mpp5 5 gpio, ge(mdio), ua1(rxd), ua0(cts)
mpp6 6 gpio, ge0(txclkout), ge0(crs), dev(cs3)
mpp7 7 gpio, ge0(txd0), dev(ad9)
mpp8 8 gpio, ge0(txd1), dev(ad10)
mpp9 9 gpio, ge0(txd2), dev(ad11)
mpp10 10 gpio, ge0(txd3), dev(ad12)
mpp11 11 gpio, ge0(txctl), dev(ad13)
mpp12 12 gpio, ge0(rxd0), pcie0(rstout), pcie1(rstout) [1], spi0(cs1), dev(ad14)
mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15)
mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1)
mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi), pcie1(rstout) [1]
mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq)
mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt)
mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0), pcie1(rstout) [1]
mpp19 19 gpio, ge0(col), ptp(event_req), pcie0(clkreq), sata1(prsnt), ua0(cts)
mpp20 20 gpio, ge0(txclk), ptp(clk), pcie1(rstout) [1], sata0(prsnt), ua0(rts)
mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs)
mpp22 22 gpio, spi0(mosi), dev(ad0)
mpp23 23 gpio, spi0(sck), dev(ad2)
mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0)
mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
mpp27 27 gpio, spi0(cs3), ge1(txclkout), i2c1(sda), sd0(d7), dev(cs2)
mpp28 28 gpio, ge1(txd0), sd0(clk), dev(ad5)
mpp29 29 gpio, ge1(txd1), dev(ale0)
mpp30 30 gpio, ge1(txd2), dev(oen)
mpp31 31 gpio, ge1(txd3), dev(ale1)
mpp32 32 gpio, ge1(txctl), dev(wen0)
mpp33 33 gpio, m(decc_err), dev(ad3)
mpp34 34 gpio, dev(ad1)
mpp35 35 gpio, ref(clk_out1), dev(a1)
mpp36 36 gpio, ptp(trig_gen), dev(a0)
mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8)
mpp38 38 gpio, ptp(event_req), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4)
mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2)
mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6)
mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last)
mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7)
mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), pcie0(rstout), dev(clkout)
mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3], pcie0(rstout)
mpp45 45 gpio, ref(clk_out0), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)
mpp46 46 gpio, ref(clk_out1), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)
mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], spi1(cs2), sata3(prsnt) [2]
mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4)
mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5)
mpp50 50 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(drx), audio(extclk), sd0(cmd)
mpp51 51 gpio, tdm2c(dtx), audio(sdo), m(decc_err)
mpp52 52 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(intn), audio(sdi), sd0(d6)
mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7)
mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), pcie1(rstout) [1], sd0(d3)
mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0)
mpp56 56 gpio, ua1(rts), ge(mdc), m(decc_err), spi1(mosi)
mpp57 57 gpio, spi1(sck), sd0(clk)
mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1)
mpp59 59 gpio, pcie0(rstout), i2c1(sda), pcie1(rstout) [1], spi1(cs0), sd0(d2)
[1]: only available on 88F6820 and 88F6828
[2]: only available on 88F6828

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* Marvell Armada XP SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
"marvell,mv78460-pinctrl"
- reg: register specifier of MPP registers
This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.
* Marvell Armada XP (all variants)
name pins functions
================================================================================
mpp0 0 gpio, ge0(txclko), lcd(d0)
mpp1 1 gpio, ge0(txd0), lcd(d1)
mpp2 2 gpio, ge0(txd1), lcd(d2)
mpp3 3 gpio, ge0(txd2), lcd(d3)
mpp4 4 gpio, ge0(txd3), lcd(d4)
mpp5 5 gpio, ge0(txctl), lcd(d5)
mpp6 6 gpio, ge0(rxd0), lcd(d6)
mpp7 7 gpio, ge0(rxd1), lcd(d7)
mpp8 8 gpio, ge0(rxd2), lcd(d8)
mpp9 9 gpio, ge0(rxd3), lcd(d9)
mpp10 10 gpio, ge0(rxctl), lcd(d10)
mpp11 11 gpio, ge0(rxclk), lcd(d11)
mpp12 12 gpio, ge0(txd4), ge1(txd0), lcd(d12)
mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13)
mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15)
mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16)
mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16)
mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17)
mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
mpp24 24 gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
mpp25 25 gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig)
mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq)
mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
mpp30 30 gpio, tdm(int1), sd0(clk)
mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat)
mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt)
mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt)
mpp36 36 gpio, spi(mosi)
mpp37 37 gpio, spi(miso)
mpp38 38 gpio, spi(sck)
mpp39 39 gpio, spi(cs0)
mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
pcie(clkreq0)
mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
pcie(clkreq1)
mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
vdd(cpu0-pd)
mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
vdd(cpu2-3-pd){1}
mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
mem(bat)
mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
ref(clkout)
mpp48 48 gpio, tclk, dev(burst/last)
* Marvell Armada XP (mv78260 and mv78460 only)
name pins functions
================================================================================
mpp49 49 gpio, dev(we3)
mpp50 50 gpio, dev(we2)
mpp51 51 gpio, dev(ad16)
mpp52 52 gpio, dev(ad17)
mpp53 53 gpio, dev(ad18)
mpp54 54 gpio, dev(ad19)
mpp55 55 gpio, dev(ad20), vdd(cpu0-pd)
mpp56 56 gpio, dev(ad21), vdd(cpu1-pd)
mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1}
mpp58 58 gpio, dev(ad23)
mpp59 59 gpio, dev(ad24)
mpp60 60 gpio, dev(ad25)
mpp61 61 gpio, dev(ad26)
mpp62 62 gpio, dev(ad27)
mpp63 63 gpio, dev(ad28)
mpp64 64 gpio, dev(ad29)
mpp65 65 gpio, dev(ad30)
mpp66 66 gpio, dev(ad31)
Notes:
* {1} vdd(cpu2-3-pd) only available on mv78460.

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* Marvell Dove SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,dove-pinctrl"
- clocks: (optional) phandle of pdma clock
- reg: register specifiers of MPP, MPP4, and PMU MPP registers
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.
Note: pmu* also allows for Power Management functions listed below
name pins functions
================================================================================
mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
uart1(rts), pmu*
mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
uart1(cts), lcd-spi(cs1), pmu*
mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi), pmu*
mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck), pmu*
mpp8 8 gpio, pmu, watchdog(rstout), pmu*
mpp9 9 gpio, pmu, pex1(clkreq), pmu*
mpp10 10 gpio, pmu, ssp(sclk), pmu*
mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
sdio1(ledctrl), pex0(clkreq), pmu*
mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd),
sata(act), pmu*
mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
ssp(extclk), pmu*
mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd), pmu*
mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm), pmu*
mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
ac97-1(sysclko)
mpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
mpp19 19 gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
ac97(sysclko)
mpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
uart1(cts), ssp(sfrm)
mpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
lcd-spi(mosi), uart1(cts), ssp(txd)
mpp23 23 gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
lcd-spi(sck), ssp(sclk)
mpp_camera 24-39 gpio, camera
mpp_sdio0 40-45 gpio, sdio0
mpp_sdio1 46-51 gpio, sdio1
mpp_audio1 52-57 gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
ssp/twsi
mpp_spi0 58-61 gpio, spi0
mpp_uart1 62-63 gpio, uart1
mpp_nand 64-71 gpo, nand
audio0 - i2s, ac97
twsi - none, opt1, opt2, opt3
Power Management functions (pmu*):
pmu-nc Pin not driven by any PM function
pmu-low Pin driven low (0)
pmu-high Pin driven high (1)
pmic(sdi) Pin is used for PMIC SDI
cpu-pwr-down Pin is used for CPU_PWRDWN
standby-pwr-down Pin is used for STBY_PWRDWN
core-pwr-good Pin is used for CORE_PWR_GOOD (Pins 0-7 only)
cpu-pwr-good Pin is used for CPU_PWR_GOOD (Pins 8-15 only)
bat-fault Pin is used for BATTERY_FAULT
ext0-wakeup Pin is used for EXT0_WU
ext1-wakeup Pin is used for EXT0_WU
ext2-wakeup Pin is used for EXT0_WU
pmu-blink Pin is used for blink function
Notes:
* group "mpp_audio1" allows the following functions and gpio pins:
- gpio : gpio on pins 52-57
- i2s1/spdifo : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
- i2s1 : audio1 i2s on pins 52-55, gpio on pins 56,57
- spdifo : spdifo on pin 57, gpio on pins 52-55
- twsi : twsi on pins 56,57, gpio on pins 52-55
- ssp/spdifo : ssp on pins 52-55, spdifo on pin 57, no gpios
- ssp : ssp on pins 52-55, gpio on pins 56,57
- ssp/twsi : ssp on pins 52-55, twsi on pins 56,57, no gpios
* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
audio0 pins.
* group "twsi" internally muxes twsi controller to the dedicated or option pins.

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* Marvell Kirkwood SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,88f6180-pinctrl",
"marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
"marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
"marvell,98dx4122-pinctrl"
- reg: register specifier of MPP registers
This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.
* Marvell Kirkwood 88f6180
name pins functions
================================================================================
mpp0 0 gpio, nand(io2), spi(cs)
mpp1 1 gpo, nand(io3), spi(mosi)
mpp2 2 gpo, nand(io4), spi(sck)
mpp3 3 gpo, nand(io5), spi(miso)
mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig)
mpp6 6 sysrst(out), spi(mosi), ptp(trig)
mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
mii(col)
mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
mii(crs)
mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig)
mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
ptp-2(trig)
mpp12 12 gpo, sdio(clk)
mpp13 13 gpio, sdio(cmd), uart1(txd)
mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd)
mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
mpp17 17 gpio, sdio(d3)
mpp18 18 gpo, nand(io0)
mpp19 19 gpo, nand(io1)
mpp20 20 gpio, mii(rxerr)
mpp21 21 gpio, audio(spdifi)
mpp22 22 gpio, audio(spdifo)
mpp23 23 gpio, audio(rmclk)
mpp24 24 gpio, audio(bclk)
mpp25 25 gpio, audio(sdo)
mpp26 26 gpio, audio(lrclk)
mpp27 27 gpio, audio(mclk)
mpp28 28 gpio, audio(sdi)
mpp29 29 gpio, audio(extclk)
* Marvell Kirkwood 88f6190
name pins functions
================================================================================
mpp0 0 gpio, nand(io2), spi(cs)
mpp1 1 gpo, nand(io3), spi(mosi)
mpp2 2 gpo, nand(io4), spi(sck)
mpp3 3 gpo, nand(io5), spi(miso)
mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
mpp6 6 sysrst(out), spi(mosi), ptp(trig)
mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
mii(col), mii-1(rxerr)
mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
mii(crs), sata0(prsnt)
mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig)
mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
ptp-2(trig), sata0(act)
mpp12 12 gpo, sdio(clk)
mpp13 13 gpio, sdio(cmd), uart1(txd)
mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
mpp17 17 gpio, sdio(d3), sata0(prsnt)
mpp18 18 gpo, nand(io0)
mpp19 19 gpo, nand(io1)
mpp20 20 gpio, ge1(txd0)
mpp21 21 gpio, ge1(txd1), sata0(act)
mpp22 22 gpio, ge1(txd2)
mpp23 23 gpio, ge1(txd3), sata0(prsnt)
mpp24 24 gpio, ge1(rxd0)
mpp25 25 gpio, ge1(rxd1)
mpp26 26 gpio, ge1(rxd2)
mpp27 27 gpio, ge1(rxd3)
mpp28 28 gpio, ge1(col)
mpp29 29 gpio, ge1(txclk)
mpp30 30 gpio, ge1(rxclk)
mpp31 31 gpio, ge1(rxclk)
mpp32 32 gpio, ge1(txclko)
mpp33 33 gpo, ge1(txclk)
mpp34 34 gpio, ge1(txen)
mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr)
* Marvell Kirkwood 88f6192
name pins functions
================================================================================
mpp0 0 gpio, nand(io2), spi(cs)
mpp1 1 gpo, nand(io3), spi(mosi)
mpp2 2 gpo, nand(io4), spi(sck)
mpp3 3 gpo, nand(io5), spi(miso)
mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
mpp6 6 sysrst(out), spi(mosi), ptp(trig)
mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
mii(col), mii-1(rxerr), sata1(prsnt)
mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
mii(crs), sata0(prsnt)
mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
ptp-2(trig), sata0(act)
mpp12 12 gpo, sdio(clk)
mpp13 13 gpio, sdio(cmd), uart1(txd)
mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
sata1(act)
mpp17 17 gpio, sdio(d3), sata0(prsnt)
mpp18 18 gpo, nand(io0)
mpp19 19 gpo, nand(io1)
mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
sata1(act)
mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
audio(spdifo)
mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
sata1(prsnt)
mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
audio(bclk)
mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst)
mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk)
mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs)
mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx)
mpp33 33 gpo, ge1(txclk), tdm(drx)
mpp34 34 gpio, ge1(txen), tdm(spi-cs1)
mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
* Marvell Kirkwood 88f6281
name pins functions
================================================================================
mpp0 0 gpio, nand(io2), spi(cs)
mpp1 1 gpo, nand(io3), spi(mosi)
mpp2 2 gpo, nand(io4), spi(sck)
mpp3 3 gpo, nand(io5), spi(miso)
mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
mpp6 6 sysrst(out), spi(mosi), ptp(trig)
mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
mii(col), mii-1(rxerr), sata1(prsnt)
mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
mii(crs), sata0(prsnt)
mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
ptp-2(trig), sata0(act)
mpp12 12 gpio, sdio(clk)
mpp13 13 gpio, sdio(cmd), uart1(txd)
mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
sata1(act)
mpp17 17 gpio, sdio(d3), sata0(prsnt)
mpp18 18 gpo, nand(io0)
mpp19 19 gpo, nand(io1)
mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
sata1(act)
mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
audio(spdifo)
mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
sata1(prsnt)
mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
audio(bclk)
mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst)
mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk)
mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs)
mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx)
mpp33 33 gpo, ge1(txclk), tdm(drx)
mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act)
mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo)
mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi)
mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk)
mpp45 45 gpio, ts(mp9), tdm(pclk)
mpp46 46 gpio, ts(mp10), tdm(fs)
mpp47 47 gpio, ts(mp11), tdm(drx)
mpp48 48 gpio, ts(mp12), tdm(dtx)
mpp49 49 gpio, ts(mp9), tdm(rx0ql), ptp(clk)
* Marvell Kirkwood 88f6282
name pins functions
================================================================================
mpp0 0 gpio, nand(io2), spi(cs)
mpp1 1 gpo, nand(io3), spi(mosi)
mpp2 2 gpo, nand(io4), spi(sck)
mpp3 3 gpo, nand(io5), spi(miso)
mpp4 4 gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
mpp5 5 gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
mpp6 6 sysrst(out), spi(mosi)
mpp7 7 gpo, spi(cs), lcd(pwm)
mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
mii-1(rxerr), sata1(prsnt)
mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
sata0(prsnt)
mpp10 10 gpo, spi(sck), uart0(txd), sata1(act)
mpp11 11 gpio, spi(miso), uart0(rxd), sata0(act)
mpp12 12 gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
mpp13 13 gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
audio(spdifi), audio-1(sdi)
mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
spi(cs)
mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
sata1(act), lcd(extclk)
mpp17 17 gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
mpp18 18 gpo, nand(io0), pex(clkreq)
mpp19 19 gpo, nand(io1)
mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
sata1(act), lcd(d0)
mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
audio(spdifo), lcd(d1)
mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
sata1(prsnt), lcd(d2)
mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
audio(bclk), lcd(d3)
mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
lcd(d4)
mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
lcd(d5)
mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
lcd(d6)
mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
lcd(d7)
mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
lcd(d8)
mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
mpp33 33 gpo, ge1(txclk), tdm(drx), lcd(d13)
mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
lcd(d15)
mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
mpp45 45 gpio, ts(mp9), tdm(pclk), lcd(e)
mpp46 46 gpio, ts(mp10), tdm(fs), lcd(hsync)
mpp47 47 gpio, ts(mp11), tdm(drx), lcd(vsync)
mpp48 48 gpio, ts(mp12), tdm(dtx), lcd(d16)
mpp49 49 gpo, tdm(rx0ql), pex(clkreq), lcd(d17)
* Marvell Bobcat 98dx4122
name pins functions
================================================================================
mpp0 0 gpio, nand(io2), spi(cs)
mpp1 1 gpo, nand(io3), spi(mosi)
mpp2 2 gpo, nand(io4), spi(sck)
mpp3 3 gpo, nand(io5), spi(miso)
mpp4 4 gpio, nand(io6), uart0(rxd)
mpp5 5 gpo, nand(io7), uart0(txd)
mpp6 6 sysrst(out), spi(mosi)
mpp7 7 gpo, pex(rsto), spi(cs)
mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts)
mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts)
mpp10 10 gpo, spi(sck), uart0(txd)
mpp11 11 gpio, spi(miso), uart0(rxd)
mpp13 13 gpio, uart1(txd)
mpp14 14 gpio, uart1(rxd)
mpp15 15 gpio, uart0(rts)
mpp16 16 gpio, uart0(cts)
mpp18 18 gpo, nand(io0)
mpp19 19 gpo, nand(io1)
mpp34 34 gpio
mpp35 35 gpio
mpp36 36 gpio
mpp37 37 gpio
mpp38 38 gpio
mpp39 39 gpio
mpp40 40 gpio
mpp41 41 gpio
mpp42 42 gpio
mpp43 43 gpio
mpp44 44 gpio
mpp45 45 gpio
mpp49 49 gpio

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* Marvell SoC pinctrl core driver for mpp
The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
(mpp) to a specific function. For each SoC family there is a SoC specific
driver using this core driver.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
A Marvell SoC pin configuration node is a node of a group of pins which can
be used for a specific device or function. Each node requires one or more
mpp pins or group of pins and a mpp function common to all pins.
Required properties for pinctrl driver:
- compatible: "marvell,<soc>-pinctrl"
Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
Required properties for pin configuration node:
- marvell,pins: string array of mpp pins or group of pins to be muxed.
- marvell,function: string representing a function to mux to for all
marvell,pins given in this pin configuration node. The function has to be
common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
valid pin/pin group names and available function names for each SoC.
Examples:
uart1: serial@12100 {
compatible = "ns16550a";
reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <7>;
pinctrl-0 = <&pmx_uart1_sw>;
pinctrl-names = "default";
};
pinctrl: pinctrl@d0200 {
compatible = "marvell,dove-pinctrl";
reg = <0xd0200 0x14>, <0xd0440 0x04>, <0xd802c 0x08>;
pmx_uart1_sw: pmx-uart1-sw {
marvell,pins = "mpp_uart1";
marvell,function = "uart1";
};
};

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* Marvell Orion SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",
"marvell,88f5281-pinctrl"
- reg: two register areas, the first one describing the first two
contiguous MPP registers, and the second one describing the single
final MPP register, separated from the previous one.
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.
* Marvell Orion 88f5181l
name pins functions
================================================================================
mpp0 0 pcie(rstout), pci(req2), gpio
mpp1 1 gpio, pci(gnt2)
mpp2 2 gpio, pci(req3), pci-1(pme)
mpp3 3 gpio, pci(gnt3)
mpp4 4 gpio, pci(req4)
mpp5 5 gpio, pci(gnt4)
mpp6 6 gpio, pci(req5), pci-1(clk)
mpp7 7 gpio, pci(gnt5), pci-1(clk)
mpp8 8 gpio, ge(col)
mpp9 9 gpio, ge(rxerr)
mpp10 10 gpio, ge(crs)
mpp11 11 gpio, ge(txerr)
mpp12 12 gpio, ge(txd4)
mpp13 13 gpio, ge(txd5)
mpp14 14 gpio, ge(txd6)
mpp15 15 gpio, ge(txd7)
mpp16 16 ge(rxd4)
mpp17 17 ge(rxd5)
mpp18 18 ge(rxd6)
mpp19 19 ge(rxd7)
* Marvell Orion 88f5182
name pins functions
================================================================================
mpp0 0 pcie(rstout), pci(req2), gpio
mpp1 1 gpio, pci(gnt2)
mpp2 2 gpio, pci(req3), pci-1(pme)
mpp3 3 gpio, pci(gnt3)
mpp4 4 gpio, pci(req4), bootnand(re), sata0(prsnt)
mpp5 5 gpio, pci(gnt4), bootnand(we), sata1(prsnt)
mpp6 6 gpio, pci(req5), nand(re0), sata0(act)
mpp7 7 gpio, pci(gnt5), nand(we0), sata1(act)
mpp8 8 gpio, ge(col)
mpp9 9 gpio, ge(rxerr)
mpp10 10 gpio, ge(crs)
mpp11 11 gpio, ge(txerr)
mpp12 12 gpio, ge(txd4), nand(re1), sata0(ledprsnt)
mpp13 13 gpio, ge(txd5), nand(we1), sata1(ledprsnt)
mpp14 14 gpio, ge(txd6), nand(re2), sata0(ledact)
mpp15 15 gpio, ge(txd7), nand(we2), sata1(ledact)
mpp16 16 uart1(rxd), ge(rxd4), gpio
mpp17 17 uart1(txd), ge(rxd5), gpio
mpp18 18 uart1(cts), ge(rxd6), gpio
mpp19 19 uart1(rts), ge(rxd7), gpio
* Marvell Orion 88f5281
name pins functions
================================================================================
mpp0 0 pcie(rstout), pci(req2), gpio
mpp1 1 gpio, pci(gnt2)
mpp2 2 gpio, pci(req3), pci(pme)
mpp3 3 gpio, pci(gnt3)
mpp4 4 gpio, pci(req4), bootnand(re)
mpp5 5 gpio, pci(gnt4), bootnand(we)
mpp6 6 gpio, pci(req5), nand(re0)
mpp7 7 gpio, pci(gnt5), nand(we0)
mpp8 8 gpio, ge(col)
mpp9 9 gpio, ge(rxerr)
mpp10 10 gpio, ge(crs)
mpp11 11 gpio, ge(txerr)
mpp12 12 gpio, ge(txd4), nand(re1)
mpp13 13 gpio, ge(txd5), nand(we1)
mpp14 14 gpio, ge(txd6), nand(re2)
mpp15 15 gpio, ge(txd7), nand(we2)
mpp16 16 uart1(rxd), ge(rxd4)
mpp17 17 uart1(txd), ge(rxd5)
mpp18 18 uart1(cts), ge(rxd6)
mpp19 19 uart1(rts), ge(rxd7)

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NVIDIA Tegra114 pinmux controller
The Tegra114 pinctrl binding is very similar to the Tegra20 and Tegra30
pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
a baseline, and only documents the differences between the two bindings.
Required properties:
- compatible: "nvidia,tegra114-pinmux"
- reg: Should contain the register physical address and length for each of
the pad control and mux registers. The first bank of address must be the
driver strength pad control register address and second bank address must
be pinmux register address.
Tegra114 adds the following optional properties for pin configuration subnodes:
- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
- nvidia,lock: Integer. Lock the pin configuration against further changes
until reset. 0: no, 1: yes.
- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
- nvidia,rcv-sel: Integer. Select VIL/VIH receivers. 0: normal, 1: high.
- nvidia,drive-type: Integer. Valid range 0...3.
As with Tegra20 and Terga30, see the Tegra TRM for complete details regarding
which groups support which functionality.
Valid values for pin and group names are:
per-pin mux groups:
These all support nvidia,function, nvidia,tristate, nvidia,pull,
nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
nvidia,io-reset and nvidia,rcv-sel.
ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, ulpi_data3_po4,
ulpi_data4_po5, ulpi_data5_po6, ulpi_data6_po7, ulpi_data7_po0,
ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0,
dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6,
sdmmc1_dat0_py7, clk2_out_pw5, clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4,
ddc_sda_pv5, uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, uart3_cts_n_pa1,
uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, pu5, pu6, gen1_i2c_sda_pc5,
gen1_i2c_scl_pc4, dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7,
clk3_out_pee0, clk3_req_pee1, gmi_wp_n_pc7, gmi_iordy_pi5, gmi_wait_pi7,
gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs0_n_pj0, gmi_cs1_n_pj2, gmi_cs2_n_pk3,
gmi_cs3_n_pk4, gmi_cs4_n_pk2, gmi_cs6_n_pi3, gmi_cs7_n_pi6, gmi_ad0_pg0,
gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
gmi_a16_pj7, gmi_a17_pb0, gmi_a18_pb1, gmi_a19_pk7, gmi_wr_n_pi0,
gmi_oe_n_pi1, gmi_dqs_p_pj3, gmi_rst_n_pi4, gen2_i2c_scl_pt5,
gen2_i2c_sda_pt6, sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0,
sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, cam_mclk_pcc0,
pcc1, pbb0, cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
pbb7, pcc2, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, kb_row1_pr1,
kb_row2_pr2, kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6,
kb_row7_pr7, kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_col0_pq0,
kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
kb_col6_pq6, kb_col7_pq7, clk_32k_out_pa0, sys_clk_req_pz5, core_pwr_req,
cpu_pwr_req, pwr_int_n, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2,
dap1_sclk_pn3, clk1_req_pee2, clk1_out_pw4, spdif_in_pk6, spdif_out_pk5,
dap2_fs_pa2, dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0,
gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, gpio_x4_aud_px4,
gpio_x5_aud_px5, gpio_x6_aud_px6, gpio_x7_aud_px7, sdmmc3_clk_pa6,
sdmmc3_cmd_pa7, sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5,
sdmmc3_dat3_pb4, hdmi_cec_pee3, sdmmc1_wp_n_pv3, sdmmc3_cd_n_pv2,
gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4, usb_vbus_en1_pn5,
sdmmc3_clk_lb_in_pee5, sdmmc3_clk_lb_out_pee4, reset_out_n.
drive groups:
These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode
and nvidia,drive-type.
ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, dap1, dap2, dap3, dap4,
dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
gmh, owr, uda.
Valid values for nvidia,functions are:
blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya,
displaya_alt, displayb, dtv, emc_dll, extperiph1, extperiph2,
extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2, i2c3, i2c4, i2cpwr,
i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc, nand, nand_alt, owr, pmi,
pwm0, pwm1, pwm2, pwm3, pwron, reset_out_n, rsvd1, rsvd2, rsvd3,
rsvd4, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc, spdif, spi1, spi2, spi3,
spi4, spi5, spi6, sysclk, trace, uarta, uartb, uartc, uartd, ulpi,
usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt3
Example:
pinmux: pinmux {
compatible = "nvidia,tegra114-pinmux";
reg = <0x70000868 0x148 /* Pad control registers */
0x70003000 0x40c>; /* PinMux registers */
};
Example board file extract:
pinctrl {
sdmmc4_default: pinmux {
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4",
nvidia,function = "sdmmc4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
sdmmc4_dat0_paa0 {
nvidia,pins = "sdmmc4_dat0_paa0",
"sdmmc4_dat1_paa1",
"sdmmc4_dat2_paa2",
"sdmmc4_dat3_paa3",
"sdmmc4_dat4_paa4",
"sdmmc4_dat5_paa5",
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,function = "sdmmc4";
nvidia,pull = <2>;
nvidia,tristate = <0>;
};
};
};
sdhci@78000400 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc4_default>;
};

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NVIDIA Tegra124 pinmux controller
The Tegra124 pinctrl binding is very similar to the Tegra20 and Tegra30
pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
a baseline, and only documents the differences between the two bindings.
Required properties:
- compatible: "nvidia,tegra124-pinmux"
- reg: Should contain a list of base address and size pairs for:
-- first entry - the drive strength and pad control registers.
-- second entry - the pinmux registers
-- third entry - the MIPI_PAD_CTRL register
Tegra124 adds the following optional properties for pin configuration subnodes.
The macros for options are defined in the
include/dt-binding/pinctrl/pinctrl-tegra.h.
- nvidia,enable-input: Integer. Enable the pin's input path.
enable :TEGRA_PIN_ENABLE0 and
disable or output only: TEGRA_PIN_DISABLE.
- nvidia,open-drain: Integer.
enable: TEGRA_PIN_ENABLE.
disable: TEGRA_PIN_DISABLE.
- nvidia,lock: Integer. Lock the pin configuration against further changes
until reset.
enable: TEGRA_PIN_ENABLE.
disable: TEGRA_PIN_DISABLE.
- nvidia,io-reset: Integer. Reset the IO path.
enable: TEGRA_PIN_ENABLE.
disable: TEGRA_PIN_DISABLE.
- nvidia,rcv-sel: Integer. Select VIL/VIH receivers.
normal: TEGRA_PIN_DISABLE
high: TEGRA_PIN_ENABLE
Please refer the Tegra TRM for complete details regarding which groups
support which functionality.
Valid values for pin and group names are:
per-pin mux groups:
These all support nvidia,function, nvidia,tristate, nvidia,pull,
nvidia,enable-input. Some support nvidia,lock nvidia,open-drain,
nvidia,io-reset and nvidia,rcv-sel.
ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, ulpi_data3_po4,
ulpi_data4_po5, ulpi_data5_po6, ulpi_data6_po7, ulpi_data7_po0,
ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0,
dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6,
sdmmc1_dat0_py7, clk2_out_pw5, clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4,
ddc_sda_pv5, uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, uart3_cts_n_pa1,
uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, pu5, pu6, gen1_i2c_scl_pc4,
gen1_i2c_sda_pc5, dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6,
dap4_sclk_pp7, clk3_out_pee0, clk3_req_pee1, pc7, pi5, pi7, pk0, pk1,
pj0, pj2, pk3, pk4, pk2, pi3, pi6, pg0, pg1, pg2, pg3, pg4, pg5, pg6,
pg7, ph0, ph1, ph2, ph3, ph4, ph5, ph6, ph7, pj7, pb0, pb1, pk7, pi0,
pi1, pi2, pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6, sdmmc4_clk_pcc4,
sdmmc4_cmd_pt7, sdmmc4_dat0_paa0, sdmmc4_dat1_paa1, sdmmc4_dat2_paa2,
sdmmc4_dat3_paa3, sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6,
sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0, cam_i2c_scl_pbb1,
cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7, pcc2, jtag_rtck,
pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, kb_col0_pq0, kb_col1_pq1,
kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5, kb_col6_pq6,
kb_col7_pq7, clk_32k_out_pa0, core_pwr_req, cpu_pwr_req, pwr_int_n,
clk_32k_in, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2,
dap1_sclk_pn3, dap_mclk1_req_pee2, dap_mclk1_pw4, spdif_in_pk6,
spdif_out_pk5, dap2_fs_pa2, dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3,
dvfs_pwm_px0, gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2,
gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6, gpio_x7_aud_px7,
sdmmc3_clk_pa6, sdmmc3_cmd_pa7, sdmmc3_dat0_pb7, sdmmc3_dat1_pb6,
sdmmc3_dat2_pb5, sdmmc3_dat3_pb4, pex_l0_rst_n_pdd1,
pex_l0_clkreq_n_pdd2, pex_wake_n_pdd3, pex_l1_rst_n_pdd5,
pex_l1_clkreq_n_pdd6, hdmi_cec_pee3, sdmmc1_wp_n_pv3,
sdmmc3_cd_n_pv2, gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4,
usb_vbus_en1_pn5, sdmmc3_clk_lb_out_pee4, sdmmc3_clk_lb_in_pee5,
gmi_clk_lb, reset_out_n, kb_row16_pt0, kb_row17_pt1, usb_vbus_en2_pff1,
pff2, dp_hpd_pff0,
drive groups:
These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode
and nvidia,drive-type.
ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, dap1, dap2, dap3, dap4,
dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
gmh, owr, uda, gpv, dev3, cec, usb_vbus_en, ao3, ao0, hv0, sdio4, ao4.
MIPI pad control groups:
These support only the nvidia,function property.
dsi_b
Valid values for nvidia,functions are:
blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya,
displaya_alt, displayb, dtv, extperiph1, extperiph2, extperiph3,
gmi, gmi_alt, hda, hsi, i2c1, i2c2, i2c3, i2c4, i2cpwr, i2s0,
i2s1, i2s2, i2s3, i2s4, irda, kbc, owr, pmi, pwm0, pwm1, pwm2, pwm3,
pwron, reset_out_n, rsvd1, rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2, sdmmc3,
sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta,
uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6,
vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla, pe0, pe, pe1,
dp, rtck, sys, clk tmds, csi, dsi_b
Example:
pinmux: pinmux {
compatible = "nvidia,tegra124-pinmux";
reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
<0x0 0x70003000 0x0 0x434>, /* Mux registers */
<0x0 0x70000820 0x0 0x8>; /* MIPI pad control */
};
Example pinmux entries:
pinctrl {
sdmmc4_default: pinmux {
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4",
nvidia,function = "sdmmc4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc4_dat0_paa0 {
nvidia,pins = "sdmmc4_dat0_paa0",
"sdmmc4_dat1_paa1",
"sdmmc4_dat2_paa2",
"sdmmc4_dat3_paa3",
"sdmmc4_dat4_paa4",
"sdmmc4_dat5_paa5",
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,function = "sdmmc4";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
};
};
sdhci@78000400 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc4_default>;
};

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Device tree binding for NVIDIA Tegra XUSB pad controller
========================================================
The Tegra XUSB pad controller manages a set of lanes, each of which can be
assigned to one out of a set of different pads. Some of these pads have an
associated PHY that must be powered up before the pad can be used.
This document defines the device-specific binding for the XUSB pad controller.
Refer to pinctrl-bindings.txt in this directory for generic information about
pin controller device tree bindings and ../phy/phy-bindings.txt for details on
how to describe and reference PHYs in device trees.
Required properties:
--------------------
- compatible: should be "nvidia,tegra124-xusb-padctl"
- reg: Physical base address and length of the controller's registers.
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- padctl
- #phy-cells: Should be 1. The specifier is the index of the PHY to reference.
See <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> for the list of valid values.
Lane muxing:
------------
Child nodes contain the pinmux configurations following the conventions from
the pinctrl-bindings.txt document. Typically a single, static configuration is
given and applied at boot time.
Each subnode describes groups of lanes along with parameters and pads that
they should be assigned to. The name of these subnodes is not important. All
subnodes should be parsed solely based on their content.
Each subnode only applies the parameters that are explicitly listed. In other
words, if a subnode that lists a function but no pin configuration parameters
implies no information about any pin configuration parameters. Similarly, a
subnode that describes only an IDDQ parameter implies no information about
what function the pins are assigned to. For this reason even seemingly boolean
values are actually tristates in this binding: unspecified, off or on.
Unspecified is represented as an absent property, and off/on are represented
as integer values 0 and 1.
Required properties:
- nvidia,lanes: An array of strings. Each string is the name of a lane.
Optional properties:
- nvidia,function: A string that is the name of the function (pad) that the
pin or group should be assigned to. Valid values for function names are
listed below.
- nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes)
Note that not all of these properties are valid for all lanes. Lanes can be
divided into three groups:
- otg-0, otg-1, otg-2:
Valid functions for this group are: "snps", "xusb", "uart", "rsvd".
The nvidia,iddq property does not apply to this group.
- ulpi-0, hsic-0, hsic-1:
Valid functions for this group are: "snps", "xusb".
The nvidia,iddq property does not apply to this group.
- pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0:
Valid functions for this group are: "pcie", "usb3", "sata", "rsvd".
Example:
========
SoC file extract:
-----------------
padctl@0,7009f000 {
compatible = "nvidia,tegra124-xusb-padctl";
reg = <0x0 0x7009f000 0x0 0x1000>;
resets = <&tegra_car 142>;
reset-names = "padctl";
#phy-cells = <1>;
};
Board file extract:
-------------------
pcie-controller@0,01003000 {
...
phys = <&padctl 0>;
phy-names = "pcie";
...
};
...
padctl: padctl@0,7009f000 {
pinctrl-0 = <&padctl_default>;
pinctrl-names = "default";
padctl_default: pinmux {
usb3 {
nvidia,lanes = "pcie-0", "pcie-1";
nvidia,function = "usb3";
nvidia,iddq = <0>;
};
pcie {
nvidia,lanes = "pcie-2", "pcie-3",
"pcie-4";
nvidia,function = "pcie";
nvidia,iddq = <0>;
};
sata {
nvidia,lanes = "sata-0";
nvidia,function = "sata";
nvidia,iddq = <0>;
};
};
};

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NVIDIA Tegra20 pinmux controller
Required properties:
- compatible: "nvidia,tegra20-pinmux"
- reg: Should contain the register physical address and length for each of
the tri-state, mux, pull-up/down, and pad control register sets.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Tegra's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, tristate, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function or tristate parameter. For this
reason, even seemingly boolean values are actually tristates in this binding:
unspecified, off, or on. Unspecified is represented as an absent property,
and off/on are represented as integer values 0 and 1.
Required subnode-properties:
- nvidia,pins : An array of strings. Each string contains the name of a pin or
group. Valid values for these names are listed below.
Optional subnode-properties:
- nvidia,function: A string containing the name of the function to mux to the
pin or group. Valid values for function names are listed below. See the Tegra
TRM to determine which are valid for each pin or group.
- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
0: none, 1: down, 2: up.
- nvidia,tristate: Integer.
0: drive, 1: tristate.
- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
0: no, 1: yes.
- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
0: no, 1: yes.
- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
most power. Controls the drive power or current. See "Low Power Mode"
or "LPMD1" and "LPMD0" in the Tegra TRM.
- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
Tegra TRM.
- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
Tegra TRM.
- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
fastest. The range of valid values depends on the pingroup. See
"DRVDN_SLWR" in the Tegra TRM.
- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
fastest. The range of valid values depends on the pingroup. See
"DRVUP_SLWF" in the Tegra TRM.
Note that many of these properties are only valid for certain specific pins
or groups. See the Tegra TRM and various pinmux spreadsheets for complete
details regarding which groups support which functionality. The Linux pinctrl
driver may also be a useful reference, since it consolidates, disambiguates,
and corrects data from all those sources.
Valid values for pin and group names are:
mux groups:
These all support nvidia,function, nvidia,tristate, and many support
nvidia,pull.
ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4,
ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn,
ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp,
lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs,
owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi,
spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad,
uca, ucb, uda.
tristate groups:
These only support nvidia,pull.
ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
ld19_18, ld21_20, ld23_22.
drive groups:
With some exceptions, these support nvidia,high-speed-mode,
nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
nvidia,pull-up-strength, nvidia,slew-rate-rising, nvidia,slew-rate-falling.
drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,
drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a,
drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc,
drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
drive_uda.
Valid values for nvidia,functions are:
ahb_clk, apb_clk, audio_sync, crt, dap1, dap2, dap3, dap4, dap5,
displaya, displayb, emc_test0_dll, emc_test1_dll, gmi, gmi_int,
hdmi, i2cp, i2c1, i2c2, i2c3, ide, irda, kbc, mio, mipi_hs, nand,
osc, owr, pcie, plla_out, pllc_out1, pllm_out1, pllp_out2, pllp_out3,
pllp_out4, pwm, pwr_intr, pwr_on, rsvd1, rsvd2, rsvd3, rsvd4, rtck,
sdio1, sdio2, sdio3, sdio4, sflash, spdif, spi1, spi2, spi2_alt,
spi3, spi4, trace, twc, uarta, uartb, uartc, uartd, uarte, ulpi,
vi, vi_sensor_clk, xio
Example:
pinctrl@70000000 {
compatible = "nvidia,tegra20-pinmux";
reg = < 0x70000014 0x10 /* Tri-state registers */
0x70000080 0x20 /* Mux registers */
0x700000a0 0x14 /* Pull-up/down registers */
0x70000868 0xa8 >; /* Pad control registers */
};
Example board file extract:
pinctrl@70000000 {
sdio4_default: sdio4_default {
atb {
nvidia,pins = "atb", "gma", "gme";
nvidia,function = "sdio4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
};
};
sdhci@c8000600 {
pinctrl-names = "default";
pinctrl-0 = <&sdio4_default>;
};

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NVIDIA Tegra30 pinmux controller
The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding,
as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
that binding as a baseline, and only documents the differences between the
two bindings.
Required properties:
- compatible: "nvidia,tegra30-pinmux"
- reg: Should contain the register physical address and length for each of
the pad control and mux registers.
Tegra30 adds the following optional properties for pin configuration subnodes:
- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
- nvidia,lock: Integer. Lock the pin configuration against further changes
until reset. 0: no, 1: yes.
- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
As with Tegra20, see the Tegra TRM for complete details regarding which groups
support which functionality.
Valid values for pin and group names are:
per-pin mux groups:
These all support nvidia,function, nvidia,tristate, nvidia,pull,
nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
nvidia,io-reset.
clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3,
dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0,
gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1,
uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5,
lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2,
sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7,
lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5,
lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3,
lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0,
gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4,
gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1,
gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2,
gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7,
vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5,
vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0,
dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5,
lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3,
dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0,
kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0,
pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7,
lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1,
spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6,
spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3,
sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4,
sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0,
sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7,
cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4,
clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7,
pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1,
clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr,
pwr_int_n.
drive groups:
These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode.
ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1,
dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg,
gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2,
uart3, uda, vi1.
Valid values for nvidia,functions are:
blink, cec, clk_12m_out, clk_32k_in, core_pwr_req, cpu_pwr_req, crt,
dap, ddr, dev3, displaya, displayb, dtv, extperiph1, extperiph2,
extperiph3, gmi, gmi_alt, hda, hdcp, hdmi, hsi, i2c1, i2c2, i2c3,
i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, invalid, kbc, mio, nand,
nand_alt, owr, pcie, pwm0, pwm1, pwm2, pwm3, pwr_int_n, rsvd1, rsvd2,
rsvd3, rsvd4, rtck, sata, sdmmc1, sdmmc2, sdmmc3, sdmmc4, spdif, spi1,
spi2, spi2_alt, spi3, spi4, spi5, spi6, sysclk, test, trace, uarta,
uartb, uartc, uartd, uarte, ulpi, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6,
vi, vi_alt1, vi_alt2, vi_alt3
Example:
pinctrl@70000000 {
compatible = "nvidia,tegra30-pinmux";
reg = < 0x70000868 0xd0 /* Pad control registers */
0x70003000 0x3e0 >; /* Mux registers */
};
Example board file extract:
pinctrl@70000000 {
sdmmc4_default: pinmux {
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4",
"sdmmc4_rst_n_pcc3";
nvidia,function = "sdmmc4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
sdmmc4_dat0_paa0 {
nvidia,pins = "sdmmc4_dat0_paa0",
"sdmmc4_dat1_paa1",
"sdmmc4_dat2_paa2",
"sdmmc4_dat3_paa3",
"sdmmc4_dat4_paa4",
"sdmmc4_dat5_paa5",
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,function = "sdmmc4";
nvidia,pull = <2>;
nvidia,tristate = <0>;
};
};
};
sdhci@78000400 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc4_default>;
};

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== Introduction ==
Hardware modules that control pin multiplexing or configuration parameters
such as pull-up/down, tri-state, drive-strength etc are designated as pin
controllers. Each pin controller must be represented as a node in device tree,
just like any other hardware module.
Hardware modules whose signals are affected by pin configuration are
designated client devices. Again, each client device must be represented as a
node in device tree, just like any other hardware module.
For a client device to operate correctly, certain pin controllers must
set up certain specific pin configurations. Some client devices need a
single static pin configuration, e.g. set up during initialization. Others
need to reconfigure pins at run-time, for example to tri-state pins when the
device is inactive. Hence, each client device can define a set of named
states. The number and names of those states is defined by the client device's
own binding.
The common pinctrl bindings defined in this file provide an infrastructure
for client device device tree nodes to map those state names to the pin
configuration used by those states.
Note that pin controllers themselves may also be client devices of themselves.
For example, a pin controller may set up its own "active" state when the
driver loads. This would allow representing a board's static pin configuration
in a single place, rather than splitting it across multiple client device
nodes. The decision to do this or not somewhat rests with the author of
individual board device tree files, and any requirements imposed by the
bindings for the individual client devices in use by that board, i.e. whether
they require certain specific named states for dynamic pin configuration.
== Pinctrl client devices ==
For each client device individually, every pin state is assigned an integer
ID. These numbers start at 0, and are contiguous. For each state ID, a unique
property exists to define the pin configuration. Each state may also be
assigned a name. When names are used, another property exists to map from
those names to the integer IDs.
Each client device's own binding determines the set of states the must be
defined in its device tree node, and whether to define the set of state
IDs that must be provided, or whether to define the set of state names that
must be provided.
Required properties:
pinctrl-0: List of phandles, each pointing at a pin configuration
node. These referenced pin configuration nodes must be child
nodes of the pin controller that they configure. Multiple
entries may exist in this list so that multiple pin
controllers may be configured, or so that a state may be built
from multiple nodes for a single pin controller, each
contributing part of the overall configuration. See the next
section of this document for details of the format of these
pin configuration nodes.
In some cases, it may be useful to define a state, but for it
to be empty. This may be required when a common IP block is
used in an SoC either without a pin controller, or where the
pin controller does not affect the HW module in question. If
the binding for that IP block requires certain pin states to
exist, they must still be defined, but may be left empty.
Optional properties:
pinctrl-1: List of phandles, each pointing at a pin configuration
node within a pin controller.
...
pinctrl-n: List of phandles, each pointing at a pin configuration
node within a pin controller.
pinctrl-names: The list of names to assign states. List entry 0 defines the
name for integer state ID 0, list entry 1 for state ID 1, and
so on.
For example:
/* For a client device requiring named states */
device {
pinctrl-names = "active", "idle";
pinctrl-0 = <&state_0_node_a>;
pinctrl-1 = <&state_1_node_a &state_1_node_b>;
};
/* For the same device if using state IDs */
device {
pinctrl-0 = <&state_0_node_a>;
pinctrl-1 = <&state_1_node_a &state_1_node_b>;
};
/*
* For an IP block whose binding supports pin configuration,
* but in use on an SoC that doesn't have any pin control hardware
*/
device {
pinctrl-names = "active", "idle";
pinctrl-0 = <>;
pinctrl-1 = <>;
};
== Pin controller devices ==
Pin controller devices should contain the pin configuration nodes that client
devices reference.
For example:
pincontroller {
... /* Standard DT properties for the device itself elided */
state_0_node_a {
...
};
state_1_node_a {
...
};
state_1_node_b {
...
};
}
The contents of each of those pin configuration child nodes is defined
entirely by the binding for the individual pin controller device. There
exists no common standard for this content.
The pin configuration nodes need not be direct children of the pin controller
device; they may be grandchildren, for example. Whether this is legal, and
whether there is any interaction between the child and intermediate parent
nodes, is again defined entirely by the binding for the individual pin
controller device.
== Generic pin multiplexing node content ==
pin multiplexing nodes:
function - the mux function to select
groups - the list of groups to select with this function
Example:
state_0_node_a {
function = "uart0";
groups = "u0rxtx", "u0rtscts";
};
state_1_node_a {
function = "spi0";
groups = "spi0pins";
};
== Generic pin configuration node content ==
Many data items that are represented in a pin configuration node are common
and generic. Pin control bindings should use the properties defined below
where they are applicable; not all of these properties are relevant or useful
for all hardware or binding structures. Each individual binding document
should state which of these generic properties, if any, are used, and the
structure of the DT nodes that contain these properties.
Supported generic properties are:
pins - the list of pins that properties in the node
apply to (either this or "group" has to be
specified)
group - the group to apply the properties to, if the driver
supports configuration of whole groups rather than
individual pins (either this or "pins" has to be
specified)
bias-disable - disable any pin bias
bias-high-impedance - high impedance mode ("third-state", "floating")
bias-bus-hold - latch weakly
bias-pull-up - pull up the pin
bias-pull-down - pull down the pin
bias-pull-pin-default - use pin-default pull state
drive-push-pull - drive actively high and low
drive-open-drain - drive with open drain
drive-open-source - drive with open source
drive-strength - sink or source at most X mA
input-enable - enable input on pin (no effect on output)
input-disable - disable input on pin (no effect on output)
input-schmitt-enable - enable schmitt-trigger mode
input-schmitt-disable - disable schmitt-trigger mode
input-debounce - debounce mode with debound time X
power-source - select between different power supplies
low-power-enable - enable low power mode
low-power-disable - disable low power mode
output-low - set the pin to output mode with low level
output-high - set the pin to output mode with high level
slew-rate - set the slew rate
For example:
state_0_node_a {
pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
bias-pull-up;
};
state_1_node_a {
pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
output-high;
};
state_2_node_a {
group = "foo-group";
bias-pull-up;
};
Some of the generic properties take arguments. For those that do, the
arguments are described below.
- pins takes a list of pin names or IDs as a required argument. The specific
binding for the hardware defines:
- Whether the entries are integers or strings, and their meaning.
- bias-pull-up, -down and -pin-default take as optional argument on hardware
supporting it the pull strength in Ohm. bias-disable will disable the pull.
- drive-strength takes as argument the target strength in mA.
- input-debounce takes the debounce time in usec as argument
or 0 to disable debouncing
More in-depth documentation on these parameters can be found in
<include/linux/pinctrl/pinconfig-generic.h>

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Palmas Pincontrol bindings
The pins of Palmas device can be set on different option and provides
the configuration for Pull UP/DOWN, open drain etc.
Required properties:
- compatible: It must be one of following:
- "ti,palmas-pinctrl" for Palma series of the pincontrol.
- "ti,tps65913-pinctrl" for Palma series device TPS65913.
- "ti,tps80036-pinctrl" for Palma series device TPS80036.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Palmas's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
list of pins. This configuration can include the mux function to select on
those pin(s), and various pin configuration parameters, such as pull-up,
open drain.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
Optional properties:
- ti,palmas-enable-dvfs1: Enable DVFS1. Configure pins for DVFS1 mode.
Selection primary or secondary function associated to I2C2_SCL_SCE,
I2C2_SDA_SDO pin/pad for DVFS1 interface
- ti,palmas-enable-dvfs2: Enable DVFS2. Configure pins for DVFS2 mode.
Selection primary or secondary function associated to GPADC_START
and SYSEN2 pin/pad for DVFS2 interface
This binding uses the following generic properties as defined in
pinctrl-bindings.txt:
Required: pins
Options: function, bias-disable, bias-pull-up, bias-pull-down,
drive-open-drain.
Note that many of these properties are only valid for certain specific pins.
See the Palmas device datasheet for complete details regarding which pins
support which functionality.
Valid values for pin names are:
gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, gpio9,
gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, vac, powergood,
nreswarm, pwrdown, gpadc_start, reset_in, nsleep, enable1, enable2,
int.
Valid value of function names are:
gpio, led, pwm, regen, sysen, clk32kgaudio, id, vbus_det, chrg_det,
vac, vacok, powergood, usb_psel, msecure, pwrhold, int, nreswarm,
simrsto, simrsti, low_vbat, wireless_chrg1, rcm, pwrdown, gpadc_start,
reset_in, nsleep, enable.
There are 4 special functions: opt0, opt1, opt2 and opt3. If any of these
functions is selected then directly pins register will be written with 0, 1, 2
or 3 respectively if it is valid for that pins or list of pins.
Example:
palmas: tps65913 {
....
pinctrl {
compatible = "ti,tps65913-pinctrl";
ti,palmas-enable-dvfs1;
pinctrl-names = "default";
pinctrl-0 = <&palmas_pins_state>;
palmas_pins_state: pinmux {
gpio0 {
pins = "gpio0";
function = "id";
bias-pull-up;
};
vac {
pins = "vac";
function = "vacok";
bias-pull-down;
};
gpio5 {
pins = "gpio5";
function = "opt0";
drive-open-drain = <1>;
};
};
};
....
};

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One-register-per-pin type device tree based pinctrl driver
Required properties:
- compatible : "pinctrl-single" or "pinconf-single".
"pinctrl-single" means that pinconf isn't supported.
"pinconf-single" means that generic pinconf is supported.
- reg : offset and length of the register set for the mux registers
- pinctrl-single,register-width : pinmux register access width in bits
- pinctrl-single,function-mask : mask of allowed pinmux function bits
in the pinmux register
Optional properties:
- pinctrl-single,function-off : function off mode for disabled state if
available and same for all registers; if not specified, disabling of
pin functions is ignored
- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
more than one pin, for which "pinctrl-single,function-mask" property specifies
position mask of pin.
- pinctrl-single,drive-strength : array of value that are used to configure
drive strength in the pinmux register. They're value of drive strength
current and drive strength mask.
/* drive strength current, mask */
pinctrl-single,power-source = <0x30 0xf0>;
- pinctrl-single,bias-pullup : array of value that are used to configure the
input bias pullup in the pinmux register.
/* input, enabled pullup bits, disabled pullup bits, mask */
pinctrl-single,bias-pullup = <0 1 0 1>;
- pinctrl-single,bias-pulldown : array of value that are used to configure the
input bias pulldown in the pinmux register.
/* input, enabled pulldown bits, disabled pulldown bits, mask */
pinctrl-single,bias-pulldown = <2 2 0 2>;
* Two bits to control input bias pullup and pulldown: User should use
pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
pullup, and the other one bit means pulldown.
* Three bits to control input bias enable, pullup and pulldown. User should
use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
enable bit should be included in pullup or pulldown bits.
* Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
pinctrl-single,bias-disable. Because pinctrl single driver could implement
it by calling pulldown, pullup disabled.
- pinctrl-single,input-schmitt : array of value that are used to configure
input schmitt in the pinmux register. In some silicons, there're two input
schmitt value (rising-edge & falling-edge) in the pinmux register.
/* input schmitt value, mask */
pinctrl-single,input-schmitt = <0x30 0x70>;
- pinctrl-single,input-schmitt-enable : array of value that are used to
configure input schmitt enable or disable in the pinmux register.
/* input, enable bits, disable bits, mask */
pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
- pinctrl-single,low-power-mode : array of value that are used to configure
low power mode of this pin. For some silicons, the low power mode will
control the output of the pin when the pad including the pin enter low
power mode.
/* low power mode value, mask */
pinctrl-single,low-power-mode = <0x288 0x388>;
- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
range. They're value of subnode phandle, pin base in pinctrl device, pin
number in this range, GPIO function value of this GPIO range.
The number of parameters is depend on #pinctrl-single,gpio-range-cells
property.
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
- interrupt-controller : standard interrupt controller binding if using
interrupts for wake-up events for example. In this case pinctrl-single
is set up as a chained interrupt controller and the wake-up interrupts
can be requested by the drivers using request_irq().
- #interrupt-cells : standard interrupt binding if using interrupts
This driver assumes that there is only one register for each pin (unless the
pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
specified in the pinctrl-bindings.txt document in this directory.
The pin configuration nodes for pinctrl-single are specified as pinctrl
register offset and value pairs using pinctrl-single,pins. Only the bits
specified in pinctrl-single,function-mask are updated. For example, setting
a pin for a device could be done with:
pinctrl-single,pins = <0xdc 0x118>;
Where 0xdc is the offset from the pinctrl register base address for the
device pinctrl register, and 0x118 contains the desired value of the
pinctrl register. See the device example and static board pins example
below for more information.
In case when one register changes more than one pin's mux the
pinctrl-single,bits need to be used which takes three parameters:
pinctrl-single,bits = <0xdc 0x18 0xff>;
Where 0xdc is the offset from the pinctrl register base address for the
device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
be used when applying this change to the register.
Optional sub-node: In case some pins could be configured as GPIO in the pinmux
register, those pins could be defined as a GPIO range. This sub-node is required
by pinctrl-single,gpio-range property.
Required properties in sub-node:
- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
pinctrl-single,gpio-range property.
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
Example:
/* SoC common file */
/* first controller instance for pins in core domain */
pmx_core: pinmux@4a100040 {
compatible = "pinctrl-single";
reg = <0x4a100040 0x0196>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xffff>;
};
/* second controller instance for pins in wkup domain */
pmx_wkup: pinmux@4a31e040 {
compatible = "pinctrl-single";
reg = <0x4a31e040 0x0038>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xffff>;
};
control_devconf0: pinmux@48002274 {
compatible = "pinctrl-single";
reg = <0x48002274 4>; /* Single register */
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x5F>;
};
/* third controller instance for pins in gpio domain */
pmx_gpio: pinmux@d401e000 {
compatible = "pinconf-single";
reg = <0xd401e000 0x0330>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <7>;
/* sparse GPIO range could be supported */
pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
&range 12 1 0 &range 13 29 1
&range 43 1 0 &range 44 49 1
&range 94 1 1 &range 96 2 1>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};
/* board specific .dts file */
&pmx_core {
/*
* map all board specific static pins enabled by the pinctrl driver
* itself during the boot (or just set them up in the bootloader)
*/
pinctrl-names = "default";
pinctrl-0 = <&board_pins>;
board_pins: pinmux_board_pins {
pinctrl-single,pins = <
0x6c 0xf
0x6e 0xf
0x70 0xf
0x72 0xf
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x208 0 /* UART0_RXD (IOCFG138) */
0x20c 0 /* UART0_TXD (IOCFG139) */
>;
pinctrl-single,bias-pulldown = <0 2 2>;
pinctrl-single,bias-pullup = <0 1 1>;
};
/* map uart2 pins */
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
0xd8 0x118
0xda 0
0xdc 0x118
0xde 0
>;
};
};
&control_devconf0 {
mcbsp1_pins: pinmux_mcbsp1_pins {
pinctrl-single,bits = <
0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
>;
};
mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins {
pinctrl-single,bits = <
0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
};

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CSR SiRFprimaII pinmux controller
Required properties:
- compatible : "sirf,prima2-pinctrl"
- reg : Address range of the pinctrl registers
- interrupts : Interrupts used by every GPIO group
- gpio-controller : Indicates this device is a GPIO controller
- interrupt-controller : Marks the device node as an interrupt controller
Optional properties:
- sirf,pullups : if n-th bit of m-th bank is set, set a pullup on GPIO-n of bank m
- sirf,pulldowns : if n-th bit of m-th bank is set, set a pulldown on GPIO-n of bank m
Please refer to pinctrl-bindings.txt in this directory for details of the common
pinctrl bindings used by client devices.
SiRFprimaII's pinmux nodes act as a container for an arbitrary number of subnodes.
Each of these subnodes represents some desired configuration for a group of pins.
Required subnode-properties:
- sirf,pins : An array of strings. Each string contains the name of a group.
- sirf,function: A string containing the name of the function to mux to the
group.
Valid values for group and function names can be found from looking at the
group and function arrays in driver files:
drivers/pinctrl/pinctrl-sirf.c
For example, pinctrl might have subnodes like the following:
uart2_pins_a: uart2@0 {
uart {
sirf,pins = "uart2grp";
sirf,function = "uart2";
};
};
uart2_noflow_pins_a: uart2@1 {
uart {
sirf,pins = "uart2_nostreamctrlgrp";
sirf,function = "uart2_nostreamctrl";
};
};
For a specific board, if it wants to use uart2 without hardware flow control,
it can add the following to its board-specific .dts file.
uart2: uart@0xb0070000 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_noflow_pins_a>;
}

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*ST pin controller.
Each multi-function pin is controlled, driven and routed through the
PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
and multiple alternate functions(ALT1 - ALTx) that directly connect
the pin to different hardware blocks.
When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
Pull Up (PU) are driven by the related PIO block.
ST pinctrl driver controls PIO multiplexing block and also interacts with
gpio driver to configure a pin.
GPIO bank can have one of the two possible types of interrupt-wirings.
First type is via irqmux, single interrupt is used by multiple gpio banks. This
reduces number of overall interrupts numbers required. All these banks belong to
a single pincontroller.
_________
| |----> [gpio-bank (n) ]
| |----> [gpio-bank (n + 1)]
[irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
| |----> [gpio-bank (... )]
|_________|----> [gpio-bank (n + 7)]
Second type has a dedicated interrupt per gpio bank.
[irqN]----> [gpio-bank (n)]
Pin controller node:
Required properties:
- compatible : should be "st,<SOC>-<pio-block>-pinctrl"
like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on.
- st,syscfg : Should be a phandle of the syscfg node.
- st,retime-pin-mask : Should be mask to specify which pins can be retimed.
If the property is not present, it is assumed that all the pins in the
bank are capable of retiming. Retiming is mainly used to improve the
IO timing margins of external synchronous interfaces.
- ranges : defines mapping between pin controller node (parent) to gpio-bank
node (children).
Optional properties:
- interrupts : Interrupt number of the irqmux. If the interrupt is shared
with other gpio banks via irqmux.
a irqline and gpio banks.
- reg : irqmux memory resource. If irqmux is present.
- reg-names : irqmux resource should be named as "irqmux".
GPIO controller/bank node.
Required properties:
- gpio-controller : Indicates this device is a GPIO controller
- #gpio-cells : Should be one. The first cell is the pin number.
- st,bank-name : Should be a name string for this bank as specified in
datasheet.
Optional properties:
- interrupts : Interrupt number for this gpio bank. If there is a dedicated
interrupt wired up for this gpio bank.
- interrupt-controller : Indicates this device is a interrupt controller. GPIO
bank can be an interrupt controller iff one of the interrupt type either via
irqmux or a dedicated interrupt per bank is specified.
- #interrupt-cells: the value of this property should be 2.
- First Cell: represents the external gpio interrupt number local to the
gpio interrupt space of the controller.
- Second Cell: flags to identify the type of the interrupt
- 1 = rising edge triggered
- 2 = falling edge triggered
- 3 = rising and falling edge triggered
- 4 = high level triggered
- 8 = low level triggered
for related macros look in:
include/dt-bindings/interrupt-controller/irq.h
Example:
pin-controller-sbc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih415-sbc-pinctrl";
st,syscfg = <&syscfg_sbc>;
reg = <0xfe61f080 0x4>;
reg-names = "irqmux";
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irqmux";
ranges = <0 0xfe610000 0x5000>;
PIO0: gpio@fe610000 {
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 0x100>;
st,bank-name = "PIO0";
};
...
pin-functions nodes follow...
};
Contents of function subnode node:
----------------------
Required properties for pin configuration node:
- st,pins : Child node with list of pins with configuration.
Below is the format of how each pin conf should look like.
<bank offset mux mode rt_type rt_delay rt_clk>
Every PIO is represented with 4-7 parameters depending on retime configuration.
Each parameter is explained as below.
-bank : Should be bank phandle to which this PIO belongs.
-offset : Offset in the PIO bank.
-mux : Should be alternate function number associated this pin.
Use same numbers from datasheet.
-mode :pin configuration is selected from one of the below values.
IN
IN_PU
OUT
BIDIR
BIDIR_PU
-rt_type Retiming Configuration for the pin.
Possible retime configuration are:
------- -------------
value args
------- -------------
NICLK <delay> <clk>
ICLK_IO <delay> <clk>
BYPASS <delay>
DE_IO <delay> <clk>
SE_ICLK_IO <delay> <clk>
SE_NICLK_IO <delay> <clk>
- delay is retime delay in pico seconds as mentioned in data sheet.
- rt_clk :clk to be use for retime.
Possible values are:
CLK_A
CLK_B
CLK_C
CLK_D
Example of mmcclk pin which is a bi-direction pull pu with retime config
as non inverted clock retimed with CLK_B and delay of 0 pico seconds:
pin-controller {
...
mmc0 {
pinctrl_mmc: mmc {
st,pins {
mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
...
};
};
...
};
};
sdhci0:sdhci@fe810000{
...
interrupt-parent = <&PIO3>;
#interrupt-cells = <2>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */
interrupt-names = "card-detect";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc>;
};

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VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller
These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as
either a GPIO in, GPIO out or as an alternate function (I2C, SPI etc).
Required properties:
- compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl",
"wm8750-pinctrl" or "wm,wm8850-pinctrl"
- reg: Should contain the physical address of the module's registers.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters.
bit 0 - active low
Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Each pin configuration node lists the pin(s) to which it applies, and one or
more of the mux functions to select on those pin(s), and pull-up/down
configuration. Each subnode only affects those parameters that are explicitly
listed. In other words, a subnode that lists only a mux function implies no
information about any pull configuration. Similarly, a subnode that lists only
a pull parameter implies no information about the mux function.
Required subnode-properties:
- wm,pins: An array of cells. Each cell contains the ID of a pin.
Optional subnode-properties:
- wm,function: Integer, containing the function to mux to the pin(s):
0: GPIO in
1: GPIO out
2: alternate
- wm,pull: Integer, representing the pull-down/up to apply to the pin(s):
0: none
1: down
2: up
Each of wm,function and wm,pull may contain either a single value which
will be applied to all pins in wm,pins, or one value for each entry in
wm,pins.
Example:
pinctrl: pinctrl {
compatible = "wm,wm8505-pinctrl";
reg = <0xD8110000 0x10000>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};

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ST Microelectronics, SPEAr pinmux controller
Required properties:
- compatible : "st,spear300-pinmux"
: "st,spear310-pinmux"
: "st,spear320-pinmux"
: "st,spear1310-pinmux"
: "st,spear1340-pinmux"
- reg : Address range of the pinctrl registers
- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
- Its values for SPEAr300:
- NAND_MODE : <0>
- NOR_MODE : <1>
- PHOTO_FRAME_MODE : <2>
- LEND_IP_PHONE_MODE : <3>
- HEND_IP_PHONE_MODE : <4>
- LEND_WIFI_PHONE_MODE : <5>
- HEND_WIFI_PHONE_MODE : <6>
- ATA_PABX_WI2S_MODE : <7>
- ATA_PABX_I2S_MODE : <8>
- CAML_LCDW_MODE : <9>
- CAMU_LCD_MODE : <10>
- CAMU_WLCD_MODE : <11>
- CAML_LCD_MODE : <12>
- Its values for SPEAr320:
- AUTO_NET_SMII_MODE : <0>
- AUTO_NET_MII_MODE : <1>
- AUTO_EXP_MODE : <2>
- SMALL_PRINTERS_MODE : <3>
- EXTENDED_MODE : <4>
Please refer to pinctrl-bindings.txt in this directory for details of the common
pinctrl bindings used by client devices.
SPEAr's pinmux nodes act as a container for an arbitrary number of subnodes. Each
of these subnodes represents muxing for a pin, a group, or a list of pins or
groups.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Required subnode-properties:
- st,pins : An array of strings. Each string contains the name of a pin or
group.
- st,function: A string containing the name of the function to mux to the pin or
group. See the SPEAr's TRM to determine which are valid for each pin or group.
Valid values for group and function names can be found from looking at the
group and function arrays in driver files:
drivers/pinctrl/spear/pinctrl-spear3*0.c
Valid values for group names are:
For All SPEAr3xx machines:
"firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp",
"gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp",
"gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp",
"timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp"
For SPEAr300 machines:
"fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp",
"clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp",
"dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp",
"gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
For SPEAr310 machines:
"emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp",
"uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp"
For SPEAr320 machines:
"clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp",
"sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp",
"uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp",
"uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp",
"uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp",
"uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp",
"uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp",
"uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
"uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp",
"uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp",
"uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp",
"can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp",
"pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp",
"pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp",
"pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp",
"pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp",
"pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp",
"pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp",
"ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp",
"ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp",
"ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp",
"rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
"i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
For SPEAr1310 machines:
"i2c0_grp", "ssp0_grp", "ssp0_cs0_grp", "ssp0_cs1_2_grp", "i2s0_grp",
"i2s1_grp", "clcd_grp", "clcd_high_res_grp", "arm_gpio_grp",
"smi_2_chips_grp", "smi_4_chips_grp", "gmii_grp", "rgmii_grp",
"smii_0_1_2_grp", "ras_mii_txclk_grp", "nand_8bit_grp",
"nand_16bit_grp", "nand_4_chips_grp", "keyboard_6x6_grp",
"keyboard_rowcol6_8_grp", "uart0_grp", "uart0_modem_grp",
"gpt0_tmr0_grp", "gpt0_tmr1_grp", "gpt1_tmr0_grp", "gpt1_tmr1_grp",
"sdhci_grp", "cf_grp", "xd_grp", "touch_xy_grp",
"uart1_disable_i2c_grp", "uart1_disable_sd_grp", "uart2_3_grp",
"uart4_grp", "uart5_grp", "rs485_0_1_tdm_0_1_grp", "i2c_1_2_grp",
"i2c3_dis_smi_clcd_grp", "i2c3_dis_sd_i2s0_grp", "i2c_4_5_dis_smi_grp",
"i2c4_dis_sd_grp", "i2c5_dis_sd_grp", "i2c_6_7_dis_kbd_grp",
"i2c6_dis_sd_grp", "i2c7_dis_sd_grp", "can0_dis_nor_grp",
"can0_dis_sd_grp", "can1_dis_sd_grp", "can1_dis_kbd_grp", "pcie0_grp",
"pcie1_grp", "pcie2_grp", "sata0_grp", "sata1_grp", "sata2_grp",
"ssp1_dis_kbd_grp", "ssp1_dis_sd_grp", "gpt64_grp"
For SPEAr1340 machines:
"pads_as_gpio_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "fsmc_pnor_grp",
"keyboard_row_col_grp", "keyboard_col5_grp", "spdif_in_grp",
"spdif_out_grp", "gpt_0_1_grp", "pwm0_grp", "pwm1_grp", "pwm2_grp",
"pwm3_grp", "vip_mux_grp", "vip_mux_cam0_grp", "vip_mux_cam1_grp",
"vip_mux_cam2_grp", "vip_mux_cam3_grp", "cam0_grp", "cam1_grp",
"cam2_grp", "cam3_grp", "smi_grp", "ssp0_grp", "ssp0_cs1_grp",
"ssp0_cs2_grp", "ssp0_cs3_grp", "uart0_grp", "uart0_enh_grp",
"uart1_grp", "i2s_in_grp", "i2s_out_grp", "gmii_grp", "rgmii_grp",
"rmii_grp", "sgmii_grp", "i2c0_grp", "i2c1_grp", "cec0_grp", "cec1_grp",
"sdhci_grp", "cf_grp", "xd_grp", "clcd_grp", "arm_trace_grp",
"miphy_dbg_grp", "pcie_grp", "sata_grp"
Valid values for function names are:
For All SPEAr3xx machines:
"firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
"uart0", "timer_0_1", "timer_2_3"
For SPEAr300 machines:
"fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1"
For SPEAr310 machines:
"emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0",
"rs485_1", "tdm"
For SPEAr320 machines:
"clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem",
"uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
"can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
"mii0_1", "i2c1", "i2c2"
For SPEAr1310 machines:
"i2c0", "ssp0", "i2s0", "i2s1", "clcd", "arm_gpio", "smi", "gmii",
"rgmii", "smii_0_1_2", "ras_mii_txclk", "nand", "keyboard", "uart0",
"gpt0", "gpt1", "sdhci", "cf", "xd", "touchscreen", "uart1", "uart2_3",
"uart4", "uart5", "rs485_0_1_tdm_0_1", "i2c_1_2", "i2c3_i2s1",
"i2c_4_5", "i2c_6_7", "can0", "can1", "pci", "sata", "ssp1", "gpt64"
For SPEAr1340 machines:
"pads_as_gpio", "fsmc", "keyboard", "spdif_in", "spdif_out", "gpt_0_1",
"pwm", "vip", "cam0", "cam1", "cam2", "cam3", "smi", "ssp0", "uart0",
"uart1", "i2s", "gmac", "i2c0", "i2c1", "cec0", "cec1", "sdhci", "cf",
"xd", "clcd", "arm_trace", "miphy_dbg", "pcie", "sata"

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Qualcomm APQ8064 TLMM block
Required properties:
- compatible: "qcom,apq8064-pinctrl"
- reg: Should be the base address and length of the TLMM block.
- interrupts: Should be the parent IRQ of the TLMM block.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two.
The first cell is the gpio pin number and the
second cell is used for optional parameters.
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength,
output-low, output-high.
Non-empty subnodes must specify the 'pins' property.
Valid values for pins are:
gpio0-gpio89
Valid values for function are:
cam_mclk, codec_mic_i2s, codec_spkr_i2s, gpio, gsbi1, gsbi2, gsbi3, gsbi4,
gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,
gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,
gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,
riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, ps_hold
Example:
msmgpio: pinctrl@800000 {
compatible = "qcom,apq8064-pinctrl";
reg = <0x800000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 16 0x4>;
pinctrl-names = "default";
pinctrl-0 = <&gsbi5_uart_default>;
gsbi5_uart_default: gsbi5_uart_default {
mux {
pins = "gpio51", "gpio52";
function = "gsbi5";
};
tx {
pins = "gpio51";
drive-strength = <4>;
bias-disable;
};
rx {
pins = "gpio52";
drive-strength = <2>;
bias-pull-up;
};
};
};

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Qualcomm APQ8084 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
MSM8960 platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,apq8084-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode. Valid pins are:
gpio0-gpio146,
sdc1_clk,
sdc1_cmd,
sdc1_data
sdc2_clk,
sdc2_cmd,
sdc2_data
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3,
blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5,
blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3,
blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8,
blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2,
cam_mclk3, cci_async, cci_async_in0, cci_i2c0, cci_i2c1,
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, gcc_obt, gcc_vtt,i
gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, gp1_clk, gpio,
hdmi_cec, hdmi_ddc, hdmi_dtest, hdmi_hpd, hdmi_rcv, hsic,
ldo_en, ldo_update, mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst,
pci_e1, pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s,
qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n,
sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus,
spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s, tsif1,
tsif2, uim, uim_batt_alarm
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@fd510000 {
compatible = "qcom,apq8084-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 208 0>;
uart2: uart2-default {
mux {
pins = "gpio4", "gpio5";
function = "blsp_uart2";
};
tx {
pins = "gpio4";
drive-strength = <4>;
bias-disable;
};
rx {
pins = "gpio5";
drive-strength = <2>;
bias-pull-up;
};
};
};

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Qualcomm IPQ8064 TLMM block
Required properties:
- compatible: "qcom,ipq8064-pinctrl"
- reg: Should be the base address and length of the TLMM block.
- interrupts: Should be the parent IRQ of the TLMM block.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two.
The first cell is the gpio pin number and the
second cell is used for optional parameters.
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength,
output-low, output-high.
Non-empty subnodes must specify the 'pins' property.
Valid values for qcom,pins are:
gpio0-gpio68
Supports mux, bias, and drive-strength
sdc3_clk, sdc3_cmd, sdc3_data
Supports bias and drive-strength
Valid values for function are:
mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5,
gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1,
spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata,
pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt,
pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren,
pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n,
pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold
Example:
pinmux: pinctrl@800000 {
compatible = "qcom,ipq8064-pinctrl";
reg = <0x800000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 32 0x4>;
pinctrl-names = "default";
pinctrl-0 = <&gsbi5_uart_default>;
gsbi5_uart_default: gsbi5_uart_default {
mux {
pins = "gpio18", "gpio19";
function = "gsbi5";
};
tx {
pins = "gpio18";
drive-strength = <4>;
bias-disable;
};
rx {
pins = "gpio19";
drive-strength = <2>;
bias-pull-up;
};
};
};

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Qualcomm MSM8960 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
MSM8960 platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,msm8960-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode. Valid pins are:
gpio0-gpio151,
sdc1_clk,
sdc1_cmd,
sdc1_data
sdc3_clk,
sdc3_cmd,
sdc3_data
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
audio_pcm, bt, cam_mclk0, cam_mclk1, cam_mclk2,
codec_mic_i2s, codec_spkr_i2s, ext_gps, fm, gps_blanking,
gps_pps_in, gps_pps_out, gp_clk_0a, gp_clk_0b, gp_clk_1a,
gp_clk_1b, gp_clk_2a, gp_clk_2b, gp_mn, gp_pdm_0a,
gp_pdm_0b, gp_pdm_1a, gp_pdm_1b, gp_pdm_2a, gp_pdm_2b, gpio,
gsbi1, gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n, gsbi1_spi_cs2b_n,
gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n,
gsbi2_spi_cs3_n, gsbi3, gsbi4, gsbi4_3d_cam_i2c_l,
gsbi4_3d_cam_i2c_r, gsbi5, gsbi5_3d_cam_i2c_l,
gsbi5_3d_cam_i2c_r, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10,
gsbi11, gsbi11_spi_cs1a_n, gsbi11_spi_cs1b_n,
gsbi11_spi_cs2a_n, gsbi11_spi_cs2b_n, gsbi11_spi_cs3_n,
gsbi12, hdmi_cec, hdmi_ddc_clock, hdmi_ddc_data,
hdmi_hot_plug_detect, hsic, mdp_vsync, mi2s, mic_i2s,
pmb_clk, pmb_ext_ctrl, ps_hold, rpm_wdog, sdc2, sdc4, sdc5,
slimbus1, slimbus2, spkr_i2s, ssbi1, ssbi2, ssbi_ext_gps,
ssbi_pmic2, ssbi_qpa1, ssbi_ts, tsif1, tsif2, ts_eoc,
usb_fs1, usb_fs1_oe, usb_fs1_oe_n, usb_fs2, usb_fs2_oe,
usb_fs2_oe_n, vfe_camif_timer1_a, vfe_camif_timer1_b,
vfe_camif_timer2, vfe_camif_timer3_a, vfe_camif_timer3_b,
vfe_camif_timer4_a, vfe_camif_timer4_b, vfe_camif_timer4_c,
vfe_camif_timer5_a, vfe_camif_timer5_b, vfe_camif_timer6_a,
vfe_camif_timer6_b, vfe_camif_timer6_c, vfe_camif_timer7_a,
vfe_camif_timer7_b, vfe_camif_timer7_c, wlan
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
msmgpio: pinctrl@800000 {
compatible = "qcom,msm8960-pinctrl";
reg = <0x800000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 16 0x4>;
gsbi8_uart: gsbi8-uart {
mux {
pins = "gpio34", "gpio35";
function = "gsbi8";
};
tx {
pins = "gpio34";
drive-strength = <4>;
bias-disable;
};
rx {
pins = "gpio35";
drive-strength = <2>;
bias-pull-up;
};
};
};

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Qualcomm MSM8974 TLMM block
Required properties:
- compatible: "qcom,msm8974-pinctrl"
- reg: Should be the base address and length of the TLMM block.
- interrupts: Should be the parent IRQ of the TLMM block.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two.
The first cell is the gpio pin number and the
second cell is used for optional parameters.
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength.
Non-empty subnodes must specify the 'pins' property.
Note that not all properties are valid for all pins.
Valid values for pins are:
gpio0-gpio145
Supports mux, bias and drive-strength
sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data
Supports bias and drive-strength
Valid values for function are:
cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm,
blsp_uim1, blsp_uart1, blsp_i2c1, blsp_spi1,
blsp_uim2, blsp_uart2, blsp_i2c2, blsp_spi2,
blsp_uim3, blsp_uart3, blsp_i2c3, blsp_spi3,
blsp_uim4, blsp_uart4, blsp_i2c4, blsp_spi4,
blsp_uim5, blsp_uart5, blsp_i2c5, blsp_spi5,
blsp_uim6, blsp_uart6, blsp_i2c6, blsp_spi6,
blsp_uim7, blsp_uart7, blsp_i2c7, blsp_spi7,
blsp_uim8, blsp_uart8, blsp_i2c8, blsp_spi8,
blsp_uim9, blsp_uart9, blsp_i2c9, blsp_spi9,
blsp_uim10, blsp_uart10, blsp_i2c10, blsp_spi10,
blsp_uim11, blsp_uart11, blsp_i2c11, blsp_spi11,
blsp_uim12, blsp_uart12, blsp_i2c12, blsp_spi12,
blsp_spi1_cs1, blsp_spi2_cs2, blsp_spi_cs3, blsp_spi2_cs1, blsp_spi2_cs2
blsp_spi2_cs3, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3,
sdc3, sdc4, gcc_gp_clk1, gcc_gp_clk2, gcc_gp_clk3, cci_timer0, cci_timer1,
cci_timer2, cci_timer3, cci_async_in0, cci_async_in1, cci_async_in2,
cam_mckl0, cam_mclk1, cam_mclk2, cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc,
hdmi_hpd, edp_hpd, gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk,
gp_mn, tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s, spkr_mi2s,
ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, gpio
(Note that this is not yet the complete list of functions)
Example:
msmgpio: pinctrl@fd510000 {
compatible = "qcom,msm8974-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 208 0>;
pinctrl-names = "default";
pinctrl-0 = <&uart2_default>;
uart2_default: uart2_default {
mux {
pins = "gpio4", "gpio5";
function = "blsp_uart2";
};
tx {
pins = "gpio4";
drive-strength = <4>;
bias-disable;
};
rx {
pins = "gpio5";
drive-strength = <2>;
bias-pull-up;
};
};
};

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* Renesas Pin Function Controller (GPIO and Pin Mux/Config)
The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH7372,
SH73A0, R8A73A4 and R8A7740 it also acts as a GPIO controller.
Pin Control
-----------
Required Properties:
- compatible: should be one of the following.
- "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
- "renesas,pfc-r8a7791": for R8A7791 (R-Car M2) compatible pin-controller.
- "renesas,pfc-sh7372": for SH7372 (SH-Mobile AP4) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
- reg: Base address and length of each memory resource used by the pin
controller hardware module.
Optional properties:
- #gpio-range-cells: Mandatory when the PFC doesn't handle GPIO, forbidden
otherwise. Should be 3.
- interrupts-extended: Specify the interrupts associated with external
IRQ pins. This property is mandatory when the PFC handles GPIOs and
forbidden otherwise. When specified, it must contain one interrupt per
external IRQ, sorted by external IRQ number.
The PFC node also acts as a container for pin configuration nodes. Please refer
to pinctrl-bindings.txt in this directory for the definition of the term "pin
configuration node" and for the common pinctrl bindings used by client devices.
Each pin configuration node represents a desired configuration for a pin, a
pin group, or a list of pins or pin groups. The configuration can include the
function to select on those pin(s) and pin configuration parameters (such as
pull-up and pull-down).
Pin configuration nodes contain pin configuration properties, either directly
or grouped in child subnodes. Both pin muxing and configuration parameters can
be grouped in that way and referenced as a single pin configuration node by
client devices.
A configuration node or subnode must reference at least one pin (through the
pins or pin groups properties) and contain at least a function or one
configuration parameter. When the function is present only pin groups can be
used to reference pins.
All pin configuration nodes and subnodes names are ignored. All of those nodes
are parsed through phandles and processed purely based on their content.
Pin Configuration Node Properties:
- renesas,pins : An array of strings, each string containing the name of a pin.
- renesas,groups : An array of strings, each string containing the name of a pin
group.
- renesas,function: A string containing the name of the function to mux to the
pin group(s) specified by the renesas,groups property
Valid values for pin, group and function names can be found in the group and
function arrays of the PFC data file corresponding to the SoC
(drivers/pinctrl/sh-pfc/pfc-*.c)
The pin configuration parameters use the generic pinconf bindings defined in
pinctrl-bindings.txt in this directory. The supported parameters are
bias-disable, bias-pull-up and bias-pull-down.
GPIO
----
On SH7372, SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller
node.
Required Properties:
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be 2. The first cell is the GPIO number and the second
cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
The syntax of the gpio specifier used by client nodes should be the following
with values derived from the SoC user manual.
<[phandle of the gpio controller node]
[pin number within the gpio controller]
[flags]>
On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver.
Please refer to Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
for documentation of the GPIO device tree bindings on those platforms.
Examples
--------
Example 1: SH73A0 (SH-Mobile AG5) pin controller node
pfc: pfc@e6050000 {
compatible = "renesas,pfc-sh73a0";
reg = <0xe6050000 0x8000>,
<0xe605801c 0x1c>;
gpio-controller;
#gpio-cells = <2>;
interrupts-extended =
<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
};
Example 2: A GPIO LED node that references a GPIO
#include <dt-bindings/gpio/gpio.h>
leds {
compatible = "gpio-leds";
led1 {
gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
};
};
Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps
for the MMCIF and SCIFA4 devices
&pfc {
pinctrl-0 = <&scifa4_pins>;
pinctrl-names = "default";
mmcif_pins: mmcif {
mux {
renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
renesas,function = "mmc0";
};
cfg {
renesas,groups = "mmc0_data8_0";
renesas,pins = "PORT279";
bias-pull-up;
};
};
scifa4_pins: scifa4 {
renesas,groups = "scifa4_data", "scifa4_ctrl";
renesas,function = "scifa4";
};
};
Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device
&mmcif {
pinctrl-0 = <&mmcif_pins>;
pinctrl-names = "default";
bus-width = <8>;
vmmc-supply = <&reg_1p8v>;
status = "okay";
};

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* Rockchip Pinmux Controller
The Rockchip Pinmux Controller, enables the IC
to share one PAD to several functional blocks. The sharing is done by
multiplexing the PAD input/output signals. For each PAD there are several
muxing options with option 0 being the use as a GPIO.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The Rockchip pin configuration node is a node of a group of pins which can be
used for a specific device or function. This node represents both mux and
config of the pins in that group. The 'pins' selects the function mode(also
named pin mode) this pin can work on and the 'config' configures various pad
settings such as pull-up, etc.
The pins are grouped into up to 5 individual pin banks which need to be
defined as gpio sub-nodes of the pinmux controller.
Required properties for iomux controller:
- compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
"rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
"rockchip,rk3288-pinctrl"
- rockchip,grf: phandle referencing a syscon providing the
"general register files"
Optional properties for iomux controller:
- rockchip,pmu: phandle referencing a syscon providing the pmu registers
as some SoCs carry parts of the iomux controller registers there.
Required for at least rk3188 and rk3288.
Deprecated properties for iomux controller:
- reg: first element is the general register space of the iomux controller
It should be large enough to contain also separate pull registers.
second element is the separate pull register space of the rk3188.
Use rockchip,grf and rockchip,pmu described above instead.
Required properties for gpio sub nodes:
- compatible: "rockchip,gpio-bank"
- reg: register of the gpio bank (different than the iomux registerset)
- interrupts: base interrupt of the gpio bank in the interrupt controller
- clocks: clock that drives this bank
- gpio-controller: identifies the node as a gpio controller and pin bank.
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See generic
GPIO binding documentation for description of particular cells.
- interrupt-controller: identifies the controller node as interrupt-parent.
- #interrupt-cells: the value of this property should be 2 and the interrupt
cells should use the standard two-cell scheme described in
bindings/interrupt-controller/interrupts.txt
Deprecated properties for gpio sub nodes:
- compatible: "rockchip,rk3188-gpio-bank0"
- reg: second element: separate pull register for rk3188 bank0, use
rockchip,pmu described above instead
Required properties for pin configuration node:
- rockchip,pins: 3 integers array, represents a group of pins mux and config
setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
The MUX 0 means gpio and MUX 1 to N mean the specific device function.
The phandle of a node containing the generic pinconfig options
to use, as described in pinctrl-bindings.txt in this directory.
Examples:
#include <dt-bindings/pinctrl/rockchip.h>
...
pinctrl@20008000 {
compatible = "rockchip,rk3066a-pinctrl";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio0@20034000 {
compatible = "rockchip,gpio-bank";
reg = <0x20034000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 9>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
...
pcfg_pull_default: pcfg_pull_default {
bias-pull-pin-default
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,
<RK_GPIO1 9 1 &pcfg_pull_default>;
};
};
};
uart2: serial@20064000 {
compatible = "snps,dw-apb-uart";
reg = <0x20064000 0x400>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&mux_uart2>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
};
Example for rk3188:
pinctrl@20008000 {
compatible = "rockchip,rk3188-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmu>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio0@0x2000a000 {
compatible = "rockchip,rk3188-gpio-bank0";
reg = <0x2000a000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 9>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio1@0x2003c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003c000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 10>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
...
};

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Samsung GPIO and Pin Mux/Config controller
Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware
controller. It controls the input/output settings on the available pads/pins
and also provides ability to multiplex and configure the output of various
on-chip controllers onto these pads.
Required Properties:
- compatible: should be one of the following.
- "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
- "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
- "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
- "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
- "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
- "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
- "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
- "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
- "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
- Pin banks as child nodes: Pin banks of the controller are represented by child
nodes of the controller node. Bank name is taken from name of the node. Each
bank node must contain following properties:
- gpio-controller: identifies the node as a gpio controller and pin bank.
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
Eg: <&gpx2 6 0>
<[phandle of the gpio controller node]
[pin number within the gpio controller]
[flags]>
Values for gpio specifier:
- Pin number: is a value between 0 to 7.
- Flags: 0 - Active High
1 - Active Low
- Pin mux/config groups as child nodes: The pin mux (selecting pin function
mode) and pin config (pull up/down, driver strength) settings are represented
as child nodes of the pin-controller node. There should be atleast one
child node and there is no limit on the count of these child nodes. It is
also possible for a child node to consist of several further child nodes
to allow grouping multiple pinctrl groups into one. The format of second
level child nodes is exactly the same as for first level ones and is
described below.
The child node should contain a list of pin(s) on which a particular pin
function selection or pin configuration (or both) have to applied. This
list of pins is specified using the property name "samsung,pins". There
should be atleast one pin specfied for this property and there is no upper
limit on the count of pins that can be specified. The pins are specified
using pin names which are derived from the hardware manual of the SoC. As
an example, the pins in GPA0 bank of the pin controller can be represented
as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case.
The format of the pin names should be (as per the hardware manual)
"[pin bank name]-[pin number within the bank]".
The pin function selection that should be applied on the pins listed in the
child node is specified using the "samsung,pin-function" property. The value
of this property that should be applied to each of the pins listed in the
"samsung,pins" property should be picked from the hardware manual of the SoC
for the specified pin group. This property is optional in the child node if
no specific function selection is desired for the pins listed in the child
node. The value of this property is used as-is to program the pin-controller
function selector register of the pin-bank.
The child node can also optionally specify one or more of the pin
configuration that should be applied on all the pins listed in the
"samsung,pins" property of the child node. The following pin configuration
properties are supported.
- samsung,pin-val: Initial value of pin output buffer.
- samsung,pin-pud: Pull up/down configuration.
- samsung,pin-drv: Drive strength configuration.
- samsung,pin-pud-pdn: Pull up/down configuration in power down mode.
- samsung,pin-drv-pdn: Drive strength configuration in power down mode.
The values specified by these config properties should be derived from the
hardware manual and these values are programmed as-is into the pin
pull up/down and driver strength register of the pin-controller.
Note: A child should include atleast a pin function selection property or
pin configuration property (one or more) or both.
The client nodes that require a particular pin function selection and/or
pin configuration should use the bindings listed in the "pinctrl-bindings.txt"
file.
External GPIO and Wakeup Interrupts:
The controller supports two types of external interrupts over gpio. The first
is the external gpio interrupt and second is the external wakeup interrupts.
The difference between the two is that the external wakeup interrupts can be
used as system wakeup events.
A. External GPIO Interrupts: For supporting external gpio interrupts, the
following properties should be specified in the pin-controller device node.
- interrupt-parent: phandle of the interrupt parent to which the external
GPIO interrupts are forwarded to.
- interrupts: interrupt specifier for the controller. The format and value of
the interrupt specifier depends on the interrupt parent for the controller.
In addition, following properties must be present in node of every bank
of pins supporting GPIO interrupts:
- interrupt-controller: identifies the controller node as interrupt-parent.
- #interrupt-cells: the value of this property should be 2.
- First Cell: represents the external gpio interrupt number local to the
external gpio interrupt space of the controller.
- Second Cell: flags to identify the type of the interrupt
- 1 = rising edge triggered
- 2 = falling edge triggered
- 3 = rising and falling edge triggered
- 4 = high level triggered
- 8 = low level triggered
B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
child node representing the external wakeup interrupt controller should be
included in the pin-controller device node. This child node should include
the following properties.
- compatible: identifies the type of the external wakeup interrupt controller
The possible values are:
- samsung,s3c2410-wakeup-eint: represents wakeup interrupt controller
found on Samsung S3C24xx SoCs except S3C2412 and S3C2413,
- samsung,s3c2412-wakeup-eint: represents wakeup interrupt controller
found on Samsung S3C2412 and S3C2413 SoCs,
- samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller
found on Samsung S3C64xx SoCs,
- samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs.
- interrupt-parent: phandle of the interrupt parent to which the external
wakeup interrupts are forwarded to.
- interrupts: interrupt used by multiplexed wakeup interrupts.
In addition, following properties must be present in node of every bank
of pins supporting wake-up interrupts:
- interrupt-controller: identifies the node as interrupt-parent.
- #interrupt-cells: the value of this property should be 2
- First Cell: represents the external wakeup interrupt number local to
the external wakeup interrupt space of the controller.
- Second Cell: flags to identify the type of the interrupt
- 1 = rising edge triggered
- 2 = falling edge triggered
- 3 = rising and falling edge triggered
- 4 = high level triggered
- 8 = low level triggered
Node of every bank of pins supporting direct wake-up interrupts (without
multiplexing) must contain following properties:
- interrupt-parent: phandle of the interrupt parent to which the external
wakeup interrupts are forwarded to.
- interrupts: interrupts of the interrupt parent which are used for external
wakeup interrupts from pins of the bank, must contain interrupts for all
pins of the bank.
Aliases:
All the pin controller nodes should be represented in the aliases node using
the following format 'pinctrl{n}' where n is a unique number for the alias.
Example: A pin-controller node with pin banks:
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
interrupts = <0 47 0>;
/* ... */
/* Pin bank without external interrupts */
gpy0: gpy0 {
gpio-controller;
#gpio-cells = <2>;
};
/* ... */
/* Pin bank with external GPIO or muxed wake-up interrupts */
gpj0: gpj0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/* ... */
/* Pin bank with external direct wake-up interrupts */
gpx0: gpx0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
#interrupt-cells = <2>;
};
/* ... */
};
Example 1: A pin-controller node with pin groups.
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
interrupts = <0 47 0>;
/* ... */
uart0_data: uart0-data {
samsung,pins = "gpa0-0", "gpa0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart0_fctl: uart0-fctl {
samsung,pins = "gpa0-2", "gpa0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart1_data: uart1-data {
samsung,pins = "gpa0-4", "gpa0-5";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart1_fctl: uart1-fctl {
samsung,pins = "gpa0-6", "gpa0-7";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2c2_bus: i2c2-bus {
samsung,pins = "gpa0-6", "gpa0-7";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
sd4_bus8: sd4-bus-width8 {
part-1 {
samsung,pins = "gpk0-3", "gpk0-4",
"gpk0-5", "gpk0-6";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
part-2 {
samsung,pins = "gpk1-3", "gpk1-4",
"gpk1-5", "gpk1-6";
samsung,pin-function = <4>;
samsung,pin-pud = <4>;
samsung,pin-drv = <3>;
};
};
};
Example 2: A pin-controller node with external wakeup interrupt controller node.
pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11000000 0x1000>;
interrupts = <0 46 0>
/* ... */
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
interrupts = <0 32 0>;
};
};
Example 3: A uart client node that supports 'default' and 'flow-control' states.
uart@13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>;
interrupts = <0 52 0>;
pinctrl-names = "default", "flow-control;
pinctrl-0 = <&uart0_data>;
pinctrl-1 = <&uart0_data &uart0_fctl>;
};
Example 4: Set up the default pin state for uart controller.
static int s3c24xx_serial_probe(struct platform_device *pdev) {
struct pinctrl *pinctrl;
/* ... */
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
}
Example 5: A display port client node that supports 'default' pinctrl state
and gpio binding.
display-port-controller {
/* ... */
samsung,hpd-gpio = <&gpx2 6 0>;
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
};
Example 6: Request the gpio for display port controller
static int exynos_dp_probe(struct platform_device *pdev)
{
int hpd_gpio, ret;
struct device *dev = &pdev->dev;
struct device_node *dp_node = dev->of_node;
/* ... */
hpd_gpio = of_get_named_gpio(dp_node, "samsung,hpd-gpio", 0);
/* ... */
ret = devm_gpio_request_one(&pdev->dev, hpd_gpio, GPIOF_IN,
"hpd_gpio");
/* ... */
}

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ST Ericsson abx500 pinmux controller
Required properties:
- compatible: "stericsson,ab8500-gpio", "stericsson,ab8540-gpio",
"stericsson,ab8505-gpio", "stericsson,ab9540-gpio",
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
ST Ericsson's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as input, output, pull up, pull down...
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Required subnode-properties:
- ste,pins : An array of strings. Each string contains the name of a pin or
group.
Optional subnode-properties:
- ste,function: A string containing the name of the function to mux to the
pin or group.
- generic pin configuration option to use. Example :
default_cfg {
ste,pins = "GPIO1";
bias-disable;
};
- ste,config: Handle of pin configuration node containing the generic
pinconfig options to use, as described in pinctrl-bindings.txt in
this directory. Example :
pcfg_bias_disable: pcfg_bias_disable {
bias-disable;
};
default_cfg {
ste,pins = "GPIO1";
ste.config = <&pcfg_bias_disable>;
};
Example board file extract:
&pinctrl_abx500 {
pinctrl-names = "default";
pinctrl-0 = <&sysclkreq2_default_mode>, <&sysclkreq3_default_mode>, <&gpio3_default_mode>, <&sysclkreq6_default_mode>, <&pwmout1_default_mode>, <&pwmout2_default_mode>, <&pwmout3_default_mode>, <&adi1_default_mode>, <&dmic12_default_mode>, <&dmic34_default_mode>, <&dmic56_default_mode>, <&sysclkreq5_default_mode>, <&batremn_default_mode>, <&service_default_mode>, <&pwrctrl0_default_mode>, <&pwrctrl1_default_mode>, <&pwmextvibra1_default_mode>, <&pwmextvibra2_default_mode>, <&gpio51_default_mode>, <&gpio52_default_mode>, <&gpio53_default_mode>, <&gpio54_default_mode>, <&pdmclkdat_default_mode>;
sysclkreq2 {
sysclkreq2_default_mode: sysclkreq2_default {
default_mux {
ste,function = "sysclkreq";
ste,pins = "sysclkreq2_d_1";
};
default_cfg {
ste,pins = "GPIO1";
bias-disable;
};
};
};
sysclkreq3 {
sysclkreq3_default_mode: sysclkreq3_default {
default_mux {
ste,function = "sysclkreq";
ste,pins = "sysclkreq3_d_1";
};
default_cfg {
ste,pins = "GPIO2";
output-low;
};
};
};
gpio3 {
gpio3_default_mode: gpio3_default {
default_mux {
ste,function = "gpio";
ste,pins = "gpio3_a_1";
};
default_cfg {
ste,pins = "GPIO3";
output-low;
};
};
};
sysclkreq6 {
sysclkreq6_default_mode: sysclkreq6_default {
default_mux {
ste,function = "sysclkreq";
ste,pins = "sysclkreq6_d_1";
};
default_cfg {
ste,pins = "GPIO4";
bias-disable;
};
};
};
pwmout1 {
pwmout1_default_mode: pwmout1_default {
default_mux {
ste,function = "pwmout";
ste,pins = "pwmout1_d_1";
};
default_cfg {
ste,pins = "GPIO14";
output-low;
};
};
};
pwmout2 {
pwmout2_default_mode: pwmout2_default {
pwmout2_default_mux {
ste,function = "pwmout";
ste,pins = "pwmout2_d_1";
};
pwmout2_default_cfg {
ste,pins = "GPIO15";
output-low;
};
};
};
pwmout3 {
pwmout3_default_mode: pwmout3_default {
pwmout3_default_mux {
ste,function = "pwmout";
ste,pins = "pwmout3_d_1";
};
pwmout3_default_cfg {
ste,pins = "GPIO16";
output-low;
};
};
};
adi1 {
adi1_default_mode: adi1_default {
adi1_default_mux {
ste,function = "adi1";
ste,pins = "adi1_d_1";
};
adi1_default_cfg1 {
ste,pins = "GPIO17","GPIO19","GPIO20";
bias-disable;
};
adi1_default_cfg2 {
ste,pins = "GPIO18";
output-low;
};
};
};
dmic12 {
dmic12_default_mode: dmic12_default {
dmic12_default_mux {
ste,function = "dmic";
ste,pins = "dmic12_d_1";
};
dmic12_default_cfg1 {
ste,pins = "GPIO27";
output-low;
};
dmic12_default_cfg2 {
ste,pins = "GPIO28";
bias-disable;
};
};
};
dmic34 {
dmic34_default_mode: dmic34_default {
dmic34_default_mux {
ste,function = "dmic";
ste,pins = "dmic34_d_1";
};
dmic34_default_cfg1 {
ste,pins = "GPIO29";
output-low;
};
dmic34_default_cfg2 {
ste,pins = "GPIO30";
bias-disable;{
};
};
};
dmic56 {
dmic56_default_mode: dmic56_default {
dmic56_default_mux {
ste,function = "dmic";
ste,pins = "dmic56_d_1";
};
dmic56_default_cfg1 {
ste,pins = "GPIO31";
output-low;
};
dmic56_default_cfg2 {
ste,pins = "GPIO32";
bias-disable;
};
};
};
sysclkreq5 {
sysclkreq5_default_mode: sysclkreq5_default {
sysclkreq5_default_mux {
ste,function = "sysclkreq";
ste,pins = "sysclkreq5_d_1";
};
sysclkreq5_default_cfg {
ste,pins = "GPIO42";
output-low;
};
};
};
batremn {
batremn_default_mode: batremn_default {
batremn_default_mux {
ste,function = "batremn";
ste,pins = "batremn_d_1";
};
batremn_default_cfg {
ste,pins = "GPIO43";
bias-disable;
};
};
};
service {
service_default_mode: service_default {
service_default_mux {
ste,function = "service";
ste,pins = "service_d_1";
};
service_default_cfg {
ste,pins = "GPIO44";
bias-disable;
};
};
};
pwrctrl0 {
pwrctrl0_default_mux: pwrctrl0_mux {
pwrctrl0_default_mux {
ste,function = "pwrctrl";
ste,pins = "pwrctrl0_d_1";
};
};
pwrctrl0_default_mode: pwrctrl0_default {
pwrctrl0_default_cfg {
ste,pins = "GPIO45";
bias-disable;
};
};
};
pwrctrl1 {
pwrctrl1_default_mux: pwrctrl1_mux {
pwrctrl1_default_mux {
ste,function = "pwrctrl";
ste,pins = "pwrctrl1_d_1";
};
};
pwrctrl1_default_mode: pwrctrl1_default {
pwrctrl1_default_cfg {
ste,pins = "GPIO46";
bias-disable;
};
};
};
pwmextvibra1 {
pwmextvibra1_default_mode: pwmextvibra1_default {
pwmextvibra1_default_mux {
ste,function = "pwmextvibra";
ste,pins = "pwmextvibra1_d_1";
};
pwmextvibra1_default_cfg {
ste,pins = "GPIO47";
bias-disable;
};
};
};
pwmextvibra2 {
pwmextvibra2_default_mode: pwmextvibra2_default {
pwmextvibra2_default_mux {
ste,function = "pwmextvibra";
ste,pins = "pwmextvibra2_d_1";
};
pwmextvibra1_default_cfg {
ste,pins = "GPIO48";
bias-disable;
};
};
};
gpio51 {
gpio51_default_mode: gpio51_default {
gpio51_default_mux {
ste,function = "gpio";
ste,pins = "gpio51_a_1";
};
gpio51_default_cfg {
ste,pins = "GPIO51";
output-low;
};
};
};
gpio52 {
gpio52_default_mode: gpio52_default {
gpio52_default_mux {
ste,function = "gpio";
ste,pins = "gpio52_a_1";
};
gpio52_default_cfg {
ste,pins = "GPIO52";
bias-pull-down;
};
};
};
gpio53 {
gpio53_default_mode: gpio53_default {
gpio53_default_mux {
ste,function = "gpio";
ste,pins = "gpio53_a_1";
};
gpio53_default_cfg {
ste,pins = "GPIO53";
bias-pull-down;
};
};
};
gpio54 {
gpio54_default_mode: gpio54_default {
gpio54_default_mux {
ste,function = "gpio";
ste,pins = "gpio54_a_1";
};
gpio54_default_cfg {
ste,pins = "GPIO54";
output-low;
};
};
};
pdmclkdat {
pdmclkdat_default_mode: pdmclkdat_default {
pdmclkdat_default_mux {
ste,function = "pdm";
ste,pins = "pdmclkdat_d_1";
};
pdmclkdat_default_cfg {
ste,pins = "GPIO55", "GPIO56";
bias-disable;
};
};
};
};

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ST Ericsson Nomadik pinmux controller
Required properties:
- compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
"stericsson,stn8815-pinctrl"
- reg: Should contain the register physical address and length of the PRCMU.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
ST Ericsson's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as input, output, pull up, pull down...
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Required subnode-properties:
- ste,pins : An array of strings. Each string contains the name of a pin or
group.
Optional subnode-properties:
- ste,function: A string containing the name of the function to mux to the
pin or group.
- ste,config: Handle of pin configuration node (e.g. ste,config = <&slpm_in_wkup_pdis>)
- ste,input : <0/1/2>
0: input with no pull
1: input with pull up,
2: input with pull down,
- ste,output: <0/1/2>
0: output low,
1: output high,
2: output (value is not specified).
- ste,sleep: <0/1>
0: sleep mode disable,
1: sleep mode enable.
- ste,sleep-input: <0/1/2/3>
0: sleep input with no pull,
1: sleep input with pull up,
2: sleep input with pull down.
3: sleep input and keep last input configuration (no pull, pull up or pull down).
- ste,sleep-output: <0/1/2>
0: sleep output low,
1: sleep output high,
2: sleep output (value is not specified).
- ste,sleep-gpio: <0/1>
0: disable sleep gpio mode,
1: enable sleep gpio mode.
- ste,sleep-wakeup: <0/1>
0: wake-up detection enabled,
1: wake-up detection disabled.
- ste,sleep-pull-disable: <0/1>
0: GPIO pull-up or pull-down resistor is enabled, when pin is an input,
1: GPIO pull-up and pull-down resistor are disabled.
Example board file extract:
pinctrl@80157000 {
compatible = "stericsson,db8500-pinctrl";
reg = <0x80157000 0x2000>;
pinctrl-names = "default";
slpm_in_wkup_pdis: slpm_in_wkup_pdis {
ste,sleep = <1>;
ste,sleep-input = <3>;
ste,sleep-wakeup = <1>;
ste,sleep-pull-disable = <0>;
};
slpm_out_hi_wkup_pdis: slpm_out_hi_wkup_pdis {
ste,sleep = <1>;
ste,sleep-output = <1>;
ste,sleep-wakeup = <1>;
ste,sleep-pull-disable = <0>;
};
slpm_out_wkup_pdis: slpm_out_wkup_pdis {
ste,sleep = <1>;
ste,sleep-output = <2>;
ste,sleep-wakeup = <1>;
ste,sleep-pull-disable = <0>;
};
uart0 {
uart0_default_mux: uart0_mux {
u0_default_mux {
ste,function = "u0";
ste,pins = "u0_a_1";
};
};
uart0_default_mode: uart0_default {
uart0_default_cfg1 {
ste,pins = "GPIO0", "GPIO2";
ste,input = <1>;
};
uart0_default_cfg2 {
ste,pins = "GPIO1", "GPIO3";
ste,output = <1>;
};
};
uart0_sleep_mode: uart0_sleep {
uart0_sleep_cfg1 {
ste,pins = "GPIO0", "GPIO2";
ste,config = <&slpm_in_wkup_pdis>;
};
uart0_sleep_cfg2 {
ste,pins = "GPIO1";
ste,config = <&slpm_out_hi_wkup_pdis>;
};
uart0_sleep_cfg3 {
ste,pins = "GPIO3";
ste,config = <&slpm_out_wkup_pdis>;
};
};
};
};
uart@80120000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x80120000 0x1000>;
interrupts = <0 11 0x4>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>;
pinctrl-1 = <&uart0_sleep_mode>;
};

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Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt Normal file
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OMAP Pinctrl definitions
Required properties:
- compatible : Should be one of:
"ti,omap2420-padconf" - OMAP2420 compatible pinctrl
"ti,omap2430-padconf" - OMAP2430 compatible pinctrl
"ti,omap3-padconf" - OMAP3 compatible pinctrl
"ti,omap4-padconf" - OMAP4 compatible pinctrl
"ti,omap5-padconf" - OMAP5 compatible pinctrl
"ti,dra7-padconf" - DRA7 compatible pinctrl
"ti,am437-padconf" - AM437x compatible pinctrl
See Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for further details.