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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-07 16:58:04 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
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50820 changed files with 20846062 additions and 0 deletions
54
Documentation/devicetree/bindings/powerpc/4xx/akebono.txt
Normal file
54
Documentation/devicetree/bindings/powerpc/4xx/akebono.txt
Normal file
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@ -0,0 +1,54 @@
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IBM Akebono board device tree
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=============================
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The IBM Akebono board is a development board for the PPC476GTR SoC.
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0) The root node
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Required properties:
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- model : "ibm,akebono".
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- compatible : "ibm,akebono" , "ibm,476gtr".
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1.a) The Secure Digital Host Controller Interface (SDHCI) node
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Represent the Secure Digital Host Controller Interfaces.
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Required properties:
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- compatible : should be "ibm,476gtr-sdhci","generic-sdhci".
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- reg : should contain the SDHCI registers location and length.
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- interrupt-parent : a phandle for the interrupt controller.
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- interrupts : should contain the SDHCI interrupt.
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1.b) The Advanced Host Controller Interface (AHCI) SATA node
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Represents the advanced host controller SATA interface.
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Required properties:
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- compatible : should be "ibm,476gtr-ahci".
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- reg : should contain the AHCI registers location and length.
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- interrupt-parent : a phandle for the interrupt controller.
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- interrupts : should contain the AHCI interrupt.
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1.c) The FPGA node
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The Akebono board stores some board information such as the revision
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number in an FPGA which is represented by this node.
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Required properties:
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- compatible : should be "ibm,akebono-fpga".
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- reg : should contain the FPGA registers location and length.
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1.d) The AVR node
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The Akebono board has an Atmel AVR microprocessor attached to the I2C
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bus as a power controller for the board.
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Required properties:
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- compatible : should be "ibm,akebono-avr".
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- reg : should contain the I2C bus address for the AVR.
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52
Documentation/devicetree/bindings/powerpc/4xx/cpm.txt
Normal file
52
Documentation/devicetree/bindings/powerpc/4xx/cpm.txt
Normal file
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@ -0,0 +1,52 @@
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PPC4xx Clock Power Management (CPM) node
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Required properties:
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- compatible : compatible list, currently only "ibm,cpm"
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- dcr-access-method : "native"
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- dcr-reg : < DCR register range >
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Optional properties:
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- er-offset : All 4xx SoCs with a CPM controller have
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one of two different order for the CPM
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registers. Some have the CPM registers
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in the following order (ER,FR,SR). The
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others have them in the following order
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(SR,ER,FR). For the second case set
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er-offset = <1>.
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- unused-units : specifier consist of one cell. For each
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bit in the cell, the corresponding bit
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in CPM will be set to turn off unused
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devices.
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- idle-doze : specifier consist of one cell. For each
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bit in the cell, the corresponding bit
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in CPM will be set to turn off unused
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devices. This is usually just CPM[CPU].
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- standby : specifier consist of one cell. For each
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bit in the cell, the corresponding bit
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in CPM will be set on standby and
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restored on resume.
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- suspend : specifier consist of one cell. For each
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bit in the cell, the corresponding bit
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in CPM will be set on suspend (mem) and
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restored on resume. Note, for standby
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and suspend the corresponding bits can
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be different or the same. Usually for
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standby only class 2 and 3 units are set.
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However, the interface does not care.
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If they are the same, the additional
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power saving will be seeing if support
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is available to put the DDR in self
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refresh mode and any additional power
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saving techniques for the specific SoC.
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Example:
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CPM0: cpm {
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compatible = "ibm,cpm";
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dcr-access-method = "native";
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dcr-reg = <0x160 0x003>;
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er-offset = <0>;
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unused-units = <0x00000100>;
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idle-doze = <0x02000000>;
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standby = <0xfeff0000>;
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suspend = <0xfeff791d>;
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};
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148
Documentation/devicetree/bindings/powerpc/4xx/emac.txt
Normal file
148
Documentation/devicetree/bindings/powerpc/4xx/emac.txt
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@ -0,0 +1,148 @@
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4xx/Axon EMAC ethernet nodes
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The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
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the Axon bridge. To operate this needs to interact with a this
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special McMAL DMA controller, and sometimes an RGMII or ZMII
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interface. In addition to the nodes and properties described
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below, the node for the OPB bus on which the EMAC sits must have a
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correct clock-frequency property.
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i) The EMAC node itself
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Required properties:
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- device_type : "network"
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- compatible : compatible list, contains 2 entries, first is
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"ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
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405gp, Axon) and second is either "ibm,emac" or
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"ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
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"ibm,emac4"
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- interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
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- interrupt-parent : optional, if needed for interrupt mapping
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- reg : <registers mapping>
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- local-mac-address : 6 bytes, MAC address
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- mal-device : phandle of the associated McMAL node
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- mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
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with this EMAC
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- mal-rx-channel : 1 cell, index of the rx channel on McMAL associated
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with this EMAC
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- cell-index : 1 cell, hardware index of the EMAC cell on a given
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ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
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each Axon chip)
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- max-frame-size : 1 cell, maximum frame size supported in bytes
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- rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
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operations.
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For Axon, 2048
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- tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
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operations.
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For Axon, 2048.
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- fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
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thresholds).
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For Axon, 0x00000010
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- mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds)
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in bytes.
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For Axon, 0x00000100 (I think ...)
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- phy-mode : string, mode of operations of the PHY interface.
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Supported values are: "mii", "rmii", "smii", "rgmii",
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"tbi", "gmii", rtbi", "sgmii".
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For Axon on CAB, it is "rgmii"
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- mdio-device : 1 cell, required iff using shared MDIO registers
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(440EP). phandle of the EMAC to use to drive the
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MDIO lines for the PHY used by this EMAC.
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- zmii-device : 1 cell, required iff connected to a ZMII. phandle of
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the ZMII device node
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- zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII
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channel or 0xffffffff if ZMII is only used for MDIO.
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- rgmii-device : 1 cell, required iff connected to an RGMII. phandle
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of the RGMII device node.
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For Axon: phandle of plb5/plb4/opb/rgmii
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- rgmii-channel : 1 cell, required iff connected to an RGMII. Which
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RGMII channel is used by this EMAC.
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Fox Axon: present, whatever value is appropriate for each
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EMAC, that is the content of the current (bogus) "phy-port"
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property.
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Optional properties:
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- phy-address : 1 cell, optional, MDIO address of the PHY. If absent,
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a search is performed.
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- phy-map : 1 cell, optional, bitmap of addresses to probe the PHY
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for, used if phy-address is absent. bit 0x00000001 is
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MDIO address 0.
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For Axon it can be absent, though my current driver
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doesn't handle phy-address yet so for now, keep
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0x00ffffff in it.
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- rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
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operations (if absent the value is the same as
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rx-fifo-size). For Axon, either absent or 2048.
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- tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
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operations (if absent the value is the same as
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tx-fifo-size). For Axon, either absent or 2048.
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- tah-device : 1 cell, optional. If connected to a TAH engine for
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offload, phandle of the TAH device node.
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- tah-channel : 1 cell, optional. If appropriate, channel used on the
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TAH engine.
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Example:
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EMAC0: ethernet@40000800 {
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device_type = "network";
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compatible = "ibm,emac-440gp", "ibm,emac";
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interrupt-parent = <&UIC1>;
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interrupts = <1c 4 1d 4>;
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reg = <40000800 70>;
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local-mac-address = [00 04 AC E3 1B 1E];
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mal-device = <&MAL0>;
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mal-tx-channel = <0 1>;
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mal-rx-channel = <0>;
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cell-index = <0>;
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max-frame-size = <5dc>;
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rx-fifo-size = <1000>;
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tx-fifo-size = <800>;
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phy-mode = "rmii";
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phy-map = <00000001>;
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zmii-device = <&ZMII0>;
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zmii-channel = <0>;
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};
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ii) McMAL node
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Required properties:
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- device_type : "dma-controller"
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- compatible : compatible list, containing 2 entries, first is
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"ibm,mcmal-CHIP" where CHIP is the host ASIC (like
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emac) and the second is either "ibm,mcmal" or
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"ibm,mcmal2".
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For Axon, "ibm,mcmal-axon","ibm,mcmal2"
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- interrupts : <interrupt mapping for the MAL interrupts sources:
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5 sources: tx_eob, rx_eob, serr, txde, rxde>.
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For Axon: This is _different_ from the current
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firmware. We use the "delayed" interrupts for txeob
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and rxeob. Thus we end up with mapping those 5 MPIC
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interrupts, all level positive sensitive: 10, 11, 32,
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33, 34 (in decimal)
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- dcr-reg : < DCR registers range >
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- dcr-parent : if needed for dcr-reg
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- num-tx-chans : 1 cell, number of Tx channels
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- num-rx-chans : 1 cell, number of Rx channels
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iii) ZMII node
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Required properties:
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- compatible : compatible list, containing 2 entries, first is
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"ibm,zmii-CHIP" where CHIP is the host ASIC (like
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EMAC) and the second is "ibm,zmii".
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For Axon, there is no ZMII node.
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- reg : <registers mapping>
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iv) RGMII node
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Required properties:
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- compatible : compatible list, containing 2 entries, first is
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"ibm,rgmii-CHIP" where CHIP is the host ASIC (like
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EMAC) and the second is "ibm,rgmii".
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For Axon, "ibm,rgmii-axon","ibm,rgmii"
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- reg : <registers mapping>
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- revision : as provided by the RGMII new version register if
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available.
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For Axon: 0x0000012a
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19
Documentation/devicetree/bindings/powerpc/4xx/hsta.txt
Normal file
19
Documentation/devicetree/bindings/powerpc/4xx/hsta.txt
Normal file
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@ -0,0 +1,19 @@
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ppc476gtr High Speed Serial Assist (HSTA) node
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==============================================
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The 476gtr SoC contains a high speed serial assist module attached
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between the plb4 and plb6 system buses to provide high speed data
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transfer between memory and system peripherals as well as support for
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PCI message signalled interrupts.
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Currently only the MSI support is used by Linux using the following
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device tree entries:
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Require properties:
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- compatible : "ibm,476gtr-hsta-msi", "ibm,hsta-msi"
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- reg : register mapping for the HSTA MSI space
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- interrupt-parent : parent controller for mapping interrupts
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- interrupts : ordered interrupt mapping for each MSI in the register
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space. The first interrupt should be associated with a
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register offset of 0x00, the second to 0x10, etc.
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39
Documentation/devicetree/bindings/powerpc/4xx/ndfc.txt
Normal file
39
Documentation/devicetree/bindings/powerpc/4xx/ndfc.txt
Normal file
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@ -0,0 +1,39 @@
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AMCC NDFC (NanD Flash Controller)
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Required properties:
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- compatible : "ibm,ndfc".
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- reg : should specify chip select and size used for the chip (0x2000).
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Optional properties:
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- ccr : NDFC config and control register value (default 0).
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- bank-settings : NDFC bank configuration register value (default 0).
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Notes:
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- partition(s) - follows the OF MTD standard for partitions
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Example:
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ndfc@1,0 {
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compatible = "ibm,ndfc";
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reg = <0x00000001 0x00000000 0x00002000>;
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ccr = <0x00001000>;
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bank-settings = <0x80002222>;
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#address-cells = <1>;
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#size-cells = <1>;
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nand {
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "kernel";
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reg = <0x00000000 0x00200000>;
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};
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partition@200000 {
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label = "root";
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reg = <0x00200000 0x03E00000>;
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};
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};
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};
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@ -0,0 +1,93 @@
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PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
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Device nodes needed for operation of the ppc440spe-adma driver
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are specified hereby. These are I2O/DMA, DMA and XOR nodes
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for DMA engines and Memory Queue Module node. The latter is used
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by ADMA driver for configuration of RAID-6 H/W capabilities of
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the PPC440SPe. In addition to the nodes and properties described
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below, the ranges property of PLB node must specify ranges for
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DMA devices.
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i) The I2O node
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Required properties:
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- compatible : "ibm,i2o-440spe";
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- reg : <registers mapping>
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- dcr-reg : <DCR registers range>
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Example:
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I2O: i2o@400100000 {
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compatible = "ibm,i2o-440spe";
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reg = <0x00000004 0x00100000 0x100>;
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dcr-reg = <0x060 0x020>;
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};
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ii) The DMA node
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Required properties:
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- compatible : "ibm,dma-440spe";
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- cell-index : 1 cell, hardware index of the DMA engine
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(typically 0x0 and 0x1 for DMA0 and DMA1)
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- reg : <registers mapping>
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- dcr-reg : <DCR registers range>
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- interrupts : <interrupt mapping for DMA0/1 interrupts sources:
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2 sources: DMAx CS FIFO Needs Service IRQ (on UIC0)
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and DMA Error IRQ (on UIC1). The latter is common
|
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for both DMA engines>.
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- interrupt-parent : needed for interrupt mapping
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Example:
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DMA0: dma0@400100100 {
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compatible = "ibm,dma-440spe";
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cell-index = <0>;
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reg = <0x00000004 0x00100100 0x100>;
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dcr-reg = <0x060 0x020>;
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interrupt-parent = <&DMA0>;
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interrupts = <0 1>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = <
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0 &UIC0 0x14 4
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1 &UIC1 0x16 4>;
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};
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iii) XOR Accelerator node
|
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|
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Required properties:
|
||||
|
||||
- compatible : "amcc,xor-accelerator";
|
||||
- reg : <registers mapping>
|
||||
- interrupts : <interrupt mapping for XOR interrupt source>
|
||||
- interrupt-parent : for interrupt mapping
|
||||
|
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Example:
|
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|
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xor-accel@400200000 {
|
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compatible = "amcc,xor-accelerator";
|
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reg = <0x00000004 0x00200000 0x400>;
|
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interrupt-parent = <&UIC1>;
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interrupts = <0x1f 4>;
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};
|
||||
|
||||
|
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iv) Memory Queue Module node
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : "ibm,mq-440spe";
|
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- dcr-reg : <DCR registers range>
|
||||
|
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Example:
|
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|
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MQ0: mq {
|
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compatible = "ibm,mq-440spe";
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dcr-reg = <0x040 0x020>;
|
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};
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18
Documentation/devicetree/bindings/powerpc/4xx/reboot.txt
Normal file
18
Documentation/devicetree/bindings/powerpc/4xx/reboot.txt
Normal file
|
|
@ -0,0 +1,18 @@
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Reboot property to control system reboot on PPC4xx systems:
|
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|
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By setting "reset_type" to one of the following values, the default
|
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software reset mechanism may be overridden. Here the possible values of
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"reset_type":
|
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|
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1 - PPC4xx core reset
|
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2 - PPC4xx chip reset
|
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3 - PPC4xx system reset (default)
|
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|
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Example:
|
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|
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cpu@0 {
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device_type = "cpu";
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model = "PowerPC,440SPe";
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...
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reset-type = <2>; /* Use chip-reset */
|
||||
};
|
||||
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