mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-07 08:48:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
78
Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
Normal file
78
Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
QCOM GSBI (General Serial Bus Interface) Driver
|
||||
|
||||
The GSBI controller is modeled as a node with zero or more child nodes, each
|
||||
representing a serial sub-node device that is mux'd as part of the GSBI
|
||||
configuration settings. The mode setting will govern the input/output mode of
|
||||
the 4 GSBI IOs.
|
||||
|
||||
Required properties:
|
||||
- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
|
||||
- reg: Address range for GSBI registers
|
||||
- clocks: required clock
|
||||
- clock-names: must contain "iface" entry
|
||||
- qcom,mode : indicates MUX value for configuration of the serial interface.
|
||||
Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
|
||||
|
||||
Optional properties:
|
||||
- qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
|
||||
dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
|
||||
|
||||
Required properties if child node exists:
|
||||
- #address-cells: Must be 1
|
||||
- #size-cells: Must be 1
|
||||
- ranges: Must be present
|
||||
|
||||
Properties for children:
|
||||
|
||||
A GSBI controller node can contain 0 or more child nodes representing serial
|
||||
devices. These serial devices can be a QCOM UART, I2C controller, spi
|
||||
controller, or some combination of aforementioned devices.
|
||||
|
||||
See the following for child node definitions:
|
||||
Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
|
||||
Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
|
||||
Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
|
||||
|
||||
Example for APQ8064:
|
||||
|
||||
#include <dt-bindings/soc/qcom,gsbi.h>
|
||||
|
||||
gsbi4@16300000 {
|
||||
compatible = "qcom,gsbi-v1.0.0";
|
||||
reg = <0x16300000 0x100>;
|
||||
clocks = <&gcc GSBI4_H_CLK>;
|
||||
clock-names = "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
qcom,crci = <GSBI_CRCI_QUP>;
|
||||
|
||||
/* child nodes go under here */
|
||||
|
||||
i2c_qup4: i2c@16380000 {
|
||||
compatible = "qcom,i2c-qup-v1.1.1";
|
||||
reg = <0x16380000 0x1000>;
|
||||
interrupts = <0 153 0>;
|
||||
|
||||
clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
|
||||
clock-frequency = <200000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
};
|
||||
|
||||
uart4: serial@16340000 {
|
||||
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
||||
reg = <0x16340000 0x1000>,
|
||||
<0x16300000 0x1000>;
|
||||
interrupts = <0 152 0x0>;
|
||||
clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "ok";
|
||||
};
|
||||
};
|
||||
|
||||
113
Documentation/devicetree/bindings/soc/samsung/usi.txt
Normal file
113
Documentation/devicetree/bindings/soc/samsung/usi.txt
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
* EXYNOS - USI(Universal Serial Interface) devicetree making guide
|
||||
|
||||
The USI can operate as UART, HSI2C and SPI.
|
||||
So the configuration for one specific function
|
||||
should be needed with SYSREG(System Registers).
|
||||
|
||||
To configure USI port as one specific function,
|
||||
function string(ex, "spi" or "hsi2c0" or "hsi2c1" or "spi" or "uart" or
|
||||
"hsi2c0_hsi2c1" or "uart_hsi2c1")
|
||||
should be declared in "usi_mode" property in board devicetree file.
|
||||
|
||||
Becuase USI configuration can differ from board schematic.
|
||||
|
||||
* Required SoC Specific Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- samsung,exynos-usi: for exynos7, exynos8 platforms.
|
||||
|
||||
- reg: physical base address of the SYSREG for specific USI port
|
||||
and length of memory mapped region.
|
||||
|
||||
* Required Board Specific Properties:
|
||||
- usi_mode: function string for one specific IP operation.
|
||||
hsi2c0: for HSI2C0
|
||||
hsi2c1: for HSI2C1
|
||||
spi: for SPI
|
||||
uart: for UART
|
||||
hsi2c0_hsi2c1: for HSI2C0 and HSI2C1
|
||||
uart_hsi2c1: for UART(without hardware flow control) and HSI2C1
|
||||
|
||||
In case of HSI2C function of USI,
|
||||
hsi2c0 and hsi2c1 should be declared in according to board schemetic.
|
||||
If shemetic describes USI pin as "XUSI##_SDA0" and XUSI##_SCL0",
|
||||
we need to use "hsi2c0" for usi_mode.
|
||||
If shemetic describes USI pin as "XUSI##_SDA1" and XUSI##_SCL1",
|
||||
we need to use "hsi2c1" for usi_mode.
|
||||
If shemetic describes USI pin as "XUSI##_SDA0" and XUSI##_SCL0",
|
||||
and there is also "XUSI##_SDA1" and XUSI##_SCL1",
|
||||
we need to use "hsi2c0_hsi2c1" for usi_mode.
|
||||
|
||||
* Exsamples:
|
||||
|
||||
- SoC Specific Portion
|
||||
|
||||
/* USI_0 */
|
||||
usi_0: usi@10421000 {
|
||||
compatible = "samsung,exynos-usi";
|
||||
reg = <0x0 0x10421000 0x4>;
|
||||
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
|
||||
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* USI_1 */
|
||||
usi_1: usi@10421004 {
|
||||
compatible = "samsung,exynos-usi";
|
||||
reg = <0x0 0x10421004 0x4>;
|
||||
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
|
||||
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* USI_2 */
|
||||
usi_2: usi@10421008 {
|
||||
compatible = "samsung,exynos-usi";
|
||||
reg = <0x0 0x10421008 0x4>;
|
||||
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
|
||||
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
- Board Specific Portion
|
||||
|
||||
/* USI MODE SETTINGS
|
||||
|
||||
usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
|
||||
or "hsi2c0_hsi2c1" or "uart_hsi2c1"
|
||||
*/
|
||||
|
||||
usi_0: usi@10421000 {
|
||||
usi_mode = "spi";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usi_1: usi@10421004 {
|
||||
usi_mode = "spi";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usi_2: usi@10421008 {
|
||||
usi_mode = "hsi2c0";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
If USI configuration was done successfully, the booting log will be shown as below.
|
||||
|
||||
[ 0.700485] [1: swapper/0: 1] usi 10421000.usi: usi_probe() mode:4
|
||||
[ 0.702369] [1: swapper/0: 1] usi 10421004.usi: usi_probe() mode:4
|
||||
[ 0.704134] [1: swapper/0: 1] usi 10421008.usi: usi_probe() mode:1
|
||||
|
||||
This means the usi_0 was set as "spi" and usi_1 was set as "spi" and
|
||||
usi_2 was set as "hsi2c0".
|
||||
|
||||
The mode values are as below.
|
||||
|
||||
/* USI mode */
|
||||
#define USI_HSI2C0_SINGLE_MODE 0x1
|
||||
#define USI_HSI2C1_SINGLE_MODE 0x2
|
||||
#define USI_HSI2C0_HSI2C1_DUAL_MODE 0x3
|
||||
#define USI_SPI_SINGLE_MODE 0x4
|
||||
#define USI_UART_SINGLE_MODE 0x8
|
||||
#define USI_UART_HSI2C1_DUAL_MODE 0xA
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||||
|
|
@ -0,0 +1,111 @@
|
|||
Keystone Navigator DMA Controller
|
||||
|
||||
This document explains the device tree bindings for the packet dma
|
||||
on keystone devices. The Keystone Navigator DMA driver sets up the dma
|
||||
channels and flows for the QMSS(Queue Manager SubSystem) who triggers
|
||||
the actual data movements across clients using destination queues. Every
|
||||
client modules like NETCP(Network Coprocessor), SRIO(Serial Rapid IO),
|
||||
CRYPTO Engines etc has its own instance of dma hardware. QMSS has also
|
||||
an internal packet DMA module which is used as an infrastructure DMA
|
||||
with zero copy.
|
||||
|
||||
Navigator DMA cloud layout:
|
||||
------------------
|
||||
| Navigator DMAs |
|
||||
------------------
|
||||
|
|
||||
|-> DMA instance #0
|
||||
|
|
||||
|-> DMA instance #1
|
||||
.
|
||||
.
|
||||
|
|
||||
|-> DMA instance #n
|
||||
|
||||
Navigator DMA properties:
|
||||
Required properties:
|
||||
- compatible: Should be "ti,keystone-navigator-dma"
|
||||
- clocks: phandle to dma instances clocks. The clock handles can be as
|
||||
many as the dma instances. The order should be maintained as per
|
||||
the dma instances.
|
||||
- ti,navigator-cloud-address: Should contain base address for the multi-core
|
||||
navigator cloud and number of addresses depends on SOC integration
|
||||
configuration.. Navigator cloud global address needs to be programmed
|
||||
into DMA and the DMA uses it as the physical addresses to reach queue
|
||||
managers. Note that these addresses though points to queue managers,
|
||||
they are relevant only from DMA perspective. The QMSS may not choose to
|
||||
use them since it has a different address space view to reach all
|
||||
its components.
|
||||
|
||||
DMA instance properties:
|
||||
Required properties:
|
||||
- reg: Should contain register location and length of the following dma
|
||||
register regions. Register regions should be specified in the following
|
||||
order.
|
||||
- Global control register region (global).
|
||||
- Tx DMA channel configuration register region (txchan).
|
||||
- Rx DMA channel configuration register region (rxchan).
|
||||
- Tx DMA channel Scheduler configuration register region (txsched).
|
||||
- Rx DMA flow configuration register region (rxflow).
|
||||
|
||||
Optional properties:
|
||||
- reg-names: Names for the register regions.
|
||||
- ti,enable-all: Enable all DMA channels vs clients opening specific channels
|
||||
what they need. This property is useful for the userspace fast path
|
||||
case where the linux drivers enables the channels used by userland
|
||||
stack.
|
||||
- ti,loop-back: To loopback Tx streaming I/F to Rx streaming I/F. Used for
|
||||
infrastructure transfers.
|
||||
- ti,rx-retry-timeout: Number of dma cycles to wait before retry on buffer
|
||||
starvation.
|
||||
|
||||
Example:
|
||||
|
||||
knav_dmas: knav_dmas@0 {
|
||||
compatible = "ti,keystone-navigator-dma";
|
||||
clocks = <&papllclk>, <&clkxge>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,navigator-cloud-address = <0x23a80000 0x23a90000
|
||||
0x23aa0000 0x23ab0000>;
|
||||
|
||||
dma_gbe: dma_gbe@0 {
|
||||
reg = <0x2004000 0x100>,
|
||||
<0x2004400 0x120>,
|
||||
<0x2004800 0x300>,
|
||||
<0x2004c00 0x120>,
|
||||
<0x2005000 0x400>;
|
||||
reg-names = "global", "txchan", "rxchan",
|
||||
"txsched", "rxflow";
|
||||
};
|
||||
|
||||
dma_xgbe: dma_xgbe@0 {
|
||||
reg = <0x2fa1000 0x100>,
|
||||
<0x2fa1400 0x200>,
|
||||
<0x2fa1800 0x200>,
|
||||
<0x2fa1c00 0x200>,
|
||||
<0x2fa2000 0x400>;
|
||||
reg-names = "global", "txchan", "rxchan",
|
||||
"txsched", "rxflow";
|
||||
};
|
||||
};
|
||||
|
||||
Navigator DMA client:
|
||||
Required properties:
|
||||
- ti,navigator-dmas: List of one or more DMA specifiers, each consisting of
|
||||
- A phandle pointing to DMA instance node
|
||||
- A DMA channel number as a phandle arg.
|
||||
- ti,navigator-dma-names: Contains dma channel name for each DMA specifier in
|
||||
the 'ti,navigator-dmas' property.
|
||||
|
||||
Example:
|
||||
|
||||
netcp: netcp@2090000 {
|
||||
..
|
||||
ti,navigator-dmas = <&dma_gbe 22>,
|
||||
<&dma_gbe 23>,
|
||||
<&dma_gbe 8>;
|
||||
ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
|
||||
..
|
||||
};
|
||||
|
|
@ -0,0 +1,232 @@
|
|||
* Texas Instruments Keystone Navigator Queue Management SubSystem driver
|
||||
|
||||
The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
|
||||
the main hardware sub system which forms the backbone of the Keystone
|
||||
multi-core Navigator. QMSS consist of queue managers, packed-data structure
|
||||
processors(PDSP), linking RAM, descriptor pools and infrastructure
|
||||
Packet DMA.
|
||||
The Queue Manager is a hardware module that is responsible for accelerating
|
||||
management of the packet queues. Packets are queued/de-queued by writing or
|
||||
reading descriptor address to a particular memory mapped location. The PDSPs
|
||||
perform QMSS related functions like accumulation, QoS, or event management.
|
||||
Linking RAM registers are used to link the descriptors which are stored in
|
||||
descriptor RAM. Descriptor RAM is configurable as internal or external memory.
|
||||
The QMSS driver manages the PDSP setups, linking RAM regions,
|
||||
queue pool management (allocation, push, pop and notify) and descriptor
|
||||
pool management.
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible : Must be "ti,keystone-navigator-qmss";
|
||||
- clocks : phandle to the reference clock for this device.
|
||||
- queue-range : <start number> total range of queue numbers for the device.
|
||||
- linkram0 : <address size> for internal link ram, where size is the total
|
||||
link ram entries.
|
||||
- linkram1 : <address size> for external link ram, where size is the total
|
||||
external link ram entries. If the address is specified as "0"
|
||||
driver will allocate memory.
|
||||
- qmgrs : child node describing the individual queue managers on the
|
||||
SoC. On keystone 1 devices there should be only one node.
|
||||
On keystone 2 devices there can be more than 1 node.
|
||||
-- managed-queues : the actual queues managed by each queue manager
|
||||
instance, specified as <"base queue #" "# of queues">.
|
||||
-- reg : Address and size of the register set for the device.
|
||||
Register regions should be specified in the following
|
||||
order
|
||||
- Queue Peek region.
|
||||
- Queue status RAM.
|
||||
- Queue configuration region.
|
||||
- Descriptor memory setup region.
|
||||
- Queue Management/Queue Proxy region for queue Push.
|
||||
- Queue Management/Queue Proxy region for queue Pop.
|
||||
- queue-pools : child node classifying the queue ranges into pools.
|
||||
Queue ranges are grouped into 3 type of pools:
|
||||
- qpend : pool of qpend(interruptible) queues
|
||||
- general-purpose : pool of general queues, primarly used
|
||||
as free descriptor queues or the
|
||||
transmit DMA queues.
|
||||
- accumulator : pool of queues on PDSP accumulator channel
|
||||
Each range can have the following properties:
|
||||
-- qrange : number of queues to use per queue range, specified as
|
||||
<"base queue #" "# of queues">.
|
||||
-- interrupts : Optional property to specify the interrupt mapping
|
||||
for interruptible queues. The driver additionaly sets
|
||||
the interrupt affinity hint based on the cpu mask.
|
||||
-- qalloc-by-id : Optional property to specify that the queues in this
|
||||
range can only be allocated by queue id.
|
||||
-- accumulator : Accumulator channel specification. Any of the PDSPs in
|
||||
QMSS can be loaded with the accumulator firmware. The
|
||||
accumulator firmware’s job is to poll a select number of
|
||||
queues looking for descriptors that have been pushed
|
||||
into them. Descriptors are popped from the queue and
|
||||
placed in a buffer provided by the host. When the list
|
||||
becomes full or a programmed time period expires, the
|
||||
accumulator triggers an interrupt to the host to read
|
||||
the buffer for descriptor information. This firmware
|
||||
comes in 16, 32, and 48 channel builds. Each of these
|
||||
channels can be configured to monitor 32 contiguous
|
||||
queues. Accumulator channel property is specified as:
|
||||
<pdsp-id, channel, entries, pacing mode, latency>
|
||||
pdsp-id : QMSS PDSP running accumulator firmware
|
||||
on which the channel has to be
|
||||
configured
|
||||
channel : Accumulator channel number
|
||||
entries : Size of the accumulator descriptor list
|
||||
pacing mode : Interrupt pacing mode
|
||||
0 : None, i.e interrupt on list full only
|
||||
1 : Time delay since last interrupt
|
||||
2 : Time delay since first new packet
|
||||
3 : Time delay since last new packet
|
||||
latency : time to delay the interrupt, specified
|
||||
in microseconds.
|
||||
-- multi-queue : Optional property to specify that the channel has to
|
||||
monitor upto 32 queues starting at the base queue #.
|
||||
- descriptor-regions : child node describing the memory regions for keystone
|
||||
navigator packet DMA descriptors. The memory for
|
||||
descriptors will be allocated by the driver.
|
||||
-- id : region number in QMSS.
|
||||
-- region-spec : specifies the number of descriptors in the
|
||||
region, specified as
|
||||
<"# of descriptors" "descriptor size">.
|
||||
-- link-index : start index, i.e. index of the first
|
||||
descriptor in the region.
|
||||
|
||||
Optional properties:
|
||||
- dma-coherent : Present if DMA operations are coherent.
|
||||
- pdsps : child node describing the PDSP configuration.
|
||||
-- firmware : firmware to be loaded on the PDSP.
|
||||
-- id : the qmss pdsp that will run the firmware.
|
||||
-- reg : Address and size of the register set for the PDSP.
|
||||
Register regions should be specified in the following
|
||||
order
|
||||
- PDSP internal RAM region.
|
||||
- PDSP control/status region registers.
|
||||
- QMSS interrupt distributor registers.
|
||||
- PDSP command interface region.
|
||||
|
||||
Example:
|
||||
|
||||
qmss: qmss@2a40000 {
|
||||
compatible = "ti,keystone-qmss";
|
||||
dma-coherent;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&chipclk13>;
|
||||
ranges;
|
||||
queue-range = <0 0x4000>;
|
||||
linkram0 = <0x100000 0x8000>;
|
||||
linkram1 = <0x0 0x10000>;
|
||||
|
||||
qmgrs {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
qmgr0 {
|
||||
managed-queues = <0 0x2000>;
|
||||
reg = <0x2a40000 0x20000>,
|
||||
<0x2a06000 0x400>,
|
||||
<0x2a02000 0x1000>,
|
||||
<0x2a03000 0x1000>,
|
||||
<0x23a80000 0x20000>,
|
||||
<0x2a80000 0x20000>;
|
||||
};
|
||||
|
||||
qmgr1 {
|
||||
managed-queues = <0x2000 0x2000>;
|
||||
reg = <0x2a60000 0x20000>,
|
||||
<0x2a06400 0x400>,
|
||||
<0x2a04000 0x1000>,
|
||||
<0x2a05000 0x1000>,
|
||||
<0x23aa0000 0x20000>,
|
||||
<0x2aa0000 0x20000>;
|
||||
};
|
||||
};
|
||||
queue-pools {
|
||||
qpend {
|
||||
qpend-0 {
|
||||
qrange = <658 8>;
|
||||
interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
|
||||
0 43 0xf04 0 44 0xf04 0 45 0xf04
|
||||
0 46 0xf04 0 47 0xf04>;
|
||||
};
|
||||
qpend-1 {
|
||||
qrange = <8704 16>;
|
||||
interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
|
||||
0 51 0xf04 0 52 0xf04 0 53 0xf04
|
||||
0 54 0xf04 0 55 0xf04 0 56 0xf04
|
||||
0 57 0xf04 0 58 0xf04 0 59 0xf04
|
||||
0 60 0xf04 0 61 0xf04 0 62 0xf04
|
||||
0 63 0xf04>;
|
||||
qalloc-by-id;
|
||||
};
|
||||
qpend-2 {
|
||||
qrange = <8720 16>;
|
||||
interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
|
||||
0 59 0xf04 0 68 0xf04 0 69 0xf04
|
||||
0 70 0xf04 0 71 0xf04 0 72 0xf04
|
||||
0 73 0xf04 0 74 0xf04 0 75 0xf04
|
||||
0 76 0xf04 0 77 0xf04 0 78 0xf04
|
||||
0 79 0xf04>;
|
||||
};
|
||||
};
|
||||
general-purpose {
|
||||
gp-0 {
|
||||
qrange = <4000 64>;
|
||||
};
|
||||
netcp-tx {
|
||||
qrange = <640 9>;
|
||||
qalloc-by-id;
|
||||
};
|
||||
};
|
||||
accumulator {
|
||||
acc-0 {
|
||||
qrange = <128 32>;
|
||||
accumulator = <0 36 16 2 50>;
|
||||
interrupts = <0 215 0xf01>;
|
||||
multi-queue;
|
||||
qalloc-by-id;
|
||||
};
|
||||
acc-1 {
|
||||
qrange = <160 32>;
|
||||
accumulator = <0 37 16 2 50>;
|
||||
interrupts = <0 216 0xf01>;
|
||||
multi-queue;
|
||||
};
|
||||
acc-2 {
|
||||
qrange = <192 32>;
|
||||
accumulator = <0 38 16 2 50>;
|
||||
interrupts = <0 217 0xf01>;
|
||||
multi-queue;
|
||||
};
|
||||
acc-3 {
|
||||
qrange = <224 32>;
|
||||
accumulator = <0 39 16 2 50>;
|
||||
interrupts = <0 218 0xf01>;
|
||||
multi-queue;
|
||||
};
|
||||
};
|
||||
};
|
||||
descriptor-regions {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
region-12 {
|
||||
id = <12>;
|
||||
region-spec = <8192 128>; /* num_desc desc_size */
|
||||
link-index = <0x4000>;
|
||||
};
|
||||
};
|
||||
pdsps {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
pdsp0@0x2a10000 {
|
||||
firmware = "keystone/qmss_pdsp_acc48_k2_le_1_0_0_8.fw";
|
||||
reg = <0x2a10000 0x1000>,
|
||||
<0x2a0f000 0x100>,
|
||||
<0x2a0c000 0x3c8>,
|
||||
<0x2a20000 0x4000>;
|
||||
id = <0>;
|
||||
};
|
||||
};
|
||||
}; /* qmss */
|
||||
Loading…
Add table
Add a link
Reference in a new issue