AetherDroid/android_kernel_samsung_on5xelte
1
0
Fork 0
mirror of https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git synced 2025-09-06 16:28:04 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Fixed MTP to work with TWRP

Browse source
This commit is contained in:
awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

197
Documentation/devicetree/bindings/usb/am33xx-usb.txt Normal file
View file

@ -0,0 +1,197 @@
AM33xx MUSB
~~~~~~~~~~~~~~~
- compatible: ti,am33xx-usb
- reg: offset and length of the usbss register sets
- ti,hwmods : must be "usb_otg_hs"
The glue layer contains multiple child nodes. It is required the have
at least a control module node, USB node and a PHY node. The second USB
node and its PHY node is optional. The DMA node is also optional.
Reset module
~~~~~~~~~~~~
- compatible: ti,am335x-usb-ctrl-module
- reg: offset and length of the "USB control registers" in the "Control
Module" block. A second offset and length for the USB wake up control
in the same memory block.
- reg-names: "phy_ctrl" for the "USB control registers" and "wakeup" for
the USB wake up control register.
USB PHY
~~~~~~~
compatible: ti,am335x-usb-phy
reg: offset and length of the "USB PHY" register space
ti,ctrl_mod: reference to the "reset module" node
reg-names: phy
The PHY should have a "phy" alias numbered properly in the alias
node.
USB
~~~
- compatible: ti,musb-am33xx
- reg: offset and length of "USB Controller Registers", and offset and
length of "USB Core" register space.
- reg-names: control for the ""USB Controller Registers" and "mc" for
"USB Core" register space
- interrupts: USB interrupt number
- interrupt-names: mc
- dr_mode: Should be one of "host", "peripheral" or "otg".
- mentor,multipoint: Should be "1" indicating the musb controller supports
multipoint. This is a MUSB configuration-specific setting.
- mentor,num-eps: Specifies the number of endpoints. This is also a
MUSB configuration-specific setting. Should be set to "16"
- mentor,ram-bits: Specifies the ram address size. Should be set to "12"
- mentor,power: Should be "500". This signifies the controller can supply up to
500mA when operating in host mode.
- phys: reference to the USB phy
- dmas: specifies the dma channels
- dma-names: specifies the names of the channels. Use "rxN" for receive
and "txN" for transmit endpoints. N specifies the endpoint number.
The controller should have an "usb" alias numbered properly in the alias
node.
DMA
~~~
- compatible: ti,am3359-cppi41
- reg: offset and length of the following register spaces: USBSS, USB
CPPI DMA Controller, USB CPPI DMA Scheduler, USB Queue Manager
- reg-names: glue, controller, scheduler, queuemgr
- #dma-cells: should be set to 2. The first number represents the
endpoint number (0 … 14 for endpoints 1 … 15 on instance 0 and 15 … 29
for endpoints 1 … 15 on instance 1). The second number is 0 for RX and
1 for TX transfers.
- #dma-channels: should be set to 30 representing the 15 endpoints for
each USB instance.
Example:
~~~~~~~~
The following example contains all the nodes as used on am335x-evm:
aliases {
usb0 = &usb0;
usb1 = &usb1;
phy0 = &usb0_phy;
phy1 = &usb1_phy;
};
usb: usb@47400000 {
compatible = "ti,am33xx-usb";
reg = <0x47400000 0x1000>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
ti,hwmods = "usb_otg_hs";
ctrl_mod: control@44e10000 {
compatible = "ti,am335x-usb-ctrl-module";
reg = <0x44e10620 0x10
0x44e10648 0x4>;
reg-names = "phy_ctrl", "wakeup";
};
usb0_phy: usb-phy@47401300 {
compatible = "ti,am335x-usb-phy";
reg = <0x47401300 0x100>;
reg-names = "phy";
ti,ctrl_mod = <&ctrl_mod>;
};
usb0: usb@47401000 {
compatible = "ti,musb-am33xx";
reg = <0x47401400 0x400
0x47401000 0x200>;
reg-names = "mc", "control";
interrupts = <18>;
interrupt-names = "mc";
dr_mode = "otg"
mentor,multipoint = <1>;
mentor,num-eps = <16>;
mentor,ram-bits = <12>;
mentor,power = <500>;
phys = <&usb0_phy>;
dmas = <&cppi41dma 0 0 &cppi41dma 1 0
&cppi41dma 2 0 &cppi41dma 3 0
&cppi41dma 4 0 &cppi41dma 5 0
&cppi41dma 6 0 &cppi41dma 7 0
&cppi41dma 8 0 &cppi41dma 9 0
&cppi41dma 10 0 &cppi41dma 11 0
&cppi41dma 12 0 &cppi41dma 13 0
&cppi41dma 14 0 &cppi41dma 0 1
&cppi41dma 1 1 &cppi41dma 2 1
&cppi41dma 3 1 &cppi41dma 4 1
&cppi41dma 5 1 &cppi41dma 6 1
&cppi41dma 7 1 &cppi41dma 8 1
&cppi41dma 9 1 &cppi41dma 10 1
&cppi41dma 11 1 &cppi41dma 12 1
&cppi41dma 13 1 &cppi41dma 14 1>;
dma-names =
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
"rx14", "rx15",
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
"tx14", "tx15";
};
usb1_phy: usb-phy@47401b00 {
compatible = "ti,am335x-usb-phy";
reg = <0x47401b00 0x100>;
reg-names = "phy";
ti,ctrl_mod = <&ctrl_mod>;
};
usb1: usb@47401800 {
compatible = "ti,musb-am33xx";
reg = <0x47401c00 0x400
0x47401800 0x200>;
reg-names = "mc", "control";
interrupts = <19>;
interrupt-names = "mc";
dr_mode = "host"
mentor,multipoint = <1>;
mentor,num-eps = <16>;
mentor,ram-bits = <12>;
mentor,power = <500>;
phys = <&usb1_phy>;
dmas = <&cppi41dma 15 0 &cppi41dma 16 0
&cppi41dma 17 0 &cppi41dma 18 0
&cppi41dma 19 0 &cppi41dma 20 0
&cppi41dma 21 0 &cppi41dma 22 0
&cppi41dma 23 0 &cppi41dma 24 0
&cppi41dma 25 0 &cppi41dma 26 0
&cppi41dma 27 0 &cppi41dma 28 0
&cppi41dma 29 0 &cppi41dma 15 1
&cppi41dma 16 1 &cppi41dma 17 1
&cppi41dma 18 1 &cppi41dma 19 1
&cppi41dma 20 1 &cppi41dma 21 1
&cppi41dma 22 1 &cppi41dma 23 1
&cppi41dma 24 1 &cppi41dma 25 1
&cppi41dma 26 1 &cppi41dma 27 1
&cppi41dma 28 1 &cppi41dma 29 1>;
dma-names =
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
"rx14", "rx15",
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
"tx14", "tx15";
};
cppi41dma: dma-controller@07402000 {
compatible = "ti,am3359-cppi41";
reg = <0x47400000 0x1000
0x47402000 0x1000
0x47403000 0x1000
0x47404000 0x4000>;
reg-names = "glue", "controller", "scheduler", "queuemgr";
interrupts = <17>;
interrupt-names = "glue";
#dma-cells = <2>;
#dma-channels = <30>;
#dma-requests = <256>;
};
};

131
Documentation/devicetree/bindings/usb/atmel-usb.txt Normal file
View file

@ -0,0 +1,131 @@
Atmel SOC USB controllers
OHCI
Required properties:
- compatible: Should be "atmel,at91rm9200-ohci" for USB controllers
used in host mode.
- num-ports: Number of ports.
- atmel,vbus-gpio: If present, specifies a gpio that needs to be
activated for the bus to be powered.
- atmel,oc-gpio: If present, specifies a gpio that needs to be
activated for the overcurrent detection.
usb0: ohci@00500000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 4>;
num-ports = <2>;
};
EHCI
Required properties:
- compatible: Should be "atmel,at91sam9g45-ehci" for USB controllers
used in host mode.
usb1: ehci@00800000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00800000 0x100000>;
interrupts = <22 4>;
};
AT91 USB device controller
Required properties:
- compatible: Should be "atmel,at91rm9200-udc"
- reg: Address and length of the register set for the device
- interrupts: Should contain macb interrupt
Optional properties:
- atmel,vbus-gpio: If present, specifies a gpio that needs to be
activated for the bus to be powered.
usb1: gadget@fffa4000 {
compatible = "atmel,at91rm9200-udc";
reg = <0xfffa4000 0x4000>;
interrupts = <10 4>;
atmel,vbus-gpio = <&pioC 5 0>;
};
Atmel High-Speed USB device controller
Required properties:
- compatible: Should be "atmel,at91sam9rl-udc"
- reg: Address and length of the register set for the device
- interrupts: Should contain usba interrupt
- ep childnode: To specify the number of endpoints and their properties.
Optional properties:
- atmel,vbus-gpio: If present, specifies a gpio that allows to detect whether
vbus is present (USB is connected).
Required child node properties:
- name: Name of the endpoint.
- reg: Num of the endpoint.
- atmel,fifo-size: Size of the fifo.
- atmel,nb-banks: Number of banks.
- atmel,can-dma: Boolean to specify if the endpoint support DMA.
- atmel,can-isoc: Boolean to specify if the endpoint support ISOC.
usb2: gadget@fff78000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "atmel,at91sam9rl-udc";
reg = <0x00600000 0x80000
0xfff78000 0x400>;
interrupts = <27 4 0>;
atmel,vbus-gpio = <&pioB 19 0>;
ep0 {
reg = <0>;
atmel,fifo-size = <64>;
atmel,nb-banks = <1>;
};
ep1 {
reg = <1>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-dma;
atmel,can-isoc;
};
ep2 {
reg = <2>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-dma;
atmel,can-isoc;
};
ep3 {
reg = <3>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
ep4 {
reg = <4>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
ep5 {
reg = <5>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
atmel,can-isoc;
};
ep6 {
reg = <6>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
atmel,can-isoc;
};
};

35
Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt Normal file
View file

@ -0,0 +1,35 @@
* Freescale i.MX ci13xxx usb controllers
Required properties:
- compatible: Should be "fsl,imx27-usb"
- reg: Should contain registers location and length
- interrupts: Should contain controller interrupt
- fsl,usbphy: phandle of usb phy that connects to the port
Recommended properies:
- phy_type: the type of the phy connected to the core. Should be one
of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this
property the PORTSC register won't be touched
- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
Optional properties:
- fsl,usbmisc: phandler of non-core register device, with one argument
that indicate usb controller index
- vbus-supply: regulator for vbus
- disable-over-current: disable over current detect
- external-vbus-divider: enables off-chip resistor divider for Vbus
- maximum-speed: limit the maximum connection speed to "full-speed".
- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
Examples:
usb@02184000 { /* USB OTG */
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184000 0x200>;
interrupts = <0 43 0x04>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc 0>;
disable-over-current;
external-vbus-divider;
maximum-speed = "full-speed";
tpl-support;
};

17
Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt Normal file
View file

@ -0,0 +1,17 @@
Qualcomm CI13xxx (Chipidea) USB controllers
Required properties:
- compatible: should contain "qcom,ci-hdrc"
- reg: offset and length of the register set in the memory map
- interrupts: interrupt-specifier for the controller interrupt.
- usb-phy: phandle for the PHY device
- dr_mode: Should be "peripheral"
Examples:
gadget@f9a55000 {
compatible = "qcom,ci-hdrc";
reg = <0xf9a55000 0x400>;
dr_mode = "peripheral";
interrupts = <0 134 0>;
usb-phy = <&usbphy0>;
};

17
Documentation/devicetree/bindings/usb/ci-hdrc-zevio.txt Normal file
View file

@ -0,0 +1,17 @@
* LSI Zevio USB OTG Controller
Required properties:
- compatible: Should be "lsi,zevio-usb"
- reg: Should contain registers location and length
- interrupts: Should contain controller interrupt
Optional properties:
- vbus-supply: regulator for vbus
Examples:
usb0: usb@b0000000 {
reg = <0xb0000000 0x1000>;
compatible = "lsi,zevio-usb";
interrupts = <8>;
vbus-supply = <&vbus_reg>;
};

34
Documentation/devicetree/bindings/usb/dwc2.txt Normal file
View file

@ -0,0 +1,34 @@
Platform DesignWare HS OTG USB 2.0 controller
-----------------------------------------------------
Required properties:
- compatible : One of:
- brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
- rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
- "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
- "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
- snps,dwc2: A generic DWC2 USB controller with default parameters.
- reg : Should contain 1 register range (address and length)
- interrupts : Should contain 1 interrupt
- clocks: clock provider specifier
- clock-names: shall be "otg"
Refer to clk/clock-bindings.txt for generic clock consumer properties
Optional properties:
- phys: phy provider specifier
- phy-names: shall be "usb2-phy"
Refer to phy/phy-bindings.txt for generic phy consumer properties
- dr_mode: shall be one of "host", "peripheral" and "otg"
Refer to usb/generic.txt
Example:
usb@101c0000 {
compatible = "ralink,rt3050-usb, snps,dwc2";
reg = <0x101c0000 40000>;
interrupts = <18>;
clocks = <&usb_otg_ahb_clk>;
clock-names = "otg";
phys = <&usbphy>;
phy-names = "usb2-phy";
};

68
Documentation/devicetree/bindings/usb/dwc3-st.txt Normal file
View file

@ -0,0 +1,68 @@
ST DWC3 glue logic
This file documents the parameters for the dwc3-st driver.
This driver controls the glue logic used to configure the dwc3 core on
STiH407 based platforms.
Required properties:
- compatible : must be "st,stih407-dwc3"
- reg : glue logic base address and USB syscfg ctrl register offset
- reg-names : should be "reg-glue" and "syscfg-reg"
- st,syscon : should be phandle to system configuration node which
encompasses the glue registers
- resets : list of phandle and reset specifier pairs. There should be two entries, one
for the powerdown and softreset lines of the usb3 IP
- reset-names : list of reset signal names. Names should be "powerdown" and "softreset"
See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
See: Documentation/devicetree/bindings/reset/reset.txt
- #address-cells, #size-cells : should be '1' if the device has sub-nodes
with 'reg' property
- pinctl-names : A pinctrl state named "default" must be defined
See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
- pinctrl-0 : Pin control group
See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
- ranges : allows valid 1:1 translation between child's address space and
parent's address space
Sub-nodes:
The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
example below. The DT binding details of dwc3 can be found in:
Documentation/devicetree/bindings/usb/dwc3.txt
NB: The dr_mode property described in [1] is NOT optional for this driver, as the default value
is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
or "device".
[1] Documentation/devicetree/bindings/usb/generic.txt
Example:
st_dwc3: dwc3@8f94000 {
status = "disabled";
compatible = "st,stih407-dwc3";
reg = <0x08f94000 0x1000>, <0x110 0x4>;
reg-names = "reg-glue", "syscfg-reg";
st,syscfg = <&syscfg_core>;
resets = <&powerdown STIH407_USB3_POWERDOWN>,
<&softreset STIH407_MIPHY2_SOFTRESET>;
reset-names = "powerdown",
"softreset";
#address-cells = <1>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3>;
ranges;
dwc3: dwc3@9900000 {
compatible = "snps,dwc3";
reg = <0x09900000 0x100000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
dr_mode = "host";
phys-names = "usb2-phy", "usb3-phy";
phys = <&usb2_picophy2>, <&phy_port2 MIPHY_TYPE_USB>;
};
};

26
Documentation/devicetree/bindings/usb/dwc3.txt Normal file
View file

@ -0,0 +1,26 @@
synopsys DWC3 CORE
DWC3- USB3 CONTROLLER
Required properties:
- compatible: must be "snps,dwc3"
- reg : Address and length of the register set for the device
- interrupts: Interrupts used by the dwc3 controller.
Optional properties:
- usb-phy : array of phandle for the PHY device. The first element
in the array is expected to be a handle to the USB2/HS PHY and
the second element is expected to be a handle to the USB3/SS PHY
- phys: from the *Generic PHY* bindings
- phy-names: from the *Generic PHY* bindings
- tx-fifo-resize: determines if the FIFO *has* to be reallocated.
This is usually a subnode to DWC3 glue to which it is connected.
dwc3@4a030000 {
compatible = "snps,dwc3";
reg = <0x4a030000 0xcfff>;
interrupts = <0 92 4>
usb-phy = <&usb2_phy>, <&usb3,phy>;
tx-fifo-resize;
};

32
Documentation/devicetree/bindings/usb/ehci-omap.txt Normal file
View file

@ -0,0 +1,32 @@
OMAP HS USB EHCI controller
This device is usually the child of the omap-usb-host
Documentation/devicetree/bindings/mfd/omap-usb-host.txt
Required properties:
- compatible: should be "ti,ehci-omap"
- reg: should contain one register range i.e. start and length
- interrupts: description of the interrupt line
Optional properties:
- phys: list of phandles to PHY nodes.
This property is required if at least one of the ports are in
PHY mode i.e. OMAP_EHCI_PORT_MODE_PHY
To specify the port mode, see
Documentation/devicetree/bindings/mfd/omap-usb-host.txt
Example for OMAP4:
usbhsehci: ehci@4a064c00 {
compatible = "ti,ehci-omap";
reg = <0x4a064c00 0x400>;
interrupts = <0 77 0x4>;
};
&usbhsehci {
phys = <&hsusb1_phy 0 &hsusb3_phy>;
};

20
Documentation/devicetree/bindings/usb/ehci-orion.txt Normal file
View file

@ -0,0 +1,20 @@
* EHCI controller, Orion Marvell variants
Required properties:
- compatible: must be "marvell,orion-ehci"
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: The EHCI interrupt
Optional properties:
- clocks: reference to the clock
- phys: reference to the USB PHY
- phy-names: name of the USB PHY, should be "usb"
Example:
ehci@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x1000>;
interrupts = <19>;
};

39
Documentation/devicetree/bindings/usb/ehci-st.txt Normal file
View file

@ -0,0 +1,39 @@
ST USB EHCI controller
Required properties:
- compatible : must be "st,st-ehci-300x"
- reg : physical base addresses of the controller and length of memory mapped
region
- interrupts : one EHCI interrupt should be described here
- pinctrl-names : a pinctrl state named "default" must be defined
- pinctrl-0 : phandle referencing pin configuration of the USB controller
See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
- clocks : phandle list of usb clocks
- clock-names : should be "ic" for interconnect clock and "clk48"
See: Documentation/devicetree/bindings/clock/clock-bindings.txt
- phys : phandle for the PHY device
- phy-names : should be "usb"
- resets : phandle + reset specifier pairs to the powerdown and softreset lines
of the USB IP
- reset-names : should be "power" and "softreset"
See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
See: Documentation/devicetree/bindings/reset/reset.txt
Example:
ehci1: usb@0xfe203e00 {
compatible = "st,st-ehci-300x";
reg = <0xfe203e00 0x100>;
interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&clk_s_a1_ls 0>;
phys = <&usb2_phy>;
phy-names = "usb";
status = "okay";
resets = <&powerdown STIH416_USB1_POWERDOWN>,
<&softreset STIH416_USB1_SOFTRESET>;
reset-names = "power", "softreset";
};

115
Documentation/devicetree/bindings/usb/exynos-usb.txt Normal file
View file

@ -0,0 +1,115 @@
Samsung Exynos SoC USB controller
The USB devices interface with USB controllers on Exynos SOCs.
The device node has following properties.
EHCI
Required properties:
- compatible: should be "samsung,exynos4210-ehci" for USB 2.0
EHCI controller in host mode.
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
- clocks: from common clock binding: handle to usb clock.
- clock-names: from common clock binding: Shall be "usbhost".
- port: if in the SoC there are EHCI phys, they should be listed here.
One phy per port. Each port should have following entries:
- reg: port number on EHCI controller, e.g
On Exynos5250, port 0 is USB2.0 otg phy
port 1 is HSIC phy0
port 2 is HSIC phy1
- phys: from the *Generic PHY* bindings; specifying phy used by port.
Optional properties:
- samsung,vbus-gpio: if present, specifies the GPIO that
needs to be pulled up for the bus to be powered.
Example:
usb@12110000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
interrupts = <0 71 0>;
samsung,vbus-gpio = <&gpx2 6 1 3 3>;
clocks = <&clock 285>;
clock-names = "usbhost";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&usb2phy 1>;
status = "disabled";
};
};
OHCI
Required properties:
- compatible: should be "samsung,exynos4210-ohci" for USB 2.0
OHCI companion controller in host mode.
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
- clocks: from common clock binding: handle to usb clock.
- clock-names: from common clock binding: Shall be "usbhost".
- port: if in the SoC there are OHCI phys, they should be listed here.
One phy per port. Each port should have following entries:
- reg: port number on OHCI controller, e.g
On Exynos5250, port 0 is USB2.0 otg phy
port 1 is HSIC phy0
port 2 is HSIC phy1
- phys: from the *Generic PHY* bindings, specifying phy used by port.
Example:
usb@12120000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>;
interrupts = <0 71 0>;
clocks = <&clock 285>;
clock-names = "usbhost";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&usb2phy 1>;
status = "disabled";
};
};
DWC3
Required properties:
- compatible: should be "samsung,exynos5250-dwusb3" for USB 3.0 DWC3
controller.
- #address-cells, #size-cells : should be '1' if the device has sub-nodes
with 'reg' property.
- ranges: allows valid 1:1 translation between child's address space and
parent's address space
- clocks: Clock IDs array as required by the controller.
- clock-names: names of clocks correseponding to IDs in the clock property
Sub-nodes:
The dwc3 core should be added as subnode to Exynos dwc3 glue.
- dwc3 :
The binding details of dwc3 can be found in:
Documentation/devicetree/bindings/usb/dwc3.txt
Example:
usb@12000000 {
compatible = "samsung,exynos5250-dwusb3";
clocks = <&clock 286>;
clock-names = "usbdrd30";
#address-cells = <1>;
#size-cells = <1>;
ranges;
dwc3 {
compatible = "synopsys,dwc3";
reg = <0x12000000 0x10000>;
interrupts = <0 72 0>;
usb-phy = <&usb2_phy &usb3_phy>;
};
};

83
Documentation/devicetree/bindings/usb/fsl-usb.txt Normal file
View file

@ -0,0 +1,83 @@
Freescale SOC USB controllers
The device node for a USB controller that is part of a Freescale
SOC is as described in the document "Open Firmware Recommended
Practice : Universal Serial Bus" with the following modifications
and additions :
Required properties :
- compatible : Should be "fsl-usb2-mph" for multi port host USB
controllers, or "fsl-usb2-dr" for dual role USB controllers
or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121.
Wherever applicable, the IP version of the USB controller should
also be mentioned (for eg. fsl-usb2-dr-v2.2 for bsc9132).
- phy_type : For multi port host USB controllers, should be one of
"ulpi", or "serial". For dual role USB controllers, should be
one of "ulpi", "utmi", "utmi_wide", or "serial".
- reg : Offset and length of the register set for the device
- port0 : boolean; if defined, indicates port0 is connected for
fsl-usb2-mph compatible controllers. Either this property or
"port1" (or both) must be defined for "fsl-usb2-mph" compatible
controllers.
- port1 : boolean; if defined, indicates port1 is connected for
fsl-usb2-mph compatible controllers. Either this property or
"port0" (or both) must be defined for "fsl-usb2-mph" compatible
controllers.
- dr_mode : indicates the working mode for "fsl-usb2-dr" compatible
controllers. Can be "host", "peripheral", or "otg". Default to
"host" if not defined for backward compatibility.
Recommended properties :
- interrupts : <a b> where a is the interrupt number and b is a
field that represents an encoding of the sense and level
information for the interrupt. This should be encoded based on
the information in section 2) depending on the type of interrupt
controller you have.
- interrupt-parent : the phandle for the interrupt controller that
services interrupts for this device.
Optional properties :
- fsl,invert-drvvbus : boolean; for MPC5121 USB0 only. Indicates the
port power polarity of internal PHY signal DRVVBUS is inverted.
- fsl,invert-pwr-fault : boolean; for MPC5121 USB0 only. Indicates
the PWR_FAULT signal polarity is inverted.
Example multi port host USB controller device node :
usb@22000 {
compatible = "fsl-usb2-mph";
reg = <22000 1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <700>;
interrupts = <27 1>;
phy_type = "ulpi";
port0;
port1;
};
Example dual role USB controller device node :
usb@23000 {
compatible = "fsl-usb2-dr";
reg = <23000 1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <700>;
interrupts = <26 1>;
dr_mode = "otg";
phy = "ulpi";
};
Example dual role USB controller device node for MPC5121ADS:
usb@4000 {
compatible = "fsl,mpc5121-usb2-dr";
reg = <0x4000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = < &ipic >;
interrupts = <44 0x8>;
dr_mode = "otg";
phy_type = "utmi_wide";
fsl,invert-drvvbus;
fsl,invert-pwr-fault;
};

24
Documentation/devicetree/bindings/usb/generic.txt Normal file
View file

@ -0,0 +1,24 @@
Generic USB Properties
Optional properties:
- maximum-speed: tells USB controllers we want to work up to a certain
speed. Valid arguments are "super-speed", "high-speed",
"full-speed" and "low-speed". In case this isn't passed
via DT, USB controllers should default to their maximum
HW capability.
- dr_mode: tells Dual-Role USB controllers that we want to work on a
particular mode. Valid arguments are "host",
"peripheral" and "otg". In case this attribute isn't
passed via DT, USB DRD controllers should default to
OTG.
This is an attribute to a USB controller such as:
dwc3@4a030000 {
compatible = "synopsys,dwc3";
reg = <0x4a030000 0xcfff>;
interrupts = <0 92 4>
usb-phy = <&usb2_phy>, <&usb3,phy>;
maximum-speed = "super-speed";
dr_mode = "otg";
};

34
Documentation/devicetree/bindings/usb/gr-udc.txt Normal file
View file

@ -0,0 +1,34 @@
USB Peripheral Controller driver for Aeroflex Gaisler GRUSBDC.
The GRUSBDC USB Device Controller core is available in the GRLIB VHDL
IP core library.
Note: In the ordinary environment for the core, a Leon SPARC system,
these properties are built from information in the AMBA plug&play.
Required properties:
- name : Should be "GAISLER_USBDC" or "01_021"
- reg : Address and length of the register set for the device
- interrupts : Interrupt numbers for this device. Either one interrupt number
for all interrupts, or one for status related interrupts, one for IN
endpoint related interrupts and one for OUT endpoint related interrupts.
Optional properties:
- epobufsizes : Array of buffer sizes for OUT endpoints when they differ
from the default size of 1024. The array is indexed by the OUT endpoint
number. If the property is present it typically contains one entry for
each OUT endpoint of the core. Fewer entries overrides the default sizes
only for as many endpoints as the array contains.
- epibufsizes : Array of buffer sizes for IN endpoints when they differ
from the default size of 1024. The array is indexed by the IN endpoint
number. If the property is present it typically contains one entry for
each IN endpoint of the core. Fewer entries overrides the default sizes
only for as many endpoints as the array contains.
For further information look in the documentation for the GLIB IP core library:
http://www.gaisler.com/products/grlib/grip.pdf

25
Documentation/devicetree/bindings/usb/isp1301.txt Normal file
View file

@ -0,0 +1,25 @@
* NXP ISP1301 USB transceiver
Required properties:
- compatible: must be "nxp,isp1301"
- reg: I2C address of the ISP1301 device
Optional properties of devices using ISP1301:
- transceiver: phandle of isp1301 - this helps the ISP1301 driver to find the
ISP1301 instance associated with the respective USB driver
Example:
isp1301: usb-transceiver@2c {
compatible = "nxp,isp1301";
reg = <0x2c>;
};
usbd@31020000 {
compatible = "nxp,lpc3220-udc";
reg = <0x31020000 0x300>;
interrupt-parent = <&mic>;
interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
transceiver = <&isp1301>;
status = "okay";
};

20
Documentation/devicetree/bindings/usb/keystone-phy.txt Normal file
View file

@ -0,0 +1,20 @@
TI Keystone USB PHY
Required properties:
- compatible: should be "ti,keystone-usbphy".
- #address-cells, #size-cells : should be '1' if the device has sub-nodes
with 'reg' property.
- reg : Address and length of the usb phy control register set.
The main purpose of this PHY driver is to enable the USB PHY reference clock
gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
an NOP PHY driver. Hence this node is referenced as both the usb2 and usb3
phy node in the USB Glue layer driver node.
usb_phy: usb_phy@2620738 {
compatible = "ti,keystone-usbphy";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2620738 32>;
status = "disabled";
};

42
Documentation/devicetree/bindings/usb/keystone-usb.txt Normal file
View file

@ -0,0 +1,42 @@
TI Keystone Soc USB Controller
DWC3 GLUE
Required properties:
- compatible: should be "ti,keystone-dwc3".
- #address-cells, #size-cells : should be '1' if the device has sub-nodes
with 'reg' property.
- reg : Address and length of the register set for the USB subsystem on
the SOC.
- interrupts : The irq number of this device that is used to interrupt the
MPU.
- ranges: allows valid 1:1 translation between child's address space and
parent's address space.
- clocks: Clock IDs array as required by the controller.
- clock-names: names of clocks correseponding to IDs in the clock property.
Sub-nodes:
The dwc3 core should be added as subnode to Keystone DWC3 glue.
- dwc3 :
The binding details of dwc3 can be found in:
Documentation/devicetree/bindings/usb/dwc3.txt
Example:
usb: usb@2680000 {
compatible = "ti,keystone-dwc3";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2680000 0x10000>;
clocks = <&clkusb>;
clock-names = "usb";
interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
ranges;
status = "disabled";
dwc3@2690000 {
compatible = "synopsys,dwc3";
reg = <0x2690000 0x70000>;
interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
usb-phy = <&usb_phy>, <&usb_phy>;
};
};

28
Documentation/devicetree/bindings/usb/lpc32xx-udc.txt Normal file
View file

@ -0,0 +1,28 @@
* NXP LPC32xx SoC USB Device Controller (UDC)
Required properties:
- compatible: Must be "nxp,lpc3220-udc"
- reg: Physical base address of the controller and length of memory mapped
region.
- interrupts: The USB interrupts:
* USB Device Low Priority Interrupt
* USB Device High Priority Interrupt
* USB Device DMA Interrupt
* External USB Transceiver Interrupt (OTG ATX)
- transceiver: phandle of the associated ISP1301 device - this is necessary for
the UDC controller for connecting to the USB physical layer
Example:
isp1301: usb-transceiver@2c {
compatible = "nxp,isp1301";
reg = <0x2c>;
};
usbd@31020000 {
compatible = "nxp,lpc3220-udc";
reg = <0x31020000 0x300>;
interrupt-parent = <&mic>;
interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
transceiver = <&isp1301>;
};

95
Documentation/devicetree/bindings/usb/msm-hsusb.txt Normal file
View file

@ -0,0 +1,95 @@
MSM SoC HSUSB controllers
EHCI
Required properties:
- compatible: Should contain "qcom,ehci-host"
- regs: offset and length of the register set in the memory map
- usb-phy: phandle for the PHY device
Example EHCI controller device node:
ehci: ehci@f9a55000 {
compatible = "qcom,ehci-host";
reg = <0xf9a55000 0x400>;
usb-phy = <&usb_otg>;
};
USB PHY with optional OTG:
Required properties:
- compatible: Should contain:
"qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
"qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
- regs: Offset and length of the register set in the memory map
- interrupts: interrupt-specifier for the OTG interrupt.
- clocks: A list of phandle + clock-specifier pairs for the
clocks listed in clock-names
- clock-names: Should contain the following:
"phy" USB PHY reference clock
"core" Protocol engine clock
"iface" Interface bus clock
"alt_core" Protocol engine clock for targets with asynchronous
reset methodology. (optional)
- vdccx-supply: phandle to the regulator for the vdd supply for
digital circuit operation.
- v1p8-supply: phandle to the regulator for the 1.8V supply
- v3p3-supply: phandle to the regulator for the 3.3V supply
- resets: A list of phandle + reset-specifier pairs for the
resets listed in reset-names
- reset-names: Should contain the following:
"phy" USB PHY controller reset
"link" USB LINK controller reset
- qcom,otg-control: OTG control (VBUS and ID notifications) can be one of
1 - PHY control
2 - PMIC control
Optional properties:
- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
- qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device
Mode Eye Diagram test. Start address at which these values will be
written is ULPI_EXT_VENDOR_SPECIFIC. Value of -1 is reserved as
"do not overwrite default value at this address".
For example: qcom,phy-init-sequence = < -1 0x63 >;
Will update only value at address ULPI_EXT_VENDOR_SPECIFIC + 1.
- qcom,phy-num: Select number of pyco-phy to use, can be one of
0 - PHY one, default
1 - Second PHY
Some platforms may have configuration to allow USB
controller work with any of the two HSPHYs present.
- qcom,vdd-levels: This property must be a list of three integer values
(no, min, max) where each value represents either a voltage
in microvolts or a value corresponding to voltage corner.
Example HSUSB OTG controller device node:
usb@f9a55000 {
compatible = "qcom,usb-otg-snps";
reg = <0xf9a55000 0x400>;
interrupts = <0 134 0>;
dr_mode = "peripheral";
clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
<&gcc GCC_USB_HS_AHB_CLK>;
clock-names = "phy", "core", "iface";
vddcx-supply = <&pm8841_s2_corner>;
v1p8-supply = <&pm8941_l6>;
v3p3-supply = <&pm8941_l24>;
resets = <&gcc GCC_USB2A_PHY_BCR>, <&gcc GCC_USB_HS_BCR>;
reset-names = "phy", "link";
qcom,otg-control = <1>;
qcom,phy-init-sequence = < -1 0x63 >;
qcom,vdd-levels = <1 5 7>;
};

21
Documentation/devicetree/bindings/usb/mxs-phy.txt Normal file
View file

@ -0,0 +1,21 @@
* Freescale MXS USB Phy Device
Required properties:
- compatible: should contain:
* "fsl,imx23-usbphy" for imx23 and imx28
* "fsl,imx6q-usbphy" for imx6dq and imx6dl
* "fsl,imx6sl-usbphy" for imx6sl
* "fsl,vf610-usbphy" for Vybrid vf610
* "fsl,imx6sx-usbphy" for imx6sx
"fsl,imx23-usbphy" is still a fallback for other strings
- reg: Should contain registers location and length
- interrupts: Should contain phy interrupt
- fsl,anatop: phandle for anatop register, it is only for imx6 SoC series
Example:
usbphy1: usbphy@020c9000 {
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
reg = <0x020c9000 0x1000>;
interrupts = <0 44 0x04>;
fsl,anatop = <&anatop>;
};

20
Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt Normal file
View file

@ -0,0 +1,20 @@
Tegra SOC USB controllers
The device node for a USB controller that is part of a Tegra
SOC is as described in the document "Open Firmware Recommended
Practice : Universal Serial Bus" with the following modifications
and additions :
Required properties :
- compatible : Should be "nvidia,tegra20-ehci".
- nvidia,phy : phandle of the PHY that the controller is connected to.
- clocks : Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details.
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
- usb
Optional properties:
- nvidia,needs-double-reset : boolean is to be set for some of the Tegra20
USB ports, which need reset twice due to hardware issues.

69
Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt Normal file
View file

@ -0,0 +1,69 @@
Tegra SOC USB PHY
The device node for Tegra SOC USB PHY:
Required properties :
- compatible : Should be "nvidia,tegra<chip>-usb-phy".
- reg : Defines the following set of registers, in the order listed:
- The PHY's own register set.
Always present.
- The register set of the PHY containing the UTMI pad control registers.
Present if-and-only-if phy_type == utmi.
- phy_type : Should be one of "utmi", "ulpi" or "hsic".
- clocks : Defines the clocks listed in the clock-names property.
- clock-names : The following clock names must be present:
- reg: The clock needed to access the PHY's own registers. This is the
associated EHCI controller's clock. Always present.
- pll_u: PLL_U. Always present.
- timer: The timeout clock (clk_m). Present if phy_type == utmi.
- utmi-pads: The clock needed to access the UTMI pad control registers.
Present if phy_type == utmi.
- ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2).
Present if phy_type == ulpi, and ULPI link mode is in use.
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
- usb: The PHY's own reset signal.
- utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control
registers. Required even if phy_type == ulpi.
Required properties for phy_type == ulpi:
- nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
Required PHY timing params for utmi phy, for all chips:
- nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before
start of sync launches RxActive
- nvidia,elastic-limit : Variable FIFO Depth of elastic input store
- nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait
before declare IDLE.
- nvidia,term-range-adj : Range adjusment on terminations
- Either one of the following for HS driver output control:
- nvidia,xcvr-setup : integer, uses the provided value.
- nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read
from the on-chip fuses
If both are provided, nvidia,xcvr-setup-use-fuses takes precedence.
- nvidia,xcvr-lsfslew : LS falling slew rate control.
- nvidia,xcvr-lsrslew : LS rising slew rate control.
Required PHY timing params for utmi phy, only on Tegra30 and above:
- nvidia,xcvr-hsslew : HS slew rate control.
- nvidia,hssquelch-level : HS squelch detector level.
- nvidia,hsdiscon-level : HS disconnect detector level.
Optional properties:
- nvidia,has-legacy-mode : boolean indicates whether this controller can
operate in legacy mode (as APX 2500 / 2600). In legacy mode some
registers are accessed through the APB_MISC base address instead of
the USB controller.
- nvidia,is-wired : boolean. Indicates whether we can do certain kind of power
optimizations for the devices that are always connected. e.g. modem.
- dr_mode : dual role mode. Indicates the working mode for the PHY. Can be
"host", "peripheral", or "otg". Defaults to "host" if not defined.
host means this is a host controller
peripheral means it is device controller
otg means it can operate as either ("on the go")
- nvidia,has-utmi-pad-registers : boolean indicates whether this controller
contains the UTMI pad control registers common to all USB controllers.
VBUS control (required for dr_mode == otg, optional for dr_mode == host):
- vbus-supply: regulator for VBUS

24
Documentation/devicetree/bindings/usb/ohci-nxp.txt Normal file
View file

@ -0,0 +1,24 @@
* OHCI controller, NXP ohci-nxp variant
Required properties:
- compatible: must be "nxp,ohci-nxp"
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: The OHCI interrupt
- transceiver: phandle of the associated ISP1301 device - this is necessary for
the UDC controller for connecting to the USB physical layer
Example (LPC32xx):
isp1301: usb-transceiver@2c {
compatible = "nxp,isp1301";
reg = <0x2c>;
};
ohci@31020000 {
compatible = "nxp,ohci-nxp";
reg = <0x31020000 0x300>;
interrupt-parent = <&mic>;
interrupts = <0x3b 0>;
transceiver = <&isp1301>;
};

15
Documentation/devicetree/bindings/usb/ohci-omap3.txt Normal file
View file

@ -0,0 +1,15 @@
OMAP HS USB OHCI controller (OMAP3 and later)
Required properties:
- compatible: should be "ti,ohci-omap3"
- reg: should contain one register range i.e. start and length
- interrupts: description of the interrupt line
Example for OMAP4:
usbhsohci: ohci@4a064800 {
compatible = "ti,ohci-omap3";
reg = <0x4a064800 0x400>;
interrupts = <0 76 0x4>;
};

37
Documentation/devicetree/bindings/usb/ohci-st.txt Normal file
View file

@ -0,0 +1,37 @@
ST USB OHCI controller
Required properties:
- compatible : must be "st,st-ohci-300x"
- reg : physical base addresses of the controller and length of memory mapped
region
- interrupts : one OHCI controller interrupt should be described here
- clocks : phandle list of usb clocks
- clock-names : should be "ic" for interconnect clock and "clk48"
See: Documentation/devicetree/bindings/clock/clock-bindings.txt
- phys : phandle for the PHY device
- phy-names : should be "usb"
- resets : phandle to the powerdown and reset controller for the USB IP
- reset-names : should be "power" and "softreset".
See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
See: Documentation/devicetree/bindings/reset/reset.txt
Example:
ohci0: usb@0xfe1ffc00 {
compatible = "st,st-ohci-300x";
reg = <0xfe1ffc00 0x100>;
interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
clocks = <&clk_s_a1_ls 0>,
<&clockgen_b0 0>;
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
status = "okay";
resets = <&powerdown STIH416_USB0_POWERDOWN>,
<&softreset STIH416_USB0_SOFTRESET>;
reset-names = "power", "softreset";
};

80
Documentation/devicetree/bindings/usb/omap-usb.txt Normal file
View file

@ -0,0 +1,80 @@
OMAP GLUE AND OTHER OMAP SPECIFIC COMPONENTS
OMAP MUSB GLUE
- compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
- ti,hwmods : must be "usb_otg_hs"
- multipoint : Should be "1" indicating the musb controller supports
multipoint. This is a MUSB configuration-specific setting.
- num-eps : Specifies the number of endpoints. This is also a
MUSB configuration-specific setting. Should be set to "16"
- ram-bits : Specifies the ram address size. Should be set to "12"
- interface-type : This is a board specific setting to describe the type of
interface between the controller and the phy. It should be "0" or "1"
specifying ULPI and UTMI respectively.
- mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
represents PERIPHERAL.
- power : Should be "50". This signifies the controller can supply up to
100mA when operating in host mode.
- usb-phy : the phandle for the PHY device
- phys : the phandle for the PHY device (used by generic PHY framework)
- phy-names : the names of the PHY corresponding to the PHYs present in the
*phy* phandle.
Optional properties:
- ctrl-module : phandle of the control module this glue uses to write to
mailbox
SOC specific device node entry
usb_otg_hs: usb_otg_hs@4a0ab000 {
compatible = "ti,omap4-musb";
ti,hwmods = "usb_otg_hs";
multipoint = <1>;
num-eps = <16>;
ram-bits = <12>;
ctrl-module = <&omap_control_usb>;
phys = <&usb2_phy>;
phy-names = "usb2-phy";
};
Board specific device node entry
&usb_otg_hs {
interface-type = <1>;
mode = <3>;
power = <50>;
};
OMAP DWC3 GLUE
- compatible : Should be
* "ti,dwc3" for OMAP5 and DRA7
* "ti,am437x-dwc3" for AM437x
- ti,hwmods : Should be "usb_otg_ss"
- reg : Address and length of the register set for the device.
- interrupts : The irq number of this device that is used to interrupt the
MPU
- #address-cells, #size-cells : Must be present if the device has sub-nodes
- utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID.
It should be set to "1" for HW mode and "2" for SW mode.
- ranges: the child address space are mapped 1:1 onto the parent address space
Optional Properties:
- extcon : phandle for the extcon device omap dwc3 uses to detect
connect/disconnect events.
- vbus-supply : phandle to the regulator device tree node if needed.
Sub-nodes:
The dwc3 core should be added as subnode to omap dwc3 glue.
- dwc3 :
The binding details of dwc3 can be found in:
Documentation/devicetree/bindings/usb/dwc3.txt
omap_dwc3 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss";
reg = <0x4a020000 0x1ff>;
interrupts = <0 93 4>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <2>;
ranges;
};

31
Documentation/devicetree/bindings/usb/pxa-usb.txt Normal file
View file

@ -0,0 +1,31 @@
PXA USB controllers
OHCI
Required properties:
- compatible: Should be "marvell,pxa-ohci" for USB controllers
used in host mode.
Optional properties:
- "marvell,enable-port1", "marvell,enable-port2", "marvell,enable-port3"
If present, enables the appropriate USB port of the controller.
- "marvell,port-mode" selects the mode of the ports:
1 = PMM_NPS_MODE
2 = PMM_GLOBAL_MODE
3 = PMM_PERPORT_MODE
- "marvell,power-sense-low" - power sense pin is low-active.
- "marvell,power-control-low" - power control pin is low-active.
- "marvell,no-oc-protection" - disable over-current protection.
- "marvell,oc-mode-perport" - enable per-port over-current protection.
- "marvell,power_on_delay" Power On to Power Good time - in ms.
Example:
usb0: ohci@4c000000 {
compatible = "marvell,pxa-ohci", "usb-ohci";
reg = <0x4c000000 0x100000>;
interrupts = <18>;
marvell,enable-port1;
marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */
};

66
Documentation/devicetree/bindings/usb/qcom,dwc3.txt Normal file
View file

@ -0,0 +1,66 @@
Qualcomm SuperSpeed DWC3 USB SoC controller
Required properties:
- compatible: should contain "qcom,dwc3"
- clocks: A list of phandle + clock-specifier pairs for the
clocks listed in clock-names
- clock-names: Should contain the following:
"core" Master/Core clock, have to be >= 125 MHz for SS
operation and >= 60MHz for HS operation
Optional clocks:
"iface" System bus AXI clock. Not present on all platforms
"sleep" Sleep clock, used when USB3 core goes into low
power mode (U3).
Required child node:
A child node must exist to represent the core DWC3 IP block. The name of
the node is not important. The content of the node is defined in dwc3.txt.
Phy documentation is provided in the following places:
Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt
Example device nodes:
hs_phy: phy@100f8800 {
compatible = "qcom,dwc3-hs-usb-phy";
reg = <0x100f8800 0x30>;
clocks = <&gcc USB30_0_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
status = "ok";
};
ss_phy: phy@100f8830 {
compatible = "qcom,dwc3-ss-usb-phy";
reg = <0x100f8830 0x30>;
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
status = "ok";
};
usb3_0: usb30@0 {
compatible = "qcom,dwc3";
#address-cells = <1>;
#size-cells = <1>;
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "core";
ranges;
status = "ok";
dwc3@10000000 {
compatible = "snps,dwc3";
reg = <0x10000000 0xcd00>;
interrupts = <0 205 0x4>;
phys = <&hs_phy>, <&ss_phy>;
phy-names = "usb2-phy", "usb3-phy";
tx-fifo-resize;
dr_mode = "host";
};
};

24
Documentation/devicetree/bindings/usb/renesas_usbhs.txt Normal file
View file

@ -0,0 +1,24 @@
Renesas Electronics USBHS driver
Required properties:
- compatible: Must contain one of the following:
- "renesas,usbhs-r8a7790"
- "renesas,usbhs-r8a7791"
- reg: Base address and length of the register for the USBHS
- interrupts: Interrupt specifier for the USBHS
- clocks: A list of phandle + clock specifier pairs
Optional properties:
- renesas,buswait: Integer to use BUSWAIT register
- renesas,enable-gpio: A gpio specifier to check GPIO determining if USB
function should be enabled
- phys: phandle + phy specifier pair
- phy-names: must be "usb"
Example:
usbhs: usb@e6590000 {
compatible = "renesas,usbhs-r8a7790";
reg = <0 0xe6590000 0 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
};

40
Documentation/devicetree/bindings/usb/samsung-hsotg.txt Normal file
View file

@ -0,0 +1,40 @@
Samsung High Speed USB OTG controller
-----------------------------
The Samsung HSOTG IP can be found on Samsung SoCs, from S3C6400 onwards.
It gives functionality of OTG-compliant USB 2.0 host and device with
support for USB 2.0 high-speed (480Mbps) and full-speed (12 Mbps)
operation.
Currently only device mode is supported.
Binding details
-----
Required properties:
- compatible: "samsung,s3c6400-hsotg" should be used for all currently
supported SoC,
- interrupt-parent: phandle for the interrupt controller to which the
interrupt signal of the HSOTG block is routed,
- interrupts: specifier of interrupt signal of interrupt controller,
according to bindings of interrupt controller,
- clocks: contains an array of clock specifiers:
- first entry: OTG clock
- clock-names: contains array of clock names:
- first entry: must be "otg"
- vusb_d-supply: phandle to voltage regulator of digital section,
- vusb_a-supply: phandle to voltage regulator of analog section.
Example
-----
hsotg@12480000 {
compatible = "samsung,s3c6400-hsotg";
reg = <0x12480000 0x20000>;
interrupts = <0 71 0>;
clocks = <&clock 305>;
clock-names = "otg";
vusb_d-supply = <&vusb_reg>;
vusb_a-supply = <&vusbdac_reg>;
};

117
Documentation/devicetree/bindings/usb/samsung-usbphy.txt Normal file
View file

@ -0,0 +1,117 @@
SAMSUNG USB-PHY controllers
** Samsung's usb 2.0 phy transceiver
The Samsung's usb 2.0 phy transceiver is used for controlling
usb 2.0 phy for s3c-hsotg as well as ehci-s5p and ohci-exynos
usb controllers across Samsung SOCs.
TODO: Adding the PHY binding with controller(s) according to the under
development generic PHY driver.
Required properties:
Exynos4210:
- compatible : should be "samsung,exynos4210-usb2phy"
- reg : base physical address of the phy registers and length of memory mapped
region.
- clocks: Clock IDs array as required by the controller.
- clock-names: names of clock correseponding IDs clock property as requested
by the controller driver.
Exynos5250:
- compatible : should be "samsung,exynos5250-usb2phy"
- reg : base physical address of the phy registers and length of memory mapped
region.
Optional properties:
- #address-cells: should be '1' when usbphy node has a child node with 'reg'
property.
- #size-cells: should be '1' when usbphy node has a child node with 'reg'
property.
- ranges: allows valid translation between child's address space and parent's
address space.
- The child node 'usbphy-sys' to the node 'usbphy' is for the system controller
interface for usb-phy. It should provide the following information required by
usb-phy controller to control phy.
- reg : base physical address of PHY_CONTROL registers.
The size of this register is the total sum of size of all PHY_CONTROL
registers that the SoC has. For example, the size will be
'0x4' in case we have only one PHY_CONTROL register (e.g.
OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210)
and, '0x8' in case we have two PHY_CONTROL registers (e.g.
USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).
and so on.
Example:
- Exynos4210
usbphy@125B0000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "samsung,exynos4210-usb2phy";
reg = <0x125B0000 0x100>;
ranges;
clocks = <&clock 2>, <&clock 305>;
clock-names = "xusbxti", "otg";
usbphy-sys {
/* USB device and host PHY_CONTROL registers */
reg = <0x10020704 0x8>;
};
};
** Samsung's usb 3.0 phy transceiver
Starting exynso5250, Samsung's SoC have usb 3.0 phy transceiver
which is used for controlling usb 3.0 phy for dwc3-exynos usb 3.0
controllers across Samsung SOCs.
Required properties:
Exynos5250:
- compatible : should be "samsung,exynos5250-usb3phy"
- reg : base physical address of the phy registers and length of memory mapped
region.
- clocks: Clock IDs array as required by the controller.
- clock-names: names of clocks correseponding to IDs in the clock property
as requested by the controller driver.
Optional properties:
- #address-cells: should be '1' when usbphy node has a child node with 'reg'
property.
- #size-cells: should be '1' when usbphy node has a child node with 'reg'
property.
- ranges: allows valid translation between child's address space and parent's
address space.
- The child node 'usbphy-sys' to the node 'usbphy' is for the system controller
interface for usb-phy. It should provide the following information required by
usb-phy controller to control phy.
- reg : base physical address of PHY_CONTROL registers.
The size of this register is the total sum of size of all PHY_CONTROL
registers that the SoC has. For example, the size will be
'0x4' in case we have only one PHY_CONTROL register (e.g.
OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210)
and, '0x8' in case we have two PHY_CONTROL registers (e.g.
USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).
and so on.
Example:
usbphy@12100000 {
compatible = "samsung,exynos5250-usb3phy";
reg = <0x12100000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&clock 1>, <&clock 286>;
clock-names = "ext_xtal", "usbdrd30";
usbphy-sys {
/* USB device and host PHY_CONTROL registers */
reg = <0x10040704 0x8>;
};
};

39
Documentation/devicetree/bindings/usb/spear-usb.txt Normal file
View file

@ -0,0 +1,39 @@
ST SPEAr SoC USB controllers:
-----------------------------
EHCI:
-----
Required properties:
- compatible: "st,spear600-ehci"
- interrupt-parent: Should be the phandle for the interrupt controller
that services interrupts for this device
- interrupts: Should contain the EHCI interrupt
Example:
ehci@e1800000 {
compatible = "st,spear600-ehci", "usb-ehci";
reg = <0xe1800000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <27>;
};
OHCI:
-----
Required properties:
- compatible: "st,spear600-ohci"
- interrupt-parent: Should be the phandle for the interrupt controller
that services interrupts for this device
- interrupts: Should contain the OHCI interrupt
Example:
ohci@e1900000 {
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe1800000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <26>;
};

40
Documentation/devicetree/bindings/usb/twlxxxx-usb.txt Normal file
View file

@ -0,0 +1,40 @@
USB COMPARATOR OF TWL CHIPS
TWL6030 USB COMPARATOR
- compatible : Should be "ti,twl6030-usb"
- interrupts : Two interrupt numbers to the cpu should be specified. First
interrupt number is the otg interrupt number that raises ID interrupts when
the controller has to act as host and the second interrupt number is the
usb interrupt number that raises VBUS interrupts when the controller has to
act as device
- usb-supply : phandle to the regulator device tree node. It should be vusb
if it is twl6030 or ldousb if it is twl6032 subclass.
twl6030-usb {
compatible = "ti,twl6030-usb";
interrupts = < 4 10 >;
};
Board specific device node entry
&twl6030-usb {
usb-supply = <&vusb>;
};
TWL4030 USB PHY AND COMPARATOR
- compatible : Should be "ti,twl4030-usb"
- interrupts : The interrupt numbers to the cpu should be specified. First
interrupt number is the otg interrupt number that raises ID interrupts
and VBUS interrupts. The second interrupt number is optional.
- <supply-name>-supply : phandle to the regulator device tree node.
<supply-name> should be vusb1v5, vusb1v8 and vusb3v1
- usb_mode : The mode used by the phy to connect to the controller. "1"
specifies "ULPI" mode and "2" specifies "CEA2011_3PIN" mode.
twl4030-usb {
compatible = "ti,twl4030-usb";
interrupts = < 10 4 >;
usb1v5-supply = <&vusb1v5>;
usb1v8-supply = <&vusb1v8>;
usb3v1-supply = <&vusb3v1>;
usb_mode = <1>;
};

18
Documentation/devicetree/bindings/usb/udc-xilinx.txt Normal file
View file

@ -0,0 +1,18 @@
Xilinx USB2 device controller
Required properties:
- compatible : Should be "xlnx,usb2-device-4.00.a"
- reg : Physical base address and size of the USB2
device registers map.
- interrupts : Should contain single irq line of USB2 device
controller
- xlnx,has-builtin-dma : if DMA is included
Example:
axi-usb2-device@42e00000 {
compatible = "xlnx,usb2-device-4.00.a";
interrupts = <0x0 0x39 0x1>;
reg = <0x42e00000 0x10000>;
xlnx,has-builtin-dma;
};

37
Documentation/devicetree/bindings/usb/usb-ehci.txt Normal file
View file

@ -0,0 +1,37 @@
USB EHCI controllers
Required properties:
- compatible : should be "generic-ehci".
- reg : should contain at least address and length of the standard EHCI
register set for the device. Optional platform-dependent registers
(debug-port or other) can be also specified here, but only after
definition of standard EHCI registers.
- interrupts : one EHCI interrupt should be described here.
Optional properties:
- big-endian-regs : boolean, set this for hcds with big-endian registers
- big-endian-desc : boolean, set this for hcds with big-endian descriptors
- big-endian : boolean, for hcds with big-endian-regs + big-endian-desc
- clocks : a list of phandle + clock specifier pairs
- phys : phandle + phy specifier pair
- phy-names : "usb"
- resets : phandle + reset specifier pair
Example (Sequoia 440EPx):
ehci@e0000300 {
compatible = "ibm,usb-ehci-440epx", "usb-ehci";
interrupt-parent = <&UIC0>;
interrupts = <1a 4>;
reg = <0 e0000300 90 0 e0000390 70>;
big-endian;
};
Example (Allwinner sun4i A10 SoC):
ehci0: usb@01c14000 {
compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
reg = <0x01c14000 0x100>;
interrupts = <39>;
clocks = <&ahb_gates 1>;
phys = <&usbphy 1>;
phy-names = "usb";
};

33
Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt Normal file
View file

@ -0,0 +1,33 @@
USB NOP PHY
Required properties:
- compatible: should be usb-nop-xceiv
Optional properties:
- clocks: phandle to the PHY clock. Use as per Documentation/devicetree
/bindings/clock/clock-bindings.txt
This property is required if clock-frequency is specified.
- clock-names: Should be "main_clk"
- clock-frequency: the clock frequency (in Hz) that the PHY clock must
be configured to.
- vcc-supply: phandle to the regulator that provides RESET to the PHY.
- reset-gpios: Should specify the GPIO for reset.
Example:
hsusb1_phy {
compatible = "usb-nop-xceiv";
clock-frequency = <19200000>;
clocks = <&osc 0>;
clock-names = "main_clk";
vcc-supply = <&hsusb1_vcc_regulator>;
reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
};
hsusb1_phy is a NOP USB PHY device that gets its clock from an oscillator
and expects that clock to be configured to 19.2MHz by the NOP PHY driver.
hsusb1_vcc_regulator provides power to the PHY and GPIO 7 controls RESET.

26
Documentation/devicetree/bindings/usb/usb-ohci.txt Normal file
View file

@ -0,0 +1,26 @@
USB OHCI controllers
Required properties:
- compatible : "generic-ohci"
- reg : ohci controller register range (address and length)
- interrupts : ohci controller interrupt
Optional properties:
- big-endian-regs : boolean, set this for hcds with big-endian registers
- big-endian-desc : boolean, set this for hcds with big-endian descriptors
- big-endian : boolean, for hcds with big-endian-regs + big-endian-desc
- clocks : a list of phandle + clock specifier pairs
- phys : phandle + phy specifier pair
- phy-names : "usb"
- resets : phandle + reset specifier pair
Example:
ohci0: usb@01c14400 {
compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
reg = <0x01c14400 0x100>;
interrupts = <64>;
clocks = <&usb_clk 6>, <&ahb_gates 2>;
phys = <&usbphy 1>;
phy-names = "usb";
};

15
Documentation/devicetree/bindings/usb/usb-uhci.txt Normal file
View file

@ -0,0 +1,15 @@
Generic Platform UHCI Controller
-----------------------------------------------------
Required properties:
- compatible : "generic-uhci" (deprecated: "platform-uhci")
- reg : Should contain 1 register ranges(address and length)
- interrupts : UHCI controller interrupt
Example:
uhci@d8007b00 {
compatible = "generic-uhci";
reg = <0xd8007b00 0x200>;
interrupts = <43>;
};

21
Documentation/devicetree/bindings/usb/usb-xhci.txt Normal file
View file

@ -0,0 +1,21 @@
USB xHCI controllers
Required properties:
- compatible: should be one of "generic-xhci",
"marvell,armada-375-xhci", "marvell,armada-380-xhci",
"renesas,xhci-r8a7790", "renesas,xhci-r8a7791" (deprecated:
"xhci-platform").
- reg: should contain address and length of the standard XHCI
register set for the device.
- interrupts: one XHCI interrupt should be described here.
Optional properties:
- clocks: reference to a clock
- usb3-lpm-capable: determines if platform is USB3 LPM capable
Example:
usb@f0931000 {
compatible = "generic-xhci";
reg = <0xf0931000 0x8c8>;
interrupts = <0x0 0x4e 0x0>;
};

36
Documentation/devicetree/bindings/usb/usb3503.txt Normal file
View file

@ -0,0 +1,36 @@
SMSC USB3503 High-Speed Hub Controller
Required properties:
- compatible: Should be "smsc,usb3503" or "smsc,usb3503a".
Optional properties:
- reg: Specifies the i2c slave address, it is required and should be 0x08
if I2C is used.
- connect-gpios: Should specify GPIO for connect.
- disabled-ports: Should specify the ports unused.
'1' or '2' or '3' are available for this property to describe the port
number. 1~3 property values are possible to be described.
Do not describe this property if all ports have to be enabled.
- intn-gpios: Should specify GPIO for interrupt.
- reset-gpios: Should specify GPIO for reset.
- initial-mode: Should specify initial mode.
(1 for HUB mode, 2 for STANDBY mode)
- refclk: Clock used for driving REFCLK signal (optional, if not provided
the driver assumes that clock signal is always available, its
rate is specified by REF_SEL pins and a value from the primary
reference clock frequencies table is used)
- refclk-frequency: Frequency of the REFCLK signal as defined by REF_SEL
pins (optional, if not provided, driver will not set rate of the
REFCLK signal and assume that a value from the primary reference
clock frequencies table is used)
Examples:
usb3503@08 {
compatible = "smsc,usb3503";
reg = <0x08>;
connect-gpios = <&gpx3 0 1>;
disabled-ports = <2 3>;
intn-gpios = <&gpx3 4 1>;
reset-gpios = <&gpx3 5 1>;
initial-mode = <1>;
};

15
Documentation/devicetree/bindings/usb/usbmisc-imx.txt Normal file
View file

@ -0,0 +1,15 @@
* Freescale i.MX non-core registers
Required properties:
- #index-cells: Cells used to descibe usb controller index. Should be <1>
- compatible: Should be one of below:
"fsl,imx6q-usbmisc" for imx6q
"fsl,vf610-usbmisc" for Vybrid vf610
- reg: Should contain registers location and length
Examples:
usbmisc@02184800 {
#index-cells = <1>;
compatible = "fsl,imx6q-usbmisc";
reg = <0x02184800 0x200>;
};

50
Documentation/devicetree/bindings/usb/ux500-usb.txt Normal file
View file

@ -0,0 +1,50 @@
Ux500 MUSB
Required properties:
- compatible : Should be "stericsson,db8500-musb"
- reg : Offset and length of registers
- interrupts : Interrupt; mode, number and trigger
- dr_mode : Dual-role; either host mode "host", peripheral mode "peripheral"
or both "otg"
Optional properties:
- dmas : A list of dma channels;
dma-controller, event-line, fixed-channel, flags
- dma-names : An ordered list of channel names affiliated to the above
Example:
usb_per5@a03e0000 {
compatible = "stericsson,db8500-musb";
reg = <0xa03e0000 0x10000>;
interrupts = <0 23 0x4>;
interrupt-names = "mc";
dr_mode = "otg";
dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
<&dma 38 0 0x0>, /* Logical - MemToDev */
<&dma 37 0 0x2>, /* Logical - DevToMem */
<&dma 37 0 0x0>, /* Logical - MemToDev */
<&dma 36 0 0x2>, /* Logical - DevToMem */
<&dma 36 0 0x0>, /* Logical - MemToDev */
<&dma 19 0 0x2>, /* Logical - DevToMem */
<&dma 19 0 0x0>, /* Logical - MemToDev */
<&dma 18 0 0x2>, /* Logical - DevToMem */
<&dma 18 0 0x0>, /* Logical - MemToDev */
<&dma 17 0 0x2>, /* Logical - DevToMem */
<&dma 17 0 0x0>, /* Logical - MemToDev */
<&dma 16 0 0x2>, /* Logical - DevToMem */
<&dma 16 0 0x0>, /* Logical - MemToDev */
<&dma 39 0 0x2>, /* Logical - DevToMem */
<&dma 39 0 0x0>; /* Logical - MemToDev */
dma-names = "iep_1_9", "oep_1_9",
"iep_2_10", "oep_2_10",
"iep_3_11", "oep_3_11",
"iep_4_12", "oep_4_12",
"iep_5_13", "oep_5_13",
"iep_6_14", "oep_6_14",
"iep_7_15", "oep_7_15",
"iep_8", "oep_8";
};