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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
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Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
240
arch/arc/boot/dts/abilis_tb10x.dtsi
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240
arch/arc/boot/dts/abilis_tb10x.dtsi
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/*
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* Abilis Systems TB10X SOC device tree
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*
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* Copyright (C) Abilis Systems 2013
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*
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* Author: Christian Ruppert <christian.ruppert@abilis.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/ {
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compatible = "abilis,arc-tb10x";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "snps,arc770d";
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reg = <0>;
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};
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};
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soc100 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0xfe000000 0xfe000000 0x02000000
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0x000F0000 0x000F0000 0x00010000>;
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compatible = "abilis,tb10x", "simple-bus";
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pll0: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "pll0";
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};
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cpu_clk: clkdiv_cpu {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clocks = <&pll0>;
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clock-output-names = "cpu_clk";
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};
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ahb_clk: clkdiv_ahb {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clocks = <&pll0>;
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clock-output-names = "ahb_clk";
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};
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iomux: iomux@FF10601c {
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compatible = "abilis,tb10x-iomux";
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#gpio-range-cells = <3>;
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reg = <0xFF10601c 0x4>;
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};
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intc: interrupt-controller {
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compatible = "snps,arc700-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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tb10x_ictl: pic@fe002000 {
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compatible = "abilis,tb10x-ictl";
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reg = <0xFE002000 0x20>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
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20 21 22 23 24 25 26 27 28 29 30 31>;
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};
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uart@FF100000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xFF100000 0x100>;
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clock-frequency = <166666666>;
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interrupts = <25 8>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupt-parent = <&tb10x_ictl>;
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};
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ethernet@FE100000 {
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compatible = "snps,dwmac-3.70a","snps,dwmac";
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reg = <0xFE100000 0x1058>;
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interrupt-parent = <&tb10x_ictl>;
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interrupts = <6 8>;
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interrupt-names = "macirq";
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clocks = <&ahb_clk>;
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clock-names = "stmmaceth";
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};
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dma@FE000000 {
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compatible = "snps,dma-spear1340";
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reg = <0xFE000000 0x400>;
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interrupt-parent = <&tb10x_ictl>;
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interrupts = <14 8>;
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dma-channels = <6>;
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dma-requests = <0>;
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dma-masters = <1>;
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#dma-cells = <3>;
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chan_allocation_order = <0>;
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chan_priority = <1>;
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block_size = <0x7ff>;
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data_width = <2 0 0 0>;
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clocks = <&ahb_clk>;
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clock-names = "hclk";
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};
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i2c0: i2c@FF120000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xFF120000 0x1000>;
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interrupt-parent = <&tb10x_ictl>;
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interrupts = <12 8>;
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clocks = <&ahb_clk>;
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};
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i2c1: i2c@FF121000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xFF121000 0x1000>;
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interrupt-parent = <&tb10x_ictl>;
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interrupts = <12 8>;
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clocks = <&ahb_clk>;
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};
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i2c2: i2c@FF122000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xFF122000 0x1000>;
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interrupt-parent = <&tb10x_ictl>;
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interrupts = <12 8>;
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clocks = <&ahb_clk>;
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};
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i2c3: i2c@FF123000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xFF123000 0x1000>;
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interrupt-parent = <&tb10x_ictl>;
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interrupts = <12 8>;
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clocks = <&ahb_clk>;
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};
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i2c4: i2c@FF124000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xFF124000 0x1000>;
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interrupt-parent = <&tb10x_ictl>;
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interrupts = <12 8>;
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clocks = <&ahb_clk>;
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};
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spi0: spi@0xFE010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "abilis,tb100-spi";
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num-cs = <1>;
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reg = <0xFE010000 0x20>;
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interrupt-parent = <&tb10x_ictl>;
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interrupts = <26 8>;
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clocks = <&ahb_clk>;
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};
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spi1: spi@0xFE011000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "abilis,tb100-spi";
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num-cs = <2>;
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reg = <0xFE011000 0x20>;
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interrupt-parent = <&tb10x_ictl>;
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interrupts = <10 8>;
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clocks = <&ahb_clk>;
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};
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tb10x_tsm: tb10x-tsm@ff316000 {
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compatible = "abilis,tb100-tsm";
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reg = <0xff316000 0x400>;
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interrupt-parent = <&tb10x_ictl>;
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interrupts = <17 8>;
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output-clkdiv = <4>;
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global-packet-delay = <0x21>;
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port-packet-delay = <0>;
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};
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tb10x_stream_proc: tb10x-stream-proc {
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compatible = "abilis,tb100-streamproc";
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reg = <0xfff00000 0x200>,
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<0x000f0000 0x10000>,
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<0xfff00200 0x105>,
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<0xff10600c 0x1>,
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<0xfe001018 0x1>;
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reg-names = "mbox",
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"sp_iccm",
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"mbox_irq",
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"cpuctrl",
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"a6it_int_force";
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interrupt-parent = <&tb10x_ictl>;
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interrupts = <20 2>, <19 2>;
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interrupt-names = "cmd_irq", "event_irq";
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};
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tb10x_mdsc0: tb10x-mdscr@FF300000 {
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compatible = "abilis,tb100-mdscr";
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reg = <0xFF300000 0x7000>;
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tb100-mdscr-manage-tsin;
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};
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tb10x_mscr0: tb10x-mdscr@FF307000 {
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compatible = "abilis,tb100-mdscr";
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reg = <0xFF307000 0x7000>;
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};
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tb10x_scr0: tb10x-mdscr@ff30e000 {
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compatible = "abilis,tb100-mdscr";
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reg = <0xFF30e000 0x4000>;
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tb100-mdscr-manage-tsin;
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};
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tb10x_scr1: tb10x-mdscr@ff312000 {
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compatible = "abilis,tb100-mdscr";
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reg = <0xFF312000 0x4000>;
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tb100-mdscr-manage-tsin;
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};
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tb10x_wfb: tb10x-wfb@ff319000 {
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compatible = "abilis,tb100-wfb";
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reg = <0xff319000 0x1000>;
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interrupt-parent = <&tb10x_ictl>;
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interrupts = <16 8>;
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};
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};
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};
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