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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-02 00:55:37 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
357
arch/arm/boot/dts/bcm21664.dtsi
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357
arch/arm/boot/dts/bcm21664.dtsi
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/*
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* Copyright (C) 2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "dt-bindings/clock/bcm21664.h"
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#include "skeleton.dtsi"
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/ {
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model = "BCM21664 SoC";
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compatible = "brcm,bcm21664";
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interrupt-parent = <&gic>;
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chosen {
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bootargs = "console=ttyS0,115200n8";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "brcm,bcm11351-cpu-method";
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secondary-boot-reg = <0x35004178>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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};
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};
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gic: interrupt-controller@3ff00100 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x3ff01000 0x1000>,
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<0x3ff00100 0x100>;
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};
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smc@0x3404e000 {
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compatible = "brcm,bcm21664-smc", "brcm,kona-smc";
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reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
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};
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uart@3e000000 {
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compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
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status = "disabled";
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reg = <0x3e000000 0x118>;
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clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart@3e001000 {
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compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
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status = "disabled";
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reg = <0x3e001000 0x118>;
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clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart@3e002000 {
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compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
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status = "disabled";
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reg = <0x3e002000 0x118>;
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clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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L2: l2-cache {
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compatible = "arm,pl310-cache";
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reg = <0x3ff20000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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brcm,resetmgr@35001f00 {
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compatible = "brcm,bcm21664-resetmgr";
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reg = <0x35001f00 0x24>;
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};
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timer@35006000 {
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compatible = "brcm,kona-timer";
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reg = <0x35006000 0x1c>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
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};
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gpio: gpio@35003000 {
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compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio";
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reg = <0x35003000 0x524>;
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interrupts =
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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gpio-controller;
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interrupt-controller;
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};
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sdio1: sdio@3f180000 {
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compatible = "brcm,kona-sdhci";
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reg = <0x3f180000 0x801c>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
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status = "disabled";
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};
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sdio2: sdio@3f190000 {
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compatible = "brcm,kona-sdhci";
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reg = <0x3f190000 0x801c>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
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status = "disabled";
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};
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sdio3: sdio@3f1a0000 {
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compatible = "brcm,kona-sdhci";
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reg = <0x3f1a0000 0x801c>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
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status = "disabled";
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};
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sdio4: sdio@3f1b0000 {
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compatible = "brcm,kona-sdhci";
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reg = <0x3f1b0000 0x801c>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
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status = "disabled";
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};
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i2c@3e016000 {
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compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
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reg = <0x3e016000 0x70>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
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status = "disabled";
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};
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i2c@3e017000 {
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compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
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reg = <0x3e017000 0x70>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
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status = "disabled";
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};
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i2c@3e018000 {
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compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
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reg = <0x3e018000 0x70>;
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interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
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status = "disabled";
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};
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i2c@3e01c000 {
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compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
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reg = <0x3e01c000 0x70>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
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status = "disabled";
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* Fixed clocks are defined before CCUs whose
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* clocks may depend on them.
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*/
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ref_32k_clk: ref_32k {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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bbl_32k_clk: bbl_32k {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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ref_13m_clk: ref_13m {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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};
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var_13m_clk: var_13m {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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};
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dft_19_5m_clk: dft_19_5m {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <19500000>;
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};
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ref_crystal_clk: ref_crystal {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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};
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ref_52m_clk: ref_52m {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <52000000>;
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};
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var_52m_clk: var_52m {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <52000000>;
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};
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usb_otg_ahb_clk: usb_otg_ahb {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <52000000>;
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};
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ref_96m_clk: ref_96m {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <96000000>;
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};
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var_96m_clk: var_96m {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <96000000>;
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};
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ref_104m_clk: ref_104m {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <104000000>;
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};
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var_104m_clk: var_104m {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <104000000>;
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};
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ref_156m_clk: ref_156m {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <156000000>;
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};
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var_156m_clk: var_156m {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <156000000>;
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};
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root_ccu: root_ccu {
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compatible = BCM21664_DT_ROOT_CCU_COMPAT;
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reg = <0x35001000 0x0f00>;
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#clock-cells = <1>;
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clock-output-names = "frac_1m";
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};
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aon_ccu: aon_ccu {
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compatible = BCM21664_DT_AON_CCU_COMPAT;
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reg = <0x35002000 0x0f00>;
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#clock-cells = <1>;
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clock-output-names = "hub_timer";
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};
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master_ccu: master_ccu {
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compatible = BCM21664_DT_MASTER_CCU_COMPAT;
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reg = <0x3f001000 0x0f00>;
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#clock-cells = <1>;
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clock-output-names = "sdio1",
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"sdio2",
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"sdio3",
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"sdio4",
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"sdio1_sleep",
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"sdio2_sleep",
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"sdio3_sleep",
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"sdio4_sleep";
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};
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slave_ccu: slave_ccu {
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compatible = BCM21664_DT_SLAVE_CCU_COMPAT;
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reg = <0x3e011000 0x0f00>;
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#clock-cells = <1>;
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clock-output-names = "uartb",
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"uartb2",
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"uartb3",
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"bsc1",
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"bsc2",
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"bsc3",
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"bsc4";
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};
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};
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usbotg: usb@3f120000 {
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compatible = "snps,dwc2";
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reg = <0x3f120000 0x10000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usb_otg_ahb_clk>;
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clock-names = "otg";
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phys = <&usbphy>;
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phy-names = "usb2-phy";
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status = "disabled";
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};
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usbphy: usb-phy@3f130000 {
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compatible = "brcm,kona-usb2-phy";
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reg = <0x3f130000 0x28>;
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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