mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-01 08:38:52 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
319
arch/arm/boot/dts/berlin2cd.dtsi
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319
arch/arm/boot/dts/berlin2cd.dtsi
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/*
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* Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
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*
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* based on GPL'ed 2.6 kernel sources
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* (c) Marvell International Ltd.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/berlin2.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Marvell Armada 1500-mini (BG2CD) SoC";
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compatible = "marvell,berlin2cd", "marvell,berlin";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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next-level-cache = <&l2>;
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reg = <0>;
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};
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};
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refclk: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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ranges = <0 0xf7000000 0x1000000>;
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l2: l2-cache-controller@ac0000 {
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compatible = "arm,pl310-cache";
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reg = <0xac0000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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gic: interrupt-controller@ad1000 {
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compatible = "arm,cortex-a9-gic";
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reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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local-timer@ad0600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xad0600 0x20>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&chip CLKID_TWD>;
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};
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apb@e80000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xe80000 0x10000>;
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interrupt-parent = <&aic>;
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gpio0: gpio@0400 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0400 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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porta: gpio-port@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0>;
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};
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};
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gpio1: gpio@0800 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0800 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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portb: gpio-port@1 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <1>;
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};
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};
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gpio2: gpio@0c00 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0c00 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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portc: gpio-port@2 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <2>;
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};
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};
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gpio3: gpio@1000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x1000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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portd: gpio-port@3 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <3>;
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};
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};
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timer0: timer@2c00 {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c00 0x14>;
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interrupts = <8>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "okay";
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};
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timer1: timer@2c14 {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c14 0x14>;
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interrupts = <9>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "okay";
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};
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timer2: timer@2c28 {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c28 0x14>;
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interrupts = <10>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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timer3: timer@2c3c {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c3c 0x14>;
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interrupts = <11>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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timer4: timer@2c50 {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c50 0x14>;
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interrupts = <12>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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timer5: timer@2c64 {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c64 0x14>;
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interrupts = <13>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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timer6: timer@2c78 {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c78 0x14>;
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interrupts = <14>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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timer7: timer@2c8c {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c8c 0x14>;
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interrupts = <15>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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aic: interrupt-controller@3000 {
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compatible = "snps,dw-apb-ictl";
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reg = <0x3000 0xc00>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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chip: chip-control@ea0000 {
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compatible = "marvell,berlin2cd-chip-ctrl";
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#clock-cells = <1>;
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reg = <0xea0000 0x400>;
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clocks = <&refclk>;
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clock-names = "refclk";
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uart0_pmux: uart0-pmux {
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groups = "G6";
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function = "uart0";
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};
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};
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apb@fc0000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xfc0000 0x10000>;
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interrupt-parent = <&sic>;
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sm_gpio1: gpio@5000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x5000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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portf: gpio-port@5 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <0>;
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};
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};
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sm_gpio0: gpio@c000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0xc000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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porte: gpio-port@4 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <0>;
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};
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};
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uart0: serial@9000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x9000 0x100>;
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reg-shift = <2>;
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reg-io-width = <1>;
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interrupts = <8>;
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clocks = <&refclk>;
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pinctrl-0 = <&uart0_pmux>;
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pinctrl-names = "default";
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status = "disabled";
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};
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uart1: serial@a000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xa000 0x100>;
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reg-shift = <2>;
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reg-io-width = <1>;
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interrupts = <9>;
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clocks = <&refclk>;
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status = "disabled";
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};
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sysctrl: system-controller@d000 {
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compatible = "marvell,berlin2cd-system-ctrl";
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reg = <0xd000 0x100>;
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};
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sic: interrupt-controller@e000 {
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compatible = "snps,dw-apb-ictl";
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reg = <0xe000 0x400>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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};
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