mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
305
arch/arm/boot/dts/exynos5440.dtsi
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305
arch/arm/boot/dts/exynos5440.dtsi
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/*
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* SAMSUNG EXYNOS5440 SoC device tree source
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/clock/exynos5440.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "samsung,exynos5440", "samsung,exynos5";
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &serial_0;
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serial1 = &serial_1;
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spi0 = &spi_0;
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tmuctrl0 = &tmuctrl_0;
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tmuctrl1 = &tmuctrl_1;
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tmuctrl2 = &tmuctrl_2;
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};
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clock: clock-controller@160000 {
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compatible = "samsung,exynos5440-clock";
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reg = <0x160000 0x1000>;
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#clock-cells = <1>;
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};
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gic: interrupt-controller@2E0000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x2E1000 0x1000>,
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<0x2E2000 0x1000>,
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<0x2E4000 0x2000>,
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<0x2E6000 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <3>;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
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interrupts = <0 52 4>,
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<0 53 4>,
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<0 54 4>,
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<0 55 4>;
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};
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timer {
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compatible = "arm,cortex-a15-timer",
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"arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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clock-frequency = <50000000>;
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};
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cpufreq@160000 {
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compatible = "samsung,exynos5440-cpufreq";
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reg = <0x160000 0x1000>;
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interrupts = <0 57 0>;
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operating-points = <
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/* KHz uV */
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1500000 1100000
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1400000 1075000
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1300000 1050000
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1200000 1025000
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1100000 1000000
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1000000 975000
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900000 950000
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800000 925000
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>;
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};
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serial_0: serial@B0000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0xB0000 0x1000>;
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interrupts = <0 2 0>;
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clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
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clock-names = "uart", "clk_uart_baud0";
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};
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serial_1: serial@C0000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0xC0000 0x1000>;
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interrupts = <0 3 0>;
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clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
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clock-names = "uart", "clk_uart_baud0";
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};
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spi_0: spi@D0000 {
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compatible = "samsung,exynos5440-spi";
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reg = <0xD0000 0x100>;
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interrupts = <0 4 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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samsung,spi-src-clk = <0>;
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num-cs = <1>;
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clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
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clock-names = "spi", "spi_busclk0";
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};
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pin_ctrl: pinctrl {
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compatible = "samsung,exynos5440-pinctrl";
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reg = <0xE0000 0x1000>;
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interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
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<0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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#gpio-cells = <2>;
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fan: fan {
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samsung,exynos5440-pin-function = <1>;
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};
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hdd_led0: hdd_led0 {
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samsung,exynos5440-pin-function = <2>;
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};
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hdd_led1: hdd_led1 {
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samsung,exynos5440-pin-function = <3>;
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};
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uart1: uart1 {
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samsung,exynos5440-pin-function = <4>;
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};
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};
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i2c@F0000 {
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compatible = "samsung,exynos5440-i2c";
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reg = <0xF0000 0x1000>;
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interrupts = <0 5 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock CLK_B_125>;
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clock-names = "i2c";
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};
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i2c@100000 {
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compatible = "samsung,exynos5440-i2c";
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reg = <0x100000 0x1000>;
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interrupts = <0 6 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock CLK_B_125>;
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clock-names = "i2c";
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};
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watchdog@110000 {
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compatible = "samsung,s3c2410-wdt";
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reg = <0x110000 0x1000>;
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interrupts = <0 1 0>;
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clocks = <&clock CLK_B_125>;
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clock-names = "watchdog";
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};
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gmac: ethernet@00230000 {
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compatible = "snps,dwmac-3.70a";
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reg = <0x00230000 0x8000>;
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interrupt-parent = <&gic>;
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interrupts = <0 31 4>;
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interrupt-names = "macirq";
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phy-mode = "sgmii";
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clocks = <&clock CLK_GMAC0>;
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clock-names = "stmmaceth";
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};
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amba {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,amba-bus";
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interrupt-parent = <&gic>;
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ranges;
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};
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rtc {
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compatible = "samsung,s3c6410-rtc";
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reg = <0x130000 0x1000>;
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interrupts = <0 17 0>, <0 16 0>;
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clocks = <&clock CLK_B_125>;
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clock-names = "rtc";
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};
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tmuctrl_0: tmuctrl@160118 {
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compatible = "samsung,exynos5440-tmu";
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reg = <0x160118 0x230>, <0x160368 0x10>;
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interrupts = <0 58 0>;
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clocks = <&clock CLK_B_125>;
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clock-names = "tmu_apbif";
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};
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tmuctrl_1: tmuctrl@16011C {
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compatible = "samsung,exynos5440-tmu";
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reg = <0x16011C 0x230>, <0x160368 0x10>;
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interrupts = <0 58 0>;
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clocks = <&clock CLK_B_125>;
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clock-names = "tmu_apbif";
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};
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tmuctrl_2: tmuctrl@160120 {
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compatible = "samsung,exynos5440-tmu";
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reg = <0x160120 0x230>, <0x160368 0x10>;
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interrupts = <0 58 0>;
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clocks = <&clock CLK_B_125>;
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clock-names = "tmu_apbif";
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};
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sata@210000 {
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compatible = "snps,exynos5440-ahci";
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reg = <0x210000 0x10000>;
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interrupts = <0 30 0>;
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clocks = <&clock CLK_SATA>;
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clock-names = "sata";
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};
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ohci@220000 {
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compatible = "samsung,exynos5440-ohci";
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reg = <0x220000 0x1000>;
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interrupts = <0 29 0>;
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clocks = <&clock CLK_USB>;
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clock-names = "usbhost";
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};
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ehci@221000 {
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compatible = "samsung,exynos5440-ehci";
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reg = <0x221000 0x1000>;
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interrupts = <0 29 0>;
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clocks = <&clock CLK_USB>;
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clock-names = "usbhost";
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};
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pcie@290000 {
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compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
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reg = <0x290000 0x1000
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0x270000 0x1000
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0x271000 0x40>;
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interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
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clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
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clock-names = "pcie", "pcie_bus";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
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0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0x0 0 &gic 53>;
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num-lanes = <4>;
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status = "disabled";
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};
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pcie@2a0000 {
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compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
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reg = <0x2a0000 0x1000
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0x272000 0x1000
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0x271040 0x40>;
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interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
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clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
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clock-names = "pcie", "pcie_bus";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
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0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0x0 0 &gic 56>;
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num-lanes = <4>;
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status = "disabled";
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};
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};
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