mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 08:08:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
310
arch/arm/boot/dts/imx6q.dtsi
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310
arch/arm/boot/dts/imx6q.dtsi
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "imx6q-pinfunc.h"
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#include "imx6qdl.dtsi"
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/ {
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aliases {
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spi4 = &ecspi5;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1150000
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396000 975000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks IMX6QDL_CLK_ARM>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_STEP>,
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<&clks IMX6QDL_CLK_PLL1_SW>,
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<&clks IMX6QDL_CLK_PLL1_SYS>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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cpu@2 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <2>;
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next-level-cache = <&L2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <3>;
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next-level-cache = <&L2>;
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};
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};
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soc {
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ocram: sram@00900000 {
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compatible = "mmio-sram";
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reg = <0x00900000 0x40000>;
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clocks = <&clks IMX6QDL_CLK_OCRAM>;
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};
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aips-bus@02000000 { /* AIPS1 */
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spba-bus@02000000 {
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ecspi5: ecspi@02018000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
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reg = <0x02018000 0x4000>;
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interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6Q_CLK_ECSPI5>,
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<&clks IMX6Q_CLK_ECSPI5>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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};
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iomuxc: iomuxc@020e0000 {
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compatible = "fsl,imx6q-iomuxc";
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ipu2 {
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pinctrl_ipu2_1: ipu2grp-1 {
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fsl,pins = <
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MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
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MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
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MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
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MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
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MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
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MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
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MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
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MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
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MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
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MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
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MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
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MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
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MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
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MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
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MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
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MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
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MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
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MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
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MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
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MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
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MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
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MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
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MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
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MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
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MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
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MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
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MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
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MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
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MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
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>;
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};
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};
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};
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};
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sata: sata@02200000 {
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compatible = "fsl,imx6q-ahci";
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reg = <0x02200000 0x4000>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_SATA>,
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<&clks IMX6QDL_CLK_SATA_REF_100M>,
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<&clks IMX6QDL_CLK_AHB>;
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clock-names = "sata", "sata_ref", "ahb";
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status = "disabled";
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};
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ipu2: ipu@02800000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-ipu";
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reg = <0x02800000 0x400000>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_IPU2>,
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<&clks IMX6QDL_CLK_IPU2_DI0>,
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<&clks IMX6QDL_CLK_IPU2_DI1>;
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clock-names = "bus", "di0", "di1";
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resets = <&src 4>;
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ipu2_csi0: port@0 {
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reg = <0>;
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};
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ipu2_csi1: port@1 {
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reg = <1>;
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};
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ipu2_di0: port@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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ipu2_di0_disp0: endpoint@0 {
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};
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ipu2_di0_hdmi: endpoint@1 {
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remote-endpoint = <&hdmi_mux_2>;
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};
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ipu2_di0_mipi: endpoint@2 {
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};
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ipu2_di0_lvds0: endpoint@3 {
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remote-endpoint = <&lvds0_mux_2>;
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};
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ipu2_di0_lvds1: endpoint@4 {
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remote-endpoint = <&lvds1_mux_2>;
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};
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};
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ipu2_di1: port@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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ipu2_di1_hdmi: endpoint@1 {
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remote-endpoint = <&hdmi_mux_3>;
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};
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ipu2_di1_mipi: endpoint@2 {
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};
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ipu2_di1_lvds0: endpoint@3 {
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remote-endpoint = <&lvds0_mux_3>;
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};
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ipu2_di1_lvds1: endpoint@4 {
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remote-endpoint = <&lvds1_mux_3>;
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};
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};
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};
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};
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display-subsystem {
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compatible = "fsl,imx-display-subsystem";
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ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
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};
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};
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&hdmi {
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compatible = "fsl,imx6q-hdmi";
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port@2 {
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reg = <2>;
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hdmi_mux_2: endpoint {
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remote-endpoint = <&ipu2_di0_hdmi>;
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};
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};
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port@3 {
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reg = <3>;
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hdmi_mux_3: endpoint {
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remote-endpoint = <&ipu2_di1_hdmi>;
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};
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};
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};
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&ldb {
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clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
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<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
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<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
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<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
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clock-names = "di0_pll", "di1_pll",
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"di0_sel", "di1_sel", "di2_sel", "di3_sel",
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"di0", "di1";
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lvds-channel@0 {
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port@2 {
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reg = <2>;
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lvds0_mux_2: endpoint {
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remote-endpoint = <&ipu2_di0_lvds0>;
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};
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};
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port@3 {
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reg = <3>;
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lvds0_mux_3: endpoint {
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remote-endpoint = <&ipu2_di1_lvds0>;
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};
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};
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};
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lvds-channel@1 {
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port@2 {
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reg = <2>;
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lvds1_mux_2: endpoint {
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remote-endpoint = <&ipu2_di0_lvds1>;
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};
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};
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port@3 {
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reg = <3>;
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lvds1_mux_3: endpoint {
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remote-endpoint = <&ipu2_di1_lvds1>;
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};
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};
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};
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};
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&mipi_dsi {
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port@2 {
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reg = <2>;
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mipi_mux_2: endpoint {
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remote-endpoint = <&ipu2_di0_mipi>;
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};
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};
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port@3 {
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reg = <3>;
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mipi_mux_3: endpoint {
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remote-endpoint = <&ipu2_di1_mipi>;
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};
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};
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};
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