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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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267
arch/arm/boot/dts/k2l-clocks.dtsi Normal file
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/*
* Copyright 2013-2014 Texas Instruments, Inc.
*
* Keystone 2 lamarr SoC clock nodes
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
clocks {
armpllclk: armpllclk@2620370 {
#clock-cells = <0>;
compatible = "ti,keystone,pll-clock";
clocks = <&refclksys>;
clock-output-names = "arm-pll-clk";
reg = <0x02620370 4>;
reg-names = "control";
};
mainpllclk: mainpllclk@2310110 {
#clock-cells = <0>;
compatible = "ti,keystone,main-pll-clock";
clocks = <&refclksys>;
reg = <0x02620350 4>, <0x02310110 4>;
reg-names = "control", "multiplier";
fixed-postdiv = <2>;
};
papllclk: papllclk@2620358 {
#clock-cells = <0>;
compatible = "ti,keystone,pll-clock";
clocks = <&refclksys>;
clock-output-names = "papllclk";
reg = <0x02620358 4>;
reg-names = "control";
};
ddr3apllclk: ddr3apllclk@2620360 {
#clock-cells = <0>;
compatible = "ti,keystone,pll-clock";
clocks = <&refclksys>;
clock-output-names = "ddr-3a-pll-clk";
reg = <0x02620360 4>;
reg-names = "control";
};
clkdfeiqnsys: clkdfeiqnsys {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk12>;
clock-output-names = "dfe";
reg-names = "control", "domain";
reg = <0x02350004 0xb00>, <0x02350000 0x400>;
domain-id = <0>;
};
clkpcie1: clkpcie1 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk12>;
clock-output-names = "pcie";
reg = <0x0235002c 0xb00>, <0x02350000 0x400>;
reg-names = "control", "domain";
domain-id = <4>;
};
clkgem1: clkgem1 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk1>;
clock-output-names = "gem1";
reg = <0x02350040 0xb00>, <0x02350024 0x400>;
reg-names = "control", "domain";
domain-id = <9>;
};
clkgem2: clkgem2 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk1>;
clock-output-names = "gem2";
reg = <0x02350044 0xb00>, <0x02350028 0x400>;
reg-names = "control", "domain";
domain-id = <10>;
};
clkgem3: clkgem3 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk1>;
clock-output-names = "gem3";
reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
reg-names = "control", "domain";
domain-id = <11>;
};
clktac: clktac {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
clock-output-names = "tac";
reg = <0x02350064 0xb00>, <0x02350044 0x400>;
reg-names = "control", "domain";
domain-id = <17>;
};
clkrac: clkrac {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
clock-output-names = "rac";
reg = <0x02350068 0xb00>, <0x02350044 0x400>;
reg-names = "control", "domain";
domain-id = <17>;
};
clkdfepd0: clkdfepd0 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
clock-output-names = "dfe-pd0";
reg = <0x0235006c 0xb00>, <0x02350044 0x400>;
reg-names = "control", "domain";
domain-id = <18>;
};
clkfftc0: clkfftc0 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
clock-output-names = "fftc-0";
reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
reg-names = "control", "domain";
domain-id = <19>;
};
clkosr: clkosr {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
clock-output-names = "osr";
reg = <0x02350088 0xb00>, <0x0235004c 0x400>;
reg-names = "control", "domain";
domain-id = <21>;
};
clktcp3d0: clktcp3d0 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
clock-output-names = "tcp3d-0";
reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
reg-names = "control", "domain";
domain-id = <22>;
};
clktcp3d1: clktcp3d1 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
clock-output-names = "tcp3d-1";
reg = <0x02350094 0xb00>, <0x02350058 0x400>;
reg-names = "control", "domain";
domain-id = <23>;
};
clkvcp0: clkvcp0 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
clock-output-names = "vcp-0";
reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
reg-names = "control", "domain";
domain-id = <24>;
};
clkvcp1: clkvcp1 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
clock-output-names = "vcp-1";
reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
reg-names = "control", "domain";
domain-id = <24>;
};
clkvcp2: clkvcp2 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
clock-output-names = "vcp-2";
reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
reg-names = "control", "domain";
domain-id = <24>;
};
clkvcp3: clkvcp3 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
clock-output-names = "vcp-3";
reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
reg-names = "control", "domain";
domain-id = <24>;
};
clkbcp: clkbcp {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
clock-output-names = "bcp";
reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
reg-names = "control", "domain";
domain-id = <26>;
};
clkdfepd1: clkdfepd1 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
clock-output-names = "dfe-pd1";
reg = <0x023500c0 0xb00>, <0x02350044 0x400>;
reg-names = "control", "domain";
domain-id = <27>;
};
clkfftc1: clkfftc1 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
clock-output-names = "fftc-1";
reg = <0x023500c4 0xb00>, <0x023504c0 0x400>;
reg-names = "control", "domain";
domain-id = <28>;
};
clkiqnail: clkiqnail {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk13>;
clock-output-names = "iqn-ail";
reg = <0x023500c8 0xb00>, <0x0235004c 0x400>;
reg-names = "control", "domain";
domain-id = <29>;
};
clkuart2: clkuart2 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkmodrst0>;
clock-output-names = "uart2";
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
reg-names = "control", "domain";
domain-id = <0>;
};
clkuart3: clkuart3 {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&clkmodrst0>;
clock-output-names = "uart3";
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
reg-names = "control", "domain";
domain-id = <0>;
};
};