mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
344
arch/arm/boot/dts/omap2430-clocks.dtsi
Normal file
344
arch/arm/boot/dts/omap2430-clocks.dtsi
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/*
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* Device Tree Source for OMAP2430 clock data
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*
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* Copyright (C) 2014 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&scrm_clocks {
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mcbsp3_mux_fck: mcbsp3_mux_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&func_96m_ck>, <&mcbsp_clks>;
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reg = <0x02e8>;
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};
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mcbsp3_fck: mcbsp3_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
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};
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mcbsp4_mux_fck: mcbsp4_mux_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&func_96m_ck>, <&mcbsp_clks>;
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ti,bit-shift = <2>;
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reg = <0x02e8>;
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};
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mcbsp4_fck: mcbsp4_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
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};
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mcbsp5_mux_fck: mcbsp5_mux_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&func_96m_ck>, <&mcbsp_clks>;
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ti,bit-shift = <4>;
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reg = <0x02e8>;
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};
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mcbsp5_fck: mcbsp5_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
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};
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};
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&prcm_clocks {
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iva2_1_gate_ick: iva2_1_gate_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-gate-clock";
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clocks = <&dsp_fck>;
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ti,bit-shift = <0>;
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reg = <0x0800>;
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};
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iva2_1_div_ick: iva2_1_div_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&dsp_fck>;
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ti,bit-shift = <5>;
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ti,max-div = <3>;
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reg = <0x0840>;
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ti,index-starts-at-one;
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};
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iva2_1_ick: iva2_1_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
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};
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mdm_gate_ick: mdm_gate_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-interface-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <0>;
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reg = <0x0c10>;
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};
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mdm_div_ick: mdm_div_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&core_ck>;
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reg = <0x0c40>;
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ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>;
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};
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mdm_ick: mdm_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&mdm_gate_ick>, <&mdm_div_ick>;
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};
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mdm_osc_ck: mdm_osc_ck {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&osc_ck>;
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ti,bit-shift = <1>;
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reg = <0x0c00>;
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};
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mcbsp3_ick: mcbsp3_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l4_ck>;
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ti,bit-shift = <3>;
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reg = <0x0214>;
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};
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mcbsp3_gate_fck: mcbsp3_gate_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-gate-clock";
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clocks = <&mcbsp_clks>;
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ti,bit-shift = <3>;
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reg = <0x0204>;
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};
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mcbsp4_ick: mcbsp4_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l4_ck>;
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ti,bit-shift = <4>;
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reg = <0x0214>;
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};
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mcbsp4_gate_fck: mcbsp4_gate_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-gate-clock";
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clocks = <&mcbsp_clks>;
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ti,bit-shift = <4>;
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reg = <0x0204>;
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};
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mcbsp5_ick: mcbsp5_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l4_ck>;
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ti,bit-shift = <5>;
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reg = <0x0214>;
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};
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mcbsp5_gate_fck: mcbsp5_gate_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-gate-clock";
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clocks = <&mcbsp_clks>;
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ti,bit-shift = <5>;
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reg = <0x0204>;
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};
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mcspi3_ick: mcspi3_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l4_ck>;
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ti,bit-shift = <9>;
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reg = <0x0214>;
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};
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mcspi3_fck: mcspi3_fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&func_48m_ck>;
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ti,bit-shift = <9>;
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reg = <0x0204>;
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};
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icr_ick: icr_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&sys_ck>;
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ti,bit-shift = <6>;
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reg = <0x0410>;
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};
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i2chs1_fck: i2chs1_fck {
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#clock-cells = <0>;
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compatible = "ti,omap2430-interface-clock";
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clocks = <&func_96m_ck>;
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ti,bit-shift = <19>;
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reg = <0x0204>;
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};
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i2chs2_fck: i2chs2_fck {
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#clock-cells = <0>;
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compatible = "ti,omap2430-interface-clock";
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clocks = <&func_96m_ck>;
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ti,bit-shift = <20>;
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reg = <0x0204>;
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};
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usbhs_ick: usbhs_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&core_l3_ck>;
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ti,bit-shift = <6>;
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reg = <0x0214>;
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};
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mmchs1_ick: mmchs1_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l4_ck>;
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ti,bit-shift = <7>;
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reg = <0x0214>;
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};
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mmchs1_fck: mmchs1_fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&func_96m_ck>;
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ti,bit-shift = <7>;
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reg = <0x0204>;
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};
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mmchs2_ick: mmchs2_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l4_ck>;
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ti,bit-shift = <8>;
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reg = <0x0214>;
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};
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mmchs2_fck: mmchs2_fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&func_96m_ck>;
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ti,bit-shift = <8>;
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reg = <0x0204>;
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};
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gpio5_ick: gpio5_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l4_ck>;
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ti,bit-shift = <10>;
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reg = <0x0214>;
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};
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gpio5_fck: gpio5_fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&func_32k_ck>;
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ti,bit-shift = <10>;
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reg = <0x0204>;
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};
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mdm_intc_ick: mdm_intc_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l4_ck>;
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ti,bit-shift = <11>;
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reg = <0x0214>;
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};
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mmchsdb1_fck: mmchsdb1_fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&func_32k_ck>;
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ti,bit-shift = <16>;
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reg = <0x0204>;
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};
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mmchsdb2_fck: mmchsdb2_fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&func_32k_ck>;
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ti,bit-shift = <17>;
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reg = <0x0204>;
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};
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};
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&prcm_clockdomains {
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gfx_clkdm: gfx_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&gfx_ick>;
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};
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core_l3_clkdm: core_l3_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>;
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};
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wkup_clkdm: wkup_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
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<&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
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<&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>,
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<&icr_ick>;
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};
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dss_clkdm: dss_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&dss_ick>, <&dss_54m_fck>;
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};
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core_l4_clkdm: core_l4_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
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<&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
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<&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
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<&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
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<&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>,
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<&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
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<&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>,
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<&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>,
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<&uart3_fck>, <&cam_ick>, <&mailboxes_ick>,
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<&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>,
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<&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>,
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<&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>,
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<&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
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<&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>,
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<&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>,
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<&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>,
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<&mmchsdb2_fck>;
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};
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mdm_clkdm: mdm_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&mdm_osc_ck>;
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};
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};
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&func_96m_ck {
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compatible = "ti,mux-clock";
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clocks = <&apll96_ck>, <&alt_ck>;
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ti,bit-shift = <4>;
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reg = <0x0540>;
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};
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&dsp_div_fck {
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ti,max-div = <4>;
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ti,index-starts-at-one;
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};
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&ssi_ssr_sst_div_fck {
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ti,max-div = <5>;
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ti,index-starts-at-one;
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};
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