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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 08:08:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
232
arch/arm/boot/dts/orion5x.dtsi
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232
arch/arm/boot/dts/orion5x.dtsi
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/*
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* Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include "skeleton.dtsi"
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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/ {
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model = "Marvell Orion5x SoC";
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compatible = "marvell,orion5x";
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interrupt-parent = <&intc>;
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aliases {
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gpio0 = &gpio0;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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devbus_bootcs: devbus-bootcs {
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compatible = "marvell,orion-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
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ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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devbus_cs0: devbus-cs0 {
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compatible = "marvell,orion-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
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ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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devbus_cs1: devbus-cs1 {
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compatible = "marvell,orion-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
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ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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devbus_cs2: devbus-cs2 {
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compatible = "marvell,orion-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
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ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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internal-regs {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
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gpio0: gpio@10100 {
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compatible = "marvell,orion-gpio";
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0x10100 0x40>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <6>, <7>, <8>, <9>;
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};
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spi: spi@10600 {
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compatible = "marvell,orion-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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reg = <0x10600 0x28>;
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status = "disabled";
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};
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i2c: i2c@11000 {
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compatible = "marvell,mv64xxx-i2c";
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reg = <0x11000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <5>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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uart0: serial@12000 {
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compatible = "ns16550a";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <3>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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uart1: serial@12100 {
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compatible = "ns16550a";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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interrupts = <4>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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bridge_intc: bridge-interrupt-ctrl@20110 {
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compatible = "marvell,orion-bridge-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x20110 0x8>;
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interrupts = <0>;
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marvell,#interrupts = <4>;
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};
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intc: interrupt-controller@20200 {
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compatible = "marvell,orion-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x20200 0x08>;
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};
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timer: timer@20300 {
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compatible = "marvell,orion-timer";
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reg = <0x20300 0x20>;
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interrupt-parent = <&bridge_intc>;
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interrupts = <1>, <2>;
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clocks = <&core_clk 0>;
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};
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wdt: wdt@20300 {
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compatible = "marvell,orion-wdt";
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reg = <0x20300 0x28>;
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interrupt-parent = <&bridge_intc>;
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interrupts = <3>;
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status = "okay";
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};
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ehci0: ehci@50000 {
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compatible = "marvell,orion-ehci";
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reg = <0x50000 0x1000>;
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interrupts = <17>;
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status = "disabled";
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};
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xor: dma-controller@60900 {
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compatible = "marvell,orion-xor";
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reg = <0x60900 0x100
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0x60b00 0x100>;
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status = "okay";
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xor00 {
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interrupts = <30>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <31>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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eth: ethernet-controller@72000 {
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compatible = "marvell,orion-eth";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x72000 0x4000>;
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marvell,tx-checksum-limit = <1600>;
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status = "disabled";
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ethport: ethernet-port@0 {
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compatible = "marvell,orion-eth-port";
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reg = <0>;
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interrupts = <21>;
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/* overwrite MAC address in bootloader */
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local-mac-address = [00 00 00 00 00 00];
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/* set phy-handle property in board file */
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};
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};
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mdio: mdio-bus@72004 {
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compatible = "marvell,orion-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x72004 0x84>;
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interrupts = <22>;
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status = "disabled";
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/* add phy nodes in board file */
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};
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sata: sata@80000 {
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compatible = "marvell,orion-sata";
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reg = <0x80000 0x5000>;
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interrupts = <29>;
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status = "disabled";
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};
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ehci1: ehci@a0000 {
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compatible = "marvell,orion-ehci";
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reg = <0xa0000 0x1000>;
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interrupts = <12>;
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status = "disabled";
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};
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};
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cesa: crypto@90000 {
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compatible = "marvell,orion-crypto";
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reg = <MBUS_ID(0xf0, 0x01) 0x90000 0x10000>,
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<MBUS_ID(0x09, 0x00) 0x0 0x800>;
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reg-names = "regs", "sram";
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interrupts = <28>;
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status = "okay";
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};
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};
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};
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