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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
283
arch/arm/boot/dts/qcom-ipq8064.dtsi
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283
arch/arm/boot/dts/qcom-ipq8064.dtsi
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/dts-v1/;
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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/ {
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model = "Qualcomm IPQ8064";
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compatible = "qcom,ipq8064";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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};
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cpu@1 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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cpu-pmu {
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compatible = "qcom,krait-pmu";
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interrupts = <1 10 0x304>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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nss@40000000 {
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reg = <0x40000000 0x1000000>;
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no-map;
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};
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smem@41000000 {
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reg = <0x41000000 0x200000>;
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no-map;
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};
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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qcom_pinmux: pinmux@800000 {
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compatible = "qcom,ipq8064-pinctrl";
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reg = <0x800000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 32 0x4>;
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};
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intc: interrupt-controller@2000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x02000000 0x1000>,
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<0x02002000 0x1000>;
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};
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timer@200a000 {
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compatible = "qcom,kpss-timer", "qcom,msm-timer";
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interrupts = <1 1 0x301>,
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<1 2 0x301>,
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<1 3 0x301>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <25000000>,
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<32768>;
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cpu-offset = <0x80000>;
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};
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acc0: clock-controller@2088000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
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};
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acc1: clock-controller@2098000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
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};
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saw0: regulator@2089000 {
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compatible = "qcom,saw2";
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reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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saw1: regulator@2099000 {
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compatible = "qcom,saw2";
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reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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gsbi2: gsbi@12480000 {
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compatible = "qcom,gsbi-v1.0.0";
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reg = <0x12480000 0x100>;
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clocks = <&gcc GSBI2_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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serial@12490000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x12490000 0x1000>,
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<0x12480000 0x1000>;
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interrupts = <0 195 0x0>;
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clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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i2c@124a0000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x124a0000 0x1000>;
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interrupts = <0 196 0>;
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clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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gsbi4: gsbi@16300000 {
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compatible = "qcom,gsbi-v1.0.0";
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reg = <0x16300000 0x100>;
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clocks = <&gcc GSBI4_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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serial@16340000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16340000 0x1000>,
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<0x16300000 0x1000>;
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interrupts = <0 152 0x0>;
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clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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i2c@16380000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x16380000 0x1000>;
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interrupts = <0 153 0>;
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clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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gsbi5: gsbi@1a200000 {
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compatible = "qcom,gsbi-v1.0.0";
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reg = <0x1a200000 0x100>;
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clocks = <&gcc GSBI5_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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serial@1a240000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x1a240000 0x1000>,
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<0x1a200000 0x1000>;
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interrupts = <0 154 0x0>;
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clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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i2c@1a280000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x1a280000 0x1000>;
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interrupts = <0 155 0>;
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clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi@1a280000 {
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compatible = "qcom,spi-qup-v1.1.1";
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reg = <0x1a280000 0x1000>;
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interrupts = <0 155 0>;
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clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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sata_phy: sata-phy@1b400000 {
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compatible = "qcom,ipq806x-sata-phy";
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reg = <0x1b400000 0x200>;
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clocks = <&gcc SATA_PHY_CFG_CLK>;
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clock-names = "cfg";
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#phy-cells = <0>;
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status = "disabled";
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};
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sata@29000000 {
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compatible = "qcom,ipq806x-ahci", "generic-ahci";
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reg = <0x29000000 0x180>;
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interrupts = <0 209 0x0>;
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clocks = <&gcc SFAB_SATA_S_H_CLK>,
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<&gcc SATA_H_CLK>,
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<&gcc SATA_A_CLK>,
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<&gcc SATA_RXOOB_CLK>,
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<&gcc SATA_PMALIVE_CLK>;
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clock-names = "slave_face", "iface", "core",
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"rxoob", "pmalive";
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assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
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assigned-clock-rates = <100000000>, <100000000>;
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phys = <&sata_phy>;
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phy-names = "sata-phy";
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status = "disabled";
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};
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qcom,ssbi@500000 {
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compatible = "qcom,ssbi";
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reg = <0x00500000 0x1000>;
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qcom,controller-type = "pmic-arbiter";
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};
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gcc: clock-controller@900000 {
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compatible = "qcom,gcc-ipq8064";
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reg = <0x00900000 0x4000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};
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};
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