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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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54
arch/arm/include/debug/8250.S Normal file
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/*
* arch/arm/include/debug/8250.S
*
* Copyright (C) 1994-2013 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/serial_reg.h>
.macro addruart, rp, rv, tmp
ldr \rp, =CONFIG_DEBUG_UART_PHYS
ldr \rv, =CONFIG_DEBUG_UART_VIRT
.endm
#ifdef CONFIG_DEBUG_UART_8250_WORD
.macro store, rd, rx:vararg
str \rd, \rx
.endm
.macro load, rd, rx:vararg
ldr \rd, \rx
.endm
#else
.macro store, rd, rx:vararg
strb \rd, \rx
.endm
.macro load, rd, rx:vararg
ldrb \rd, \rx
.endm
#endif
#define UART_SHIFT CONFIG_DEBUG_UART_8250_SHIFT
.macro senduart,rd,rx
store \rd, [\rx, #UART_TX << UART_SHIFT]
.endm
.macro busyuart,rd,rx
1002: load \rd, [\rx, #UART_LSR << UART_SHIFT]
and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
bne 1002b
.endm
.macro waituart,rd,rx
#ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL
1001: load \rd, [\rx, #UART_MSR << UART_SHIFT]
tst \rd, #UART_MSR_CTS
beq 1001b
#endif
.endm

33
arch/arm/include/debug/bcm63xx.S Normal file
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/*
* Broadcom BCM63xx low-level UART debug
*
* Copyright (C) 2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/serial_bcm63xx.h>
.macro addruart, rp, rv, tmp
ldr \rp, =CONFIG_DEBUG_UART_PHYS
ldr \rv, =CONFIG_DEBUG_UART_VIRT
.endm
.macro senduart, rd, rx
/* word access do not work */
strb \rd, [\rx, #UART_FIFO_REG]
.endm
.macro waituart, rd, rx
1001: ldr \rd, [\rx, #UART_IR_REG]
tst \rd, #(1 << UART_IR_TXEMPTY)
beq 1001b
.endm
.macro busyuart, rd, rx
1002: ldr \rd, [\rx, #UART_IR_REG]
tst \rd, #(1 << UART_IR_TXTRESH)
beq 1002b
.endm

38
arch/arm/include/debug/clps711x.S Normal file
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/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef CONFIG_DEBUG_CLPS711X_UART2
#define CLPS711X_UART_PADDR (0x80000000 + 0x0000)
#define CLPS711X_UART_VADDR (0xfeff0000 + 0x0000)
#else
#define CLPS711X_UART_PADDR (0x80000000 + 0x1000)
#define CLPS711X_UART_VADDR (0xfeff0000 + 0x1000)
#endif
#define SYSFLG (0x0140)
#define SYSFLG_UBUSY (1 << 11)
#define UARTDR (0x0480)
.macro addruart, rp, rv, tmp
ldr \rv, =CLPS711X_UART_VADDR
ldr \rp, =CLPS711X_UART_PADDR
.endm
.macro waituart,rd,rx
.endm
.macro senduart,rd,rx
str \rd, [\rx, #UARTDR]
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #SYSFLG]
tst \rd, #SYSFLG_UBUSY
bne 1001b
.endm

45
arch/arm/include/debug/efm32.S Normal file
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/*
* Copyright (C) 2013 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define UARTn_CMD 0x000c
#define UARTn_CMD_TXEN 0x0004
#define UARTn_STATUS 0x0010
#define UARTn_STATUS_TXC 0x0020
#define UARTn_STATUS_TXBL 0x0040
#define UARTn_TXDATA 0x0034
.macro addruart, rx, tmp
ldr \rx, =(CONFIG_DEBUG_UART_PHYS)
/*
* enable TX. The driver might disable it to save energy. We
* don't care about disabling at the end as during debug power
* consumption isn't that important.
*/
ldr \tmp, =(UARTn_CMD_TXEN)
str \tmp, [\rx, #UARTn_CMD]
.endm
.macro senduart,rd,rx
strb \rd, [\rx, #UARTn_TXDATA]
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #UARTn_STATUS]
tst \rd, #UARTn_STATUS_TXBL
beq 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, UARTn_STATUS]
tst \rd, #UARTn_STATUS_TXC
bne 1001b
.endm

39
arch/arm/include/debug/exynos.S Normal file
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/*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* pull in the relevant register and map files. */
#define S3C_ADDR_BASE 0xF6000000
#define S3C_VA_UART S3C_ADDR_BASE + 0x01000000
#define EXYNOS4_PA_UART 0x13800000
#define EXYNOS5_PA_UART 0x12C00000
/* note, for the boot process to work we have to keep the UART
* virtual address aligned to an 1MiB boundary for the L1
* mapping the head code makes. We keep the UART virtual address
* aligned and add in the offset when we load the value here.
*/
.macro addruart, rp, rv, tmp
mrc p15, 0, \tmp, c0, c0, 0
and \tmp, \tmp, #0xf0
teq \tmp, #0xf0 @@ A15
ldreq \rp, =EXYNOS5_PA_UART
movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4
ldr \rv, =S3C_VA_UART
#if CONFIG_DEBUG_S3C_UART != 0
add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
#endif
.endm
#define fifo_full fifo_full_s5pv210
#define fifo_level fifo_level_s5pv210
#include <debug/samsung.S>

90
arch/arm/include/debug/icedcc.S Normal file
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/*
* arch/arm/include/debug/icedcc.S
*
* Copyright (C) 1994-1999 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
@@ debug using ARM EmbeddedICE DCC channel
.macro addruart, rp, rv, tmp
.endm
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
.macro senduart, rd, rx
mcr p14, 0, \rd, c0, c5, 0
.endm
.macro busyuart, rd, rx
1001:
mrc p14, 0, \rx, c0, c1, 0
tst \rx, #0x20000000
beq 1001b
.endm
.macro waituart, rd, rx
mov \rd, #0x2000000
1001:
subs \rd, \rd, #1
bmi 1002f
mrc p14, 0, \rx, c0, c1, 0
tst \rx, #0x20000000
bne 1001b
1002:
.endm
#elif defined(CONFIG_CPU_XSCALE)
.macro senduart, rd, rx
mcr p14, 0, \rd, c8, c0, 0
.endm
.macro busyuart, rd, rx
1001:
mrc p14, 0, \rx, c14, c0, 0
tst \rx, #0x10000000
beq 1001b
.endm
.macro waituart, rd, rx
mov \rd, #0x10000000
1001:
subs \rd, \rd, #1
bmi 1002f
mrc p14, 0, \rx, c14, c0, 0
tst \rx, #0x10000000
bne 1001b
1002:
.endm
#else
.macro senduart, rd, rx
mcr p14, 0, \rd, c1, c0, 0
.endm
.macro busyuart, rd, rx
1001:
mrc p14, 0, \rx, c0, c0, 0
tst \rx, #2
beq 1001b
.endm
.macro waituart, rd, rx
mov \rd, #0x2000000
1001:
subs \rd, \rd, #1
bmi 1002f
mrc p14, 0, \rx, c0, c0, 0
tst \rx, #2
bne 1001b
1002:
.endm
#endif /* CONFIG_CPU_V6 */

119
arch/arm/include/debug/imx-uart.h Normal file
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/*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DEBUG_IMX_UART_H
#define __DEBUG_IMX_UART_H
#define IMX1_UART1_BASE_ADDR 0x00206000
#define IMX1_UART2_BASE_ADDR 0x00207000
#define IMX1_UART_BASE_ADDR(n) IMX1_UART##n##_BASE_ADDR
#define IMX1_UART_BASE(n) IMX1_UART_BASE_ADDR(n)
#define IMX21_UART1_BASE_ADDR 0x1000a000
#define IMX21_UART2_BASE_ADDR 0x1000b000
#define IMX21_UART3_BASE_ADDR 0x1000c000
#define IMX21_UART4_BASE_ADDR 0x1000d000
#define IMX21_UART_BASE_ADDR(n) IMX21_UART##n##_BASE_ADDR
#define IMX21_UART_BASE(n) IMX21_UART_BASE_ADDR(n)
#define IMX25_UART1_BASE_ADDR 0x43f90000
#define IMX25_UART2_BASE_ADDR 0x43f94000
#define IMX25_UART3_BASE_ADDR 0x5000c000
#define IMX25_UART4_BASE_ADDR 0x50008000
#define IMX25_UART5_BASE_ADDR 0x5002c000
#define IMX25_UART_BASE_ADDR(n) IMX25_UART##n##_BASE_ADDR
#define IMX25_UART_BASE(n) IMX25_UART_BASE_ADDR(n)
#define IMX31_UART1_BASE_ADDR 0x43f90000
#define IMX31_UART2_BASE_ADDR 0x43f94000
#define IMX31_UART3_BASE_ADDR 0x5000c000
#define IMX31_UART4_BASE_ADDR 0x43fb0000
#define IMX31_UART5_BASE_ADDR 0x43fb4000
#define IMX31_UART_BASE_ADDR(n) IMX31_UART##n##_BASE_ADDR
#define IMX31_UART_BASE(n) IMX31_UART_BASE_ADDR(n)
#define IMX35_UART1_BASE_ADDR 0x43f90000
#define IMX35_UART2_BASE_ADDR 0x43f94000
#define IMX35_UART3_BASE_ADDR 0x5000c000
#define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR
#define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n)
#define IMX50_UART1_BASE_ADDR 0x53fbc000
#define IMX50_UART2_BASE_ADDR 0x53fc0000
#define IMX50_UART3_BASE_ADDR 0x5000c000
#define IMX50_UART4_BASE_ADDR 0x53ff0000
#define IMX50_UART5_BASE_ADDR 0x63f90000
#define IMX50_UART_BASE_ADDR(n) IMX50_UART##n##_BASE_ADDR
#define IMX50_UART_BASE(n) IMX50_UART_BASE_ADDR(n)
#define IMX51_UART1_BASE_ADDR 0x73fbc000
#define IMX51_UART2_BASE_ADDR 0x73fc0000
#define IMX51_UART3_BASE_ADDR 0x7000c000
#define IMX51_UART_BASE_ADDR(n) IMX51_UART##n##_BASE_ADDR
#define IMX51_UART_BASE(n) IMX51_UART_BASE_ADDR(n)
#define IMX53_UART1_BASE_ADDR 0x53fbc000
#define IMX53_UART2_BASE_ADDR 0x53fc0000
#define IMX53_UART3_BASE_ADDR 0x5000c000
#define IMX53_UART4_BASE_ADDR 0x53ff0000
#define IMX53_UART5_BASE_ADDR 0x63f90000
#define IMX53_UART_BASE_ADDR(n) IMX53_UART##n##_BASE_ADDR
#define IMX53_UART_BASE(n) IMX53_UART_BASE_ADDR(n)
#define IMX6Q_UART1_BASE_ADDR 0x02020000
#define IMX6Q_UART2_BASE_ADDR 0x021e8000
#define IMX6Q_UART3_BASE_ADDR 0x021ec000
#define IMX6Q_UART4_BASE_ADDR 0x021f0000
#define IMX6Q_UART5_BASE_ADDR 0x021f4000
#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
#define IMX6SL_UART1_BASE_ADDR 0x02020000
#define IMX6SL_UART2_BASE_ADDR 0x02024000
#define IMX6SL_UART3_BASE_ADDR 0x02034000
#define IMX6SL_UART4_BASE_ADDR 0x02038000
#define IMX6SL_UART5_BASE_ADDR 0x02018000
#define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR
#define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n)
#define IMX6SX_UART1_BASE_ADDR 0x02020000
#define IMX6SX_UART2_BASE_ADDR 0x021e8000
#define IMX6SX_UART3_BASE_ADDR 0x021ec000
#define IMX6SX_UART4_BASE_ADDR 0x021f0000
#define IMX6SX_UART5_BASE_ADDR 0x021f4000
#define IMX6SX_UART6_BASE_ADDR 0x022a0000
#define IMX6SX_UART_BASE_ADDR(n) IMX6SX_UART##n##_BASE_ADDR
#define IMX6SX_UART_BASE(n) IMX6SX_UART_BASE_ADDR(n)
#define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
#ifdef CONFIG_DEBUG_IMX1_UART
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX1)
#elif defined(CONFIG_DEBUG_IMX21_IMX27_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX21)
#elif defined(CONFIG_DEBUG_IMX25_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX25)
#elif defined(CONFIG_DEBUG_IMX31_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX31)
#elif defined(CONFIG_DEBUG_IMX35_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX35)
#elif defined(CONFIG_DEBUG_IMX50_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX50)
#elif defined(CONFIG_DEBUG_IMX51_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX51)
#elif defined(CONFIG_DEBUG_IMX53_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX53)
#elif defined(CONFIG_DEBUG_IMX6Q_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q)
#elif defined(CONFIG_DEBUG_IMX6SL_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL)
#elif defined(CONFIG_DEBUG_IMX6SX_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SX)
#endif
#endif /* __DEBUG_IMX_UART_H */

47
arch/arm/include/debug/imx.S Normal file
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/* arch/arm/mach-imx/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include "imx-uart.h"
/*
* FIXME: This is a copy of IMX_IO_P2V in hardware.h, and needs to
* stay sync with that. It's hard to maintain, and should be fixed
* globally for multi-platform build to use a fixed virtual address
* for low-level debug uart port across platforms.
*/
#define IMX_IO_P2V(x) ( \
(((x) & 0x80000000) >> 7) | \
(0xf4000000 + \
(((x) & 0x50000000) >> 6) + \
(((x) & 0x0b000000) >> 4) + \
(((x) & 0x000fffff))))
#define UART_VADDR IMX_IO_P2V(UART_PADDR)
.macro addruart, rp, rv, tmp
ldr \rp, =UART_PADDR @ physical
ldr \rv, =UART_VADDR @ virtual
.endm
.macro senduart,rd,rx
str \rd, [\rx, #0x40] @ TXDATA
.endm
.macro waituart,rd,rx
.endm
.macro busyuart,rd,rx
1002: ldr \rd, [\rx, #0x98] @ SR2
tst \rd, #1 << 3 @ TXDC
beq 1002b @ wait until transmit done
.endm

35
arch/arm/include/debug/meson.S Normal file
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/*
* Copyright (C) 2014 Carlo Caione
* Carlo Caione <carlo@caione.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define MESON_AO_UART_WFIFO 0x0
#define MESON_AO_UART_STATUS 0xc
#define MESON_AO_UART_TX_FIFO_EMPTY (1 << 22)
#define MESON_AO_UART_TX_FIFO_FULL (1 << 21)
.macro addruart, rp, rv, tmp
ldr \rp, =(CONFIG_DEBUG_UART_PHYS) @ physical
ldr \rv, =(CONFIG_DEBUG_UART_VIRT) @ virtual
.endm
.macro senduart,rd,rx
str \rd, [\rx, #MESON_AO_UART_WFIFO]
.endm
.macro busyuart,rd,rx
1002: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
tst \rd, #MESON_AO_UART_TX_FIFO_EMPTY
beq 1002b
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
tst \rd, #MESON_AO_UART_TX_FIFO_FULL
bne 1001b
.endm

62
arch/arm/include/debug/msm.S Normal file
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/*
*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
.macro addruart, rp, rv, tmp
#ifdef CONFIG_DEBUG_UART_PHYS
ldr \rp, =CONFIG_DEBUG_UART_PHYS
ldr \rv, =CONFIG_DEBUG_UART_VIRT
#endif
.endm
.macro senduart, rd, rx
#ifdef CONFIG_DEBUG_QCOM_UARTDM
@ Write the 1 character to UARTDM_TF
str \rd, [\rx, #0x70]
#else
str \rd, [\rx, #0x0C]
#endif
.endm
.macro waituart, rd, rx
#ifdef CONFIG_DEBUG_QCOM_UARTDM
@ check for TX_EMT in UARTDM_SR
ldr \rd, [\rx, #0x08]
tst \rd, #0x08
bne 1002f
@ wait for TXREADY in UARTDM_ISR
1001: ldr \rd, [\rx, #0x14]
tst \rd, #0x80
beq 1001b
1002:
@ Clear TX_READY by writing to the UARTDM_CR register
mov \rd, #0x300
str \rd, [\rx, #0x10]
@ Write 0x1 to NCF register
mov \rd, #0x1
str \rd, [\rx, #0x40]
@ UARTDM reg. Read to induce delay
ldr \rd, [\rx, #0x08]
#else
@ wait for TX_READY
1001: ldr \rd, [\rx, #0x08]
tst \rd, #0x04
beq 1001b
#endif
.endm
.macro busyuart, rd, rx
.endm

190
arch/arm/include/debug/omap2plus.S Normal file
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/*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/serial_reg.h>
/* OMAP2 serial ports */
#define OMAP2_UART1_BASE 0x4806a000
#define OMAP2_UART2_BASE 0x4806c000
#define OMAP2_UART3_BASE 0x4806e000
/* OMAP3 serial ports */
#define OMAP3_UART1_BASE OMAP2_UART1_BASE
#define OMAP3_UART2_BASE OMAP2_UART2_BASE
#define OMAP3_UART3_BASE 0x49020000
#define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */
#define OMAP3_UART4_AM35XX_BASE 0x4809E000 /* Only on AM35xx */
/* OMAP4 serial ports */
#define OMAP4_UART1_BASE OMAP2_UART1_BASE
#define OMAP4_UART2_BASE OMAP2_UART2_BASE
#define OMAP4_UART3_BASE 0x48020000
#define OMAP4_UART4_BASE 0x4806e000
/* TI81XX serial ports */
#define TI81XX_UART1_BASE 0x48020000
#define TI81XX_UART2_BASE 0x48022000
#define TI81XX_UART3_BASE 0x48024000
/* AM3505/3517 UART4 */
#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
/* AM33XX serial port */
#define AM33XX_UART1_BASE 0x44E09000
/* OMAP5 serial ports */
#define OMAP5_UART1_BASE OMAP2_UART1_BASE
#define OMAP5_UART2_BASE OMAP2_UART2_BASE
#define OMAP5_UART3_BASE OMAP4_UART3_BASE
#define OMAP5_UART4_BASE OMAP4_UART4_BASE
#define OMAP5_UART5_BASE 0x48066000
#define OMAP5_UART6_BASE 0x48068000
/* External port on Zoom2/3 */
#define ZOOM_UART_BASE 0x10000000
#define ZOOM_UART_VIRT 0xfa400000
#define OMAP_PORT_SHIFT 2
#define ZOOM_PORT_SHIFT 1
#define UART_OFFSET(addr) ((addr) & 0x00ffffff)
.pushsection .data
omap_uart_phys: .word 0
omap_uart_virt: .word 0
omap_uart_lsr: .word 0
.popsection
.macro addruart, rp, rv, tmp
/* Use omap_uart_phys/virt if already configured */
10: adr \rp, 99f @ get effective addr of 99f
ldr \rv, [\rp] @ get absolute addr of 99f
sub \rv, \rv, \rp @ offset between the two
ldr \rp, [\rp, #4] @ abs addr of omap_uart_phys
sub \tmp, \rp, \rv @ make it effective
ldr \rp, [\tmp, #0] @ omap_uart_phys
ldr \rv, [\tmp, #4] @ omap_uart_virt
cmp \rp, #0 @ is port configured?
cmpne \rv, #0
bne 100f @ already configured
/* Configure the UART offset from the phys/virt base */
#ifdef CONFIG_DEBUG_OMAP2UART1
mov \rp, #UART_OFFSET(OMAP2_UART1_BASE) @ omap2/3/4
b 98f
#endif
#ifdef CONFIG_DEBUG_OMAP2UART2
mov \rp, #UART_OFFSET(OMAP2_UART2_BASE) @ omap2/3/4
b 98f
#endif
#ifdef CONFIG_DEBUG_OMAP2UART3
mov \rp, #UART_OFFSET(OMAP2_UART3_BASE)
b 98f
#endif
#ifdef CONFIG_DEBUG_OMAP3UART3
mov \rp, #UART_OFFSET(OMAP3_UART1_BASE)
add \rp, \rp, #0x00fb0000
add \rp, \rp, #0x00006000 @ OMAP3_UART3_BASE
b 98f
#endif
#ifdef CONFIG_DEBUG_OMAP4UART3
mov \rp, #UART_OFFSET(OMAP4_UART3_BASE)
b 98f
#endif
#ifdef CONFIG_DEBUG_OMAP3UART4
mov \rp, #UART_OFFSET(OMAP3_UART1_BASE)
add \rp, \rp, #0x00fb0000
add \rp, \rp, #0x00028000 @ OMAP3_UART4_BASE
b 98f
#endif
#ifdef CONFIG_DEBUG_OMAP4UART4
mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
b 98f
#endif
#ifdef CONFIG_DEBUG_TI81XXUART1
mov \rp, #UART_OFFSET(TI81XX_UART1_BASE)
b 98f
#endif
#ifdef CONFIG_DEBUG_TI81XXUART2
mov \rp, #UART_OFFSET(TI81XX_UART2_BASE)
b 98f
#endif
#ifdef CONFIG_DEBUG_TI81XXUART3
mov \rp, #UART_OFFSET(TI81XX_UART3_BASE)
b 98f
#endif
#ifdef CONFIG_DEBUG_AM33XXUART1
ldr \rp, =AM33XX_UART1_BASE
and \rp, \rp, #0x00ffffff
b 97f
#endif
#ifdef CONFIG_DEBUG_ZOOM_UART
ldr \rp, =ZOOM_UART_BASE
str \rp, [\tmp, #0] @ omap_uart_phys
ldr \rp, =ZOOM_UART_VIRT
str \rp, [\tmp, #4] @ omap_uart_virt
mov \rp, #(UART_LSR << ZOOM_PORT_SHIFT)
str \rp, [\tmp, #8] @ omap_uart_lsr
#endif
b 10b
/* AM33XX: Store both phys and virt address for the uart */
97: add \rp, \rp, #0x44000000 @ phys base
str \rp, [\tmp, #0] @ omap_uart_phys
sub \rp, \rp, #0x44000000 @ phys base
add \rp, \rp, #0xf9000000 @ virt base
str \rp, [\tmp, #4] @ omap_uart_virt
mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
str \rp, [\tmp, #8] @ omap_uart_lsr
b 10b
/* Store both phys and virt address for the uart */
98: add \rp, \rp, #0x48000000 @ phys base
str \rp, [\tmp, #0] @ omap_uart_phys
sub \rp, \rp, #0x48000000 @ phys base
add \rp, \rp, #0xfa000000 @ virt base
str \rp, [\tmp, #4] @ omap_uart_virt
mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
str \rp, [\tmp, #8] @ omap_uart_lsr
b 10b
.align
99: .word .
.word omap_uart_phys
.ltorg
100: /* Pass the UART_LSR reg address */
ldr \tmp, [\tmp, #8] @ omap_uart_lsr
add \rp, \rp, \tmp
add \rv, \rv, \tmp
.endm
.macro senduart,rd,rx
orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset
bic \rx, \rx, #0xff @ get base (THR) reg address
strb \rd, [\rx] @ send lower byte of rd
orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR)
bic \rd, \rd, #(0xff << 24) @ restore original rd
.endm
.macro busyuart,rd,rx
1001: ldrb \rd, [\rx] @ rx contains UART_LSR address
and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
bne 1001b
.endm
.macro waituart,rd,rx
.endm

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/* arch/arm/include/debug/pl01x.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/amba/serial.h>
#ifdef CONFIG_DEBUG_UART_PHYS
.macro addruart, rp, rv, tmp
ldr \rp, =CONFIG_DEBUG_UART_PHYS
ldr \rv, =CONFIG_DEBUG_UART_VIRT
.endm
#endif
.macro senduart,rd,rx
strb \rd, [\rx, #UART01x_DR]
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #UART01x_FR]
ARM_BE8( rev \rd, \rd )
tst \rd, #UART01x_FR_TXFF
bne 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #UART01x_FR]
ARM_BE8( rev \rd, \rd )
tst \rd, #UART01x_FR_BUSY
bne 1001b
.endm

46
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/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Copyright (C) 2005 Simtec Electronics
*
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/serial_s3c.h>
#define S3C2410_UART1_OFF (0x4000)
.macro addruart, rp, rv, tmp
ldr \rp, = CONFIG_DEBUG_UART_PHYS
ldr \rv, = CONFIG_DEBUG_UART_VIRT
.endm
.macro fifo_full_s3c2410 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
tst \rd, #S3C2410_UFSTAT_TXFULL
.endm
.macro fifo_level_s3c2410 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
and \rd, \rd, #S3C2410_UFSTAT_TXMASK
.endm
/* Select the correct implementation depending on the configuration. The
* S3C2440 will get selected by default, as these are the most widely
* used variants of these
*/
#if defined(CONFIG_DEBUG_S3C2410_UART)
#define fifo_full fifo_full_s3c2410
#define fifo_level fifo_level_s3c2410
#endif
/* include the reset of the code which will do the work */
#include <debug/samsung.S>

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/*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* pull in the relevant register and map files. */
#define S3C_ADDR_BASE 0xF6000000
#define S3C_VA_UART S3C_ADDR_BASE + 0x01000000
#define S5PV210_PA_UART 0xe2900000
/* note, for the boot process to work we have to keep the UART
* virtual address aligned to an 1MiB boundary for the L1
* mapping the head code makes. We keep the UART virtual address
* aligned and add in the offset when we load the value here.
*/
.macro addruart, rp, rv, tmp
ldr \rp, =S5PV210_PA_UART
ldr \rv, =S3C_VA_UART
#if CONFIG_DEBUG_S3C_UART != 0
add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
#endif
.endm
#define fifo_full fifo_full_s5pv210
#define fifo_level fifo_level_s5pv210
#include <debug/samsung.S>

87
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/* arch/arm/plat-samsung/include/plat/debug-macro.S
*
* Copyright 2005, 2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/serial_s3c.h>
/* The S5PV210/S5PC110 implementations are as belows. */
.macro fifo_level_s5pv210 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
and \rd, \rd, #S5PV210_UFSTAT_TXMASK
.endm
.macro fifo_full_s5pv210 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
tst \rd, #S5PV210_UFSTAT_TXFULL
.endm
/* The S3C2440 implementations are used by default as they are the
* most widely re-used */
.macro fifo_level_s3c2440 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
and \rd, \rd, #S3C2440_UFSTAT_TXMASK
.endm
#ifndef fifo_level
#define fifo_level fifo_level_s3c2440
#endif
.macro fifo_full_s3c2440 rd, rx
ldr \rd, [\rx, # S3C2410_UFSTAT]
tst \rd, #S3C2440_UFSTAT_TXFULL
.endm
#ifndef fifo_full
#define fifo_full fifo_full_s3c2440
#endif
.macro senduart,rd,rx
strb \rd, [\rx, # S3C2410_UTXH]
.endm
.macro busyuart, rd, rx
ldr \rd, [\rx, # S3C2410_UFCON]
tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
beq 1001f @
@ FIFO enabled...
1003:
fifo_full \rd, \rx
bne 1003b
b 1002f
1001:
@ busy waiting for non fifo
ldr \rd, [\rx, # S3C2410_UTRSTAT]
tst \rd, #S3C2410_UTRSTAT_TXFE
beq 1001b
1002: @ exit busyuart
.endm
.macro waituart,rd,rx
ldr \rd, [\rx, # S3C2410_UFCON]
tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
beq 1001f @
@ FIFO enabled...
1003:
fifo_level \rd, \rx
teq \rd, #0
bne 1003b
b 1002f
1001:
@ idle waiting for non fifo
ldr \rd, [\rx, # S3C2410_UTRSTAT]
tst \rd, #S3C2410_UTRSTAT_TXFE
beq 1001b
1002: @ exit busyuart
.endm

42
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/*
* arch/arm/mach-prima2/include/mach/debug-macro.S
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
#define SIRFSOC_UART1_PA_BASE 0xb0060000
#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
#define SIRFSOC_UART1_PA_BASE 0xcc060000
#else
#define SIRFSOC_UART1_PA_BASE 0
#endif
#define SIRFSOC_UART1_VA_BASE 0xFEC60000
#define SIRFSOC_UART_TXFIFO_STATUS 0x0114
#define SIRFSOC_UART_TXFIFO_DATA 0x0118
#define SIRFSOC_UART1_TXFIFO_FULL (1 << 5)
#define SIRFSOC_UART1_TXFIFO_EMPTY (1 << 6)
.macro addruart, rp, rv, tmp
ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical
ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual
.endm
.macro senduart,rd,rx
str \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA]
.endm
.macro busyuart,rd,rx
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS]
tst \rd, #SIRFSOC_UART1_TXFIFO_EMPTY
beq 1001b
.endm

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/*
* arch/arm/include/debug/sti.S
*
* Debugging macro include header
* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define STIH41X_COMMS_BASE 0xfed00000
#define STIH41X_ASC2_BASE (STIH41X_COMMS_BASE+0x32000)
#define STIH41X_SBC_LPM_BASE 0xfe400000
#define STIH41X_SBC_COMMS_BASE (STIH41X_SBC_LPM_BASE + 0x100000)
#define STIH41X_SBC_ASC1_BASE (STIH41X_SBC_COMMS_BASE + 0x31000)
#define VIRT_ADDRESS(x) (x - 0x1000000)
#if IS_ENABLED(CONFIG_STIH41X_DEBUG_ASC2)
#define DEBUG_LL_UART_BASE STIH41X_ASC2_BASE
#endif
#if IS_ENABLED(CONFIG_STIH41X_DEBUG_SBC_ASC1)
#define DEBUG_LL_UART_BASE STIH41X_SBC_ASC1_BASE
#endif
#ifndef DEBUG_LL_UART_BASE
#error "DEBUG UART is not Configured"
#endif
#define ASC_TX_BUF_OFF 0x04
#define ASC_CTRL_OFF 0x0c
#define ASC_STA_OFF 0x14
#define ASC_STA_TX_FULL (1<<9)
#define ASC_STA_TX_EMPTY (1<<1)
.macro addruart, rp, rv, tmp
ldr \rp, =DEBUG_LL_UART_BASE @ physical base
ldr \rv, =VIRT_ADDRESS(DEBUG_LL_UART_BASE) @ virt base
.endm
.macro senduart,rd,rx
strb \rd, [\rx, #ASC_TX_BUF_OFF]
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #ASC_STA_OFF]
tst \rd, #ASC_STA_TX_FULL
bne 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #ASC_STA_OFF]
tst \rd, #ASC_STA_TX_EMPTY
beq 1001b
.endm

226
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/*
* Copyright (C) 2010,2011 Google, Inc.
* Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
*
* Author:
* Colin Cross <ccross@google.com>
* Erik Gilling <konkers@google.com>
* Doug Anderson <dianders@chromium.org>
* Stephen Warren <swarren@nvidia.com>
*
* Portions based on mach-omap2's debug-macro.S
* Copyright (C) 1994-1999 Russell King
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/serial_reg.h>
#define UART_SHIFT 2
/* Physical addresses */
#define TEGRA_CLK_RESET_BASE 0x60006000
#define TEGRA_APB_MISC_BASE 0x70000000
#define TEGRA_UARTA_BASE 0x70006000
#define TEGRA_UARTB_BASE 0x70006040
#define TEGRA_UARTC_BASE 0x70006200
#define TEGRA_UARTD_BASE 0x70006300
#define TEGRA_UARTE_BASE 0x70006400
#define TEGRA_PMC_BASE 0x7000e400
#define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04)
#define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08)
#define TEGRA_CLK_RST_DEVICES_U (TEGRA_CLK_RESET_BASE + 0x0c)
#define TEGRA_CLK_OUT_ENB_L (TEGRA_CLK_RESET_BASE + 0x10)
#define TEGRA_CLK_OUT_ENB_H (TEGRA_CLK_RESET_BASE + 0x14)
#define TEGRA_CLK_OUT_ENB_U (TEGRA_CLK_RESET_BASE + 0x18)
#define TEGRA_PMC_SCRATCH20 (TEGRA_PMC_BASE + 0xa0)
#define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804)
/*
* Must be section-aligned since a section mapping is used early on.
* Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
*/
#define UART_VIRTUAL_BASE 0xfe800000
#define checkuart(rp, rv, lhu, bit, uart) \
/* Load address of CLK_RST register */ \
ldr rp, =TEGRA_CLK_RST_DEVICES_##lhu ; \
/* Load value from CLK_RST register */ \
ldr rp, [rp, #0] ; \
/* Test UART's reset bit */ \
tst rp, #(1 << bit) ; \
/* If set, can't use UART; jump to save no UART */ \
bne 90f ; \
/* Load address of CLK_OUT_ENB register */ \
ldr rp, =TEGRA_CLK_OUT_ENB_##lhu ; \
/* Load value from CLK_OUT_ENB register */ \
ldr rp, [rp, #0] ; \
/* Test UART's clock enable bit */ \
tst rp, #(1 << bit) ; \
/* If clear, can't use UART; jump to save no UART */ \
beq 90f ; \
/* Passed all tests, load address of UART registers */ \
ldr rp, =TEGRA_UART##uart##_BASE ; \
/* Jump to save UART address */ \
b 91f
.macro addruart, rp, rv, tmp
adr \rp, 99f @ actual addr of 99f
ldr \rv, [\rp] @ linked addr is stored there
sub \rv, \rv, \rp @ offset between the two
ldr \rp, [\rp, #4] @ linked tegra_uart_config
sub \tmp, \rp, \rv @ actual tegra_uart_config
ldr \rp, [\tmp] @ Load tegra_uart_config
cmp \rp, #1 @ needs initialization?
bne 100f @ no; go load the addresses
mov \rv, #0 @ yes; record init is done
str \rv, [\tmp]
#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
/* Check ODMDATA */
10: ldr \rp, =TEGRA_PMC_SCRATCH20
ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20
lsr \rv, \rp, #18 @ 19:18 are console type
and \rv, \rv, #3
cmp \rv, #2 @ 2 and 3 mean DCC, UART
beq 11f @ some boards swap the meaning
cmp \rv, #3 @ so accept either
bne 90f
11: lsr \rv, \rp, #15 @ 17:15 are UART ID
and \rv, #7
cmp \rv, #0 @ UART 0?
beq 20f
cmp \rv, #1 @ UART 1?
beq 21f
cmp \rv, #2 @ UART 2?
beq 22f
cmp \rv, #3 @ UART 3?
beq 23f
cmp \rv, #4 @ UART 4?
beq 24f
b 90f @ invalid
#endif
#if defined(CONFIG_TEGRA_DEBUG_UARTA) || \
defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
/* Check UART A validity */
20: checkuart(\rp, \rv, L, 6, A)
#endif
#if defined(CONFIG_TEGRA_DEBUG_UARTB) || \
defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
/* Check UART B validity */
21: checkuart(\rp, \rv, L, 7, B)
#endif
#if defined(CONFIG_TEGRA_DEBUG_UARTC) || \
defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
/* Check UART C validity */
22: checkuart(\rp, \rv, H, 23, C)
#endif
#if defined(CONFIG_TEGRA_DEBUG_UARTD) || \
defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
/* Check UART D validity */
23: checkuart(\rp, \rv, U, 1, D)
#endif
#if defined(CONFIG_TEGRA_DEBUG_UARTE) || \
defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
/* Check UART E validity */
24:
checkuart(\rp, \rv, U, 2, E)
#endif
/* No valid UART found */
90: mov \rp, #0
/* fall through */
/* Record whichever UART we chose */
91: str \rp, [\tmp, #4] @ Store in tegra_uart_phys
cmp \rp, #0 @ Valid UART address?
bne 92f @ Yes, go process it
str \rp, [\tmp, #8] @ Store 0 in tegra_uart_virt
b 100f @ Done
92: and \rv, \rp, #0xffffff @ offset within 1MB section
add \rv, \rv, #UART_VIRTUAL_BASE
str \rv, [\tmp, #8] @ Store in tegra_uart_virt
b 100f
.align
99: .word .
.word tegra_uart_config
.ltorg
/* Load previously selected UART address */
100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
.endm
/*
* Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
* check to make sure that the UART address is actually valid.
*/
.macro senduart, rd, rx
cmp \rx, #0
strneb \rd, [\rx, #UART_TX << UART_SHIFT]
1001:
.endm
.macro busyuart, rd, rx
cmp \rx, #0
beq 1002f
1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
and \rd, \rd, #UART_LSR_THRE
teq \rd, #UART_LSR_THRE
bne 1001b
1002:
.endm
.macro waituart, rd, rx
#ifdef FLOW_CONTROL
cmp \rx, #0
beq 1002f
1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
tst \rd, #UART_MSR_CTS
beq 1001b
1002:
#endif
.endm
/*
* Storage for the state maintained by the macros above.
*
* In the kernel proper, this data is located in arch/arm/mach-tegra/tegra.c.
* That's because this header is included from multiple files, and we only
* want a single copy of the data. In particular, the UART probing code above
* assumes it's running using physical addresses. This is true when this file
* is included from head.o, but not when included from debug.o. So we need
* to share the probe results between the two copies, rather than having
* to re-run the probing again later.
*
* In the decompressor, we put the symbol/storage right here, since common.c
* isn't included in the decompressor build. This symbol gets put in .text
* even though it's really data, since .data is discarded from the
* decompressor. Luckily, .text is writeable in the decompressor, unless
* CONFIG_ZBOOT_ROM. That dependency is handled in arch/arm/Kconfig.debug.
*/
#if defined(ZIMAGE)
tegra_uart_config:
/* Debug UART initialization required */
.word 1
/* Debug UART physical address */
.word 0
/* Debug UART virtual address */
.word 0
#endif

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#ifdef CONFIG_DEBUG_UNCOMPRESS
extern void putc(int c);
#else
static inline void putc(int c) {}
#endif
static inline void flush(void) {}
static inline void arch_decomp_setup(void) {}

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/*
* Debugging macro include header
*
* Copyright (C) 2009 ST-Ericsson
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#if CONFIG_UX500_DEBUG_UART > 2
#error Invalid Ux500 debug UART
#endif
/*
* DEBUG_LL only works if only one SOC is built in. We don't use #else below
* in order to get "__UX500_UART redefined" warnings if more than one SOC is
* built, so that there's some hint during the build that something is wrong.
*/
#ifdef CONFIG_UX500_SOC_DB8500
#define U8500_UART0_PHYS_BASE (0x80120000)
#define U8500_UART1_PHYS_BASE (0x80121000)
#define U8500_UART2_PHYS_BASE (0x80007000)
#define U8500_UART0_VIRT_BASE (0xf8120000)
#define U8500_UART1_VIRT_BASE (0xf8121000)
#define U8500_UART2_VIRT_BASE (0xf8007000)
#define __UX500_PHYS_UART(n) U8500_UART##n##_PHYS_BASE
#define __UX500_VIRT_UART(n) U8500_UART##n##_VIRT_BASE
#endif
#if !defined(__UX500_PHYS_UART) || !defined(__UX500_VIRT_UART)
#error Unknown SOC
#endif
#define UX500_PHYS_UART(n) __UX500_PHYS_UART(n)
#define UX500_VIRT_UART(n) __UX500_VIRT_UART(n)
#define UART_PHYS_BASE UX500_PHYS_UART(CONFIG_UX500_DEBUG_UART)
#define UART_VIRT_BASE UX500_VIRT_UART(CONFIG_UX500_DEBUG_UART)
.macro addruart, rp, rv, tmp
ldr \rp, =UART_PHYS_BASE @ no, physical address
ldr \rv, =UART_VIRT_BASE @ yes, virtual address
.endm
#include <debug/pl01x.S>

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/* arch/arm/mach-realview/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define DEBUG_LL_PHYS_BASE 0x10000000
#define DEBUG_LL_UART_OFFSET 0x00009000
#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
#define DEBUG_LL_UART_OFFSET_RS1 0x00090000
#define DEBUG_LL_UART_PHYS_CRX 0xb0090000
#define DEBUG_LL_VIRT_BASE 0xf8000000
#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
.macro addruart,rp,rv,tmp
.arch armv7-a
@ Make an educated guess regarding the memory map:
@ - the original A9 core tile (based on ARM Cortex-A9 r0p1)
@ should use UART at 0x10009000
@ - all other (RS1 complaint) tiles use UART mapped
@ at 0x1c090000
mrc p15, 0, \rp, c0, c0, 0
movw \rv, #0xc091
movt \rv, #0x410f
cmp \rp, \rv
@ Original memory map
moveq \rp, #DEBUG_LL_UART_OFFSET
orreq \rv, \rp, #DEBUG_LL_VIRT_BASE
orreq \rp, \rp, #DEBUG_LL_PHYS_BASE
@ RS1 memory map
movne \rp, #DEBUG_LL_UART_OFFSET_RS1
orrne \rv, \rp, #DEBUG_LL_VIRT_BASE
orrne \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
.endm
#include <debug/pl01x.S>
#endif

37
arch/arm/include/debug/vf.S Normal file
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/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#define VF_UART0_BASE_ADDR 0x40027000
#define VF_UART1_BASE_ADDR 0x40028000
#define VF_UART2_BASE_ADDR 0x40029000
#define VF_UART3_BASE_ADDR 0x4002a000
#define VF_UART_BASE_ADDR(n) VF_UART##n##_BASE_ADDR
#define VF_UART_BASE(n) VF_UART_BASE_ADDR(n)
#define VF_UART_PHYSICAL_BASE VF_UART_BASE(CONFIG_DEBUG_VF_UART_PORT)
#define VF_UART_VIRTUAL_BASE 0xfe000000
.macro addruart, rp, rv, tmp
ldr \rp, =VF_UART_PHYSICAL_BASE @ physical
and \rv, \rp, #0xffffff @ offset within 16MB section
add \rv, \rv, #VF_UART_VIRTUAL_BASE
.endm
.macro senduart, rd, rx
strb \rd, [\rx, #0x7] @ Data Register
.endm
.macro busyuart, rd, rx
1001: ldrb \rd, [\rx, #0x4] @ Status Register 1
tst \rd, #1 << 6 @ TC
beq 1001b @ wait until transmit done
.endm
.macro waituart,rd,rx
.endm

37
arch/arm/include/debug/vt8500.S Normal file
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/*
* Debugging macro include header
*
* Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
* Moved from arch/arm/mach-vt8500/include/mach/debug-macro.S
* Minor changes for readability.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define DEBUG_LL_PHYS_BASE 0xD8000000
#define DEBUG_LL_VIRT_BASE 0xF8000000
#define DEBUG_LL_UART_OFFSET 0x00200000
#if defined(CONFIG_DEBUG_VT8500_UART0)
.macro addruart, rp, rv, tmp
mov \rp, #DEBUG_LL_UART_OFFSET
orr \rv, \rp, #DEBUG_LL_VIRT_BASE
orr \rp, \rp, #DEBUG_LL_PHYS_BASE
.endm
.macro senduart,rd,rx
strb \rd, [\rx, #0]
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #0x1c]
ands \rd, \rd, #0x2
bne 1001b
.endm
.macro waituart,rd,rx
.endm
#endif

56
arch/arm/include/debug/zynq.S Normal file
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/*
* Debugging macro include header
*
* Copyright (C) 2011 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */
#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */
#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */
#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
#define UART0_PHYS 0xE0000000
#define UART0_VIRT 0xF0000000
#define UART1_PHYS 0xE0001000
#define UART1_VIRT 0xF0001000
#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
# define LL_UART_PADDR UART1_PHYS
# define LL_UART_VADDR UART1_VIRT
#else
# define LL_UART_PADDR UART0_PHYS
# define LL_UART_VADDR UART0_VIRT
#endif
.macro addruart, rp, rv, tmp
ldr \rp, =LL_UART_PADDR @ physical
ldr \rv, =LL_UART_VADDR @ virtual
.endm
.macro senduart,rd,rx
str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #UART_SR_OFFSET]
ARM_BE8( rev \rd, \rd )
tst \rd, #UART_SR_TXEMPTY
beq 1001b
.endm
.macro busyuart,rd,rx
1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
ARM_BE8( rev \rd, \rd )
tst \rd, #UART_SR_TXFULL @
bne 1002b @ wait if FIFO is full
.endm