mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-09 01:28:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
57
arch/arm/mach-dove/include/mach/bridge-regs.h
Normal file
57
arch/arm/mach-dove/include/mach/bridge-regs.h
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@ -0,0 +1,57 @@
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/*
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* arch/arm/mach-dove/include/mach/bridge-regs.h
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*
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* Mbus-L to Mbus Bridge Registers
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_BRIDGE_REGS_H
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#define __ASM_ARCH_BRIDGE_REGS_H
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#include <mach/dove.h>
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#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000)
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#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
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#define CPU_CTRL_PCIE0_LINK 0x00000001
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#define CPU_RESET 0x00000002
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#define CPU_CTRL_PCIE1_LINK 0x00000008
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
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#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
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#define SOFT_RESET 0x00000001
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#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
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#define IRQ_CAUSE_LOW_OFF 0x0000
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#define IRQ_MASK_LOW_OFF 0x0004
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#define FIQ_MASK_LOW_OFF 0x0008
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#define ENDPOINT_MASK_LOW_OFF 0x000c
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#define IRQ_CAUSE_HIGH_OFF 0x0010
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#define IRQ_MASK_HIGH_OFF 0x0014
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#define FIQ_MASK_HIGH_OFF 0x0018
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#define ENDPOINT_MASK_HIGH_OFF 0x001c
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#define PCIE_INTERRUPT_MASK_OFF 0x0020
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#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)
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#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)
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#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)
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#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)
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#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)
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#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
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#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
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#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c)
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
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#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
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#endif
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190
arch/arm/mach-dove/include/mach/dove.h
Normal file
190
arch/arm/mach-dove/include/mach/dove.h
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@ -0,0 +1,190 @@
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/*
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* arch/arm/mach-dove/include/mach/dove.h
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*
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* Generic definitions for Marvell Dove 88AP510 SoC
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_DOVE_H
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#define __ASM_ARCH_DOVE_H
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/*
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* Marvell Dove address maps.
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*
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* phys virt size
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* c8000000 fdb00000 1M Cryptographic SRAM
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* e0000000 @runtime 128M PCIe-0 Memory space
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* e8000000 @runtime 128M PCIe-1 Memory space
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* f1000000 fde00000 8M on-chip south-bridge registers
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* f1800000 fe600000 8M on-chip north-bridge registers
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* f2000000 fee00000 1M PCIe-0 I/O space
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* f2100000 fef00000 1M PCIe-1 I/O space
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*/
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#define DOVE_CESA_PHYS_BASE 0xc8000000
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#define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
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#define DOVE_CESA_SIZE SZ_1M
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#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
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#define DOVE_PCIE0_MEM_SIZE SZ_128M
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#define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
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#define DOVE_PCIE1_MEM_SIZE SZ_128M
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#define DOVE_BOOTROM_PHYS_BASE 0xf8000000
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#define DOVE_BOOTROM_SIZE SZ_128M
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#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
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#define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
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#define DOVE_SCRATCHPAD_SIZE SZ_1M
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#define DOVE_SB_REGS_PHYS_BASE 0xf1000000
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#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000)
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#define DOVE_SB_REGS_SIZE SZ_8M
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#define DOVE_NB_REGS_PHYS_BASE 0xf1800000
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#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe600000)
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#define DOVE_NB_REGS_SIZE SZ_8M
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#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
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#define DOVE_PCIE0_IO_BUS_BASE 0x00000000
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#define DOVE_PCIE0_IO_SIZE SZ_64K
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#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000
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#define DOVE_PCIE1_IO_BUS_BASE 0x00010000
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#define DOVE_PCIE1_IO_SIZE SZ_64K
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/*
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* Dove Core Registers Map
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*/
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/* SPI, I2C, UART */
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#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000)
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#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000)
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#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000)
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#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100)
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#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100)
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#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200)
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#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200)
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#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300)
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#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300)
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#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600)
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#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600)
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/* North-South Bridge */
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#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000)
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#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000)
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#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE)
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#define BRIDGE_WINS_SZ (0x80)
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/* Cryptographic Engine */
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#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000)
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/* PCIe 0 */
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#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000)
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/* USB */
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#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000)
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#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000)
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/* XOR 0 Engine */
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#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800)
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#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800)
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#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00)
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#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00)
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/* XOR 1 Engine */
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#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900)
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#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900)
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#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00)
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#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00)
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/* Gigabit Ethernet */
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#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000)
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/* PCIe 1 */
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#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000)
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/* CAFE */
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#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000)
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#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000)
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#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000)
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#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000)
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/* SATA */
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#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000)
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/* I2S/SPDIF */
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#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000)
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#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000)
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/* NAND Flash Controller */
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#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000)
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/* MPP, GPIO, Reset Sampling */
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#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
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#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
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#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014)
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#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018)
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#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
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#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420)
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#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
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#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
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#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
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#define DOVE_NAND_GPIO_EN (1 << 0)
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#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
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#define DOVE_SPI_GPIO_SEL (1 << 5)
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#define DOVE_UART1_GPIO_SEL (1 << 4)
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#define DOVE_AU1_GPIO_SEL (1 << 3)
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#define DOVE_CAM_GPIO_SEL (1 << 2)
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#define DOVE_SD1_GPIO_SEL (1 << 1)
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#define DOVE_SD0_GPIO_SEL (1 << 0)
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/* Power Management */
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#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000)
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#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c)
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/* Real Time Clock */
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#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500)
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/* AC97 */
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#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000)
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#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000)
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/* Peripheral DMA */
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#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000)
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#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000)
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#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
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#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7)
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#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
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#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20)
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#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21)
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#define DOVE_TWSI_OPTION3_GPIO (1 << 22)
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#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000)
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#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
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#define DOVE_SSP_ON_AU1 (1 << 0)
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#define DOVE_SSP_CLOCK_ENABLE (1 << 1)
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#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11)
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/* Memory Controller */
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#define DOVE_MC_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x00000)
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#define DOVE_MC_WINS_BASE (DOVE_MC_PHYS_BASE + 0x100)
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#define DOVE_MC_WINS_SZ (0x8)
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#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000)
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/* LCD Controller */
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#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
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#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000)
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#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
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#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000)
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/* Graphic Engine */
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#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000)
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/* Video Engine */
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#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000)
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|
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#endif
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33
arch/arm/mach-dove/include/mach/entry-macro.S
Normal file
33
arch/arm/mach-dove/include/mach/entry-macro.S
Normal file
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|
@ -0,0 +1,33 @@
|
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/*
|
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* arch/arm/mach-dove/include/mach/entry-macro.S
|
||||
*
|
||||
* Low-level IRQ helper macros for Marvell Dove platforms
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
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|
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#include <mach/bridge-regs.h>
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =IRQ_VIRT_BASE
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.endm
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||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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@ check low interrupts
|
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ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
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ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
|
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mov \irqnr, #31
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||||
ands \irqstat, \irqstat, \tmp
|
||||
|
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@ if no low interrupts set, check high interrupts
|
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ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
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ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF]
|
||||
moveq \irqnr, #63
|
||||
andeqs \irqstat, \irqstat, \tmp
|
||||
|
||||
@ find first active interrupt source
|
||||
clzne \irqstat, \irqstat
|
||||
subne \irqnr, \irqnr, \irqstat
|
||||
.endm
|
||||
19
arch/arm/mach-dove/include/mach/hardware.h
Normal file
19
arch/arm/mach-dove/include/mach/hardware.h
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* arch/arm/mach-dove/include/mach/hardware.h
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_HARDWARE_H
|
||||
#define __ASM_ARCH_HARDWARE_H
|
||||
|
||||
#include "dove.h"
|
||||
|
||||
/* Macros below are required for compatibility with PXA AC'97 driver. */
|
||||
#define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \
|
||||
DOVE_SB_REGS_VIRT_BASE)))
|
||||
#define __PREG(x) (((u32)&(x)) - DOVE_SB_REGS_VIRT_BASE + \
|
||||
DOVE_SB_REGS_PHYS_BASE)
|
||||
#endif
|
||||
96
arch/arm/mach-dove/include/mach/irqs.h
Normal file
96
arch/arm/mach-dove/include/mach/irqs.h
Normal file
|
|
@ -0,0 +1,96 @@
|
|||
/*
|
||||
* arch/arm/mach-dove/include/mach/irqs.h
|
||||
*
|
||||
* IRQ definitions for Marvell Dove 88AP510 SoC
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IRQS_H
|
||||
#define __ASM_ARCH_IRQS_H
|
||||
|
||||
/*
|
||||
* Dove Low Interrupt Controller
|
||||
*/
|
||||
#define IRQ_DOVE_BRIDGE 0
|
||||
#define IRQ_DOVE_H2C 1
|
||||
#define IRQ_DOVE_C2H 2
|
||||
#define IRQ_DOVE_NAND 3
|
||||
#define IRQ_DOVE_PDMA 4
|
||||
#define IRQ_DOVE_SPI1 5
|
||||
#define IRQ_DOVE_SPI0 6
|
||||
#define IRQ_DOVE_UART_0 7
|
||||
#define IRQ_DOVE_UART_1 8
|
||||
#define IRQ_DOVE_UART_2 9
|
||||
#define IRQ_DOVE_UART_3 10
|
||||
#define IRQ_DOVE_I2C 11
|
||||
#define IRQ_DOVE_GPIO_0_7 12
|
||||
#define IRQ_DOVE_GPIO_8_15 13
|
||||
#define IRQ_DOVE_GPIO_16_23 14
|
||||
#define IRQ_DOVE_PCIE0_ERR 15
|
||||
#define IRQ_DOVE_PCIE0 16
|
||||
#define IRQ_DOVE_PCIE1_ERR 17
|
||||
#define IRQ_DOVE_PCIE1 18
|
||||
#define IRQ_DOVE_I2S0 19
|
||||
#define IRQ_DOVE_I2S0_ERR 20
|
||||
#define IRQ_DOVE_I2S1 21
|
||||
#define IRQ_DOVE_I2S1_ERR 22
|
||||
#define IRQ_DOVE_USB_ERR 23
|
||||
#define IRQ_DOVE_USB0 24
|
||||
#define IRQ_DOVE_USB1 25
|
||||
#define IRQ_DOVE_GE00_RX 26
|
||||
#define IRQ_DOVE_GE00_TX 27
|
||||
#define IRQ_DOVE_GE00_MISC 28
|
||||
#define IRQ_DOVE_GE00_SUM 29
|
||||
#define IRQ_DOVE_GE00_ERR 30
|
||||
#define IRQ_DOVE_CRYPTO 31
|
||||
|
||||
/*
|
||||
* Dove High Interrupt Controller
|
||||
*/
|
||||
#define IRQ_DOVE_AC97 32
|
||||
#define IRQ_DOVE_PMU 33
|
||||
#define IRQ_DOVE_CAM 34
|
||||
#define IRQ_DOVE_SDIO0 35
|
||||
#define IRQ_DOVE_SDIO1 36
|
||||
#define IRQ_DOVE_SDIO0_WAKEUP 37
|
||||
#define IRQ_DOVE_SDIO1_WAKEUP 38
|
||||
#define IRQ_DOVE_XOR_00 39
|
||||
#define IRQ_DOVE_XOR_01 40
|
||||
#define IRQ_DOVE_XOR0_ERR 41
|
||||
#define IRQ_DOVE_XOR_10 42
|
||||
#define IRQ_DOVE_XOR_11 43
|
||||
#define IRQ_DOVE_XOR1_ERR 44
|
||||
#define IRQ_DOVE_LCD_DCON 45
|
||||
#define IRQ_DOVE_LCD1 46
|
||||
#define IRQ_DOVE_LCD0 47
|
||||
#define IRQ_DOVE_GPU 48
|
||||
#define IRQ_DOVE_PERFORM_MNTR 49
|
||||
#define IRQ_DOVE_VPRO_DMA1 51
|
||||
#define IRQ_DOVE_SSP_TIMER 54
|
||||
#define IRQ_DOVE_SSP 55
|
||||
#define IRQ_DOVE_MC_L2_ERR 56
|
||||
#define IRQ_DOVE_CRYPTO_ERR 59
|
||||
#define IRQ_DOVE_GPIO_24_31 60
|
||||
#define IRQ_DOVE_HIGH_GPIO 61
|
||||
#define IRQ_DOVE_SATA 62
|
||||
|
||||
/*
|
||||
* DOVE General Purpose Pins
|
||||
*/
|
||||
#define IRQ_DOVE_GPIO_START 64
|
||||
#define NR_GPIO_IRQS 64
|
||||
|
||||
/*
|
||||
* PMU interrupts
|
||||
*/
|
||||
#define IRQ_DOVE_PMU_START (IRQ_DOVE_GPIO_START + NR_GPIO_IRQS)
|
||||
#define NR_PMU_IRQS 7
|
||||
#define IRQ_DOVE_RTC (IRQ_DOVE_PMU_START + 5)
|
||||
|
||||
#define NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
|
||||
|
||||
|
||||
#endif
|
||||
72
arch/arm/mach-dove/include/mach/pm.h
Normal file
72
arch/arm/mach-dove/include/mach/pm.h
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* arch/arm/mach-dove/include/mach/pm.h
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_PM_H
|
||||
#define __ASM_ARCH_PM_H
|
||||
|
||||
#include <asm/errno.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)
|
||||
#define CLOCK_GATING_BIT_USB0 0
|
||||
#define CLOCK_GATING_BIT_USB1 1
|
||||
#define CLOCK_GATING_BIT_GBE 2
|
||||
#define CLOCK_GATING_BIT_SATA 3
|
||||
#define CLOCK_GATING_BIT_PCIE0 4
|
||||
#define CLOCK_GATING_BIT_PCIE1 5
|
||||
#define CLOCK_GATING_BIT_SDIO0 8
|
||||
#define CLOCK_GATING_BIT_SDIO1 9
|
||||
#define CLOCK_GATING_BIT_NAND 10
|
||||
#define CLOCK_GATING_BIT_CAMERA 11
|
||||
#define CLOCK_GATING_BIT_I2S0 12
|
||||
#define CLOCK_GATING_BIT_I2S1 13
|
||||
#define CLOCK_GATING_BIT_CRYPTO 15
|
||||
#define CLOCK_GATING_BIT_AC97 21
|
||||
#define CLOCK_GATING_BIT_PDMA 22
|
||||
#define CLOCK_GATING_BIT_XOR0 23
|
||||
#define CLOCK_GATING_BIT_XOR1 24
|
||||
#define CLOCK_GATING_BIT_GIGA_PHY 30
|
||||
#define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0)
|
||||
#define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1)
|
||||
#define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE)
|
||||
#define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA)
|
||||
#define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0)
|
||||
#define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1)
|
||||
#define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0)
|
||||
#define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1)
|
||||
#define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND)
|
||||
#define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA)
|
||||
#define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0)
|
||||
#define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1)
|
||||
#define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO)
|
||||
#define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97)
|
||||
#define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA)
|
||||
#define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0)
|
||||
#define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1)
|
||||
#define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY)
|
||||
|
||||
#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)
|
||||
#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54)
|
||||
|
||||
static inline int pmu_to_irq(int pin)
|
||||
{
|
||||
if (pin < NR_PMU_IRQS)
|
||||
return pin + IRQ_DOVE_PMU_START;
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int irq_to_pmu(int irq)
|
||||
{
|
||||
if (IRQ_DOVE_PMU_START <= irq && irq < NR_IRQS)
|
||||
return irq - IRQ_DOVE_PMU_START;
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
#endif
|
||||
36
arch/arm/mach-dove/include/mach/uncompress.h
Normal file
36
arch/arm/mach-dove/include/mach/uncompress.h
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* arch/arm/mach-dove/include/mach/uncompress.h
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <mach/dove.h>
|
||||
|
||||
#define UART_THR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x0))
|
||||
#define UART_LSR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x14))
|
||||
|
||||
#define LSR_THRE 0x20
|
||||
|
||||
static void putc(const char c)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 0x1000; i++) {
|
||||
/* Transmit fifo not full? */
|
||||
if (*UART_LSR & LSR_THRE)
|
||||
break;
|
||||
}
|
||||
|
||||
*UART_THR = c;
|
||||
}
|
||||
|
||||
static void flush(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* nothing to do
|
||||
*/
|
||||
#define arch_decomp_setup()
|
||||
Loading…
Add table
Add a link
Reference in a new issue