mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-30 15:48:52 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
41
arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
Normal file
41
arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
Normal file
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@ -0,0 +1,41 @@
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/*
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* arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
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*/
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#ifndef __ASM_ARCH_EP93XX_REGS_H
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#define __ASM_ARCH_EP93XX_REGS_H
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/*
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* EP93xx linux memory map:
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*
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* virt phys size
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* fe800000 5M per-platform mappings
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* fed00000 80800000 2M APB
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* fef00000 80000000 1M AHB
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*/
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#define EP93XX_AHB_PHYS_BASE 0x80000000
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#define EP93XX_AHB_VIRT_BASE 0xfef00000
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#define EP93XX_AHB_SIZE 0x00100000
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#define EP93XX_AHB_PHYS(x) (EP93XX_AHB_PHYS_BASE + (x))
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#define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x))
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#define EP93XX_APB_PHYS_BASE 0x80800000
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#define EP93XX_APB_VIRT_BASE 0xfed00000
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#define EP93XX_APB_SIZE 0x00200000
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#define EP93XX_APB_PHYS(x) (EP93XX_APB_PHYS_BASE + (x))
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#define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x))
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/* APB UARTs */
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#define EP93XX_UART1_PHYS_BASE EP93XX_APB_PHYS(0x000c0000)
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#define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000)
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#define EP93XX_UART2_PHYS_BASE EP93XX_APB_PHYS(0x000d0000)
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#define EP93XX_UART2_BASE EP93XX_APB_IOMEM(0x000d0000)
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#define EP93XX_UART3_PHYS_BASE EP93XX_APB_PHYS(0x000e0000)
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#define EP93XX_UART3_BASE EP93XX_APB_IOMEM(0x000e0000)
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#endif
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110
arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
Normal file
110
arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
Normal file
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@ -0,0 +1,110 @@
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/* Include file for the EP93XX GPIO controller machine specifics */
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#ifndef __GPIO_EP93XX_H
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#define __GPIO_EP93XX_H
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#include <mach/ep93xx-regs.h>
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#define EP93XX_GPIO_PHYS_BASE EP93XX_APB_PHYS(0x00040000)
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#define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000)
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#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x))
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#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c)
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#define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0)
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#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc)
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#define EP93XX_GPIO_EEDRIVE EP93XX_GPIO_REG(0xc8)
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/* GPIO port A. */
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#define EP93XX_GPIO_LINE_A(x) ((x) + 0)
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#define EP93XX_GPIO_LINE_EGPIO0 EP93XX_GPIO_LINE_A(0)
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#define EP93XX_GPIO_LINE_EGPIO1 EP93XX_GPIO_LINE_A(1)
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#define EP93XX_GPIO_LINE_EGPIO2 EP93XX_GPIO_LINE_A(2)
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#define EP93XX_GPIO_LINE_EGPIO3 EP93XX_GPIO_LINE_A(3)
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#define EP93XX_GPIO_LINE_EGPIO4 EP93XX_GPIO_LINE_A(4)
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#define EP93XX_GPIO_LINE_EGPIO5 EP93XX_GPIO_LINE_A(5)
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#define EP93XX_GPIO_LINE_EGPIO6 EP93XX_GPIO_LINE_A(6)
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#define EP93XX_GPIO_LINE_EGPIO7 EP93XX_GPIO_LINE_A(7)
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/* GPIO port B. */
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#define EP93XX_GPIO_LINE_B(x) ((x) + 8)
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#define EP93XX_GPIO_LINE_EGPIO8 EP93XX_GPIO_LINE_B(0)
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#define EP93XX_GPIO_LINE_EGPIO9 EP93XX_GPIO_LINE_B(1)
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#define EP93XX_GPIO_LINE_EGPIO10 EP93XX_GPIO_LINE_B(2)
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#define EP93XX_GPIO_LINE_EGPIO11 EP93XX_GPIO_LINE_B(3)
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#define EP93XX_GPIO_LINE_EGPIO12 EP93XX_GPIO_LINE_B(4)
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#define EP93XX_GPIO_LINE_EGPIO13 EP93XX_GPIO_LINE_B(5)
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#define EP93XX_GPIO_LINE_EGPIO14 EP93XX_GPIO_LINE_B(6)
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#define EP93XX_GPIO_LINE_EGPIO15 EP93XX_GPIO_LINE_B(7)
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/* GPIO port C. */
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#define EP93XX_GPIO_LINE_C(x) ((x) + 40)
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#define EP93XX_GPIO_LINE_ROW0 EP93XX_GPIO_LINE_C(0)
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#define EP93XX_GPIO_LINE_ROW1 EP93XX_GPIO_LINE_C(1)
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#define EP93XX_GPIO_LINE_ROW2 EP93XX_GPIO_LINE_C(2)
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#define EP93XX_GPIO_LINE_ROW3 EP93XX_GPIO_LINE_C(3)
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#define EP93XX_GPIO_LINE_ROW4 EP93XX_GPIO_LINE_C(4)
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#define EP93XX_GPIO_LINE_ROW5 EP93XX_GPIO_LINE_C(5)
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#define EP93XX_GPIO_LINE_ROW6 EP93XX_GPIO_LINE_C(6)
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#define EP93XX_GPIO_LINE_ROW7 EP93XX_GPIO_LINE_C(7)
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/* GPIO port D. */
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#define EP93XX_GPIO_LINE_D(x) ((x) + 24)
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#define EP93XX_GPIO_LINE_COL0 EP93XX_GPIO_LINE_D(0)
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#define EP93XX_GPIO_LINE_COL1 EP93XX_GPIO_LINE_D(1)
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#define EP93XX_GPIO_LINE_COL2 EP93XX_GPIO_LINE_D(2)
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#define EP93XX_GPIO_LINE_COL3 EP93XX_GPIO_LINE_D(3)
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#define EP93XX_GPIO_LINE_COL4 EP93XX_GPIO_LINE_D(4)
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#define EP93XX_GPIO_LINE_COL5 EP93XX_GPIO_LINE_D(5)
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#define EP93XX_GPIO_LINE_COL6 EP93XX_GPIO_LINE_D(6)
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#define EP93XX_GPIO_LINE_COL7 EP93XX_GPIO_LINE_D(7)
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/* GPIO port E. */
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#define EP93XX_GPIO_LINE_E(x) ((x) + 32)
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#define EP93XX_GPIO_LINE_GRLED EP93XX_GPIO_LINE_E(0)
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#define EP93XX_GPIO_LINE_RDLED EP93XX_GPIO_LINE_E(1)
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#define EP93XX_GPIO_LINE_DIORn EP93XX_GPIO_LINE_E(2)
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#define EP93XX_GPIO_LINE_IDECS1n EP93XX_GPIO_LINE_E(3)
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#define EP93XX_GPIO_LINE_IDECS2n EP93XX_GPIO_LINE_E(4)
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#define EP93XX_GPIO_LINE_IDEDA0 EP93XX_GPIO_LINE_E(5)
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#define EP93XX_GPIO_LINE_IDEDA1 EP93XX_GPIO_LINE_E(6)
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#define EP93XX_GPIO_LINE_IDEDA2 EP93XX_GPIO_LINE_E(7)
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/* GPIO port F. */
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#define EP93XX_GPIO_LINE_F(x) ((x) + 16)
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#define EP93XX_GPIO_LINE_WP EP93XX_GPIO_LINE_F(0)
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#define EP93XX_GPIO_LINE_MCCD1 EP93XX_GPIO_LINE_F(1)
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#define EP93XX_GPIO_LINE_MCCD2 EP93XX_GPIO_LINE_F(2)
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#define EP93XX_GPIO_LINE_MCBVD1 EP93XX_GPIO_LINE_F(3)
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#define EP93XX_GPIO_LINE_MCBVD2 EP93XX_GPIO_LINE_F(4)
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#define EP93XX_GPIO_LINE_VS1 EP93XX_GPIO_LINE_F(5)
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#define EP93XX_GPIO_LINE_READY EP93XX_GPIO_LINE_F(6)
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#define EP93XX_GPIO_LINE_VS2 EP93XX_GPIO_LINE_F(7)
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/* GPIO port G. */
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#define EP93XX_GPIO_LINE_G(x) ((x) + 48)
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#define EP93XX_GPIO_LINE_EECLK EP93XX_GPIO_LINE_G(0)
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#define EP93XX_GPIO_LINE_EEDAT EP93XX_GPIO_LINE_G(1)
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#define EP93XX_GPIO_LINE_SLA0 EP93XX_GPIO_LINE_G(2)
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#define EP93XX_GPIO_LINE_SLA1 EP93XX_GPIO_LINE_G(3)
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#define EP93XX_GPIO_LINE_DD12 EP93XX_GPIO_LINE_G(4)
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#define EP93XX_GPIO_LINE_DD13 EP93XX_GPIO_LINE_G(5)
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#define EP93XX_GPIO_LINE_DD14 EP93XX_GPIO_LINE_G(6)
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#define EP93XX_GPIO_LINE_DD15 EP93XX_GPIO_LINE_G(7)
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/* GPIO port H. */
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#define EP93XX_GPIO_LINE_H(x) ((x) + 56)
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#define EP93XX_GPIO_LINE_DD0 EP93XX_GPIO_LINE_H(0)
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#define EP93XX_GPIO_LINE_DD1 EP93XX_GPIO_LINE_H(1)
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#define EP93XX_GPIO_LINE_DD2 EP93XX_GPIO_LINE_H(2)
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#define EP93XX_GPIO_LINE_DD3 EP93XX_GPIO_LINE_H(3)
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#define EP93XX_GPIO_LINE_DD4 EP93XX_GPIO_LINE_H(4)
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#define EP93XX_GPIO_LINE_DD5 EP93XX_GPIO_LINE_H(5)
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#define EP93XX_GPIO_LINE_DD6 EP93XX_GPIO_LINE_H(6)
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#define EP93XX_GPIO_LINE_DD7 EP93XX_GPIO_LINE_H(7)
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/* maximum value for gpio line identifiers */
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#define EP93XX_GPIO_LINE_MAX EP93XX_GPIO_LINE_H(7)
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/* maximum value for irq capable line identifiers */
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#define EP93XX_GPIO_LINE_MAX_IRQ EP93XX_GPIO_LINE_F(7)
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#endif /* __GPIO_EP93XX_H */
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24
arch/arm/mach-ep93xx/include/mach/hardware.h
Normal file
24
arch/arm/mach-ep93xx/include/mach/hardware.h
Normal file
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@ -0,0 +1,24 @@
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/*
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* arch/arm/mach-ep93xx/include/mach/hardware.h
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <mach/platform.h>
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/*
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* The EP93xx has two external crystal oscillators. To generate the
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* required high-frequency clocks, the processor uses two phase-locked-
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* loops (PLLs) to multiply the incoming external clock signal to much
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* higher frequencies that are then divided down by programmable dividers
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* to produce the needed clocks. The PLLs operate independently of one
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* another.
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*/
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#define EP93XX_EXT_CLK_RATE 14745600
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#define EP93XX_EXT_RTC_RATE 32768
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#define EP93XX_KEYTCHCLK_DIV4 (EP93XX_EXT_CLK_RATE / 4)
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#define EP93XX_KEYTCHCLK_DIV16 (EP93XX_EXT_CLK_RATE / 16)
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#endif
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78
arch/arm/mach-ep93xx/include/mach/irqs.h
Normal file
78
arch/arm/mach-ep93xx/include/mach/irqs.h
Normal file
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@ -0,0 +1,78 @@
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/*
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* arch/arm/mach-ep93xx/include/mach/irqs.h
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*/
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#ifndef __ASM_ARCH_IRQS_H
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#define __ASM_ARCH_IRQS_H
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#define IRQ_EP93XX_COMMRX 2
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#define IRQ_EP93XX_COMMTX 3
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#define IRQ_EP93XX_TIMER1 4
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#define IRQ_EP93XX_TIMER2 5
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#define IRQ_EP93XX_AACINTR 6
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#define IRQ_EP93XX_DMAM2P0 7
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#define IRQ_EP93XX_DMAM2P1 8
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#define IRQ_EP93XX_DMAM2P2 9
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#define IRQ_EP93XX_DMAM2P3 10
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#define IRQ_EP93XX_DMAM2P4 11
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#define IRQ_EP93XX_DMAM2P5 12
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#define IRQ_EP93XX_DMAM2P6 13
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#define IRQ_EP93XX_DMAM2P7 14
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#define IRQ_EP93XX_DMAM2P8 15
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#define IRQ_EP93XX_DMAM2P9 16
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#define IRQ_EP93XX_DMAM2M0 17
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#define IRQ_EP93XX_DMAM2M1 18
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#define IRQ_EP93XX_GPIO0MUX 19
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#define IRQ_EP93XX_GPIO1MUX 20
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#define IRQ_EP93XX_GPIO2MUX 21
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#define IRQ_EP93XX_GPIO3MUX 22
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#define IRQ_EP93XX_UART1RX 23
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#define IRQ_EP93XX_UART1TX 24
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#define IRQ_EP93XX_UART2RX 25
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#define IRQ_EP93XX_UART2TX 26
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#define IRQ_EP93XX_UART3RX 27
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#define IRQ_EP93XX_UART3TX 28
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#define IRQ_EP93XX_KEY 29
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#define IRQ_EP93XX_TOUCH 30
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#define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc
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#define IRQ_EP93XX_EXT0 32
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#define IRQ_EP93XX_EXT1 33
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#define IRQ_EP93XX_EXT2 34
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#define IRQ_EP93XX_64HZ 35
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#define IRQ_EP93XX_WATCHDOG 36
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#define IRQ_EP93XX_RTC 37
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#define IRQ_EP93XX_IRDA 38
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#define IRQ_EP93XX_ETHERNET 39
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#define IRQ_EP93XX_EXT3 40
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#define IRQ_EP93XX_PROG 41
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#define IRQ_EP93XX_1HZ 42
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#define IRQ_EP93XX_VSYNC 43
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#define IRQ_EP93XX_VIDEO_FIFO 44
|
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#define IRQ_EP93XX_SSP1RX 45
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#define IRQ_EP93XX_SSP1TX 46
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#define IRQ_EP93XX_GPIO4MUX 47
|
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#define IRQ_EP93XX_GPIO5MUX 48
|
||||
#define IRQ_EP93XX_GPIO6MUX 49
|
||||
#define IRQ_EP93XX_GPIO7MUX 50
|
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#define IRQ_EP93XX_TIMER3 51
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#define IRQ_EP93XX_UART1 52
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#define IRQ_EP93XX_SSP 53
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#define IRQ_EP93XX_UART2 54
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#define IRQ_EP93XX_UART3 55
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#define IRQ_EP93XX_USB 56
|
||||
#define IRQ_EP93XX_ETHERNET_PME 57
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||||
#define IRQ_EP93XX_DSP 58
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#define IRQ_EP93XX_GPIO_AB 59
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#define IRQ_EP93XX_SAI 60
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#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff
|
||||
|
||||
#define NR_EP93XX_IRQS (64 + 24)
|
||||
|
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#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x))
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#define EP93XX_BOARD_IRQS 32
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|
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#define NR_IRQS (NR_EP93XX_IRQS + EP93XX_BOARD_IRQS)
|
||||
|
||||
|
||||
#endif
|
||||
70
arch/arm/mach-ep93xx/include/mach/platform.h
Normal file
70
arch/arm/mach-ep93xx/include/mach/platform.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* arch/arm/mach-ep93xx/include/mach/platform.h
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/reboot.h>
|
||||
|
||||
struct device;
|
||||
struct i2c_gpio_platform_data;
|
||||
struct i2c_board_info;
|
||||
struct spi_board_info;
|
||||
struct platform_device;
|
||||
struct ep93xxfb_mach_info;
|
||||
struct ep93xx_keypad_platform_data;
|
||||
struct ep93xx_spi_info;
|
||||
|
||||
struct ep93xx_eth_data
|
||||
{
|
||||
unsigned char dev_addr[6];
|
||||
unsigned char phy_id;
|
||||
};
|
||||
|
||||
void ep93xx_map_io(void);
|
||||
void ep93xx_init_irq(void);
|
||||
|
||||
#define EP93XX_CHIP_REV_D0 3
|
||||
#define EP93XX_CHIP_REV_D1 4
|
||||
#define EP93XX_CHIP_REV_E0 5
|
||||
#define EP93XX_CHIP_REV_E1 6
|
||||
#define EP93XX_CHIP_REV_E2 7
|
||||
|
||||
unsigned int ep93xx_chip_revision(void);
|
||||
|
||||
void ep93xx_register_flash(unsigned int width,
|
||||
resource_size_t start, resource_size_t size);
|
||||
|
||||
void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr);
|
||||
void ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
|
||||
struct i2c_board_info *devices, int num);
|
||||
void ep93xx_register_spi(struct ep93xx_spi_info *info,
|
||||
struct spi_board_info *devices, int num);
|
||||
void ep93xx_register_fb(struct ep93xxfb_mach_info *data);
|
||||
void ep93xx_register_pwm(int pwm0, int pwm1);
|
||||
int ep93xx_pwm_acquire_gpio(struct platform_device *pdev);
|
||||
void ep93xx_pwm_release_gpio(struct platform_device *pdev);
|
||||
void ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data);
|
||||
int ep93xx_keypad_acquire_gpio(struct platform_device *pdev);
|
||||
void ep93xx_keypad_release_gpio(struct platform_device *pdev);
|
||||
void ep93xx_register_i2s(void);
|
||||
int ep93xx_i2s_acquire(void);
|
||||
void ep93xx_i2s_release(void);
|
||||
void ep93xx_register_ac97(void);
|
||||
void ep93xx_register_ide(void);
|
||||
int ep93xx_ide_acquire_gpio(struct platform_device *pdev);
|
||||
void ep93xx_ide_release_gpio(struct platform_device *pdev);
|
||||
|
||||
struct device *ep93xx_init_devices(void);
|
||||
extern void ep93xx_timer_init(void);
|
||||
|
||||
void ep93xx_restart(enum reboot_mode, const char *);
|
||||
void ep93xx_init_late(void);
|
||||
|
||||
#ifdef CONFIG_CRUNCH
|
||||
int crunch_init(void);
|
||||
#else
|
||||
static inline int crunch_init(void) { return 0; }
|
||||
#endif
|
||||
|
||||
#endif
|
||||
82
arch/arm/mach-ep93xx/include/mach/uncompress.h
Normal file
82
arch/arm/mach-ep93xx/include/mach/uncompress.h
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* arch/arm/mach-ep93xx/include/mach/uncompress.h
|
||||
*
|
||||
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or (at
|
||||
* your option) any later version.
|
||||
*/
|
||||
|
||||
#include <mach/ep93xx-regs.h>
|
||||
|
||||
static unsigned char __raw_readb(unsigned int ptr)
|
||||
{
|
||||
return *((volatile unsigned char *)ptr);
|
||||
}
|
||||
|
||||
static unsigned int __raw_readl(unsigned int ptr)
|
||||
{
|
||||
return *((volatile unsigned int *)ptr);
|
||||
}
|
||||
|
||||
static void __raw_writeb(unsigned char value, unsigned int ptr)
|
||||
{
|
||||
*((volatile unsigned char *)ptr) = value;
|
||||
}
|
||||
|
||||
static void __raw_writel(unsigned int value, unsigned int ptr)
|
||||
{
|
||||
*((volatile unsigned int *)ptr) = value;
|
||||
}
|
||||
|
||||
#define PHYS_UART_DATA (CONFIG_DEBUG_UART_PHYS + 0x00)
|
||||
#define PHYS_UART_FLAG (CONFIG_DEBUG_UART_PHYS + 0x18)
|
||||
#define UART_FLAG_TXFF 0x20
|
||||
|
||||
static inline void putc(int c)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 10000; i++) {
|
||||
/* Transmit fifo not full? */
|
||||
if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF))
|
||||
break;
|
||||
}
|
||||
|
||||
__raw_writeb(c, PHYS_UART_DATA);
|
||||
}
|
||||
|
||||
static inline void flush(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Some bootloaders don't turn off DMA from the ethernet MAC before
|
||||
* jumping to linux, which means that we might end up with bits of RX
|
||||
* status and packet data scribbled over the uncompressed kernel image.
|
||||
* Work around this by resetting the ethernet MAC before we uncompress.
|
||||
*/
|
||||
#define PHYS_ETH_SELF_CTL 0x80010020
|
||||
#define ETH_SELF_CTL_RESET 0x00000001
|
||||
|
||||
static void ethernet_reset(void)
|
||||
{
|
||||
unsigned int v;
|
||||
|
||||
/* Reset the ethernet MAC. */
|
||||
v = __raw_readl(PHYS_ETH_SELF_CTL);
|
||||
__raw_writel(v | ETH_SELF_CTL_RESET, PHYS_ETH_SELF_CTL);
|
||||
|
||||
/* Wait for reset to finish. */
|
||||
while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET)
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
static void arch_decomp_setup(void)
|
||||
{
|
||||
ethernet_reset();
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue