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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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21
arch/arm/mach-iop33x/Kconfig Normal file
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if ARCH_IOP33X
menu "IOP33x Implementation Options"
comment "IOP33x Platform Types"
config ARCH_IQ80331
bool "Enable support for IQ80331"
help
Say Y here if you want to run your kernel on the Intel IQ80331
evaluation kit for the IOP331 chipset.
config MACH_IQ80332
bool "Enable support for IQ80332"
help
Say Y here if you want to run your kernel on the Intel IQ80332
evaluation kit for the IOP332 chipset.
endmenu
endif

8
arch/arm/mach-iop33x/Makefile Normal file
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#
# Makefile for the linux kernel.
#
obj-y := irq.o uart.o
obj-$(CONFIG_ARCH_IQ80331) += iq80331.o
obj-$(CONFIG_MACH_IQ80332) += iq80332.o

3
arch/arm/mach-iop33x/Makefile.boot Normal file
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zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000

5
arch/arm/mach-iop33x/include/mach/adma.h Normal file
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#ifndef IOP33X_ADMA_H
#define IOP33X_ADMA_H
#include <asm/hardware/iop3xx-adma.h>
#endif

34
arch/arm/mach-iop33x/include/mach/entry-macro.S Normal file
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/*
* arch/arm/mach-iop33x/include/mach/entry-macro.S
*
* Low-level IRQ helper macros for IOP33x-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <mach/iop33x.h>
.macro get_irqnr_preamble, base, tmp
mrc p15, 0, \tmp, c15, c1, 0
orr \tmp, \tmp, #(1 << 6)
mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
mrc p15, 0, \tmp, c15, c1, 0
mov \tmp, \tmp
sub pc, pc, #4 @ cp_wait
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mrc p6, 0, \irqstat, c14, c0, 0 @ Read IINTVEC
cmp \irqstat, #0
mrceq p6, 0, \irqstat, c14, c0, 0 @ erratum 63 workaround
adds \irqnr, \irqstat, #1
movne \irqnr, \irqstat, lsr #2
.endm
.macro arch_ret_to_user, tmp1, tmp2
mrc p15, 0, \tmp1, c15, c1, 0
ands \tmp2, \tmp1, #(1 << 6)
bicne \tmp1, \tmp1, #(1 << 6)
mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
.endm

43
arch/arm/mach-iop33x/include/mach/hardware.h Normal file
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/*
* arch/arm/mach-iop33x/include/mach/hardware.h
*/
#ifndef __HARDWARE_H
#define __HARDWARE_H
#include <asm/types.h>
/*
* Note about PCI IO space mappings
*
* To make IO space accesses efficient, we store virtual addresses in
* the IO resources.
*
* The PCI IO space is located at virtual 0xfe000000 from physical
* 0x90000000. The PCI BARs must be programmed with physical addresses,
* but when we read them, we convert them to virtual addresses. See
* arch/arm/mach-iop3xx/iop3xx-pci.c
*/
#ifndef __ASSEMBLY__
void iop33x_init_irq(void);
extern struct platform_device iop33x_uart0_device;
extern struct platform_device iop33x_uart1_device;
#endif
/*
* Generic chipset bits
*
*/
#include "iop33x.h"
/*
* Board specific bits
*/
#include "iq80331.h"
#include "iq80332.h"
#endif

40
arch/arm/mach-iop33x/include/mach/iop33x.h Normal file
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/*
* arch/arm/mach-iop33x/include/mach/iop33x.h
*
* Intel IOP33X Chip definitions
*
* Author: Dave Jiang (dave.jiang@intel.com)
* Copyright (C) 2003, 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __IOP33X_H
#define __IOP33X_H
/*
* Peripherals that are shared between the iop32x and iop33x but
* located at different addresses.
*/
#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg))
#include <asm/hardware/iop3xx.h>
/* UARTs */
#define IOP33X_UART0_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1700)
#define IOP33X_UART0_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1700)
#define IOP33X_UART1_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740)
#define IOP33X_UART1_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740)
/* ATU Parameters
* set up a 1:1 bus to physical ram relationship
* w/ pci on top of physical ram in memory map
*/
#define IOP33X_MAX_RAM_SIZE 0x80000000UL
#define IOP3XX_MAX_RAM_SIZE IOP33X_MAX_RAM_SIZE
#define IOP3XX_PCI_LOWER_MEM_BA (PHYS_OFFSET + IOP33X_MAX_RAM_SIZE)
#endif

16
arch/arm/mach-iop33x/include/mach/iq80331.h Normal file
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/*
* arch/arm/mach-iop33x/include/mach/iq80331.h
*
* Intel IQ80331 evaluation board registers
*/
#ifndef __IQ80331_H
#define __IQ80331_H
#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */
#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */
#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */
#endif

16
arch/arm/mach-iop33x/include/mach/iq80332.h Normal file
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/*
* arch/arm/mach-iop33x/include/mach/iq80332.h
*
* Intel IQ80332 evaluation board registers
*/
#ifndef __IQ80332_H
#define __IQ80332_H
#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */
#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
#define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */
#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */
#endif

60
arch/arm/mach-iop33x/include/mach/irqs.h Normal file
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/*
* arch/arm/mach-iop33x/include/mach/irqs.h
*
* Author: Dave Jiang (dave.jiang@intel.com)
* Copyright: (C) 2003 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __IRQS_H
#define __IRQS_H
/*
* IOP80331 chipset interrupts
*/
#define IRQ_IOP33X_DMA0_EOT 0
#define IRQ_IOP33X_DMA0_EOC 1
#define IRQ_IOP33X_DMA1_EOT 2
#define IRQ_IOP33X_DMA1_EOC 3
#define IRQ_IOP33X_AA_EOT 6
#define IRQ_IOP33X_AA_EOC 7
#define IRQ_IOP33X_TIMER0 8
#define IRQ_IOP33X_TIMER1 9
#define IRQ_IOP33X_I2C_0 10
#define IRQ_IOP33X_I2C_1 11
#define IRQ_IOP33X_MSG 12
#define IRQ_IOP33X_MSGIBQ 13
#define IRQ_IOP33X_ATU_BIST 14
#define IRQ_IOP33X_PERFMON 15
#define IRQ_IOP33X_CORE_PMU 16
#define IRQ_IOP33X_XINT0 24
#define IRQ_IOP33X_XINT1 25
#define IRQ_IOP33X_XINT2 26
#define IRQ_IOP33X_XINT3 27
#define IRQ_IOP33X_XINT8 32
#define IRQ_IOP33X_XINT9 33
#define IRQ_IOP33X_XINT10 34
#define IRQ_IOP33X_XINT11 35
#define IRQ_IOP33X_XINT12 36
#define IRQ_IOP33X_XINT13 37
#define IRQ_IOP33X_XINT14 38
#define IRQ_IOP33X_XINT15 39
#define IRQ_IOP33X_UART0 51
#define IRQ_IOP33X_UART1 52
#define IRQ_IOP33X_PBIE 53
#define IRQ_IOP33X_ATU_CRW 54
#define IRQ_IOP33X_ATU_ERR 55
#define IRQ_IOP33X_MCU_ERR 56
#define IRQ_IOP33X_DMA0_ERR 57
#define IRQ_IOP33X_DMA1_ERR 58
#define IRQ_IOP33X_AA_ERR 60
#define IRQ_IOP33X_MSG_ERR 62
#define IRQ_IOP33X_HPI 63
#define NR_IRQS 64
#endif

4
arch/arm/mach-iop33x/include/mach/time.h Normal file
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#ifndef _IOP33X_TIME_H_
#define _IOP33X_TIME_H_
#define IRQ_IOP_TIMER0 IRQ_IOP33X_TIMER0
#endif

36
arch/arm/mach-iop33x/include/mach/uncompress.h Normal file
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/*
* arch/arm/mach-iop33x/include/mach/uncompress.h
*/
#include <asm/types.h>
#include <asm/mach-types.h>
#include <linux/serial_reg.h>
#include <mach/hardware.h>
volatile u32 *uart_base;
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
static inline void putc(char c)
{
while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
barrier();
uart_base[UART_TX] = c;
}
static inline void flush(void)
{
}
static __inline__ void __arch_decomp_setup(unsigned long arch_id)
{
if (machine_is_iq80331() || machine_is_iq80332())
uart_base = (volatile u32 *)IOP33X_UART0_PHYS;
else
uart_base = (volatile u32 *)0xfe800000;
}
/*
* nothing to do
*/
#define arch_decomp_setup() __arch_decomp_setup(arch_id)

152
arch/arm/mach-iop33x/iq80331.c Normal file
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/*
* arch/arm/mach-iop33x/iq80331.c
*
* Board support code for the Intel IQ80331 platform.
*
* Author: Dave Jiang <dave.jiang@intel.com>
* Copyright (C) 2003 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/pci.h>
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <mach/time.h>
/*
* IQ80331 timer tick configuration.
*/
static void __init iq80331_timer_init(void)
{
/* D-Step parts run at a higher internal bus frequency */
if (*IOP3XX_ATURID >= 0xa)
iop_init_time(333000000);
else
iop_init_time(266000000);
}
/*
* IQ80331 PCI.
*/
static int __init
iq80331_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
if (slot == 1 && pin == 1) {
/* PCI-X Slot INTA */
irq = IRQ_IOP33X_XINT1;
} else if (slot == 1 && pin == 2) {
/* PCI-X Slot INTB */
irq = IRQ_IOP33X_XINT2;
} else if (slot == 1 && pin == 3) {
/* PCI-X Slot INTC */
irq = IRQ_IOP33X_XINT3;
} else if (slot == 1 && pin == 4) {
/* PCI-X Slot INTD */
irq = IRQ_IOP33X_XINT0;
} else if (slot == 2) {
/* GigE */
irq = IRQ_IOP33X_XINT2;
} else {
printk(KERN_ERR "iq80331_pci_map_irq() called for unknown "
"device PCI:%d:%d:%d\n", dev->bus->number,
PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
irq = -1;
}
return irq;
}
static struct hw_pci iq80331_pci __initdata = {
.nr_controllers = 1,
.ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit_cond,
.map_irq = iq80331_pci_map_irq,
};
static int __init iq80331_pci_init(void)
{
if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) &&
machine_is_iq80331())
pci_common_init(&iq80331_pci);
return 0;
}
subsys_initcall(iq80331_pci_init);
/*
* IQ80331 machine initialisation.
*/
static struct physmap_flash_data iq80331_flash_data = {
.width = 1,
};
static struct resource iq80331_flash_resource = {
.start = 0xc0000000,
.end = 0xc07fffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device iq80331_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &iq80331_flash_data,
},
.num_resources = 1,
.resource = &iq80331_flash_resource,
};
static struct resource iq80331_gpio_res[] = {
DEFINE_RES_MEM((IOP3XX_PERIPHERAL_PHYS_BASE + 0x1780), 0x10),
};
static void __init iq80331_init_machine(void)
{
platform_device_register_simple("gpio-iop", 0,
iq80331_gpio_res,
ARRAY_SIZE(iq80331_gpio_res));
platform_device_register(&iop3xx_i2c0_device);
platform_device_register(&iop3xx_i2c1_device);
platform_device_register(&iop33x_uart0_device);
platform_device_register(&iop33x_uart1_device);
platform_device_register(&iq80331_flash_device);
platform_device_register(&iop3xx_dma_0_channel);
platform_device_register(&iop3xx_dma_1_channel);
platform_device_register(&iop3xx_aau_channel);
}
MACHINE_START(IQ80331, "Intel IQ80331")
/* Maintainer: Intel Corp. */
.atag_offset = 0x100,
.map_io = iop3xx_map_io,
.init_irq = iop33x_init_irq,
.init_time = iq80331_timer_init,
.init_machine = iq80331_init_machine,
.restart = iop3xx_restart,
MACHINE_END

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arch/arm/mach-iop33x/iq80332.c Normal file
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/*
* arch/arm/mach-iop33x/iq80332.c
*
* Board support code for the Intel IQ80332 platform.
*
* Author: Dave Jiang <dave.jiang@intel.com>
* Copyright (C) 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/pci.h>
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <mach/time.h>
/*
* IQ80332 timer tick configuration.
*/
static void __init iq80332_timer_init(void)
{
/* D-Step parts and the iop333 run at a higher internal bus frequency */
if (*IOP3XX_ATURID >= 0xa || *IOP3XX_ATUDID == 0x374)
iop_init_time(333000000);
else
iop_init_time(266000000);
}
/*
* IQ80332 PCI.
*/
static int __init
iq80332_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
if (slot == 4 && pin == 1) {
/* PCI-X Slot INTA */
irq = IRQ_IOP33X_XINT0;
} else if (slot == 4 && pin == 2) {
/* PCI-X Slot INTB */
irq = IRQ_IOP33X_XINT1;
} else if (slot == 4 && pin == 3) {
/* PCI-X Slot INTC */
irq = IRQ_IOP33X_XINT2;
} else if (slot == 4 && pin == 4) {
/* PCI-X Slot INTD */
irq = IRQ_IOP33X_XINT3;
} else if (slot == 6) {
/* GigE */
irq = IRQ_IOP33X_XINT2;
} else {
printk(KERN_ERR "iq80332_pci_map_irq() called for unknown "
"device PCI:%d:%d:%d\n", dev->bus->number,
PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
irq = -1;
}
return irq;
}
static struct hw_pci iq80332_pci __initdata = {
.nr_controllers = 1,
.ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit_cond,
.map_irq = iq80332_pci_map_irq,
};
static int __init iq80332_pci_init(void)
{
if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) &&
machine_is_iq80332())
pci_common_init(&iq80332_pci);
return 0;
}
subsys_initcall(iq80332_pci_init);
/*
* IQ80332 machine initialisation.
*/
static struct physmap_flash_data iq80332_flash_data = {
.width = 1,
};
static struct resource iq80332_flash_resource = {
.start = 0xc0000000,
.end = 0xc07fffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device iq80332_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &iq80332_flash_data,
},
.num_resources = 1,
.resource = &iq80332_flash_resource,
};
static struct resource iq80332_gpio_res[] = {
DEFINE_RES_MEM((IOP3XX_PERIPHERAL_PHYS_BASE + 0x1780), 0x10),
};
static void __init iq80332_init_machine(void)
{
platform_device_register_simple("gpio-iop", 0,
iq80332_gpio_res,
ARRAY_SIZE(iq80332_gpio_res));
platform_device_register(&iop3xx_i2c0_device);
platform_device_register(&iop3xx_i2c1_device);
platform_device_register(&iop33x_uart0_device);
platform_device_register(&iop33x_uart1_device);
platform_device_register(&iq80332_flash_device);
platform_device_register(&iop3xx_dma_0_channel);
platform_device_register(&iop3xx_dma_1_channel);
platform_device_register(&iop3xx_aau_channel);
}
MACHINE_START(IQ80332, "Intel IQ80332")
/* Maintainer: Intel Corp. */
.atag_offset = 0x100,
.map_io = iop3xx_map_io,
.init_irq = iop33x_init_irq,
.init_time = iq80332_timer_init,
.init_machine = iq80332_init_machine,
.restart = iop3xx_restart,
MACHINE_END

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arch/arm/mach-iop33x/irq.c Normal file
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/*
* arch/arm/mach-iop33x/irq.c
*
* Generic IOP331 IRQ handling functionality
*
* Author: Dave Jiang <dave.jiang@intel.com>
* Copyright (C) 2003 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
static u32 iop33x_mask0;
static u32 iop33x_mask1;
static void intctl0_write(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
}
static void intctl1_write(u32 val)
{
asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
}
static void intstr0_write(u32 val)
{
asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
}
static void intstr1_write(u32 val)
{
asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
}
static void intbase_write(u32 val)
{
asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
}
static void intsize_write(u32 val)
{
asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
}
static void
iop33x_irq_mask1 (struct irq_data *d)
{
iop33x_mask0 &= ~(1 << d->irq);
intctl0_write(iop33x_mask0);
}
static void
iop33x_irq_mask2 (struct irq_data *d)
{
iop33x_mask1 &= ~(1 << (d->irq - 32));
intctl1_write(iop33x_mask1);
}
static void
iop33x_irq_unmask1(struct irq_data *d)
{
iop33x_mask0 |= 1 << d->irq;
intctl0_write(iop33x_mask0);
}
static void
iop33x_irq_unmask2(struct irq_data *d)
{
iop33x_mask1 |= (1 << (d->irq - 32));
intctl1_write(iop33x_mask1);
}
struct irq_chip iop33x_irqchip1 = {
.name = "IOP33x-1",
.irq_ack = iop33x_irq_mask1,
.irq_mask = iop33x_irq_mask1,
.irq_unmask = iop33x_irq_unmask1,
};
struct irq_chip iop33x_irqchip2 = {
.name = "IOP33x-2",
.irq_ack = iop33x_irq_mask2,
.irq_mask = iop33x_irq_mask2,
.irq_unmask = iop33x_irq_unmask2,
};
void __init iop33x_init_irq(void)
{
int i;
iop_init_cp6_handler();
intctl0_write(0);
intctl1_write(0);
intstr0_write(0);
intstr1_write(0);
intbase_write(0);
intsize_write(1);
if (machine_is_iq80331())
*IOP3XX_PCIIRSR = 0x0f;
for (i = 0; i < NR_IRQS; i++) {
irq_set_chip_and_handler(i,
(i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2,
handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}

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arch/arm/mach-iop33x/uart.c Normal file
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/*
* arch/arm/mach-iop33x/uart.c
*
* Author: Dave Jiang (dave.jiang@intel.com)
* Copyright (C) 2004 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/major.h>
#include <linux/fs.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <linux/io.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <mach/hardware.h>
#include <asm/hardware/iop3xx.h>
#include <asm/mach/arch.h>
#define IOP33X_UART_XTAL 33334000
static struct plat_serial8250_port iop33x_uart0_data[] = {
{
.membase = (char *)IOP33X_UART0_VIRT,
.mapbase = IOP33X_UART0_PHYS,
.irq = IRQ_IOP33X_UART0,
.uartclk = IOP33X_UART_XTAL,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_SKIP_TEST,
},
{ },
};
static struct resource iop33x_uart0_resources[] = {
[0] = {
.start = IOP33X_UART0_PHYS,
.end = IOP33X_UART0_PHYS + 0x3f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP33X_UART0,
.end = IRQ_IOP33X_UART0,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device iop33x_uart0_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = iop33x_uart0_data,
},
.num_resources = 2,
.resource = iop33x_uart0_resources,
};
static struct resource iop33x_uart1_resources[] = {
[0] = {
.start = IOP33X_UART1_PHYS,
.end = IOP33X_UART1_PHYS + 0x3f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP33X_UART1,
.end = IRQ_IOP33X_UART1,
.flags = IORESOURCE_IRQ,
},
};
static struct plat_serial8250_port iop33x_uart1_data[] = {
{
.membase = (char *)IOP33X_UART1_VIRT,
.mapbase = IOP33X_UART1_PHYS,
.irq = IRQ_IOP33X_UART1,
.uartclk = IOP33X_UART_XTAL,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_SKIP_TEST,
},
{ },
};
struct platform_device iop33x_uart1_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM1,
.dev = {
.platform_data = iop33x_uart1_data,
},
.num_resources = 2,
.resource = iop33x_uart1_resources,
};