mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 01:12:45 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
58
arch/arm/mach-ixp4xx/include/mach/cpu.h
Normal file
58
arch/arm/mach-ixp4xx/include/mach/cpu.h
Normal file
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|
@ -0,0 +1,58 @@
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|||
/*
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* arch/arm/mach-ixp4xx/include/mach/cpu.h
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*
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* IXP4XX cpu type detection
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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||||
*
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||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
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*
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*/
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#ifndef __ASM_ARCH_CPU_H__
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#define __ASM_ARCH_CPU_H__
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#include <linux/io.h>
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#include <asm/cputype.h>
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/* Processor id value in CP15 Register 0 */
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#define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */
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#define IXP42X_PROCESSOR_ID_MASK 0xffffffc0
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#define IXP43X_PROCESSOR_ID_VALUE 0x69054040
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#define IXP43X_PROCESSOR_ID_MASK 0xfffffff0
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#define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */
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#define IXP46X_PROCESSOR_ID_MASK 0xfffffff0
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#define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \
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IXP42X_PROCESSOR_ID_VALUE)
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#define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \
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IXP42X_PROCESSOR_ID_VALUE)
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#define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \
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IXP43X_PROCESSOR_ID_VALUE)
|
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#define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \
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IXP46X_PROCESSOR_ID_VALUE)
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static inline u32 ixp4xx_read_feature_bits(void)
|
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{
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u32 val = ~__raw_readl(IXP4XX_EXP_CFG2);
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if (cpu_is_ixp42x_rev_a0())
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return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
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IXP4XX_FEATURE_AES);
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if (cpu_is_ixp42x())
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return val & IXP42X_FEATURE_MASK;
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if (cpu_is_ixp43x())
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return val & IXP43X_FEATURE_MASK;
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return val & IXP46X_FEATURE_MASK;
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}
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static inline void ixp4xx_write_feature_bits(u32 value)
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{
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__raw_writel(~value, IXP4XX_EXP_CFG2);
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}
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#endif /* _ASM_ARCH_CPU_H */
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41
arch/arm/mach-ixp4xx/include/mach/entry-macro.S
Normal file
41
arch/arm/mach-ixp4xx/include/mach/entry-macro.S
Normal file
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@ -0,0 +1,41 @@
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/*
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* arch/arm/mach-ixp4xx/include/mach/entry-macro.S
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*
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* Low-level IRQ helper macros for IXP4xx-based platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/hardware.h>
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
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ldr \irqstat, [\irqstat] @ get interrupts
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cmp \irqstat, #0
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beq 1001f @ upper IRQ?
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clz \irqnr, \irqstat
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mov \base, #31
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sub \irqnr, \base, \irqnr
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b 1002f @ lower IRQ being
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@ handled
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1001:
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/*
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* IXP465/IXP435 has an upper IRQ status register
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*/
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#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
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ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
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ldr \irqstat, [\irqstat] @ get upper interrupts
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mov \irqnr, #63
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clz \irqstat, \irqstat
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cmp \irqstat, #32
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subne \irqnr, \irqnr, \irqstat
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#endif
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1002:
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.endm
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36
arch/arm/mach-ixp4xx/include/mach/hardware.h
Normal file
36
arch/arm/mach-ixp4xx/include/mach/hardware.h
Normal file
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|
@ -0,0 +1,36 @@
|
|||
/*
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* arch/arm/mach-ixp4xx/include/mach/hardware.h
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*
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* Copyright (C) 2002 Intel Corporation.
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* Copyright (C) 2003-2004 MontaVista Software, Inc.
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*
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||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
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||||
*/
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|
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/*
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* Hardware definitions for IXP4xx based systems
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*/
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#ifndef __ASM_ARCH_HARDWARE_H__
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#define __ASM_ARCH_HARDWARE_H__
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#ifdef CONFIG_IXP4XX_INDIRECT_PCI
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#define PCIBIOS_MAX_MEM 0x4FFFFFFF
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#else
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#define PCIBIOS_MAX_MEM 0x4BFFFFFF
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#endif
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/* Register locations and bits */
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#include "ixp4xx-regs.h"
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#ifndef __ASSEMBLER__
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#include <mach/cpu.h>
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#endif
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/* Platform helper functions and definitions */
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#include "platform.h"
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#endif /* _ASM_ARCH_HARDWARE_H */
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503
arch/arm/mach-ixp4xx/include/mach/io.h
Normal file
503
arch/arm/mach-ixp4xx/include/mach/io.h
Normal file
|
|
@ -0,0 +1,503 @@
|
|||
/*
|
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* arch/arm/mach-ixp4xx/include/mach/io.h
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*
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* Author: Deepak Saxena <dsaxena@plexity.net>
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*
|
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* Copyright (C) 2002-2005 MontaVista Software, Inc.
|
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*
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||||
* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
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#ifndef __ASM_ARM_ARCH_IO_H
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#define __ASM_ARM_ARCH_IO_H
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#include <linux/bitops.h>
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||||
#include <mach/hardware.h>
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|
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extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
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extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
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/*
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* IXP4xx provides two methods of accessing PCI memory space:
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*
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* 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB).
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* To access PCI via this space, we simply ioremap() the BAR
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* into the kernel and we can use the standard read[bwl]/write[bwl]
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* macros. This is the preffered method due to speed but it
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* limits the system to just 64MB of PCI memory. This can be
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* problematic if using video cards and other memory-heavy targets.
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*
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* 2) If > 64MB of memory space is required, the IXP4xx can use indirect
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||||
* registers to access the whole 4 GB of PCI memory space (as we do below
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||||
* for I/O transactions). This allows currently for up to 1 GB (0x10000000
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* to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that
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* every PCI access requires three local register accesses plus a spinlock,
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* but in some cases the performance hit is acceptable. In addition, you
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* cannot mmap() PCI devices in this case.
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*/
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#ifdef CONFIG_IXP4XX_INDIRECT_PCI
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/*
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* In the case of using indirect PCI, we simply return the actual PCI
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* address and our read/write implementation use that to drive the
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* access registers. If something outside of PCI is ioremap'd, we
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* fallback to the default.
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*/
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extern unsigned long pcibios_min_mem;
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static inline int is_pci_memory(u32 addr)
|
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{
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return (addr >= pcibios_min_mem) && (addr <= 0x4FFFFFFF);
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}
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#define writeb(v, p) __indirect_writeb(v, p)
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#define writew(v, p) __indirect_writew(v, p)
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#define writel(v, p) __indirect_writel(v, p)
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#define writesb(p, v, l) __indirect_writesb(p, v, l)
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#define writesw(p, v, l) __indirect_writesw(p, v, l)
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#define writesl(p, v, l) __indirect_writesl(p, v, l)
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#define readb(p) __indirect_readb(p)
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#define readw(p) __indirect_readw(p)
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#define readl(p) __indirect_readl(p)
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#define readsb(p, v, l) __indirect_readsb(p, v, l)
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#define readsw(p, v, l) __indirect_readsw(p, v, l)
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#define readsl(p, v, l) __indirect_readsl(p, v, l)
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static inline void __indirect_writeb(u8 value, volatile void __iomem *p)
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{
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u32 addr = (u32)p;
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u32 n, byte_enables, data;
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|
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if (!is_pci_memory(addr)) {
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__raw_writeb(value, p);
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return;
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}
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n = addr % 4;
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byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
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data = value << (8*n);
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ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
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}
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static inline void __indirect_writesb(volatile void __iomem *bus_addr,
|
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const u8 *vaddr, int count)
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{
|
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while (count--)
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writeb(*vaddr++, bus_addr);
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}
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|
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static inline void __indirect_writew(u16 value, volatile void __iomem *p)
|
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{
|
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u32 addr = (u32)p;
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u32 n, byte_enables, data;
|
||||
|
||||
if (!is_pci_memory(addr)) {
|
||||
__raw_writew(value, addr);
|
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return;
|
||||
}
|
||||
|
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n = addr % 4;
|
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byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
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data = value << (8*n);
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ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
|
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}
|
||||
|
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static inline void __indirect_writesw(volatile void __iomem *bus_addr,
|
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const u16 *vaddr, int count)
|
||||
{
|
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while (count--)
|
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writew(*vaddr++, bus_addr);
|
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}
|
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|
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static inline void __indirect_writel(u32 value, volatile void __iomem *p)
|
||||
{
|
||||
u32 addr = (__force u32)p;
|
||||
|
||||
if (!is_pci_memory(addr)) {
|
||||
__raw_writel(value, p);
|
||||
return;
|
||||
}
|
||||
|
||||
ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
|
||||
}
|
||||
|
||||
static inline void __indirect_writesl(volatile void __iomem *bus_addr,
|
||||
const u32 *vaddr, int count)
|
||||
{
|
||||
while (count--)
|
||||
writel(*vaddr++, bus_addr);
|
||||
}
|
||||
|
||||
static inline unsigned char __indirect_readb(const volatile void __iomem *p)
|
||||
{
|
||||
u32 addr = (u32)p;
|
||||
u32 n, byte_enables, data;
|
||||
|
||||
if (!is_pci_memory(addr))
|
||||
return __raw_readb(p);
|
||||
|
||||
n = addr % 4;
|
||||
byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
|
||||
if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
|
||||
return 0xff;
|
||||
|
||||
return data >> (8*n);
|
||||
}
|
||||
|
||||
static inline void __indirect_readsb(const volatile void __iomem *bus_addr,
|
||||
u8 *vaddr, u32 count)
|
||||
{
|
||||
while (count--)
|
||||
*vaddr++ = readb(bus_addr);
|
||||
}
|
||||
|
||||
static inline unsigned short __indirect_readw(const volatile void __iomem *p)
|
||||
{
|
||||
u32 addr = (u32)p;
|
||||
u32 n, byte_enables, data;
|
||||
|
||||
if (!is_pci_memory(addr))
|
||||
return __raw_readw(addr);
|
||||
|
||||
n = addr % 4;
|
||||
byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
|
||||
if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
|
||||
return 0xffff;
|
||||
|
||||
return data>>(8*n);
|
||||
}
|
||||
|
||||
static inline void __indirect_readsw(const volatile void __iomem *bus_addr,
|
||||
u16 *vaddr, u32 count)
|
||||
{
|
||||
while (count--)
|
||||
*vaddr++ = readw(bus_addr);
|
||||
}
|
||||
|
||||
static inline unsigned long __indirect_readl(const volatile void __iomem *p)
|
||||
{
|
||||
u32 addr = (__force u32)p;
|
||||
u32 data;
|
||||
|
||||
if (!is_pci_memory(addr))
|
||||
return __raw_readl(p);
|
||||
|
||||
if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
|
||||
return 0xffffffff;
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
|
||||
u32 *vaddr, u32 count)
|
||||
{
|
||||
while (count--)
|
||||
*vaddr++ = readl(bus_addr);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* We can use the built-in functions b/c they end up calling writeb/readb
|
||||
*/
|
||||
#define memset_io(c,v,l) _memset_io((c),(v),(l))
|
||||
#define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l))
|
||||
#define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l))
|
||||
|
||||
#endif /* CONFIG_IXP4XX_INDIRECT_PCI */
|
||||
|
||||
#ifndef CONFIG_PCI
|
||||
|
||||
#define __io(v) __typesafe_io(v)
|
||||
|
||||
#else
|
||||
|
||||
/*
|
||||
* IXP4xx does not have a transparent cpu -> PCI I/O translation
|
||||
* window. Instead, it has a set of registers that must be tweaked
|
||||
* with the proper byte lanes, command types, and address for the
|
||||
* transaction. This means that we need to override the default
|
||||
* I/O functions.
|
||||
*/
|
||||
|
||||
static inline void outb(u8 value, u32 addr)
|
||||
{
|
||||
u32 n, byte_enables, data;
|
||||
n = addr % 4;
|
||||
byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
|
||||
data = value << (8*n);
|
||||
ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
|
||||
}
|
||||
|
||||
static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count)
|
||||
{
|
||||
while (count--)
|
||||
outb(*vaddr++, io_addr);
|
||||
}
|
||||
|
||||
static inline void outw(u16 value, u32 addr)
|
||||
{
|
||||
u32 n, byte_enables, data;
|
||||
n = addr % 4;
|
||||
byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
|
||||
data = value << (8*n);
|
||||
ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
|
||||
}
|
||||
|
||||
static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count)
|
||||
{
|
||||
while (count--)
|
||||
outw(cpu_to_le16(*vaddr++), io_addr);
|
||||
}
|
||||
|
||||
static inline void outl(u32 value, u32 addr)
|
||||
{
|
||||
ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
|
||||
}
|
||||
|
||||
static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count)
|
||||
{
|
||||
while (count--)
|
||||
outl(cpu_to_le32(*vaddr++), io_addr);
|
||||
}
|
||||
|
||||
static inline u8 inb(u32 addr)
|
||||
{
|
||||
u32 n, byte_enables, data;
|
||||
n = addr % 4;
|
||||
byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
|
||||
if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
|
||||
return 0xff;
|
||||
|
||||
return data >> (8*n);
|
||||
}
|
||||
|
||||
static inline void insb(u32 io_addr, u8 *vaddr, u32 count)
|
||||
{
|
||||
while (count--)
|
||||
*vaddr++ = inb(io_addr);
|
||||
}
|
||||
|
||||
static inline u16 inw(u32 addr)
|
||||
{
|
||||
u32 n, byte_enables, data;
|
||||
n = addr % 4;
|
||||
byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
|
||||
if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
|
||||
return 0xffff;
|
||||
|
||||
return data>>(8*n);
|
||||
}
|
||||
|
||||
static inline void insw(u32 io_addr, u16 *vaddr, u32 count)
|
||||
{
|
||||
while (count--)
|
||||
*vaddr++ = le16_to_cpu(inw(io_addr));
|
||||
}
|
||||
|
||||
static inline u32 inl(u32 addr)
|
||||
{
|
||||
u32 data;
|
||||
if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
|
||||
return 0xffffffff;
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
static inline void insl(u32 io_addr, u32 *vaddr, u32 count)
|
||||
{
|
||||
while (count--)
|
||||
*vaddr++ = le32_to_cpu(inl(io_addr));
|
||||
}
|
||||
|
||||
#define PIO_OFFSET 0x10000UL
|
||||
#define PIO_MASK 0x0ffffUL
|
||||
|
||||
#define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \
|
||||
((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
|
||||
|
||||
#define ioread8(p) ioread8(p)
|
||||
static inline unsigned int ioread8(const void __iomem *addr)
|
||||
{
|
||||
unsigned long port = (unsigned long __force)addr;
|
||||
if (__is_io_address(port))
|
||||
return (unsigned int)inb(port & PIO_MASK);
|
||||
else
|
||||
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
||||
return (unsigned int)__raw_readb(addr);
|
||||
#else
|
||||
return (unsigned int)__indirect_readb(addr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#define ioread8_rep(p, v, c) ioread8_rep(p, v, c)
|
||||
static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
|
||||
{
|
||||
unsigned long port = (unsigned long __force)addr;
|
||||
if (__is_io_address(port))
|
||||
insb(port & PIO_MASK, vaddr, count);
|
||||
else
|
||||
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
||||
__raw_readsb(addr, vaddr, count);
|
||||
#else
|
||||
__indirect_readsb(addr, vaddr, count);
|
||||
#endif
|
||||
}
|
||||
|
||||
#define ioread16(p) ioread16(p)
|
||||
static inline unsigned int ioread16(const void __iomem *addr)
|
||||
{
|
||||
unsigned long port = (unsigned long __force)addr;
|
||||
if (__is_io_address(port))
|
||||
return (unsigned int)inw(port & PIO_MASK);
|
||||
else
|
||||
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
||||
return le16_to_cpu((__force __le16)__raw_readw(addr));
|
||||
#else
|
||||
return (unsigned int)__indirect_readw(addr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#define ioread16_rep(p, v, c) ioread16_rep(p, v, c)
|
||||
static inline void ioread16_rep(const void __iomem *addr, void *vaddr,
|
||||
u32 count)
|
||||
{
|
||||
unsigned long port = (unsigned long __force)addr;
|
||||
if (__is_io_address(port))
|
||||
insw(port & PIO_MASK, vaddr, count);
|
||||
else
|
||||
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
||||
__raw_readsw(addr, vaddr, count);
|
||||
#else
|
||||
__indirect_readsw(addr, vaddr, count);
|
||||
#endif
|
||||
}
|
||||
|
||||
#define ioread32(p) ioread32(p)
|
||||
static inline unsigned int ioread32(const void __iomem *addr)
|
||||
{
|
||||
unsigned long port = (unsigned long __force)addr;
|
||||
if (__is_io_address(port))
|
||||
return (unsigned int)inl(port & PIO_MASK);
|
||||
else {
|
||||
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
||||
return le32_to_cpu((__force __le32)__raw_readl(addr));
|
||||
#else
|
||||
return (unsigned int)__indirect_readl(addr);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
#define ioread32_rep(p, v, c) ioread32_rep(p, v, c)
|
||||
static inline void ioread32_rep(const void __iomem *addr, void *vaddr,
|
||||
u32 count)
|
||||
{
|
||||
unsigned long port = (unsigned long __force)addr;
|
||||
if (__is_io_address(port))
|
||||
insl(port & PIO_MASK, vaddr, count);
|
||||
else
|
||||
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
||||
__raw_readsl(addr, vaddr, count);
|
||||
#else
|
||||
__indirect_readsl(addr, vaddr, count);
|
||||
#endif
|
||||
}
|
||||
|
||||
#define iowrite8(v, p) iowrite8(v, p)
|
||||
static inline void iowrite8(u8 value, void __iomem *addr)
|
||||
{
|
||||
unsigned long port = (unsigned long __force)addr;
|
||||
if (__is_io_address(port))
|
||||
outb(value, port & PIO_MASK);
|
||||
else
|
||||
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
||||
__raw_writeb(value, addr);
|
||||
#else
|
||||
__indirect_writeb(value, addr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#define iowrite8_rep(p, v, c) iowrite8_rep(p, v, c)
|
||||
static inline void iowrite8_rep(void __iomem *addr, const void *vaddr,
|
||||
u32 count)
|
||||
{
|
||||
unsigned long port = (unsigned long __force)addr;
|
||||
if (__is_io_address(port))
|
||||
outsb(port & PIO_MASK, vaddr, count);
|
||||
else
|
||||
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
||||
__raw_writesb(addr, vaddr, count);
|
||||
#else
|
||||
__indirect_writesb(addr, vaddr, count);
|
||||
#endif
|
||||
}
|
||||
|
||||
#define iowrite16(v, p) iowrite16(v, p)
|
||||
static inline void iowrite16(u16 value, void __iomem *addr)
|
||||
{
|
||||
unsigned long port = (unsigned long __force)addr;
|
||||
if (__is_io_address(port))
|
||||
outw(value, port & PIO_MASK);
|
||||
else
|
||||
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
||||
__raw_writew(cpu_to_le16(value), addr);
|
||||
#else
|
||||
__indirect_writew(value, addr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c)
|
||||
static inline void iowrite16_rep(void __iomem *addr, const void *vaddr,
|
||||
u32 count)
|
||||
{
|
||||
unsigned long port = (unsigned long __force)addr;
|
||||
if (__is_io_address(port))
|
||||
outsw(port & PIO_MASK, vaddr, count);
|
||||
else
|
||||
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
||||
__raw_writesw(addr, vaddr, count);
|
||||
#else
|
||||
__indirect_writesw(addr, vaddr, count);
|
||||
#endif
|
||||
}
|
||||
|
||||
#define iowrite32(v, p) iowrite32(v, p)
|
||||
static inline void iowrite32(u32 value, void __iomem *addr)
|
||||
{
|
||||
unsigned long port = (unsigned long __force)addr;
|
||||
if (__is_io_address(port))
|
||||
outl(value, port & PIO_MASK);
|
||||
else
|
||||
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
||||
__raw_writel((u32 __force)cpu_to_le32(value), addr);
|
||||
#else
|
||||
__indirect_writel(value, addr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#define iowrite32_rep(p, v, c) iowrite32_rep(p, v, c)
|
||||
static inline void iowrite32_rep(void __iomem *addr, const void *vaddr,
|
||||
u32 count)
|
||||
{
|
||||
unsigned long port = (unsigned long __force)addr;
|
||||
if (__is_io_address(port))
|
||||
outsl(port & PIO_MASK, vaddr, count);
|
||||
else
|
||||
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
||||
__raw_writesl(addr, vaddr, count);
|
||||
#else
|
||||
__indirect_writesl(addr, vaddr, count);
|
||||
#endif
|
||||
}
|
||||
|
||||
#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
|
||||
#define ioport_unmap(addr)
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#endif /* __ASM_ARM_ARCH_IO_H */
|
||||
75
arch/arm/mach-ixp4xx/include/mach/irqs.h
Normal file
75
arch/arm/mach-ixp4xx/include/mach/irqs.h
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
/*
|
||||
* arch/arm/mach-ixp4xx/include/mach/irqs.h
|
||||
*
|
||||
* IRQ definitions for IXP4XX based systems
|
||||
*
|
||||
* Copyright (C) 2002 Intel Corporation.
|
||||
* Copyright (C) 2003 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _ARCH_IXP4XX_IRQS_H_
|
||||
#define _ARCH_IXP4XX_IRQS_H_
|
||||
|
||||
#define IRQ_IXP4XX_NPEA 0
|
||||
#define IRQ_IXP4XX_NPEB 1
|
||||
#define IRQ_IXP4XX_NPEC 2
|
||||
#define IRQ_IXP4XX_QM1 3
|
||||
#define IRQ_IXP4XX_QM2 4
|
||||
#define IRQ_IXP4XX_TIMER1 5
|
||||
#define IRQ_IXP4XX_GPIO0 6
|
||||
#define IRQ_IXP4XX_GPIO1 7
|
||||
#define IRQ_IXP4XX_PCI_INT 8
|
||||
#define IRQ_IXP4XX_PCI_DMA1 9
|
||||
#define IRQ_IXP4XX_PCI_DMA2 10
|
||||
#define IRQ_IXP4XX_TIMER2 11
|
||||
#define IRQ_IXP4XX_USB 12
|
||||
#define IRQ_IXP4XX_UART2 13
|
||||
#define IRQ_IXP4XX_TIMESTAMP 14
|
||||
#define IRQ_IXP4XX_UART1 15
|
||||
#define IRQ_IXP4XX_WDOG 16
|
||||
#define IRQ_IXP4XX_AHB_PMU 17
|
||||
#define IRQ_IXP4XX_XSCALE_PMU 18
|
||||
#define IRQ_IXP4XX_GPIO2 19
|
||||
#define IRQ_IXP4XX_GPIO3 20
|
||||
#define IRQ_IXP4XX_GPIO4 21
|
||||
#define IRQ_IXP4XX_GPIO5 22
|
||||
#define IRQ_IXP4XX_GPIO6 23
|
||||
#define IRQ_IXP4XX_GPIO7 24
|
||||
#define IRQ_IXP4XX_GPIO8 25
|
||||
#define IRQ_IXP4XX_GPIO9 26
|
||||
#define IRQ_IXP4XX_GPIO10 27
|
||||
#define IRQ_IXP4XX_GPIO11 28
|
||||
#define IRQ_IXP4XX_GPIO12 29
|
||||
#define IRQ_IXP4XX_SW_INT1 30
|
||||
#define IRQ_IXP4XX_SW_INT2 31
|
||||
#define IRQ_IXP4XX_USB_HOST 32
|
||||
#define IRQ_IXP4XX_I2C 33
|
||||
#define IRQ_IXP4XX_SSP 34
|
||||
#define IRQ_IXP4XX_TSYNC 35
|
||||
#define IRQ_IXP4XX_EAU_DONE 36
|
||||
#define IRQ_IXP4XX_SHA_DONE 37
|
||||
#define IRQ_IXP4XX_SWCP_PE 58
|
||||
#define IRQ_IXP4XX_QM_PE 60
|
||||
#define IRQ_IXP4XX_MCU_ECC 61
|
||||
#define IRQ_IXP4XX_EXP_PE 62
|
||||
|
||||
#define _IXP4XX_GPIO_IRQ(n) (IRQ_IXP4XX_GPIO ## n)
|
||||
#define IXP4XX_GPIO_IRQ(n) _IXP4XX_GPIO_IRQ(n)
|
||||
|
||||
/*
|
||||
* Only first 32 sources are valid if running on IXP42x systems
|
||||
*/
|
||||
#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
|
||||
#define NR_IRQS 64
|
||||
#else
|
||||
#define NR_IRQS 32
|
||||
#endif
|
||||
|
||||
#define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU)
|
||||
|
||||
#endif
|
||||
81
arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
Normal file
81
arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* PTP 1588 clock using the IXP46X
|
||||
*
|
||||
* Copyright (C) 2010 OMICRON electronics GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef _IXP46X_TS_H_
|
||||
#define _IXP46X_TS_H_
|
||||
|
||||
#define DEFAULT_ADDEND 0xF0000029
|
||||
#define TICKS_NS_SHIFT 4
|
||||
|
||||
struct ixp46x_channel_ctl {
|
||||
u32 ch_control; /* 0x40 Time Synchronization Channel Control */
|
||||
u32 ch_event; /* 0x44 Time Synchronization Channel Event */
|
||||
u32 tx_snap_lo; /* 0x48 Transmit Snapshot Low Register */
|
||||
u32 tx_snap_hi; /* 0x4C Transmit Snapshot High Register */
|
||||
u32 rx_snap_lo; /* 0x50 Receive Snapshot Low Register */
|
||||
u32 rx_snap_hi; /* 0x54 Receive Snapshot High Register */
|
||||
u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */
|
||||
u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */
|
||||
};
|
||||
|
||||
struct ixp46x_ts_regs {
|
||||
u32 control; /* 0x00 Time Sync Control Register */
|
||||
u32 event; /* 0x04 Time Sync Event Register */
|
||||
u32 addend; /* 0x08 Time Sync Addend Register */
|
||||
u32 accum; /* 0x0C Time Sync Accumulator Register */
|
||||
u32 test; /* 0x10 Time Sync Test Register */
|
||||
u32 unused; /* 0x14 */
|
||||
u32 rsystime_lo; /* 0x18 RawSystemTime_Low Register */
|
||||
u32 rsystime_hi; /* 0x1C RawSystemTime_High Register */
|
||||
u32 systime_lo; /* 0x20 SystemTime_Low Register */
|
||||
u32 systime_hi; /* 0x24 SystemTime_High Register */
|
||||
u32 trgt_lo; /* 0x28 TargetTime_Low Register */
|
||||
u32 trgt_hi; /* 0x2C TargetTime_High Register */
|
||||
u32 asms_lo; /* 0x30 Auxiliary Slave Mode Snapshot Low */
|
||||
u32 asms_hi; /* 0x34 Auxiliary Slave Mode Snapshot High */
|
||||
u32 amms_lo; /* 0x38 Auxiliary Master Mode Snapshot Low */
|
||||
u32 amms_hi; /* 0x3C Auxiliary Master Mode Snapshot High */
|
||||
|
||||
struct ixp46x_channel_ctl channel[3];
|
||||
};
|
||||
|
||||
/* 0x00 Time Sync Control Register Bits */
|
||||
#define TSCR_AMM (1<<3)
|
||||
#define TSCR_ASM (1<<2)
|
||||
#define TSCR_TTM (1<<1)
|
||||
#define TSCR_RST (1<<0)
|
||||
|
||||
/* 0x04 Time Sync Event Register Bits */
|
||||
#define TSER_SNM (1<<3)
|
||||
#define TSER_SNS (1<<2)
|
||||
#define TTIPEND (1<<1)
|
||||
|
||||
/* 0x40 Time Synchronization Channel Control Register Bits */
|
||||
#define MASTER_MODE (1<<0)
|
||||
#define TIMESTAMP_ALL (1<<1)
|
||||
|
||||
/* 0x44 Time Synchronization Channel Event Register Bits */
|
||||
#define TX_SNAPSHOT_LOCKED (1<<0)
|
||||
#define RX_SNAPSHOT_LOCKED (1<<1)
|
||||
|
||||
/* The ptp_ixp46x module will set this variable */
|
||||
extern int ixp46x_phc_index;
|
||||
|
||||
#endif
|
||||
652
arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
Normal file
652
arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
Normal file
|
|
@ -0,0 +1,652 @@
|
|||
/*
|
||||
* arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
|
||||
*
|
||||
* Register definitions for IXP4xx chipset. This file contains
|
||||
* register location and bit definitions only. Platform specific
|
||||
* definitions and helper function declarations are in platform.h
|
||||
* and machine-name.h.
|
||||
*
|
||||
* Copyright (C) 2002 Intel Corporation.
|
||||
* Copyright (C) 2003-2004 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARM_IXP4XX_H_
|
||||
#define _ASM_ARM_IXP4XX_H_
|
||||
|
||||
/*
|
||||
* IXP4xx Linux Memory Map:
|
||||
*
|
||||
* Phy Size Virt Description
|
||||
* =========================================================================
|
||||
*
|
||||
* 0x00000000 0x10000000(max) PAGE_OFFSET System RAM
|
||||
*
|
||||
* 0x48000000 0x04000000 ioremap'd PCI Memory Space
|
||||
*
|
||||
* 0x50000000 0x10000000 ioremap'd EXP BUS
|
||||
*
|
||||
* 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals
|
||||
*
|
||||
* 0xC0000000 0x00001000 0xFEF13000 PCI CFG
|
||||
*
|
||||
* 0xC4000000 0x00001000 0xFEF14000 EXP CFG
|
||||
*
|
||||
* 0x60000000 0x00004000 0xFEF15000 QMgr
|
||||
*/
|
||||
|
||||
/*
|
||||
* Queue Manager
|
||||
*/
|
||||
#define IXP4XX_QMGR_BASE_PHYS 0x60000000
|
||||
#define IXP4XX_QMGR_BASE_VIRT IOMEM(0xFEF15000)
|
||||
#define IXP4XX_QMGR_REGION_SIZE 0x00004000
|
||||
|
||||
/*
|
||||
* Peripheral space, including debug UART. Must be section-aligned so that
|
||||
* it can be used with the low-level debug code.
|
||||
*/
|
||||
#define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000
|
||||
#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000)
|
||||
#define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000
|
||||
|
||||
/*
|
||||
* PCI Config registers
|
||||
*/
|
||||
#define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000
|
||||
#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000)
|
||||
#define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000
|
||||
|
||||
/*
|
||||
* Expansion BUS Configuration registers
|
||||
*/
|
||||
#define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000
|
||||
#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEF14000
|
||||
#define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000
|
||||
|
||||
#define IXP4XX_EXP_CS0_OFFSET 0x00
|
||||
#define IXP4XX_EXP_CS1_OFFSET 0x04
|
||||
#define IXP4XX_EXP_CS2_OFFSET 0x08
|
||||
#define IXP4XX_EXP_CS3_OFFSET 0x0C
|
||||
#define IXP4XX_EXP_CS4_OFFSET 0x10
|
||||
#define IXP4XX_EXP_CS5_OFFSET 0x14
|
||||
#define IXP4XX_EXP_CS6_OFFSET 0x18
|
||||
#define IXP4XX_EXP_CS7_OFFSET 0x1C
|
||||
#define IXP4XX_EXP_CFG0_OFFSET 0x20
|
||||
#define IXP4XX_EXP_CFG1_OFFSET 0x24
|
||||
#define IXP4XX_EXP_CFG2_OFFSET 0x28
|
||||
#define IXP4XX_EXP_CFG3_OFFSET 0x2C
|
||||
|
||||
/*
|
||||
* Expansion Bus Controller registers.
|
||||
*/
|
||||
#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
|
||||
|
||||
#define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
|
||||
#define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
|
||||
#define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET)
|
||||
#define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)
|
||||
#define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)
|
||||
#define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)
|
||||
#define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)
|
||||
#define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)
|
||||
|
||||
#define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET)
|
||||
#define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET)
|
||||
#define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET)
|
||||
#define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)
|
||||
|
||||
|
||||
/*
|
||||
* Peripheral Space Register Region Base Addresses
|
||||
*/
|
||||
#define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
|
||||
#define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
|
||||
#define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
|
||||
#define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
|
||||
#define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
|
||||
#define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
|
||||
#define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
|
||||
#define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
|
||||
#define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
|
||||
#define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
|
||||
#define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
|
||||
#define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
|
||||
/* ixp46X only */
|
||||
#define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
|
||||
#define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
|
||||
#define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
|
||||
#define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
|
||||
#define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
|
||||
#define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
|
||||
#define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
|
||||
|
||||
|
||||
#define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
|
||||
#define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
|
||||
#define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
|
||||
#define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
|
||||
#define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
|
||||
#define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
|
||||
#define IXP4XX_NPEA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x6000)
|
||||
#define IXP4XX_NPEB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x7000)
|
||||
#define IXP4XX_NPEC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x8000)
|
||||
#define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
|
||||
#define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
|
||||
#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
|
||||
/* ixp46X only */
|
||||
#define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
|
||||
#define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
|
||||
#define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
|
||||
#define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
|
||||
#define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
|
||||
#define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
|
||||
#define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
|
||||
|
||||
/*
|
||||
* Constants to make it easy to access Interrupt Controller registers
|
||||
*/
|
||||
#define IXP4XX_ICPR_OFFSET 0x00 /* Interrupt Status */
|
||||
#define IXP4XX_ICMR_OFFSET 0x04 /* Interrupt Enable */
|
||||
#define IXP4XX_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */
|
||||
#define IXP4XX_ICIP_OFFSET 0x0C /* IRQ Status */
|
||||
#define IXP4XX_ICFP_OFFSET 0x10 /* FIQ Status */
|
||||
#define IXP4XX_ICHR_OFFSET 0x14 /* Interrupt Priority */
|
||||
#define IXP4XX_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */
|
||||
#define IXP4XX_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */
|
||||
|
||||
/*
|
||||
* IXP465-only
|
||||
*/
|
||||
#define IXP4XX_ICPR2_OFFSET 0x20 /* Interrupt Status 2 */
|
||||
#define IXP4XX_ICMR2_OFFSET 0x24 /* Interrupt Enable 2 */
|
||||
#define IXP4XX_ICLR2_OFFSET 0x28 /* Interrupt IRQ/FIQ Select 2 */
|
||||
#define IXP4XX_ICIP2_OFFSET 0x2C /* IRQ Status */
|
||||
#define IXP4XX_ICFP2_OFFSET 0x30 /* FIQ Status */
|
||||
#define IXP4XX_ICEEN_OFFSET 0x34 /* Error High Pri Enable */
|
||||
|
||||
|
||||
/*
|
||||
* Interrupt Controller Register Definitions.
|
||||
*/
|
||||
|
||||
#define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x)))
|
||||
|
||||
#define IXP4XX_ICPR IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET)
|
||||
#define IXP4XX_ICMR IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET)
|
||||
#define IXP4XX_ICLR IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET)
|
||||
#define IXP4XX_ICIP IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET)
|
||||
#define IXP4XX_ICFP IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET)
|
||||
#define IXP4XX_ICHR IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)
|
||||
#define IXP4XX_ICIH IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET)
|
||||
#define IXP4XX_ICFH IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)
|
||||
#define IXP4XX_ICPR2 IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET)
|
||||
#define IXP4XX_ICMR2 IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET)
|
||||
#define IXP4XX_ICLR2 IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET)
|
||||
#define IXP4XX_ICIP2 IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET)
|
||||
#define IXP4XX_ICFP2 IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET)
|
||||
#define IXP4XX_ICEEN IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET)
|
||||
|
||||
/*
|
||||
* Constants to make it easy to access GPIO registers
|
||||
*/
|
||||
#define IXP4XX_GPIO_GPOUTR_OFFSET 0x00
|
||||
#define IXP4XX_GPIO_GPOER_OFFSET 0x04
|
||||
#define IXP4XX_GPIO_GPINR_OFFSET 0x08
|
||||
#define IXP4XX_GPIO_GPISR_OFFSET 0x0C
|
||||
#define IXP4XX_GPIO_GPIT1R_OFFSET 0x10
|
||||
#define IXP4XX_GPIO_GPIT2R_OFFSET 0x14
|
||||
#define IXP4XX_GPIO_GPCLKR_OFFSET 0x18
|
||||
#define IXP4XX_GPIO_GPDBSELR_OFFSET 0x1C
|
||||
|
||||
/*
|
||||
* GPIO Register Definitions.
|
||||
* [Only perform 32bit reads/writes]
|
||||
*/
|
||||
#define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x)))
|
||||
|
||||
#define IXP4XX_GPIO_GPOUTR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET)
|
||||
#define IXP4XX_GPIO_GPOER IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET)
|
||||
#define IXP4XX_GPIO_GPINR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET)
|
||||
#define IXP4XX_GPIO_GPISR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET)
|
||||
#define IXP4XX_GPIO_GPIT1R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET)
|
||||
#define IXP4XX_GPIO_GPIT2R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET)
|
||||
#define IXP4XX_GPIO_GPCLKR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET)
|
||||
#define IXP4XX_GPIO_GPDBSELR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET)
|
||||
|
||||
/*
|
||||
* GPIO register bit definitions
|
||||
*/
|
||||
|
||||
/* Interrupt styles
|
||||
*/
|
||||
#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0
|
||||
#define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1
|
||||
#define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2
|
||||
#define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3
|
||||
#define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4
|
||||
|
||||
/*
|
||||
* Mask used to clear interrupt styles
|
||||
*/
|
||||
#define IXP4XX_GPIO_STYLE_CLEAR 0x7
|
||||
#define IXP4XX_GPIO_STYLE_SIZE 3
|
||||
|
||||
/*
|
||||
* Constants to make it easy to access Timer Control/Status registers
|
||||
*/
|
||||
#define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */
|
||||
#define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
|
||||
#define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
|
||||
#define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
|
||||
#define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
|
||||
#define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
|
||||
#define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
|
||||
#define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
|
||||
#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
|
||||
|
||||
/*
|
||||
* Operating System Timer Register Definitions.
|
||||
*/
|
||||
|
||||
#define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))
|
||||
|
||||
#define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)
|
||||
#define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)
|
||||
#define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)
|
||||
#define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)
|
||||
#define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)
|
||||
#define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)
|
||||
#define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)
|
||||
#define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)
|
||||
#define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)
|
||||
|
||||
/*
|
||||
* Timer register values and bit definitions
|
||||
*/
|
||||
#define IXP4XX_OST_ENABLE 0x00000001
|
||||
#define IXP4XX_OST_ONE_SHOT 0x00000002
|
||||
/* Low order bits of reload value ignored */
|
||||
#define IXP4XX_OST_RELOAD_MASK 0x00000003
|
||||
#define IXP4XX_OST_DISABLED 0x00000000
|
||||
#define IXP4XX_OSST_TIMER_1_PEND 0x00000001
|
||||
#define IXP4XX_OSST_TIMER_2_PEND 0x00000002
|
||||
#define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
|
||||
#define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
|
||||
#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
|
||||
|
||||
#define IXP4XX_WDT_KEY 0x0000482E
|
||||
|
||||
#define IXP4XX_WDT_RESET_ENABLE 0x00000001
|
||||
#define IXP4XX_WDT_IRQ_ENABLE 0x00000002
|
||||
#define IXP4XX_WDT_COUNT_ENABLE 0x00000004
|
||||
|
||||
|
||||
/*
|
||||
* Constants to make it easy to access PCI Control/Status registers
|
||||
*/
|
||||
#define PCI_NP_AD_OFFSET 0x00
|
||||
#define PCI_NP_CBE_OFFSET 0x04
|
||||
#define PCI_NP_WDATA_OFFSET 0x08
|
||||
#define PCI_NP_RDATA_OFFSET 0x0c
|
||||
#define PCI_CRP_AD_CBE_OFFSET 0x10
|
||||
#define PCI_CRP_WDATA_OFFSET 0x14
|
||||
#define PCI_CRP_RDATA_OFFSET 0x18
|
||||
#define PCI_CSR_OFFSET 0x1c
|
||||
#define PCI_ISR_OFFSET 0x20
|
||||
#define PCI_INTEN_OFFSET 0x24
|
||||
#define PCI_DMACTRL_OFFSET 0x28
|
||||
#define PCI_AHBMEMBASE_OFFSET 0x2c
|
||||
#define PCI_AHBIOBASE_OFFSET 0x30
|
||||
#define PCI_PCIMEMBASE_OFFSET 0x34
|
||||
#define PCI_AHBDOORBELL_OFFSET 0x38
|
||||
#define PCI_PCIDOORBELL_OFFSET 0x3C
|
||||
#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
|
||||
#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
|
||||
#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
|
||||
#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
|
||||
#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
|
||||
#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
|
||||
|
||||
/*
|
||||
* PCI Control/Status Registers
|
||||
*/
|
||||
#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
|
||||
|
||||
#define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
|
||||
#define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
|
||||
#define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
|
||||
#define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
|
||||
#define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
|
||||
#define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
|
||||
#define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
|
||||
#define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET)
|
||||
#define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
|
||||
#define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
|
||||
#define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
|
||||
#define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
|
||||
#define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
|
||||
#define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
|
||||
#define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
|
||||
#define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
|
||||
#define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
|
||||
#define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
|
||||
#define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
|
||||
#define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
|
||||
#define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
|
||||
#define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
|
||||
|
||||
/*
|
||||
* PCI register values and bit definitions
|
||||
*/
|
||||
|
||||
/* CSR bit definitions */
|
||||
#define PCI_CSR_HOST 0x00000001
|
||||
#define PCI_CSR_ARBEN 0x00000002
|
||||
#define PCI_CSR_ADS 0x00000004
|
||||
#define PCI_CSR_PDS 0x00000008
|
||||
#define PCI_CSR_ABE 0x00000010
|
||||
#define PCI_CSR_DBT 0x00000020
|
||||
#define PCI_CSR_ASE 0x00000100
|
||||
#define PCI_CSR_IC 0x00008000
|
||||
|
||||
/* ISR (Interrupt status) Register bit definitions */
|
||||
#define PCI_ISR_PSE 0x00000001
|
||||
#define PCI_ISR_PFE 0x00000002
|
||||
#define PCI_ISR_PPE 0x00000004
|
||||
#define PCI_ISR_AHBE 0x00000008
|
||||
#define PCI_ISR_APDC 0x00000010
|
||||
#define PCI_ISR_PADC 0x00000020
|
||||
#define PCI_ISR_ADB 0x00000040
|
||||
#define PCI_ISR_PDB 0x00000080
|
||||
|
||||
/* INTEN (Interrupt Enable) Register bit definitions */
|
||||
#define PCI_INTEN_PSE 0x00000001
|
||||
#define PCI_INTEN_PFE 0x00000002
|
||||
#define PCI_INTEN_PPE 0x00000004
|
||||
#define PCI_INTEN_AHBE 0x00000008
|
||||
#define PCI_INTEN_APDC 0x00000010
|
||||
#define PCI_INTEN_PADC 0x00000020
|
||||
#define PCI_INTEN_ADB 0x00000040
|
||||
#define PCI_INTEN_PDB 0x00000080
|
||||
|
||||
/*
|
||||
* Shift value for byte enable on NP cmd/byte enable register
|
||||
*/
|
||||
#define IXP4XX_PCI_NP_CBE_BESL 4
|
||||
|
||||
/*
|
||||
* PCI commands supported by NP access unit
|
||||
*/
|
||||
#define NP_CMD_IOREAD 0x2
|
||||
#define NP_CMD_IOWRITE 0x3
|
||||
#define NP_CMD_CONFIGREAD 0xa
|
||||
#define NP_CMD_CONFIGWRITE 0xb
|
||||
#define NP_CMD_MEMREAD 0x6
|
||||
#define NP_CMD_MEMWRITE 0x7
|
||||
|
||||
/*
|
||||
* Constants for CRP access into local config space
|
||||
*/
|
||||
#define CRP_AD_CBE_BESL 20
|
||||
#define CRP_AD_CBE_WRITE 0x00010000
|
||||
|
||||
|
||||
/*
|
||||
* USB Device Controller
|
||||
*
|
||||
* These are used by the USB gadget driver, so they don't follow the
|
||||
* IXP4XX_ naming convetions.
|
||||
*
|
||||
*/
|
||||
# define IXP4XX_USB_REG(x) (*((volatile u32 *)(x)))
|
||||
|
||||
/* UDC Undocumented - Reserved1 */
|
||||
#define UDC_RES1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004)
|
||||
/* UDC Undocumented - Reserved2 */
|
||||
#define UDC_RES2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0008)
|
||||
/* UDC Undocumented - Reserved3 */
|
||||
#define UDC_RES3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x000C)
|
||||
/* UDC Control Register */
|
||||
#define UDCCR IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000)
|
||||
/* UDC Endpoint 0 Control/Status Register */
|
||||
#define UDCCS0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0010)
|
||||
/* UDC Endpoint 1 (IN) Control/Status Register */
|
||||
#define UDCCS1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0014)
|
||||
/* UDC Endpoint 2 (OUT) Control/Status Register */
|
||||
#define UDCCS2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0018)
|
||||
/* UDC Endpoint 3 (IN) Control/Status Register */
|
||||
#define UDCCS3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x001C)
|
||||
/* UDC Endpoint 4 (OUT) Control/Status Register */
|
||||
#define UDCCS4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0020)
|
||||
/* UDC Endpoint 5 (Interrupt) Control/Status Register */
|
||||
#define UDCCS5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0024)
|
||||
/* UDC Endpoint 6 (IN) Control/Status Register */
|
||||
#define UDCCS6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0028)
|
||||
/* UDC Endpoint 7 (OUT) Control/Status Register */
|
||||
#define UDCCS7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x002C)
|
||||
/* UDC Endpoint 8 (IN) Control/Status Register */
|
||||
#define UDCCS8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0030)
|
||||
/* UDC Endpoint 9 (OUT) Control/Status Register */
|
||||
#define UDCCS9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0034)
|
||||
/* UDC Endpoint 10 (Interrupt) Control/Status Register */
|
||||
#define UDCCS10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0038)
|
||||
/* UDC Endpoint 11 (IN) Control/Status Register */
|
||||
#define UDCCS11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x003C)
|
||||
/* UDC Endpoint 12 (OUT) Control/Status Register */
|
||||
#define UDCCS12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0040)
|
||||
/* UDC Endpoint 13 (IN) Control/Status Register */
|
||||
#define UDCCS13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0044)
|
||||
/* UDC Endpoint 14 (OUT) Control/Status Register */
|
||||
#define UDCCS14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0048)
|
||||
/* UDC Endpoint 15 (Interrupt) Control/Status Register */
|
||||
#define UDCCS15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x004C)
|
||||
/* UDC Frame Number Register High */
|
||||
#define UFNRH IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0060)
|
||||
/* UDC Frame Number Register Low */
|
||||
#define UFNRL IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0064)
|
||||
/* UDC Byte Count Reg 2 */
|
||||
#define UBCR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0068)
|
||||
/* UDC Byte Count Reg 4 */
|
||||
#define UBCR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x006c)
|
||||
/* UDC Byte Count Reg 7 */
|
||||
#define UBCR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0070)
|
||||
/* UDC Byte Count Reg 9 */
|
||||
#define UBCR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0074)
|
||||
/* UDC Byte Count Reg 12 */
|
||||
#define UBCR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0078)
|
||||
/* UDC Byte Count Reg 14 */
|
||||
#define UBCR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x007c)
|
||||
/* UDC Endpoint 0 Data Register */
|
||||
#define UDDR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0080)
|
||||
/* UDC Endpoint 1 Data Register */
|
||||
#define UDDR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0100)
|
||||
/* UDC Endpoint 2 Data Register */
|
||||
#define UDDR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0180)
|
||||
/* UDC Endpoint 3 Data Register */
|
||||
#define UDDR3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0200)
|
||||
/* UDC Endpoint 4 Data Register */
|
||||
#define UDDR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0400)
|
||||
/* UDC Endpoint 5 Data Register */
|
||||
#define UDDR5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00A0)
|
||||
/* UDC Endpoint 6 Data Register */
|
||||
#define UDDR6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0600)
|
||||
/* UDC Endpoint 7 Data Register */
|
||||
#define UDDR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0680)
|
||||
/* UDC Endpoint 8 Data Register */
|
||||
#define UDDR8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0700)
|
||||
/* UDC Endpoint 9 Data Register */
|
||||
#define UDDR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0900)
|
||||
/* UDC Endpoint 10 Data Register */
|
||||
#define UDDR10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00C0)
|
||||
/* UDC Endpoint 11 Data Register */
|
||||
#define UDDR11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B00)
|
||||
/* UDC Endpoint 12 Data Register */
|
||||
#define UDDR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B80)
|
||||
/* UDC Endpoint 13 Data Register */
|
||||
#define UDDR13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0C00)
|
||||
/* UDC Endpoint 14 Data Register */
|
||||
#define UDDR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0E00)
|
||||
/* UDC Endpoint 15 Data Register */
|
||||
#define UDDR15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00E0)
|
||||
/* UDC Interrupt Control Register 0 */
|
||||
#define UICR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0050)
|
||||
/* UDC Interrupt Control Register 1 */
|
||||
#define UICR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0054)
|
||||
/* UDC Status Interrupt Register 0 */
|
||||
#define USIR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0058)
|
||||
/* UDC Status Interrupt Register 1 */
|
||||
#define USIR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x005C)
|
||||
|
||||
#define UDCCR_UDE (1 << 0) /* UDC enable */
|
||||
#define UDCCR_UDA (1 << 1) /* UDC active */
|
||||
#define UDCCR_RSM (1 << 2) /* Device resume */
|
||||
#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
|
||||
#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
|
||||
#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
|
||||
#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
|
||||
#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
|
||||
|
||||
#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
|
||||
#define UDCCS0_IPR (1 << 1) /* IN packet ready */
|
||||
#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
|
||||
#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
|
||||
#define UDCCS0_SST (1 << 4) /* Sent stall */
|
||||
#define UDCCS0_FST (1 << 5) /* Force stall */
|
||||
#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
|
||||
#define UDCCS0_SA (1 << 7) /* Setup active */
|
||||
|
||||
#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
|
||||
#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
|
||||
#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
|
||||
#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
|
||||
#define UDCCS_BI_SST (1 << 4) /* Sent stall */
|
||||
#define UDCCS_BI_FST (1 << 5) /* Force stall */
|
||||
#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
|
||||
|
||||
#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
|
||||
#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
|
||||
#define UDCCS_BO_DME (1 << 3) /* DMA enable */
|
||||
#define UDCCS_BO_SST (1 << 4) /* Sent stall */
|
||||
#define UDCCS_BO_FST (1 << 5) /* Force stall */
|
||||
#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
|
||||
#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
|
||||
|
||||
#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
|
||||
#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
|
||||
#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
|
||||
#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
|
||||
#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
|
||||
|
||||
#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
|
||||
#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
|
||||
#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
|
||||
#define UDCCS_IO_DME (1 << 3) /* DMA enable */
|
||||
#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
|
||||
#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
|
||||
|
||||
#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
|
||||
#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
|
||||
#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
|
||||
#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
|
||||
#define UDCCS_INT_SST (1 << 4) /* Sent stall */
|
||||
#define UDCCS_INT_FST (1 << 5) /* Force stall */
|
||||
#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
|
||||
|
||||
#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
|
||||
#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
|
||||
#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
|
||||
#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
|
||||
#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
|
||||
#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
|
||||
#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
|
||||
#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
|
||||
|
||||
#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
|
||||
#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
|
||||
#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
|
||||
#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
|
||||
#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
|
||||
#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
|
||||
#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
|
||||
#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
|
||||
|
||||
#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
|
||||
#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
|
||||
#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
|
||||
#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
|
||||
#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
|
||||
#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
|
||||
#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
|
||||
#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
|
||||
|
||||
#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
|
||||
#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
|
||||
#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
|
||||
#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
|
||||
#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
|
||||
#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
|
||||
#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
|
||||
#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
|
||||
|
||||
#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
|
||||
|
||||
/* "fuse" bits of IXP_EXP_CFG2 */
|
||||
/* All IXP4xx CPUs */
|
||||
#define IXP4XX_FEATURE_RCOMP (1 << 0)
|
||||
#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
|
||||
#define IXP4XX_FEATURE_HASH (1 << 2)
|
||||
#define IXP4XX_FEATURE_AES (1 << 3)
|
||||
#define IXP4XX_FEATURE_DES (1 << 4)
|
||||
#define IXP4XX_FEATURE_HDLC (1 << 5)
|
||||
#define IXP4XX_FEATURE_AAL (1 << 6)
|
||||
#define IXP4XX_FEATURE_HSS (1 << 7)
|
||||
#define IXP4XX_FEATURE_UTOPIA (1 << 8)
|
||||
#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)
|
||||
#define IXP4XX_FEATURE_NPEC_ETH (1 << 10)
|
||||
#define IXP4XX_FEATURE_RESET_NPEA (1 << 11)
|
||||
#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
|
||||
#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
|
||||
#define IXP4XX_FEATURE_PCI (1 << 14)
|
||||
#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
|
||||
#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
|
||||
#define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP | \
|
||||
IXP4XX_FEATURE_USB_DEVICE | \
|
||||
IXP4XX_FEATURE_HASH | \
|
||||
IXP4XX_FEATURE_AES | \
|
||||
IXP4XX_FEATURE_DES | \
|
||||
IXP4XX_FEATURE_HDLC | \
|
||||
IXP4XX_FEATURE_AAL | \
|
||||
IXP4XX_FEATURE_HSS | \
|
||||
IXP4XX_FEATURE_UTOPIA | \
|
||||
IXP4XX_FEATURE_NPEB_ETH0 | \
|
||||
IXP4XX_FEATURE_NPEC_ETH | \
|
||||
IXP4XX_FEATURE_RESET_NPEA | \
|
||||
IXP4XX_FEATURE_RESET_NPEB | \
|
||||
IXP4XX_FEATURE_RESET_NPEC | \
|
||||
IXP4XX_FEATURE_PCI | \
|
||||
IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \
|
||||
IXP4XX_FEATURE_XSCALE_MAX_FREQ)
|
||||
|
||||
|
||||
/* IXP43x/46x CPUs */
|
||||
#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
|
||||
#define IXP4XX_FEATURE_USB_HOST (1 << 18)
|
||||
#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
|
||||
#define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK | \
|
||||
IXP4XX_FEATURE_ECC_TIMESYNC | \
|
||||
IXP4XX_FEATURE_USB_HOST | \
|
||||
IXP4XX_FEATURE_NPEA_ETH)
|
||||
|
||||
/* IXP46x CPU (including IXP455) only */
|
||||
#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
|
||||
#define IXP4XX_FEATURE_RSA (1 << 21)
|
||||
#define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK | \
|
||||
IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
|
||||
IXP4XX_FEATURE_RSA)
|
||||
|
||||
#endif
|
||||
39
arch/arm/mach-ixp4xx/include/mach/npe.h
Normal file
39
arch/arm/mach-ixp4xx/include/mach/npe.h
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
#ifndef __IXP4XX_NPE_H
|
||||
#define __IXP4XX_NPE_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
|
||||
extern const char *npe_names[];
|
||||
|
||||
struct npe_regs {
|
||||
u32 exec_addr, exec_data, exec_status_cmd, exec_count;
|
||||
u32 action_points[4];
|
||||
u32 watchpoint_fifo, watch_count;
|
||||
u32 profile_count;
|
||||
u32 messaging_status, messaging_control;
|
||||
u32 mailbox_status, /*messaging_*/ in_out_fifo;
|
||||
};
|
||||
|
||||
struct npe {
|
||||
struct resource *mem_res;
|
||||
struct npe_regs __iomem *regs;
|
||||
u32 regs_phys;
|
||||
int id;
|
||||
int valid;
|
||||
};
|
||||
|
||||
|
||||
static inline const char *npe_name(struct npe *npe)
|
||||
{
|
||||
return npe_names[npe->id];
|
||||
}
|
||||
|
||||
int npe_running(struct npe *npe);
|
||||
int npe_send_message(struct npe *npe, const void *msg, const char *what);
|
||||
int npe_recv_message(struct npe *npe, void *msg, const char *what);
|
||||
int npe_send_recv_message(struct npe *npe, void *msg, const char *what);
|
||||
int npe_load_firmware(struct npe *npe, const char *name, struct device *dev);
|
||||
struct npe *npe_request(unsigned id);
|
||||
void npe_release(struct npe *npe);
|
||||
|
||||
#endif /* __IXP4XX_NPE_H */
|
||||
135
arch/arm/mach-ixp4xx/include/mach/platform.h
Normal file
135
arch/arm/mach-ixp4xx/include/mach/platform.h
Normal file
|
|
@ -0,0 +1,135 @@
|
|||
/*
|
||||
* arch/arm/mach-ixp4xx/include/mach/platform.h
|
||||
*
|
||||
* Constants and functions that are useful to IXP4xx platform-specific code
|
||||
* and device drivers.
|
||||
*
|
||||
* Copyright (C) 2004 MontaVista Software, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_HARDWARE_H__
|
||||
#error "Do not include this directly, instead #include <mach/hardware.h>"
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/reboot.h>
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
#ifndef __ARMEB__
|
||||
#define REG_OFFSET 0
|
||||
#else
|
||||
#define REG_OFFSET 3
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Expansion bus memory regions
|
||||
*/
|
||||
#define IXP4XX_EXP_BUS_BASE_PHYS (0x50000000)
|
||||
|
||||
/*
|
||||
* The expansion bus on the IXP4xx can be configured for either 16 or
|
||||
* 32MB windows and the CS offset for each region changes based on the
|
||||
* current configuration. This means that we cannot simply hardcode
|
||||
* each offset. ixp4xx_sys_init() looks at the expansion bus configuration
|
||||
* as setup by the bootloader to determine our window size.
|
||||
*/
|
||||
extern unsigned long ixp4xx_exp_bus_size;
|
||||
|
||||
#define IXP4XX_EXP_BUS_BASE(region)\
|
||||
(IXP4XX_EXP_BUS_BASE_PHYS + ((region) * ixp4xx_exp_bus_size))
|
||||
|
||||
#define IXP4XX_EXP_BUS_END(region)\
|
||||
(IXP4XX_EXP_BUS_BASE(region) + ixp4xx_exp_bus_size - 1)
|
||||
|
||||
/* Those macros can be used to adjust timing and configure
|
||||
* other features for each region.
|
||||
*/
|
||||
|
||||
#define IXP4XX_EXP_BUS_RECOVERY_T(x) (((x) & 0x0f) << 16)
|
||||
#define IXP4XX_EXP_BUS_HOLD_T(x) (((x) & 0x03) << 20)
|
||||
#define IXP4XX_EXP_BUS_STROBE_T(x) (((x) & 0x0f) << 22)
|
||||
#define IXP4XX_EXP_BUS_SETUP_T(x) (((x) & 0x03) << 26)
|
||||
#define IXP4XX_EXP_BUS_ADDR_T(x) (((x) & 0x03) << 28)
|
||||
#define IXP4XX_EXP_BUS_SIZE(x) (((x) & 0x0f) << 10)
|
||||
#define IXP4XX_EXP_BUS_CYCLES(x) (((x) & 0x03) << 14)
|
||||
|
||||
#define IXP4XX_EXP_BUS_CS_EN (1L << 31)
|
||||
#define IXP4XX_EXP_BUS_BYTE_RD16 (1L << 6)
|
||||
#define IXP4XX_EXP_BUS_HRDY_POL (1L << 5)
|
||||
#define IXP4XX_EXP_BUS_MUX_EN (1L << 4)
|
||||
#define IXP4XX_EXP_BUS_SPLT_EN (1L << 3)
|
||||
#define IXP4XX_EXP_BUS_WR_EN (1L << 1)
|
||||
#define IXP4XX_EXP_BUS_BYTE_EN (1L << 0)
|
||||
|
||||
#define IXP4XX_EXP_BUS_CYCLES_INTEL 0x00
|
||||
#define IXP4XX_EXP_BUS_CYCLES_MOTOROLA 0x01
|
||||
#define IXP4XX_EXP_BUS_CYCLES_HPI 0x02
|
||||
|
||||
#define IXP4XX_FLASH_WRITABLE (0x2)
|
||||
#define IXP4XX_FLASH_DEFAULT (0xbcd23c40)
|
||||
#define IXP4XX_FLASH_WRITE (0xbcd23c42)
|
||||
|
||||
/*
|
||||
* Clock Speed Definitions.
|
||||
*/
|
||||
#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */
|
||||
#define IXP4XX_UART_XTAL 14745600
|
||||
|
||||
/*
|
||||
* This structure provide a means for the board setup code
|
||||
* to give information to th pata_ixp4xx driver. It is
|
||||
* passed as platform_data.
|
||||
*/
|
||||
struct ixp4xx_pata_data {
|
||||
volatile u32 *cs0_cfg;
|
||||
volatile u32 *cs1_cfg;
|
||||
unsigned long cs0_bits;
|
||||
unsigned long cs1_bits;
|
||||
void __iomem *cs0;
|
||||
void __iomem *cs1;
|
||||
};
|
||||
|
||||
#define IXP4XX_ETH_NPEA 0x00
|
||||
#define IXP4XX_ETH_NPEB 0x10
|
||||
#define IXP4XX_ETH_NPEC 0x20
|
||||
|
||||
/* Information about built-in Ethernet MAC interfaces */
|
||||
struct eth_plat_info {
|
||||
u8 phy; /* MII PHY ID, 0 - 31 */
|
||||
u8 rxq; /* configurable, currently 0 - 31 only */
|
||||
u8 txreadyq;
|
||||
u8 hwaddr[6];
|
||||
};
|
||||
|
||||
/* Information about built-in HSS (synchronous serial) interfaces */
|
||||
struct hss_plat_info {
|
||||
int (*set_clock)(int port, unsigned int clock_type);
|
||||
int (*open)(int port, void *pdev,
|
||||
void (*set_carrier_cb)(void *pdev, int carrier));
|
||||
void (*close)(int port, void *pdev);
|
||||
u8 txreadyq;
|
||||
};
|
||||
|
||||
/*
|
||||
* Frequency of clock used for primary clocksource
|
||||
*/
|
||||
extern unsigned long ixp4xx_timer_freq;
|
||||
|
||||
/*
|
||||
* Functions used by platform-level setup code
|
||||
*/
|
||||
extern void ixp4xx_map_io(void);
|
||||
extern void ixp4xx_init_early(void);
|
||||
extern void ixp4xx_init_irq(void);
|
||||
extern void ixp4xx_sys_init(void);
|
||||
extern void ixp4xx_timer_init(void);
|
||||
extern void ixp4xx_restart(enum reboot_mode, const char *);
|
||||
extern void ixp4xx_pci_preinit(void);
|
||||
struct pci_sys_data;
|
||||
extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
|
||||
extern struct pci_ops ixp4xx_ops;
|
||||
|
||||
#endif // __ASSEMBLY__
|
||||
|
||||
204
arch/arm/mach-ixp4xx/include/mach/qmgr.h
Normal file
204
arch/arm/mach-ixp4xx/include/mach/qmgr.h
Normal file
|
|
@ -0,0 +1,204 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License
|
||||
* as published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef IXP4XX_QMGR_H
|
||||
#define IXP4XX_QMGR_H
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#define DEBUG_QMGR 0
|
||||
|
||||
#define HALF_QUEUES 32
|
||||
#define QUEUES 64
|
||||
#define MAX_QUEUE_LENGTH 4 /* in dwords */
|
||||
|
||||
#define QUEUE_STAT1_EMPTY 1 /* queue status bits */
|
||||
#define QUEUE_STAT1_NEARLY_EMPTY 2
|
||||
#define QUEUE_STAT1_NEARLY_FULL 4
|
||||
#define QUEUE_STAT1_FULL 8
|
||||
#define QUEUE_STAT2_UNDERFLOW 1
|
||||
#define QUEUE_STAT2_OVERFLOW 2
|
||||
|
||||
#define QUEUE_WATERMARK_0_ENTRIES 0
|
||||
#define QUEUE_WATERMARK_1_ENTRY 1
|
||||
#define QUEUE_WATERMARK_2_ENTRIES 2
|
||||
#define QUEUE_WATERMARK_4_ENTRIES 3
|
||||
#define QUEUE_WATERMARK_8_ENTRIES 4
|
||||
#define QUEUE_WATERMARK_16_ENTRIES 5
|
||||
#define QUEUE_WATERMARK_32_ENTRIES 6
|
||||
#define QUEUE_WATERMARK_64_ENTRIES 7
|
||||
|
||||
/* queue interrupt request conditions */
|
||||
#define QUEUE_IRQ_SRC_EMPTY 0
|
||||
#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1
|
||||
#define QUEUE_IRQ_SRC_NEARLY_FULL 2
|
||||
#define QUEUE_IRQ_SRC_FULL 3
|
||||
#define QUEUE_IRQ_SRC_NOT_EMPTY 4
|
||||
#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5
|
||||
#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6
|
||||
#define QUEUE_IRQ_SRC_NOT_FULL 7
|
||||
|
||||
struct qmgr_regs {
|
||||
u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
|
||||
u32 stat1[4]; /* 0x400 - 0x40F */
|
||||
u32 stat2[2]; /* 0x410 - 0x417 */
|
||||
u32 statne_h; /* 0x418 - queue nearly empty */
|
||||
u32 statf_h; /* 0x41C - queue full */
|
||||
u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */
|
||||
u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */
|
||||
u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */
|
||||
u32 reserved[1776];
|
||||
u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */
|
||||
};
|
||||
|
||||
void qmgr_set_irq(unsigned int queue, int src,
|
||||
void (*handler)(void *pdev), void *pdev);
|
||||
void qmgr_enable_irq(unsigned int queue);
|
||||
void qmgr_disable_irq(unsigned int queue);
|
||||
|
||||
/* request_ and release_queue() must be called from non-IRQ context */
|
||||
|
||||
#if DEBUG_QMGR
|
||||
extern char qmgr_queue_descs[QUEUES][32];
|
||||
|
||||
int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
|
||||
unsigned int nearly_empty_watermark,
|
||||
unsigned int nearly_full_watermark,
|
||||
const char *desc_format, const char* name);
|
||||
#else
|
||||
int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
|
||||
unsigned int nearly_empty_watermark,
|
||||
unsigned int nearly_full_watermark);
|
||||
#define qmgr_request_queue(queue, len, nearly_empty_watermark, \
|
||||
nearly_full_watermark, desc_format, name) \
|
||||
__qmgr_request_queue(queue, len, nearly_empty_watermark, \
|
||||
nearly_full_watermark)
|
||||
#endif
|
||||
|
||||
void qmgr_release_queue(unsigned int queue);
|
||||
|
||||
|
||||
static inline void qmgr_put_entry(unsigned int queue, u32 val)
|
||||
{
|
||||
struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
|
||||
#if DEBUG_QMGR
|
||||
BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
|
||||
|
||||
printk(KERN_DEBUG "Queue %s(%i) put %X\n",
|
||||
qmgr_queue_descs[queue], queue, val);
|
||||
#endif
|
||||
__raw_writel(val, &qmgr_regs->acc[queue][0]);
|
||||
}
|
||||
|
||||
static inline u32 qmgr_get_entry(unsigned int queue)
|
||||
{
|
||||
u32 val;
|
||||
const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
|
||||
val = __raw_readl(&qmgr_regs->acc[queue][0]);
|
||||
#if DEBUG_QMGR
|
||||
BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
|
||||
|
||||
printk(KERN_DEBUG "Queue %s(%i) get %X\n",
|
||||
qmgr_queue_descs[queue], queue, val);
|
||||
#endif
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline int __qmgr_get_stat1(unsigned int queue)
|
||||
{
|
||||
const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
|
||||
return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
|
||||
>> ((queue & 7) << 2)) & 0xF;
|
||||
}
|
||||
|
||||
static inline int __qmgr_get_stat2(unsigned int queue)
|
||||
{
|
||||
const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
|
||||
BUG_ON(queue >= HALF_QUEUES);
|
||||
return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
|
||||
>> ((queue & 0xF) << 1)) & 0x3;
|
||||
}
|
||||
|
||||
/**
|
||||
* qmgr_stat_empty() - checks if a hardware queue is empty
|
||||
* @queue: queue number
|
||||
*
|
||||
* Returns non-zero value if the queue is empty.
|
||||
*/
|
||||
static inline int qmgr_stat_empty(unsigned int queue)
|
||||
{
|
||||
BUG_ON(queue >= HALF_QUEUES);
|
||||
return __qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY;
|
||||
}
|
||||
|
||||
/**
|
||||
* qmgr_stat_below_low_watermark() - checks if a queue is below low watermark
|
||||
* @queue: queue number
|
||||
*
|
||||
* Returns non-zero value if the queue is below low watermark.
|
||||
*/
|
||||
static inline int qmgr_stat_below_low_watermark(unsigned int queue)
|
||||
{
|
||||
const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
|
||||
if (queue >= HALF_QUEUES)
|
||||
return (__raw_readl(&qmgr_regs->statne_h) >>
|
||||
(queue - HALF_QUEUES)) & 0x01;
|
||||
return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY;
|
||||
}
|
||||
|
||||
/**
|
||||
* qmgr_stat_above_high_watermark() - checks if a queue is above high watermark
|
||||
* @queue: queue number
|
||||
*
|
||||
* Returns non-zero value if the queue is above high watermark
|
||||
*/
|
||||
static inline int qmgr_stat_above_high_watermark(unsigned int queue)
|
||||
{
|
||||
BUG_ON(queue >= HALF_QUEUES);
|
||||
return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* qmgr_stat_full() - checks if a hardware queue is full
|
||||
* @queue: queue number
|
||||
*
|
||||
* Returns non-zero value if the queue is full.
|
||||
*/
|
||||
static inline int qmgr_stat_full(unsigned int queue)
|
||||
{
|
||||
const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
|
||||
if (queue >= HALF_QUEUES)
|
||||
return (__raw_readl(&qmgr_regs->statf_h) >>
|
||||
(queue - HALF_QUEUES)) & 0x01;
|
||||
return __qmgr_get_stat1(queue) & QUEUE_STAT1_FULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* qmgr_stat_underflow() - checks if a hardware queue experienced underflow
|
||||
* @queue: queue number
|
||||
*
|
||||
* Returns non-zero value if the queue experienced underflow.
|
||||
*/
|
||||
static inline int qmgr_stat_underflow(unsigned int queue)
|
||||
{
|
||||
return __qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW;
|
||||
}
|
||||
|
||||
/**
|
||||
* qmgr_stat_overflow() - checks if a hardware queue experienced overflow
|
||||
* @queue: queue number
|
||||
*
|
||||
* Returns non-zero value if the queue experienced overflow.
|
||||
*/
|
||||
static inline int qmgr_stat_overflow(unsigned int queue)
|
||||
{
|
||||
return __qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW;
|
||||
}
|
||||
|
||||
#endif
|
||||
8
arch/arm/mach-ixp4xx/include/mach/udc.h
Normal file
8
arch/arm/mach-ixp4xx/include/mach/udc.h
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
/*
|
||||
* arch/arm/mach-ixp4xx/include/mach/udc.h
|
||||
*
|
||||
*/
|
||||
#include <linux/platform_data/pxa2xx_udc.h>
|
||||
|
||||
extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info);
|
||||
|
||||
56
arch/arm/mach-ixp4xx/include/mach/uncompress.h
Normal file
56
arch/arm/mach-ixp4xx/include/mach/uncompress.h
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* arch/arm/mach-ixp4xx/include/mach/uncompress.h
|
||||
*
|
||||
* Copyright (C) 2002 Intel Corporation.
|
||||
* Copyright (C) 2003-2004 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _ARCH_UNCOMPRESS_H_
|
||||
#define _ARCH_UNCOMPRESS_H_
|
||||
|
||||
#include "ixp4xx-regs.h"
|
||||
#include <asm/mach-types.h>
|
||||
#include <linux/serial_reg.h>
|
||||
|
||||
#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
|
||||
|
||||
volatile u32* uart_base;
|
||||
|
||||
static inline void putc(int c)
|
||||
{
|
||||
/* Check THRE and TEMT bits before we transmit the character.
|
||||
*/
|
||||
while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
|
||||
barrier();
|
||||
|
||||
*uart_base = c;
|
||||
}
|
||||
|
||||
static void flush(void)
|
||||
{
|
||||
}
|
||||
|
||||
static __inline__ void __arch_decomp_setup(unsigned long arch_id)
|
||||
{
|
||||
/*
|
||||
* Some boards are using UART2 as console
|
||||
*/
|
||||
if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
|
||||
machine_is_gateway7001() || machine_is_wg302v2() ||
|
||||
machine_is_devixp() || machine_is_miccpt() || machine_is_mic256())
|
||||
uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
|
||||
else
|
||||
uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
|
||||
}
|
||||
|
||||
/*
|
||||
* arch_id is a variable in decompress_kernel()
|
||||
*/
|
||||
#define arch_decomp_setup() __arch_decomp_setup(arch_id)
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue