mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 09:22:44 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
36
arch/arm/mach-ks8695/include/mach/debug-macro.S
Normal file
36
arch/arm/mach-ks8695/include/mach/debug-macro.S
Normal file
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|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/debug-macro.S
|
||||
*
|
||||
* Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
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||||
* Copyright (C) 2006 Simtec Electronics
|
||||
*
|
||||
* KS8695 - Debug macros
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <mach/hardware.h>
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||||
#include <mach/regs-uart.h>
|
||||
|
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.macro addruart, rp, rv, tmp
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ldr \rp, =KS8695_UART_PA @ physical base address
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ldr \rv, =KS8695_UART_VA @ virtual base address
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.endm
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|
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.macro senduart, rd, rx
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str \rd, [\rx, #KS8695_URTH] @ Write to Transmit Holding Register
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.endm
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|
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.macro busyuart, rd, rx
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1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register
|
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tst \rd, #URLS_URTE @ Holding & Shift registers empty?
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beq 1001b
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.endm
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||||
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||||
.macro waituart, rd, rx
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||||
1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register
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tst \rd, #URLS_URTHRE @ Holding Register empty?
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beq 1001b
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.endm
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||||
32
arch/arm/mach-ks8695/include/mach/devices.h
Normal file
32
arch/arm/mach-ks8695/include/mach/devices.h
Normal file
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|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/devices.h
|
||||
*
|
||||
* Copyright (C) 2006 Andrew Victor
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
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|
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#ifndef __ASM_ARCH_DEVICES_H
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#define __ASM_ARCH_DEVICES_H
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#include <linux/pci.h>
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|
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/* Ethernet */
|
||||
extern void __init ks8695_add_device_wan(void);
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extern void __init ks8695_add_device_lan(void);
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extern void __init ks8695_add_device_hpna(void);
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|
||||
/* PCI */
|
||||
#define KS8695_MODE_PCI 0
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#define KS8695_MODE_MINIPCI 1
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#define KS8695_MODE_CARDBUS 2
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|
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struct ks8695_pci_cfg {
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short mode;
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int (*map_irq)(const struct pci_dev *, u8, u8);
|
||||
};
|
||||
extern __init void ks8695_init_pci(struct ks8695_pci_cfg *);
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|
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#endif
|
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47
arch/arm/mach-ks8695/include/mach/entry-macro.S
Normal file
47
arch/arm/mach-ks8695/include/mach/entry-macro.S
Normal file
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|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/entry-macro.S
|
||||
*
|
||||
* Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
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||||
* Copyright (C) 2006 Simtec Electronics
|
||||
*
|
||||
* Low-level IRQ helper macros for KS8695
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*
|
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* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
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|
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#include <mach/hardware.h>
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#include <mach/regs-irq.h>
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||||
|
||||
.macro get_irqnr_preamble, base, tmp
|
||||
ldr \base, =KS8695_IRQ_VA @ Base address of interrupt controller
|
||||
.endm
|
||||
|
||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
||||
ldr \irqstat, [\base, #KS8695_INTMS] @ Mask Status register
|
||||
|
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teq \irqstat, #0
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beq 1001f
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|
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mov \irqnr, #0
|
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|
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tst \irqstat, #0xff
|
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moveq \irqstat, \irqstat, lsr #8
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addeq \irqnr, \irqnr, #8
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tsteq \irqstat, #0xff
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moveq \irqstat, \irqstat, lsr #8
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addeq \irqnr, \irqnr, #8
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tsteq \irqstat, #0xff
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moveq \irqstat, \irqstat, lsr #8
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addeq \irqnr, \irqnr, #8
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tst \irqstat, #0x0f
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moveq \irqstat, \irqstat, lsr #4
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addeq \irqnr, \irqnr, #4
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tst \irqstat, #0x03
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moveq \irqstat, \irqstat, lsr #2
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addeq \irqnr, \irqnr, #2
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tst \irqstat, #0x01
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addeqs \irqnr, \irqnr, #1
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1001:
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.endm
|
||||
39
arch/arm/mach-ks8695/include/mach/gpio-ks8695.h
Normal file
39
arch/arm/mach-ks8695/include/mach/gpio-ks8695.h
Normal file
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|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright (C) 2006 Andrew Victor
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_KS8659_GPIO_H
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#define __MACH_KS8659_GPIO_H
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#include <linux/kernel.h>
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#define KS8695_GPIO_0 0
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#define KS8695_GPIO_1 1
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#define KS8695_GPIO_2 2
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#define KS8695_GPIO_3 3
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#define KS8695_GPIO_4 4
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#define KS8695_GPIO_5 5
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#define KS8695_GPIO_6 6
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#define KS8695_GPIO_7 7
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#define KS8695_GPIO_8 8
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#define KS8695_GPIO_9 9
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#define KS8695_GPIO_10 10
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#define KS8695_GPIO_11 11
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#define KS8695_GPIO_12 12
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#define KS8695_GPIO_13 13
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#define KS8695_GPIO_14 14
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#define KS8695_GPIO_15 15
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|
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/*
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* Configure GPIO pin as external interrupt source.
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*/
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extern int ks8695_gpio_interrupt(unsigned int pin, unsigned int type);
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|
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/* Register the GPIOs */
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extern void ks8695_register_gpios(void);
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|
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#endif /* __MACH_KS8659_GPIO_H */
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45
arch/arm/mach-ks8695/include/mach/hardware.h
Normal file
45
arch/arm/mach-ks8695/include/mach/hardware.h
Normal file
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|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/hardware.h
|
||||
*
|
||||
* Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
|
||||
* Copyright (C) 2006 Simtec Electronics
|
||||
*
|
||||
* KS8695 - Memory Map definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
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||||
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||||
#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <asm/sizes.h>
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|
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/*
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* Clocks are derived from MCLK, which is 25Mhz
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||||
*/
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#define KS8695_CLOCK_RATE 25000000
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|
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/*
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* Physical RAM address.
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*/
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#define KS8695_SDRAM_PA 0x00000000
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|
||||
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||||
/*
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* We map an entire MiB with the System Configuration Registers in even
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* though only 64KiB is needed. This makes it easier for use with the
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* head debug code as the initial MMU setup only deals in L1 sections.
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||||
*/
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#define KS8695_IO_PA 0x03F00000
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#define KS8695_IO_VA IOMEM(0xF0000000)
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#define KS8695_IO_SIZE SZ_1M
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#define KS8695_PCIMEM_PA 0x60000000
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#define KS8695_PCIMEM_SIZE SZ_512M
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#define KS8695_PCIIO_PA 0x80000000
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#define KS8695_PCIIO_SIZE SZ_64K
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#endif
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54
arch/arm/mach-ks8695/include/mach/irqs.h
Normal file
54
arch/arm/mach-ks8695/include/mach/irqs.h
Normal file
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|
@ -0,0 +1,54 @@
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|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/irqs.h
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||||
*
|
||||
* Copyright (C) 2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
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||||
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||||
#ifndef __ASM_ARCH_IRQS_H
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#define __ASM_ARCH_IRQS_H
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||||
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#define NR_IRQS 32
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/*
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* IRQ definitions
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||||
*/
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#define KS8695_IRQ_COMM_RX 0
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#define KS8695_IRQ_COMM_TX 1
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#define KS8695_IRQ_EXTERN0 2
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#define KS8695_IRQ_EXTERN1 3
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#define KS8695_IRQ_EXTERN2 4
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#define KS8695_IRQ_EXTERN3 5
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#define KS8695_IRQ_TIMER0 6
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#define KS8695_IRQ_TIMER1 7
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#define KS8695_IRQ_UART_TX 8
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#define KS8695_IRQ_UART_RX 9
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#define KS8695_IRQ_UART_LINE_STATUS 10
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#define KS8695_IRQ_UART_MODEM_STATUS 11
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#define KS8695_IRQ_LAN_RX_STOP 12
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#define KS8695_IRQ_LAN_TX_STOP 13
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#define KS8695_IRQ_LAN_RX_BUF 14
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#define KS8695_IRQ_LAN_TX_BUF 15
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#define KS8695_IRQ_LAN_RX_STATUS 16
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#define KS8695_IRQ_LAN_TX_STATUS 17
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#define KS8695_IRQ_HPNA_RX_STOP 18
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#define KS8695_IRQ_HPNA_TX_STOP 19
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#define KS8695_IRQ_HPNA_RX_BUF 20
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#define KS8695_IRQ_HPNA_TX_BUF 21
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#define KS8695_IRQ_HPNA_RX_STATUS 22
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#define KS8695_IRQ_HPNA_TX_STATUS 23
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#define KS8695_IRQ_BUS_ERROR 24
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#define KS8695_IRQ_WAN_RX_STOP 25
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#define KS8695_IRQ_WAN_TX_STOP 26
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||||
#define KS8695_IRQ_WAN_RX_BUF 27
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#define KS8695_IRQ_WAN_TX_BUF 28
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||||
#define KS8695_IRQ_WAN_RX_STATUS 29
|
||||
#define KS8695_IRQ_WAN_TX_STATUS 30
|
||||
#define KS8695_IRQ_WAN_LINK 31
|
||||
|
||||
#endif
|
||||
51
arch/arm/mach-ks8695/include/mach/memory.h
Normal file
51
arch/arm/mach-ks8695/include/mach/memory.h
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/memory.h
|
||||
*
|
||||
* Copyright (C) 2006 Andrew Victor
|
||||
*
|
||||
* KS8695 Memory definitions
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MEMORY_H
|
||||
#define __ASM_ARCH_MEMORY_H
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
|
||||
/* PCI mappings */
|
||||
#define __virt_to_bus(x) ((x) - PAGE_OFFSET + KS8695_PCIMEM_PA)
|
||||
#define __bus_to_virt(x) ((x) - KS8695_PCIMEM_PA + PAGE_OFFSET)
|
||||
|
||||
/* Platform-bus mapping */
|
||||
extern struct bus_type platform_bus_type;
|
||||
#define is_lbus_device(dev) (dev && dev->bus == &platform_bus_type)
|
||||
#define __arch_dma_to_virt(dev, x) ({ (void *) (is_lbus_device(dev) ? \
|
||||
__phys_to_virt(x) : __bus_to_virt(x)); })
|
||||
#define __arch_virt_to_dma(dev, x) ({ is_lbus_device(dev) ? \
|
||||
(dma_addr_t)__virt_to_phys((unsigned long)x) \
|
||||
: (dma_addr_t)__virt_to_bus(x); })
|
||||
#define __arch_pfn_to_dma(dev, pfn) \
|
||||
({ dma_addr_t __dma = __pfn_to_phys(pfn); \
|
||||
if (!is_lbus_device(dev)) \
|
||||
__dma = __dma - PHYS_OFFSET + KS8695_PCIMEM_PA; \
|
||||
__dma; })
|
||||
|
||||
#define __arch_dma_to_pfn(dev, x) \
|
||||
({ dma_addr_t __dma = x; \
|
||||
if (!is_lbus_device(dev)) \
|
||||
__dma += PHYS_OFFSET - KS8695_PCIMEM_PA; \
|
||||
__phys_to_pfn(__dma); \
|
||||
})
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
55
arch/arm/mach-ks8695/include/mach/regs-gpio.h
Normal file
55
arch/arm/mach-ks8695/include/mach/regs-gpio.h
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/regs-gpio.h
|
||||
*
|
||||
* Copyright (C) 2007 Andrew Victor
|
||||
*
|
||||
* KS8695 - GPIO control registers and bit definitions.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef KS8695_GPIO_H
|
||||
#define KS8695_GPIO_H
|
||||
|
||||
#define KS8695_GPIO_OFFSET (0xF0000 + 0xE600)
|
||||
#define KS8695_GPIO_VA (KS8695_IO_VA + KS8695_GPIO_OFFSET)
|
||||
#define KS8695_GPIO_PA (KS8695_IO_PA + KS8695_GPIO_OFFSET)
|
||||
|
||||
|
||||
#define KS8695_IOPM (0x00) /* I/O Port Mode Register */
|
||||
#define KS8695_IOPC (0x04) /* I/O Port Control Register */
|
||||
#define KS8695_IOPD (0x08) /* I/O Port Data Register */
|
||||
|
||||
|
||||
/* Port Mode Register */
|
||||
#define IOPM(x) (1 << (x)) /* Mode for GPIO Pin x */
|
||||
|
||||
/* Port Control Register */
|
||||
#define IOPC_IOTIM1EN (1 << 17) /* GPIO Pin for Timer1 Enable */
|
||||
#define IOPC_IOTIM0EN (1 << 16) /* GPIO Pin for Timer0 Enable */
|
||||
#define IOPC_IOEINT3EN (1 << 15) /* GPIO Pin for External/Soft Interrupt 3 Enable */
|
||||
#define IOPC_IOEINT3TM (7 << 12) /* GPIO Pin for External/Soft Interrupt 3 Trigger Mode */
|
||||
#define IOPC_IOEINT3_MODE(x) ((x) << 12)
|
||||
#define IOPC_IOEINT2EN (1 << 11) /* GPIO Pin for External/Soft Interrupt 2 Enable */
|
||||
#define IOPC_IOEINT2TM (7 << 8) /* GPIO Pin for External/Soft Interrupt 2 Trigger Mode */
|
||||
#define IOPC_IOEINT2_MODE(x) ((x) << 8)
|
||||
#define IOPC_IOEINT1EN (1 << 7) /* GPIO Pin for External/Soft Interrupt 1 Enable */
|
||||
#define IOPC_IOEINT1TM (7 << 4) /* GPIO Pin for External/Soft Interrupt 1 Trigger Mode */
|
||||
#define IOPC_IOEINT1_MODE(x) ((x) << 4)
|
||||
#define IOPC_IOEINT0EN (1 << 3) /* GPIO Pin for External/Soft Interrupt 0 Enable */
|
||||
#define IOPC_IOEINT0TM (7 << 0) /* GPIO Pin for External/Soft Interrupt 0 Trigger Mode */
|
||||
#define IOPC_IOEINT0_MODE(x) ((x) << 0)
|
||||
|
||||
/* Trigger Modes */
|
||||
#define IOPC_TM_LOW (0) /* Level Detection (Active Low) */
|
||||
#define IOPC_TM_HIGH (1) /* Level Detection (Active High) */
|
||||
#define IOPC_TM_RISING (2) /* Rising Edge Detection */
|
||||
#define IOPC_TM_FALLING (4) /* Falling Edge Detection */
|
||||
#define IOPC_TM_EDGE (6) /* Both Edge Detection */
|
||||
|
||||
/* Port Data Register */
|
||||
#define IOPD(x) (1 << (x)) /* Signal Level of GPIO Pin x */
|
||||
|
||||
#endif
|
||||
25
arch/arm/mach-ks8695/include/mach/regs-hpna.h
Normal file
25
arch/arm/mach-ks8695/include/mach/regs-hpna.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/regs-wan.h
|
||||
*
|
||||
* Copyright (C) 2006 Andrew Victor
|
||||
*
|
||||
* KS8695 - HPNA Registers and bit definitions.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef KS8695_HPNA_H
|
||||
#define KS8695_HPNA_H
|
||||
|
||||
#define KS8695_HPNA_OFFSET (0xF0000 + 0xA000)
|
||||
#define KS8695_HPNA_VA (KS8695_IO_VA + KS8695_HPNA_OFFSET)
|
||||
#define KS8695_HPNA_PA (KS8695_IO_PA + KS8695_HPNA_OFFSET)
|
||||
|
||||
|
||||
/*
|
||||
* HPNA registers
|
||||
*/
|
||||
|
||||
#endif
|
||||
41
arch/arm/mach-ks8695/include/mach/regs-irq.h
Normal file
41
arch/arm/mach-ks8695/include/mach/regs-irq.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/regs-irq.h
|
||||
*
|
||||
* Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
|
||||
* Copyright (C) 2006 Simtec Electronics
|
||||
*
|
||||
* KS8695 - IRQ registers and bit definitions
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef KS8695_IRQ_H
|
||||
#define KS8695_IRQ_H
|
||||
|
||||
#define KS8695_IRQ_OFFSET (0xF0000 + 0xE200)
|
||||
#define KS8695_IRQ_VA (KS8695_IO_VA + KS8695_IRQ_OFFSET)
|
||||
#define KS8695_IRQ_PA (KS8695_IO_PA + KS8695_IRQ_OFFSET)
|
||||
|
||||
|
||||
/*
|
||||
* Interrupt Controller registers
|
||||
*/
|
||||
#define KS8695_INTMC (0x00) /* Mode Control Register */
|
||||
#define KS8695_INTEN (0x04) /* Interrupt Enable Register */
|
||||
#define KS8695_INTST (0x08) /* Interrupt Status Register */
|
||||
#define KS8695_INTPW (0x0c) /* Interrupt Priority (WAN MAC) */
|
||||
#define KS8695_INTPH (0x10) /* Interrupt Priority (HPNA) [KS8695 only] */
|
||||
#define KS8695_INTPL (0x14) /* Interrupt Priority (LAN MAC) */
|
||||
#define KS8695_INTPT (0x18) /* Interrupt Priority (Timer) */
|
||||
#define KS8695_INTPU (0x1c) /* Interrupt Priority (UART) */
|
||||
#define KS8695_INTPE (0x20) /* Interrupt Priority (External Interrupt) */
|
||||
#define KS8695_INTPC (0x24) /* Interrupt Priority (Communications Channel) */
|
||||
#define KS8695_INTPBE (0x28) /* Interrupt Priority (Bus Error Response) */
|
||||
#define KS8695_INTMS (0x2c) /* Interrupt Mask Status Register */
|
||||
#define KS8695_INTHPF (0x30) /* Interrupt Pending Highest Priority (FIQ) */
|
||||
#define KS8695_INTHPI (0x34) /* Interrupt Pending Highest Priority (IRQ) */
|
||||
|
||||
|
||||
#endif
|
||||
65
arch/arm/mach-ks8695/include/mach/regs-lan.h
Normal file
65
arch/arm/mach-ks8695/include/mach/regs-lan.h
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/regs-lan.h
|
||||
*
|
||||
* Copyright (C) 2006 Andrew Victor
|
||||
*
|
||||
* KS8695 - LAN Registers and bit definitions.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef KS8695_LAN_H
|
||||
#define KS8695_LAN_H
|
||||
|
||||
#define KS8695_LAN_OFFSET (0xF0000 + 0x8000)
|
||||
#define KS8695_LAN_VA (KS8695_IO_VA + KS8695_LAN_OFFSET)
|
||||
#define KS8695_LAN_PA (KS8695_IO_PA + KS8695_LAN_OFFSET)
|
||||
|
||||
|
||||
/*
|
||||
* LAN registers
|
||||
*/
|
||||
#define KS8695_LMDTXC (0x00) /* DMA Transmit Control */
|
||||
#define KS8695_LMDRXC (0x04) /* DMA Receive Control */
|
||||
#define KS8695_LMDTSC (0x08) /* DMA Transmit Start Command */
|
||||
#define KS8695_LMDRSC (0x0c) /* DMA Receive Start Command */
|
||||
#define KS8695_LTDLB (0x10) /* Transmit Descriptor List Base Address */
|
||||
#define KS8695_LRDLB (0x14) /* Receive Descriptor List Base Address */
|
||||
#define KS8695_LMAL (0x18) /* MAC Station Address Low */
|
||||
#define KS8695_LMAH (0x1c) /* MAC Station Address High */
|
||||
#define KS8695_LMAAL(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */
|
||||
#define KS8695_LMAAH(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */
|
||||
|
||||
|
||||
/* DMA Transmit Control Register */
|
||||
#define LMDTXC_LMTRST (1 << 31) /* Soft Reset */
|
||||
#define LMDTXC_LMTBS (0x3f << 24) /* Transmit Burst Size */
|
||||
#define LMDTXC_LMTUCG (1 << 18) /* Transmit UDP Checksum Generate */
|
||||
#define LMDTXC_LMTTCG (1 << 17) /* Transmit TCP Checksum Generate */
|
||||
#define LMDTXC_LMTICG (1 << 16) /* Transmit IP Checksum Generate */
|
||||
#define LMDTXC_LMTFCE (1 << 9) /* Transmit Flow Control Enable */
|
||||
#define LMDTXC_LMTLB (1 << 8) /* Loopback mode */
|
||||
#define LMDTXC_LMTEP (1 << 2) /* Transmit Enable Padding */
|
||||
#define LMDTXC_LMTAC (1 << 1) /* Transmit Add CRC */
|
||||
#define LMDTXC_LMTE (1 << 0) /* TX Enable */
|
||||
|
||||
/* DMA Receive Control Register */
|
||||
#define LMDRXC_LMRBS (0x3f << 24) /* Receive Burst Size */
|
||||
#define LMDRXC_LMRUCC (1 << 18) /* Receive UDP Checksum check */
|
||||
#define LMDRXC_LMRTCG (1 << 17) /* Receive TCP Checksum check */
|
||||
#define LMDRXC_LMRICG (1 << 16) /* Receive IP Checksum check */
|
||||
#define LMDRXC_LMRFCE (1 << 9) /* Receive Flow Control Enable */
|
||||
#define LMDRXC_LMRB (1 << 6) /* Receive Broadcast */
|
||||
#define LMDRXC_LMRM (1 << 5) /* Receive Multicast */
|
||||
#define LMDRXC_LMRU (1 << 4) /* Receive Unicast */
|
||||
#define LMDRXC_LMRERR (1 << 3) /* Receive Error Frame */
|
||||
#define LMDRXC_LMRA (1 << 2) /* Receive All */
|
||||
#define LMDRXC_LMRE (1 << 1) /* RX Enable */
|
||||
|
||||
/* Additional Station Address High */
|
||||
#define LMAAH_E (1 << 31) /* Address Enabled */
|
||||
|
||||
|
||||
#endif
|
||||
89
arch/arm/mach-ks8695/include/mach/regs-mem.h
Normal file
89
arch/arm/mach-ks8695/include/mach/regs-mem.h
Normal file
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/regs-mem.h
|
||||
*
|
||||
* Copyright (C) 2006 Andrew Victor
|
||||
*
|
||||
* KS8695 - Memory Controller registers and bit definitions
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef KS8695_MEM_H
|
||||
#define KS8695_MEM_H
|
||||
|
||||
#define KS8695_MEM_OFFSET (0xF0000 + 0x4000)
|
||||
#define KS8695_MEM_VA (KS8695_IO_VA + KS8695_MEM_OFFSET)
|
||||
#define KS8695_MEM_PA (KS8695_IO_PA + KS8695_MEM_OFFSET)
|
||||
|
||||
|
||||
/*
|
||||
* Memory Controller Registers
|
||||
*/
|
||||
#define KS8695_EXTACON0 (0x00) /* External I/O 0 Access Control */
|
||||
#define KS8695_EXTACON1 (0x04) /* External I/O 1 Access Control */
|
||||
#define KS8695_EXTACON2 (0x08) /* External I/O 2 Access Control */
|
||||
#define KS8695_ROMCON0 (0x10) /* ROM/SRAM/Flash 1 Control Register */
|
||||
#define KS8695_ROMCON1 (0x14) /* ROM/SRAM/Flash 2 Control Register */
|
||||
#define KS8695_ERGCON (0x20) /* External I/O and ROM/SRAM/Flash General Register */
|
||||
#define KS8695_SDCON0 (0x30) /* SDRAM Control Register 0 */
|
||||
#define KS8695_SDCON1 (0x34) /* SDRAM Control Register 1 */
|
||||
#define KS8695_SDGCON (0x38) /* SDRAM General Control */
|
||||
#define KS8695_SDBCON (0x3c) /* SDRAM Buffer Control */
|
||||
#define KS8695_REFTIM (0x40) /* SDRAM Refresh Timer */
|
||||
|
||||
|
||||
/* External I/O Access Control Registers */
|
||||
#define EXTACON_EBNPTR (0x3ff << 22) /* Last Address Pointer */
|
||||
#define EXTACON_EBBPTR (0x3ff << 12) /* Base Pointer */
|
||||
#define EXTACON_EBTACT (7 << 9) /* Write Enable/Output Enable Active Time */
|
||||
#define EXTACON_EBTCOH (7 << 6) /* Chip Select Hold Time */
|
||||
#define EXTACON_EBTACS (7 << 3) /* Address Setup Time before ECSN */
|
||||
#define EXTACON_EBTCOS (7 << 0) /* Chip Select Time before OEN */
|
||||
|
||||
/* ROM/SRAM/Flash Control Register */
|
||||
#define ROMCON_RBNPTR (0x3ff << 22) /* Next Pointer */
|
||||
#define ROMCON_RBBPTR (0x3ff << 12) /* Base Pointer */
|
||||
#define ROMCON_RBTACC (7 << 4) /* Access Cycle Time */
|
||||
#define ROMCON_RBTPA (3 << 2) /* Page Address Access Time */
|
||||
#define ROMCON_PMC (3 << 0) /* Page Mode Configuration */
|
||||
#define PMC_NORMAL (0 << 0)
|
||||
#define PMC_4WORD (1 << 0)
|
||||
#define PMC_8WORD (2 << 0)
|
||||
#define PMC_16WORD (3 << 0)
|
||||
|
||||
/* External I/O and ROM/SRAM/Flash General Register */
|
||||
#define ERGCON_TMULT (3 << 28) /* Time Multiplier */
|
||||
#define ERGCON_DSX2 (3 << 20) /* Data Width (External I/O Bank 2) */
|
||||
#define ERGCON_DSX1 (3 << 18) /* Data Width (External I/O Bank 1) */
|
||||
#define ERGCON_DSX0 (3 << 16) /* Data Width (External I/O Bank 0) */
|
||||
#define ERGCON_DSR1 (3 << 2) /* Data Width (ROM/SRAM/Flash Bank 1) */
|
||||
#define ERGCON_DSR0 (3 << 0) /* Data Width (ROM/SRAM/Flash Bank 0) */
|
||||
|
||||
/* SDRAM Control Register */
|
||||
#define SDCON_DBNPTR (0x3ff << 22) /* Last Address Pointer */
|
||||
#define SDCON_DBBPTR (0x3ff << 12) /* Base Pointer */
|
||||
#define SDCON_DBCAB (3 << 8) /* Column Address Bits */
|
||||
#define SDCON_DBBNUM (1 << 3) /* Number of Banks */
|
||||
#define SDCON_DBDBW (3 << 1) /* Data Bus Width */
|
||||
|
||||
/* SDRAM General Control Register */
|
||||
#define SDGCON_SDTRC (3 << 2) /* RAS to CAS latency */
|
||||
#define SDGCON_SDCAS (3 << 0) /* CAS latency */
|
||||
|
||||
/* SDRAM Buffer Control Register */
|
||||
#define SDBCON_SDESTA (1 << 31) /* SDRAM Engine Status */
|
||||
#define SDBCON_RBUFBDIS (1 << 24) /* Read Buffer Burst Enable */
|
||||
#define SDBCON_WFIFOEN (1 << 23) /* Write FIFO Enable */
|
||||
#define SDBCON_RBUFEN (1 << 22) /* Read Buffer Enable */
|
||||
#define SDBCON_FLUSHWFIFO (1 << 21) /* Flush Write FIFO */
|
||||
#define SDBCON_RBUFINV (1 << 20) /* Read Buffer Invalidate */
|
||||
#define SDBCON_SDINI (3 << 16) /* SDRAM Initialization Control */
|
||||
#define SDBCON_SDMODE (0x3fff << 0) /* SDRAM Mode Register Value Program */
|
||||
|
||||
/* SDRAM Refresh Timer Register */
|
||||
#define REFTIM_REFTIM (0xffff << 0) /* Refresh Timer Value */
|
||||
|
||||
|
||||
#endif
|
||||
97
arch/arm/mach-ks8695/include/mach/regs-misc.h
Normal file
97
arch/arm/mach-ks8695/include/mach/regs-misc.h
Normal file
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/regs-misc.h
|
||||
*
|
||||
* Copyright (C) 2006 Andrew Victor
|
||||
*
|
||||
* KS8695 - Miscellaneous Registers
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef KS8695_MISC_H
|
||||
#define KS8695_MISC_H
|
||||
|
||||
#define KS8695_MISC_OFFSET (0xF0000 + 0xEA00)
|
||||
#define KS8695_MISC_VA (KS8695_IO_VA + KS8695_MISC_OFFSET)
|
||||
#define KS8695_MISC_PA (KS8695_IO_PA + KS8695_MISC_OFFSET)
|
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous registers
|
||||
*/
|
||||
#define KS8695_DID (0x00) /* Device ID */
|
||||
#define KS8695_RID (0x04) /* Revision ID */
|
||||
#define KS8695_HMC (0x08) /* HPNA Miscellaneous Control [KS8695 only] */
|
||||
#define KS8695_WMC (0x0c) /* WAN Miscellaneous Control */
|
||||
#define KS8695_WPPM (0x10) /* WAN PHY Power Management */
|
||||
#define KS8695_PPS (0x1c) /* PHY PowerSave */
|
||||
|
||||
/* Device ID Register */
|
||||
#define DID_ID (0xffff << 0) /* Device ID */
|
||||
|
||||
/* Revision ID Register */
|
||||
#define RID_SUBID (0xf << 4) /* Sub-Device ID */
|
||||
#define RID_REVISION (0xf << 0) /* Revision ID */
|
||||
|
||||
/* HPNA Miscellaneous Control Register */
|
||||
#define HMC_HSS (1 << 1) /* Speed */
|
||||
#define HMC_HDS (1 << 0) /* Duplex */
|
||||
|
||||
/* WAN Miscellaneous Control Register */
|
||||
#define WMC_WANC (1 << 30) /* Auto-negotiation complete */
|
||||
#define WMC_WANR (1 << 29) /* Auto-negotiation restart */
|
||||
#define WMC_WANAP (1 << 28) /* Advertise Pause */
|
||||
#define WMC_WANA100F (1 << 27) /* Advertise 100 FDX */
|
||||
#define WMC_WANA100H (1 << 26) /* Advertise 100 HDX */
|
||||
#define WMC_WANA10F (1 << 25) /* Advertise 10 FDX */
|
||||
#define WMC_WANA10H (1 << 24) /* Advertise 10 HDX */
|
||||
#define WMC_WLS (1 << 23) /* Link status */
|
||||
#define WMC_WDS (1 << 22) /* Duplex status */
|
||||
#define WMC_WSS (1 << 21) /* Speed status */
|
||||
#define WMC_WLPP (1 << 20) /* Link Partner Pause */
|
||||
#define WMC_WLP100F (1 << 19) /* Link Partner 100 FDX */
|
||||
#define WMC_WLP100H (1 << 18) /* Link Partner 100 HDX */
|
||||
#define WMC_WLP10F (1 << 17) /* Link Partner 10 FDX */
|
||||
#define WMC_WLP10H (1 << 16) /* Link Partner 10 HDX */
|
||||
#define WMC_WAND (1 << 15) /* Auto-negotiation disable */
|
||||
#define WMC_WANF100 (1 << 14) /* Force 100 */
|
||||
#define WMC_WANFF (1 << 13) /* Force FDX */
|
||||
#define WMC_WLED1S (7 << 4) /* LED1 Select */
|
||||
#define WLED1S_SPEED (0 << 4)
|
||||
#define WLED1S_LINK (1 << 4)
|
||||
#define WLED1S_DUPLEX (2 << 4)
|
||||
#define WLED1S_COLLISION (3 << 4)
|
||||
#define WLED1S_ACTIVITY (4 << 4)
|
||||
#define WLED1S_FDX_COLLISION (5 << 4)
|
||||
#define WLED1S_LINK_ACTIVITY (6 << 4)
|
||||
#define WMC_WLED0S (7 << 0) /* LED0 Select */
|
||||
#define WLED0S_SPEED (0 << 0)
|
||||
#define WLED0S_LINK (1 << 0)
|
||||
#define WLED0S_DUPLEX (2 << 0)
|
||||
#define WLED0S_COLLISION (3 << 0)
|
||||
#define WLED0S_ACTIVITY (4 << 0)
|
||||
#define WLED0S_FDX_COLLISION (5 << 0)
|
||||
#define WLED0S_LINK_ACTIVITY (6 << 0)
|
||||
|
||||
/* WAN PHY Power Management Register */
|
||||
#define WPPM_WLPBK (1 << 14) /* Local Loopback */
|
||||
#define WPPM_WRLPKB (1 << 13) /* Remove Loopback */
|
||||
#define WPPM_WPI (1 << 12) /* PHY isolate */
|
||||
#define WPPM_WFL (1 << 10) /* Force link */
|
||||
#define WPPM_MDIXS (1 << 9) /* MDIX Status */
|
||||
#define WPPM_FEF (1 << 8) /* Far End Fault */
|
||||
#define WPPM_AMDIXP (1 << 7) /* Auto MDIX Parameter */
|
||||
#define WPPM_TXDIS (1 << 6) /* Disable transmitter */
|
||||
#define WPPM_DFEF (1 << 5) /* Disable Far End Fault */
|
||||
#define WPPM_PD (1 << 4) /* Power Down */
|
||||
#define WPPM_DMDX (1 << 3) /* Disable Auto MDI/MDIX */
|
||||
#define WPPM_FMDX (1 << 2) /* Force MDIX */
|
||||
#define WPPM_LPBK (1 << 1) /* MAX Loopback */
|
||||
|
||||
/* PHY Power Save Register */
|
||||
#define PPS_PPSM (1 << 0) /* PHY Power Save Mode */
|
||||
|
||||
|
||||
#endif
|
||||
53
arch/arm/mach-ks8695/include/mach/regs-pci.h
Normal file
53
arch/arm/mach-ks8695/include/mach/regs-pci.h
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/regs-pci.h
|
||||
*
|
||||
* Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
|
||||
* Copyright (C) 2006 Simtec Electronics
|
||||
*
|
||||
* KS8695 - PCI bridge registers and bit definitions.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#define KS8695_PCI_OFFSET (0xF0000 + 0x2000)
|
||||
#define KS8695_PCI_VA (KS8695_IO_VA + KS8695_PCI_OFFSET)
|
||||
#define KS8695_PCI_PA (KS8695_IO_PA + KS8695_PCI_OFFSET)
|
||||
|
||||
|
||||
#define KS8695_CRCFID (0x000) /* Configuration: Identification */
|
||||
#define KS8695_CRCFCS (0x004) /* Configuration: Command and Status */
|
||||
#define KS8695_CRCFRV (0x008) /* Configuration: Revision */
|
||||
#define KS8695_CRCFLT (0x00C) /* Configuration: Latency Timer */
|
||||
#define KS8695_CRCBMA (0x010) /* Configuration: Base Memory Address */
|
||||
#define KS8695_CRCSID (0x02C) /* Configuration: Subsystem ID */
|
||||
#define KS8695_CRCFIT (0x03C) /* Configuration: Interrupt */
|
||||
#define KS8695_PBCA (0x100) /* Bridge Configuration Address */
|
||||
#define KS8695_PBCD (0x104) /* Bridge Configuration Data */
|
||||
#define KS8695_PBM (0x200) /* Bridge Mode */
|
||||
#define KS8695_PBCS (0x204) /* Bridge Control and Status */
|
||||
#define KS8695_PMBA (0x208) /* Bridge Memory Base Address */
|
||||
#define KS8695_PMBAC (0x20C) /* Bridge Memory Base Address Control */
|
||||
#define KS8695_PMBAM (0x210) /* Bridge Memory Base Address Mask */
|
||||
#define KS8695_PMBAT (0x214) /* Bridge Memory Base Address Translation */
|
||||
#define KS8695_PIOBA (0x218) /* Bridge I/O Base Address */
|
||||
#define KS8695_PIOBAC (0x21C) /* Bridge I/O Base Address Control */
|
||||
#define KS8695_PIOBAM (0x220) /* Bridge I/O Base Address Mask */
|
||||
#define KS8695_PIOBAT (0x224) /* Bridge I/O Base Address Translation */
|
||||
|
||||
|
||||
/* Configuration: Identification */
|
||||
|
||||
/* Configuration: Command and Status */
|
||||
|
||||
/* Configuration: Revision */
|
||||
|
||||
|
||||
|
||||
#define CFRV_GUEST (1 << 23)
|
||||
|
||||
#define PBCA_TYPE1 (1)
|
||||
#define PBCA_ENABLE (1 << 31)
|
||||
|
||||
|
||||
66
arch/arm/mach-ks8695/include/mach/regs-switch.h
Normal file
66
arch/arm/mach-ks8695/include/mach/regs-switch.h
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/regs-switch.h
|
||||
*
|
||||
* Copyright (C) 2006 Andrew Victor
|
||||
*
|
||||
* KS8695 - Switch Registers and bit definitions.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef KS8695_SWITCH_H
|
||||
#define KS8695_SWITCH_H
|
||||
|
||||
#define KS8695_SWITCH_OFFSET (0xF0000 + 0xe800)
|
||||
#define KS8695_SWITCH_VA (KS8695_IO_VA + KS8695_SWITCH_OFFSET)
|
||||
#define KS8695_SWITCH_PA (KS8695_IO_PA + KS8695_SWITCH_OFFSET)
|
||||
|
||||
|
||||
/*
|
||||
* Switch registers
|
||||
*/
|
||||
#define KS8695_SEC0 (0x00) /* Switch Engine Control 0 */
|
||||
#define KS8695_SEC1 (0x04) /* Switch Engine Control 1 */
|
||||
#define KS8695_SEC2 (0x08) /* Switch Engine Control 2 */
|
||||
|
||||
#define KS8695_SEPXCZ(x,z) (0x0c + (((x)-1)*3 + ((z)-1))*4) /* Port Configuration Registers */
|
||||
|
||||
#define KS8695_SEP12AN (0x48) /* Port 1 & 2 Auto-Negotiation */
|
||||
#define KS8695_SEP34AN (0x4c) /* Port 3 & 4 Auto-Negotiation */
|
||||
#define KS8695_SEIAC (0x50) /* Indirect Access Control */
|
||||
#define KS8695_SEIADH2 (0x54) /* Indirect Access Data High 2 */
|
||||
#define KS8695_SEIADH1 (0x58) /* Indirect Access Data High 1 */
|
||||
#define KS8695_SEIADL (0x5c) /* Indirect Access Data Low */
|
||||
#define KS8695_SEAFC (0x60) /* Advance Feature Control */
|
||||
#define KS8695_SEDSCPH (0x64) /* TOS Priority High */
|
||||
#define KS8695_SEDSCPL (0x68) /* TOS Priority Low */
|
||||
#define KS8695_SEMAH (0x6c) /* Switch Engine MAC Address High */
|
||||
#define KS8695_SEMAL (0x70) /* Switch Engine MAC Address Low */
|
||||
#define KS8695_LPPM12 (0x74) /* Port 1 & 2 PHY Power Management */
|
||||
#define KS8695_LPPM34 (0x78) /* Port 3 & 4 PHY Power Management */
|
||||
|
||||
|
||||
/* Switch Engine Control 0 */
|
||||
#define SEC0_LLED1S (7 << 25) /* LED1 Select */
|
||||
#define LLED1S_SPEED (0 << 25)
|
||||
#define LLED1S_LINK (1 << 25)
|
||||
#define LLED1S_DUPLEX (2 << 25)
|
||||
#define LLED1S_COLLISION (3 << 25)
|
||||
#define LLED1S_ACTIVITY (4 << 25)
|
||||
#define LLED1S_FDX_COLLISION (5 << 25)
|
||||
#define LLED1S_LINK_ACTIVITY (6 << 25)
|
||||
#define SEC0_LLED0S (7 << 22) /* LED0 Select */
|
||||
#define LLED0S_SPEED (0 << 22)
|
||||
#define LLED0S_LINK (1 << 22)
|
||||
#define LLED0S_DUPLEX (2 << 22)
|
||||
#define LLED0S_COLLISION (3 << 22)
|
||||
#define LLED0S_ACTIVITY (4 << 22)
|
||||
#define LLED0S_FDX_COLLISION (5 << 22)
|
||||
#define LLED0S_LINK_ACTIVITY (6 << 22)
|
||||
#define SEC0_ENABLE (1 << 0) /* Enable Switch */
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
34
arch/arm/mach-ks8695/include/mach/regs-sys.h
Normal file
34
arch/arm/mach-ks8695/include/mach/regs-sys.h
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/regs-sys.h
|
||||
*
|
||||
* Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
|
||||
* Copyright (C) 2006 Simtec Electronics
|
||||
*
|
||||
* KS8695 - System control registers and bit definitions
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef KS8695_SYS_H
|
||||
#define KS8695_SYS_H
|
||||
|
||||
#define KS8695_SYS_OFFSET (0xF0000 + 0x0000)
|
||||
#define KS8695_SYS_VA (KS8695_IO_VA + KS8695_SYS_OFFSET)
|
||||
#define KS8695_SYS_PA (KS8695_IO_PA + KS8695_SYS_OFFSET)
|
||||
|
||||
|
||||
#define KS8695_SYSCFG (0x00) /* System Configuration Register */
|
||||
#define KS8695_CLKCON (0x04) /* System Clock and Bus Control Register */
|
||||
|
||||
|
||||
/* System Configuration Register */
|
||||
#define SYSCFG_SPRBP (0x3ff << 16) /* Register Bank Base Pointer */
|
||||
|
||||
/* System Clock and Bus Control Register */
|
||||
#define CLKCON_SFMODE (1 << 8) /* System Fast Mode for Simulation */
|
||||
#define CLKCON_SCDC (7 << 0) /* System Clock Divider Select */
|
||||
|
||||
|
||||
#endif
|
||||
92
arch/arm/mach-ks8695/include/mach/regs-uart.h
Normal file
92
arch/arm/mach-ks8695/include/mach/regs-uart.h
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/regs-uart.h
|
||||
*
|
||||
* Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
|
||||
* Copyright (C) 2006 Simtec Electronics
|
||||
*
|
||||
* KS8695 - UART register and bit definitions.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef KS8695_UART_H
|
||||
#define KS8695_UART_H
|
||||
|
||||
#define KS8695_UART_OFFSET (0xF0000 + 0xE000)
|
||||
#define KS8695_UART_VA (KS8695_IO_VA + KS8695_UART_OFFSET)
|
||||
#define KS8695_UART_PA (KS8695_IO_PA + KS8695_UART_OFFSET)
|
||||
|
||||
|
||||
/*
|
||||
* UART registers
|
||||
*/
|
||||
#define KS8695_URRB (0x00) /* Receive Buffer Register */
|
||||
#define KS8695_URTH (0x04) /* Transmit Holding Register */
|
||||
#define KS8695_URFC (0x08) /* FIFO Control Register */
|
||||
#define KS8695_URLC (0x0C) /* Line Control Register */
|
||||
#define KS8695_URMC (0x10) /* Modem Control Register */
|
||||
#define KS8695_URLS (0x14) /* Line Status Register */
|
||||
#define KS8695_URMS (0x18) /* Modem Status Register */
|
||||
#define KS8695_URBD (0x1C) /* Baud Rate Divisor Register */
|
||||
#define KS8695_USR (0x20) /* Status Register */
|
||||
|
||||
|
||||
/* FIFO Control Register */
|
||||
#define URFC_URFRT (3 << 6) /* Receive FIFO Trigger Level */
|
||||
#define URFC_URFRT_1 (0 << 6)
|
||||
#define URFC_URFRT_4 (1 << 6)
|
||||
#define URFC_URFRT_8 (2 << 6)
|
||||
#define URFC_URFRT_14 (3 << 6)
|
||||
#define URFC_URTFR (1 << 2) /* Transmit FIFO Reset */
|
||||
#define URFC_URRFR (1 << 1) /* Receive FIFO Reset */
|
||||
#define URFC_URFE (1 << 0) /* FIFO Enable */
|
||||
|
||||
/* Line Control Register */
|
||||
#define URLC_URSBC (1 << 6) /* Set Break Condition */
|
||||
#define URLC_PARITY (7 << 3) /* Parity */
|
||||
#define URPE_NONE (0 << 3)
|
||||
#define URPE_ODD (1 << 3)
|
||||
#define URPE_EVEN (3 << 3)
|
||||
#define URPE_MARK (5 << 3)
|
||||
#define URPE_SPACE (7 << 3)
|
||||
#define URLC_URSB (1 << 2) /* Stop Bits */
|
||||
#define URLC_URCL (3 << 0) /* Character Length */
|
||||
#define URCL_5 (0 << 0)
|
||||
#define URCL_6 (1 << 0)
|
||||
#define URCL_7 (2 << 0)
|
||||
#define URCL_8 (3 << 0)
|
||||
|
||||
/* Modem Control Register */
|
||||
#define URMC_URLB (1 << 4) /* Loop-back mode */
|
||||
#define URMC_UROUT2 (1 << 3) /* OUT2 signal */
|
||||
#define URMC_UROUT1 (1 << 2) /* OUT1 signal */
|
||||
#define URMC_URRTS (1 << 1) /* Request to Send */
|
||||
#define URMC_URDTR (1 << 0) /* Data Terminal Ready */
|
||||
|
||||
/* Line Status Register */
|
||||
#define URLS_URRFE (1 << 7) /* Receive FIFO Error */
|
||||
#define URLS_URTE (1 << 6) /* Transmit Empty */
|
||||
#define URLS_URTHRE (1 << 5) /* Transmit Holding Register Empty */
|
||||
#define URLS_URBI (1 << 4) /* Break Interrupt */
|
||||
#define URLS_URFE (1 << 3) /* Framing Error */
|
||||
#define URLS_URPE (1 << 2) /* Parity Error */
|
||||
#define URLS_URROE (1 << 1) /* Receive Overrun Error */
|
||||
#define URLS_URDR (1 << 0) /* Receive Data Ready */
|
||||
|
||||
/* Modem Status Register */
|
||||
#define URMS_URDCD (1 << 7) /* Data Carrier Detect */
|
||||
#define URMS_URRI (1 << 6) /* Ring Indicator */
|
||||
#define URMS_URDSR (1 << 5) /* Data Set Ready */
|
||||
#define URMS_URCTS (1 << 4) /* Clear to Send */
|
||||
#define URMS_URDDCD (1 << 3) /* Delta Data Carrier Detect */
|
||||
#define URMS_URTERI (1 << 2) /* Trailing Edge Ring Indicator */
|
||||
#define URMS_URDDST (1 << 1) /* Delta Data Set Ready */
|
||||
#define URMS_URDCTS (1 << 0) /* Delta Clear to Send */
|
||||
|
||||
/* Status Register */
|
||||
#define USR_UTI (1 << 0) /* Timeout Indication */
|
||||
|
||||
|
||||
#endif
|
||||
65
arch/arm/mach-ks8695/include/mach/regs-wan.h
Normal file
65
arch/arm/mach-ks8695/include/mach/regs-wan.h
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/regs-wan.h
|
||||
*
|
||||
* Copyright (C) 2006 Andrew Victor
|
||||
*
|
||||
* KS8695 - WAN Registers and bit definitions.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef KS8695_WAN_H
|
||||
#define KS8695_WAN_H
|
||||
|
||||
#define KS8695_WAN_OFFSET (0xF0000 + 0x6000)
|
||||
#define KS8695_WAN_VA (KS8695_IO_VA + KS8695_WAN_OFFSET)
|
||||
#define KS8695_WAN_PA (KS8695_IO_PA + KS8695_WAN_OFFSET)
|
||||
|
||||
|
||||
/*
|
||||
* WAN registers
|
||||
*/
|
||||
#define KS8695_WMDTXC (0x00) /* DMA Transmit Control */
|
||||
#define KS8695_WMDRXC (0x04) /* DMA Receive Control */
|
||||
#define KS8695_WMDTSC (0x08) /* DMA Transmit Start Command */
|
||||
#define KS8695_WMDRSC (0x0c) /* DMA Receive Start Command */
|
||||
#define KS8695_WTDLB (0x10) /* Transmit Descriptor List Base Address */
|
||||
#define KS8695_WRDLB (0x14) /* Receive Descriptor List Base Address */
|
||||
#define KS8695_WMAL (0x18) /* MAC Station Address Low */
|
||||
#define KS8695_WMAH (0x1c) /* MAC Station Address High */
|
||||
#define KS8695_WMAAL(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */
|
||||
#define KS8695_WMAAH(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */
|
||||
|
||||
|
||||
/* DMA Transmit Control Register */
|
||||
#define WMDTXC_WMTRST (1 << 31) /* Soft Reset */
|
||||
#define WMDTXC_WMTBS (0x3f << 24) /* Transmit Burst Size */
|
||||
#define WMDTXC_WMTUCG (1 << 18) /* Transmit UDP Checksum Generate */
|
||||
#define WMDTXC_WMTTCG (1 << 17) /* Transmit TCP Checksum Generate */
|
||||
#define WMDTXC_WMTICG (1 << 16) /* Transmit IP Checksum Generate */
|
||||
#define WMDTXC_WMTFCE (1 << 9) /* Transmit Flow Control Enable */
|
||||
#define WMDTXC_WMTLB (1 << 8) /* Loopback mode */
|
||||
#define WMDTXC_WMTEP (1 << 2) /* Transmit Enable Padding */
|
||||
#define WMDTXC_WMTAC (1 << 1) /* Transmit Add CRC */
|
||||
#define WMDTXC_WMTE (1 << 0) /* TX Enable */
|
||||
|
||||
/* DMA Receive Control Register */
|
||||
#define WMDRXC_WMRBS (0x3f << 24) /* Receive Burst Size */
|
||||
#define WMDRXC_WMRUCC (1 << 18) /* Receive UDP Checksum check */
|
||||
#define WMDRXC_WMRTCG (1 << 17) /* Receive TCP Checksum check */
|
||||
#define WMDRXC_WMRICG (1 << 16) /* Receive IP Checksum check */
|
||||
#define WMDRXC_WMRFCE (1 << 9) /* Receive Flow Control Enable */
|
||||
#define WMDRXC_WMRB (1 << 6) /* Receive Broadcast */
|
||||
#define WMDRXC_WMRM (1 << 5) /* Receive Multicast */
|
||||
#define WMDRXC_WMRU (1 << 4) /* Receive Unicast */
|
||||
#define WMDRXC_WMRERR (1 << 3) /* Receive Error Frame */
|
||||
#define WMDRXC_WMRA (1 << 2) /* Receive All */
|
||||
#define WMDRXC_WMRE (1 << 0) /* RX Enable */
|
||||
|
||||
/* Additional Station Address High */
|
||||
#define WMAAH_E (1 << 31) /* Address Enabled */
|
||||
|
||||
|
||||
#endif
|
||||
36
arch/arm/mach-ks8695/include/mach/uncompress.h
Normal file
36
arch/arm/mach-ks8695/include/mach/uncompress.h
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* arch/arm/mach-ks8695/include/mach/uncompress.h
|
||||
*
|
||||
* Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
|
||||
* Copyright (C) 2006 Simtec Electronics
|
||||
*
|
||||
* KS8695 - Kernel uncompressor
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_UNCOMPRESS_H
|
||||
#define __ASM_ARCH_UNCOMPRESS_H
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <mach/regs-uart.h>
|
||||
|
||||
static void putc(char c)
|
||||
{
|
||||
while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE))
|
||||
barrier();
|
||||
|
||||
__raw_writel(c, (void __iomem*)KS8695_UART_PA + KS8695_URTH);
|
||||
}
|
||||
|
||||
static inline void flush(void)
|
||||
{
|
||||
while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTE))
|
||||
barrier();
|
||||
}
|
||||
|
||||
#define arch_decomp_setup()
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue