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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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109
arch/arm/mach-msm/Kconfig Normal file
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if ARCH_MSM
choice
prompt "Qualcomm MSM SoC Type"
default ARCH_MSM7X00A
depends on ARCH_MSM
config ARCH_MSM7X00A
bool "MSM7x00A / MSM7x01A"
select ARCH_MSM_ARM11
select CPU_V6
select GPIO_MSM_V1
select MACH_TROUT if !MACH_HALIBUT
select MSM_PROC_COMM
select MSM_SMD
select CLKSRC_QCOM
select MSM_SMD_PKG3
config ARCH_MSM7X30
bool "MSM7x30"
select ARCH_MSM_SCORPION
select CPU_V7
select GPIO_MSM_V1
select MACH_MSM7X30_SURF # if !
select MSM_GPIOMUX
select MSM_PROC_COMM
select MSM_SMD
select CLKSRC_QCOM
select MSM_VIC
config ARCH_QSD8X50
bool "QSD8X50"
select ARCH_MSM_SCORPION
select CPU_V7
select GPIO_MSM_V1
select MACH_QSD8X50_SURF if !MACH_QSD8X50A_ST1_5
select MSM_GPIOMUX
select MSM_PROC_COMM
select MSM_SMD
select CLKSRC_QCOM
select MSM_VIC
endchoice
config MSM_SOC_REV_A
bool
config ARCH_MSM_ARM11
bool
config ARCH_MSM_SCORPION
bool
config MSM_VIC
bool
menu "Qualcomm MSM Board Type"
depends on ARCH_MSM
config MACH_HALIBUT
depends on ARCH_MSM
depends on ARCH_MSM7X00A
bool "Halibut Board (QCT SURF7201A)"
help
Support for the Qualcomm SURF7201A eval board.
config MACH_TROUT
depends on ARCH_MSM
depends on ARCH_MSM7X00A
bool "HTC Dream (aka trout)"
help
Support for the HTC Dream, T-Mobile G1, Android ADP1 devices.
config MACH_MSM7X30_SURF
depends on ARCH_MSM7X30
bool "MSM7x30 SURF"
help
Support for the Qualcomm MSM7x30 SURF eval board.
config MACH_QSD8X50_SURF
depends on ARCH_QSD8X50
bool "QSD8x50 SURF"
help
Support for the Qualcomm QSD8x50 SURF eval board.
config MACH_QSD8X50A_ST1_5
depends on ARCH_QSD8X50
bool "QSD8x50A ST1.5"
select MSM_SOC_REV_A
help
Support for the Qualcomm ST1.5.
endmenu
config MSM_SMD_PKG3
bool
config MSM_PROC_COMM
bool
config MSM_SMD
bool
config MSM_GPIOMUX
bool
help
Support for MSM V1 TLMM GPIOMUX architecture.
endif

23
arch/arm/mach-msm/Makefile Normal file
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obj-$(CONFIG_MSM_PROC_COMM) += clock.o
obj-$(CONFIG_MSM_VIC) += irq-vic.o
obj-$(CONFIG_ARCH_MSM7X00A) += irq.o
obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
obj-$(CONFIG_ARCH_MSM7X00A) += dma.o io.o
obj-$(CONFIG_ARCH_MSM7X30) += dma.o io.o
obj-$(CONFIG_ARCH_QSD8X50) += dma.o io.o
obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
obj-$(CONFIG_MSM_SMD) += last_radio_log.o
obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o
obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o
obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o
obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o

3
arch/arm/mach-msm/Makefile.boot Normal file
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zreladdr-y += 0x10008000
params_phys-y := 0x10000100
initrd_phys-y := 0x10800000

104
arch/arm/mach-msm/board-halibut.c Normal file
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/* linux/arch/arm/mach-msm/board-halibut.c
*
* Copyright (C) 2007 Google, Inc.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <asm/setup.h>
#include <mach/irqs.h>
#include <mach/msm_iomap.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include "devices.h"
#include "common.h"
static struct resource smc91x_resources[] = {
[0] = {
.start = 0x9C004300,
.end = 0x9C004400,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MSM_GPIO_TO_INT(49),
.end = MSM_GPIO_TO_INT(49),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
static struct platform_device *devices[] __initdata = {
&msm_clock_7x01a,
&msm_device_gpio_7201,
&msm_device_uart3,
&msm_device_smd,
&msm_device_nand,
&msm_device_hsusb,
&msm_device_i2c,
&smc91x_device,
};
static void __init halibut_init_early(void)
{
arch_ioremap_caller = __msm_ioremap_caller;
}
static void __init halibut_init_irq(void)
{
msm_init_irq();
}
static void __init halibut_init(void)
{
platform_add_devices(devices, ARRAY_SIZE(devices));
}
static void __init halibut_map_io(void)
{
msm_map_common_io();
}
static void __init halibut_init_late(void)
{
smd_debugfs_init();
}
MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
.atag_offset = 0x100,
.map_io = halibut_map_io,
.init_early = halibut_init_early,
.init_irq = halibut_init_irq,
.init_machine = halibut_init,
.init_late = halibut_init_late,
.init_time = msm7x01_timer_init,
MACHINE_END

191
arch/arm/mach-msm/board-msm7x30.c Normal file
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/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/smsc911x.h>
#include <linux/usb/msm_hsusb.h>
#include <linux/clkdev.h>
#include <linux/memblock.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/memory.h>
#include <asm/setup.h>
#include <mach/clk.h>
#include <mach/msm_iomap.h>
#include <mach/dma.h>
#include <mach/vreg.h>
#include "devices.h"
#include "gpiomux.h"
#include "proc_comm.h"
#include "common.h"
static void __init msm7x30_fixup(struct tag *tag, char **cmdline)
{
for (; tag->hdr.size; tag = tag_next(tag))
if (tag->hdr.tag == ATAG_MEM && tag->u.mem.start == 0x200000) {
tag->u.mem.start = 0;
tag->u.mem.size += SZ_2M;
}
}
static void __init msm7x30_reserve(void)
{
memblock_remove(0x0, SZ_2M);
}
static int hsusb_phy_init_seq[] = {
0x30, 0x32, /* Enable and set Pre-Emphasis Depth to 20% */
0x02, 0x36, /* Disable CDR Auto Reset feature */
-1
};
static int hsusb_link_clk_reset(struct clk *link_clk, bool assert)
{
int ret;
if (assert) {
ret = clk_reset(link_clk, CLK_RESET_ASSERT);
if (ret)
pr_err("usb hs_clk assert failed\n");
} else {
ret = clk_reset(link_clk, CLK_RESET_DEASSERT);
if (ret)
pr_err("usb hs_clk deassert failed\n");
}
return ret;
}
static int hsusb_phy_clk_reset(struct clk *phy_clk)
{
int ret;
ret = clk_reset(phy_clk, CLK_RESET_ASSERT);
if (ret) {
pr_err("usb phy clk assert failed\n");
return ret;
}
usleep_range(10000, 12000);
ret = clk_reset(phy_clk, CLK_RESET_DEASSERT);
if (ret)
pr_err("usb phy clk deassert failed\n");
return ret;
}
static struct msm_otg_platform_data msm_otg_pdata = {
.phy_init_seq = hsusb_phy_init_seq,
.mode = USB_DR_MODE_PERIPHERAL,
.otg_control = OTG_PHY_CONTROL,
.link_clk_reset = hsusb_link_clk_reset,
.phy_clk_reset = hsusb_phy_clk_reset,
};
struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
#ifdef CONFIG_SERIAL_MSM_CONSOLE
[49] = { /* UART2 RFR */
.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
GPIOMUX_FUNC_2 | GPIOMUX_VALID,
},
[50] = { /* UART2 CTS */
.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
GPIOMUX_FUNC_2 | GPIOMUX_VALID,
},
[51] = { /* UART2 RX */
.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
GPIOMUX_FUNC_2 | GPIOMUX_VALID,
},
[52] = { /* UART2 TX */
.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
GPIOMUX_FUNC_2 | GPIOMUX_VALID,
},
#endif
};
static struct platform_device *devices[] __initdata = {
&msm_clock_7x30,
&msm_device_gpio_7x30,
#if defined(CONFIG_SERIAL_MSM)
&msm_device_uart2,
#endif
&msm_device_smd,
&msm_device_otg,
&msm_device_hsusb,
&msm_device_hsusb_host,
};
static void __init msm7x30_init_irq(void)
{
msm_init_irq();
}
static void __init msm7x30_init(void)
{
msm_device_otg.dev.platform_data = &msm_otg_pdata;
msm_device_hsusb.dev.parent = &msm_device_otg.dev;
msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
platform_add_devices(devices, ARRAY_SIZE(devices));
}
static void __init msm7x30_map_io(void)
{
msm_map_msm7x30_io();
}
static void __init msm7x30_init_late(void)
{
smd_debugfs_init();
}
MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
.atag_offset = 0x100,
.fixup = msm7x30_fixup,
.reserve = msm7x30_reserve,
.map_io = msm7x30_map_io,
.init_irq = msm7x30_init_irq,
.init_machine = msm7x30_init,
.init_late = msm7x30_init_late,
.init_time = msm7x30_timer_init,
MACHINE_END
MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
.atag_offset = 0x100,
.fixup = msm7x30_fixup,
.reserve = msm7x30_reserve,
.map_io = msm7x30_map_io,
.init_irq = msm7x30_init_irq,
.init_machine = msm7x30_init,
.init_late = msm7x30_init_late,
.init_time = msm7x30_timer_init,
MACHINE_END
MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
.atag_offset = 0x100,
.fixup = msm7x30_fixup,
.reserve = msm7x30_reserve,
.map_io = msm7x30_map_io,
.init_irq = msm7x30_init_irq,
.init_machine = msm7x30_init,
.init_late = msm7x30_init_late,
.init_time = msm7x30_timer_init,
MACHINE_END

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arch/arm/mach-msm/board-qsd8x50.c Normal file
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/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/usb/msm_hsusb.h>
#include <linux/err.h>
#include <linux/clkdev.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/io.h>
#include <asm/setup.h>
#include <mach/irqs.h>
#include <mach/sirc.h>
#include <mach/vreg.h>
#include <mach/clk.h>
#include <linux/platform_data/mmc-msm_sdcc.h>
#include "devices.h"
#include "common.h"
static const resource_size_t qsd8x50_surf_smc91x_base __initconst = 0x70000300;
static const unsigned qsd8x50_surf_smc91x_gpio __initconst = 156;
/* Leave smc91x resources empty here, as we'll fill them in
* at run-time: they vary from board to board, and the true
* configuration won't be known until boot.
*/
static struct resource smc91x_resources[] = {
[0] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
static int __init msm_init_smc91x(void)
{
if (machine_is_qsd8x50_surf()) {
smc91x_resources[0].start = qsd8x50_surf_smc91x_base;
smc91x_resources[0].end = qsd8x50_surf_smc91x_base + 0xff;
smc91x_resources[1].start =
gpio_to_irq(qsd8x50_surf_smc91x_gpio);
smc91x_resources[1].end =
gpio_to_irq(qsd8x50_surf_smc91x_gpio);
platform_device_register(&smc91x_device);
}
return 0;
}
module_init(msm_init_smc91x);
static int hsusb_phy_init_seq[] = {
0x08, 0x31, /* Increase HS Driver Amplitude */
0x20, 0x32, /* Enable and set Pre-Emphasis Depth to 10% */
-1
};
static int hsusb_link_clk_reset(struct clk *link_clk, bool assert)
{
int ret;
if (assert) {
ret = clk_reset(link_clk, CLK_RESET_ASSERT);
if (ret)
pr_err("usb hs_clk assert failed\n");
} else {
ret = clk_reset(link_clk, CLK_RESET_DEASSERT);
if (ret)
pr_err("usb hs_clk deassert failed\n");
}
return ret;
}
static int hsusb_phy_clk_reset(struct clk *phy_clk)
{
int ret;
ret = clk_reset(phy_clk, CLK_RESET_ASSERT);
if (ret) {
pr_err("usb phy clk assert failed\n");
return ret;
}
usleep_range(10000, 12000);
ret = clk_reset(phy_clk, CLK_RESET_DEASSERT);
if (ret)
pr_err("usb phy clk deassert failed\n");
return ret;
}
static struct msm_otg_platform_data msm_otg_pdata = {
.phy_init_seq = hsusb_phy_init_seq,
.mode = USB_DR_MODE_PERIPHERAL,
.otg_control = OTG_PHY_CONTROL,
.link_clk_reset = hsusb_link_clk_reset,
.phy_clk_reset = hsusb_phy_clk_reset,
};
static struct platform_device *devices[] __initdata = {
&msm_clock_8x50,
&msm_device_gpio_8x50,
&msm_device_uart3,
&msm_device_smd,
&msm_device_otg,
&msm_device_hsusb,
&msm_device_hsusb_host,
};
static struct msm_mmc_gpio sdc1_gpio_cfg[] = {
{51, "sdc1_dat_3"},
{52, "sdc1_dat_2"},
{53, "sdc1_dat_1"},
{54, "sdc1_dat_0"},
{55, "sdc1_cmd"},
{56, "sdc1_clk"}
};
static struct vreg *vreg_mmc;
static unsigned long vreg_sts;
static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
{
int rc = 0;
struct platform_device *pdev;
pdev = container_of(dv, struct platform_device, dev);
if (vdd == 0) {
if (!vreg_sts)
return 0;
clear_bit(pdev->id, &vreg_sts);
if (!vreg_sts) {
rc = vreg_disable(vreg_mmc);
if (rc)
pr_err("vreg_mmc disable failed for slot "
"%d: %d\n", pdev->id, rc);
}
return 0;
}
if (!vreg_sts) {
rc = vreg_set_level(vreg_mmc, 2900);
if (rc)
pr_err("vreg_mmc set level failed for slot %d: %d\n",
pdev->id, rc);
rc = vreg_enable(vreg_mmc);
if (rc)
pr_err("vreg_mmc enable failed for slot %d: %d\n",
pdev->id, rc);
}
set_bit(pdev->id, &vreg_sts);
return 0;
}
static struct msm_mmc_gpio_data sdc1_gpio = {
.gpio = sdc1_gpio_cfg,
.size = ARRAY_SIZE(sdc1_gpio_cfg),
};
static struct msm_mmc_platform_data qsd8x50_sdc1_data = {
.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
.translate_vdd = msm_sdcc_setup_power,
.gpio_data = &sdc1_gpio,
};
static void __init qsd8x50_init_mmc(void)
{
vreg_mmc = vreg_get(NULL, "gp5");
if (IS_ERR(vreg_mmc)) {
pr_err("vreg get for vreg_mmc failed (%ld)\n",
PTR_ERR(vreg_mmc));
return;
}
msm_add_sdcc(1, &qsd8x50_sdc1_data, 0, 0);
}
static void __init qsd8x50_map_io(void)
{
msm_map_qsd8x50_io();
}
static void __init qsd8x50_init_irq(void)
{
msm_init_irq();
msm_init_sirc();
}
static void __init qsd8x50_init(void)
{
msm_device_otg.dev.platform_data = &msm_otg_pdata;
msm_device_hsusb.dev.parent = &msm_device_otg.dev;
msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
platform_add_devices(devices, ARRAY_SIZE(devices));
qsd8x50_init_mmc();
}
static void __init qsd8x50_init_late(void)
{
smd_debugfs_init();
}
MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
.atag_offset = 0x100,
.map_io = qsd8x50_map_io,
.init_irq = qsd8x50_init_irq,
.init_machine = qsd8x50_init,
.init_late = qsd8x50_init_late,
.init_time = qsd8x50_timer_init,
MACHINE_END
MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
.atag_offset = 0x100,
.map_io = qsd8x50_map_io,
.init_irq = qsd8x50_init_irq,
.init_machine = qsd8x50_init,
.init_late = qsd8x50_init_late,
.init_time = qsd8x50_timer_init,
MACHINE_END

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arch/arm/mach-msm/board-sapphire.c Normal file
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/* linux/arch/arm/mach-msm/board-sapphire.c
* Copyright (C) 2007-2009 HTC Corporation.
* Author: Thomas Tsai <thomas_tsai@htc.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <mach/vreg.h>
#include <asm/io.h>
#include <asm/delay.h>
#include <asm/setup.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/memblock.h>
#include "gpio_chip.h"
#include "board-sapphire.h"
#include "proc_comm.h"
#include "devices.h"
#include "common.h"
void msm_init_irq(void);
void msm_init_gpio(void);
static struct platform_device *devices[] __initdata = {
&msm_device_smd,
&msm_device_dmov,
&msm_device_nand,
&msm_device_uart1,
&msm_device_uart3,
};
void msm_timer_init(void);
static void __init sapphire_init_irq(void)
{
msm_init_irq();
}
static void __init sapphire_init(void)
{
platform_add_devices(devices, ARRAY_SIZE(devices));
}
static struct map_desc sapphire_io_desc[] __initdata = {
{
.virtual = SAPPHIRE_CPLD_BASE,
.pfn = __phys_to_pfn(SAPPHIRE_CPLD_START),
.length = SAPPHIRE_CPLD_SIZE,
.type = MT_DEVICE_NONSHARED
}
};
static void __init sapphire_fixup(struct tag *tags, char **cmdline)
{
int smi_sz = parse_tag_smi((const struct tag *)tags);
if (smi_sz == 32) {
memblock_add(PHYS_OFFSET, 84*SZ_1M);
} else if (smi_sz == 64) {
memblock_add(PHYS_OFFSET, 101*SZ_1M);
} else {
memblock_add(PHYS_OFFSET, 101*SZ_1M);
/* Give a default value when not get smi size */
smi_sz = 64;
}
}
static void __init sapphire_map_io(void)
{
msm_map_common_io();
iotable_init(sapphire_io_desc, ARRAY_SIZE(sapphire_io_desc));
msm_clock_init();
}
static void __init sapphire_init_late(void)
{
smd_debugfs_init();
}
MACHINE_START(SAPPHIRE, "sapphire")
/* Maintainer: Brian Swetland <swetland@google.com> */
.atag_offset = 0x100,
.fixup = sapphire_fixup,
.map_io = sapphire_map_io,
.init_irq = sapphire_init_irq,
.init_machine = sapphire_init,
.init_late = sapphire_init_late,
.init_time = msm_timer_init,
MACHINE_END

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arch/arm/mach-msm/board-trout-gpio.c Normal file
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/*
* linux/arch/arm/mach-msm/gpio.c
*
* Copyright (C) 2005 HP Labs
* Copyright (C) 2008 Google, Inc.
* Copyright (C) 2009 Pavel Machek <pavel@ucw.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include "board-trout.h"
static uint8_t trout_int_mask[2] = {
[0] = 0xff, /* mask all interrupts */
[1] = 0xff,
};
static uint8_t trout_sleep_int_mask[] = {
[0] = 0xff,
[1] = 0xff,
};
struct msm_gpio_chip {
struct gpio_chip chip;
void __iomem *reg; /* Base of register bank */
u8 shadow;
};
#define to_msm_gpio_chip(c) container_of(c, struct msm_gpio_chip, chip)
static int msm_gpiolib_get(struct gpio_chip *chip, unsigned offset)
{
struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
unsigned mask = 1 << offset;
return !!(readb(msm_gpio->reg) & mask);
}
static void msm_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
{
struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
unsigned mask = 1 << offset;
if (val)
msm_gpio->shadow |= mask;
else
msm_gpio->shadow &= ~mask;
writeb(msm_gpio->shadow, msm_gpio->reg);
}
static int msm_gpiolib_direction_input(struct gpio_chip *chip,
unsigned offset)
{
msm_gpiolib_set(chip, offset, 0);
return 0;
}
static int msm_gpiolib_direction_output(struct gpio_chip *chip,
unsigned offset, int val)
{
msm_gpiolib_set(chip, offset, val);
return 0;
}
static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
return TROUT_GPIO_TO_INT(offset + chip->base);
}
#define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val) \
{ \
.chip = { \
.label = name, \
.direction_input = msm_gpiolib_direction_input,\
.direction_output = msm_gpiolib_direction_output, \
.get = msm_gpiolib_get, \
.set = msm_gpiolib_set, \
.to_irq = trout_gpio_to_irq, \
.base = base_gpio, \
.ngpio = 8, \
}, \
.reg = reg_num + TROUT_CPLD_BASE, \
.shadow = shadow_val, \
}
static struct msm_gpio_chip msm_gpio_banks[] = {
#if defined(CONFIG_DEBUG_MSM_UART) && (CONFIG_DEBUG_UART_PHYS == 0xa9a00000)
/* H2W pins <-> UART1 */
TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x40),
#else
/* H2W pins <-> UART3, Bluetooth <-> UART1 */
TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x80),
#endif
/* I2C pull */
TROUT_GPIO_BANK("MISC3", 0x02, TROUT_GPIO_MISC3_BASE, 0x04),
TROUT_GPIO_BANK("MISC4", 0x04, TROUT_GPIO_MISC4_BASE, 0),
/* mmdi 32k en */
TROUT_GPIO_BANK("MISC5", 0x06, TROUT_GPIO_MISC5_BASE, 0x04),
TROUT_GPIO_BANK("INT2", 0x08, TROUT_GPIO_INT2_BASE, 0),
TROUT_GPIO_BANK("MISC1", 0x0a, TROUT_GPIO_MISC1_BASE, 0),
TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0),
};
static void trout_gpio_irq_ack(struct irq_data *d)
{
int bank = TROUT_INT_TO_BANK(d->irq);
uint8_t mask = TROUT_INT_TO_MASK(d->irq);
int reg = TROUT_BANK_TO_STAT_REG(bank);
/*printk(KERN_INFO "trout_gpio_irq_ack irq %d\n", d->irq);*/
writeb(mask, TROUT_CPLD_BASE + reg);
}
static void trout_gpio_irq_mask(struct irq_data *d)
{
unsigned long flags;
uint8_t reg_val;
int bank = TROUT_INT_TO_BANK(d->irq);
uint8_t mask = TROUT_INT_TO_MASK(d->irq);
int reg = TROUT_BANK_TO_MASK_REG(bank);
local_irq_save(flags);
reg_val = trout_int_mask[bank] |= mask;
/*printk(KERN_INFO "trout_gpio_irq_mask irq %d => %d:%02x\n",
d->irq, bank, reg_val);*/
writeb(reg_val, TROUT_CPLD_BASE + reg);
local_irq_restore(flags);
}
static void trout_gpio_irq_unmask(struct irq_data *d)
{
unsigned long flags;
uint8_t reg_val;
int bank = TROUT_INT_TO_BANK(d->irq);
uint8_t mask = TROUT_INT_TO_MASK(d->irq);
int reg = TROUT_BANK_TO_MASK_REG(bank);
local_irq_save(flags);
reg_val = trout_int_mask[bank] &= ~mask;
/*printk(KERN_INFO "trout_gpio_irq_unmask irq %d => %d:%02x\n",
d->irq, bank, reg_val);*/
writeb(reg_val, TROUT_CPLD_BASE + reg);
local_irq_restore(flags);
}
int trout_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
{
unsigned long flags;
int bank = TROUT_INT_TO_BANK(d->irq);
uint8_t mask = TROUT_INT_TO_MASK(d->irq);
local_irq_save(flags);
if(on)
trout_sleep_int_mask[bank] &= ~mask;
else
trout_sleep_int_mask[bank] |= mask;
local_irq_restore(flags);
return 0;
}
static void trout_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
int j, m;
unsigned v;
int bank;
int stat_reg;
int int_base = TROUT_INT_START;
uint8_t int_mask;
for (bank = 0; bank < 2; bank++) {
stat_reg = TROUT_BANK_TO_STAT_REG(bank);
v = readb(TROUT_CPLD_BASE + stat_reg);
int_mask = trout_int_mask[bank];
if (v & int_mask) {
writeb(v & int_mask, TROUT_CPLD_BASE + stat_reg);
printk(KERN_ERR "trout_gpio_irq_handler: got masked "
"interrupt: %d:%02x\n", bank, v & int_mask);
}
v &= ~int_mask;
while (v) {
m = v & -v;
j = fls(m) - 1;
/*printk(KERN_INFO "msm_gpio_irq_handler %d:%02x %02x b"
"it %d irq %d\n", bank, v, m, j, int_base + j);*/
v &= ~m;
generic_handle_irq(int_base + j);
}
int_base += TROUT_INT_BANK0_COUNT;
}
desc->irq_data.chip->irq_ack(&desc->irq_data);
}
static struct irq_chip trout_gpio_irq_chip = {
.name = "troutgpio",
.irq_ack = trout_gpio_irq_ack,
.irq_mask = trout_gpio_irq_mask,
.irq_unmask = trout_gpio_irq_unmask,
.irq_set_wake = trout_gpio_irq_set_wake,
};
/*
* Called from the processor-specific init to enable GPIO pin support.
*/
int __init trout_init_gpio(void)
{
int i;
for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) {
irq_set_chip_and_handler(i, &trout_gpio_irq_chip,
handle_edge_irq);
set_irq_flags(i, IRQF_VALID);
}
for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
gpiochip_add(&msm_gpio_banks[i].chip);
irq_set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
irq_set_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler);
irq_set_irq_wake(MSM_GPIO_TO_INT(17), 1);
return 0;
}
postcore_initcall(trout_init_gpio);

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arch/arm/mach-msm/board-trout-mmc.c Normal file
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/* linux/arch/arm/mach-msm/board-trout-mmc.c
** Author: Brian Swetland <swetland@google.com>
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sdio_ids.h>
#include <linux/err.h>
#include <linux/debugfs.h>
#include <asm/io.h>
#include <mach/vreg.h>
#include <linux/platform_data/mmc-msm_sdcc.h>
#include "devices.h"
#include "board-trout.h"
#include "proc_comm.h"
#define DEBUG_SDSLOT_VDD 1
/* ---- COMMON ---- */
static void config_gpio_table(uint32_t *table, int len)
{
int n;
unsigned id;
for(n = 0; n < len; n++) {
id = table[n];
msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &id, 0);
}
}
/* ---- SDCARD ---- */
static uint32_t sdcard_on_gpio_table[] = {
PCOM_GPIO_CFG(62, 2, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA), /* CLK */
PCOM_GPIO_CFG(63, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA), /* CMD */
PCOM_GPIO_CFG(64, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA), /* DAT3 */
PCOM_GPIO_CFG(65, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA), /* DAT2 */
PCOM_GPIO_CFG(66, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_4MA), /* DAT1 */
PCOM_GPIO_CFG(67, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_4MA), /* DAT0 */
};
static uint32_t sdcard_off_gpio_table[] = {
PCOM_GPIO_CFG(62, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* CLK */
PCOM_GPIO_CFG(63, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* CMD */
PCOM_GPIO_CFG(64, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT3 */
PCOM_GPIO_CFG(65, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT2 */
PCOM_GPIO_CFG(66, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT1 */
PCOM_GPIO_CFG(67, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT0 */
};
static uint opt_disable_sdcard;
static int __init trout_disablesdcard_setup(char *str)
{
int cal = simple_strtol(str, NULL, 0);
opt_disable_sdcard = cal;
return 1;
}
__setup("board_trout.disable_sdcard=", trout_disablesdcard_setup);
static struct vreg *vreg_sdslot; /* SD slot power */
struct mmc_vdd_xlat {
int mask;
int level;
};
static struct mmc_vdd_xlat mmc_vdd_table[] = {
{ MMC_VDD_165_195, 1800 },
{ MMC_VDD_20_21, 2050 },
{ MMC_VDD_21_22, 2150 },
{ MMC_VDD_22_23, 2250 },
{ MMC_VDD_23_24, 2350 },
{ MMC_VDD_24_25, 2450 },
{ MMC_VDD_25_26, 2550 },
{ MMC_VDD_26_27, 2650 },
{ MMC_VDD_27_28, 2750 },
{ MMC_VDD_28_29, 2850 },
{ MMC_VDD_29_30, 2950 },
};
static unsigned int sdslot_vdd = 0xffffffff;
static unsigned int sdslot_vreg_enabled;
static uint32_t trout_sdslot_switchvdd(struct device *dev, unsigned int vdd)
{
int i, rc;
BUG_ON(!vreg_sdslot);
if (vdd == sdslot_vdd)
return 0;
sdslot_vdd = vdd;
if (vdd == 0) {
#if DEBUG_SDSLOT_VDD
printk("%s: Disabling SD slot power\n", __func__);
#endif
config_gpio_table(sdcard_off_gpio_table,
ARRAY_SIZE(sdcard_off_gpio_table));
vreg_disable(vreg_sdslot);
sdslot_vreg_enabled = 0;
return 0;
}
if (!sdslot_vreg_enabled) {
rc = vreg_enable(vreg_sdslot);
if (rc) {
printk(KERN_ERR "%s: Error enabling vreg (%d)\n",
__func__, rc);
}
config_gpio_table(sdcard_on_gpio_table,
ARRAY_SIZE(sdcard_on_gpio_table));
sdslot_vreg_enabled = 1;
}
for (i = 0; i < ARRAY_SIZE(mmc_vdd_table); i++) {
if (mmc_vdd_table[i].mask == (1 << vdd)) {
#if DEBUG_SDSLOT_VDD
printk("%s: Setting level to %u\n",
__func__, mmc_vdd_table[i].level);
#endif
rc = vreg_set_level(vreg_sdslot,
mmc_vdd_table[i].level);
if (rc) {
printk(KERN_ERR
"%s: Error setting vreg level (%d)\n",
__func__, rc);
}
return 0;
}
}
printk(KERN_ERR "%s: Invalid VDD %d specified\n", __func__, vdd);
return 0;
}
static unsigned int trout_sdslot_status(struct device *dev)
{
unsigned int status;
status = (unsigned int) gpio_get_value(TROUT_GPIO_SDMC_CD_N);
return (!status);
}
#define TROUT_MMC_VDD MMC_VDD_165_195 | MMC_VDD_20_21 | MMC_VDD_21_22 \
| MMC_VDD_22_23 | MMC_VDD_23_24 | MMC_VDD_24_25 \
| MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 \
| MMC_VDD_28_29 | MMC_VDD_29_30
static struct msm_mmc_platform_data trout_sdslot_data = {
.ocr_mask = TROUT_MMC_VDD,
.status = trout_sdslot_status,
.translate_vdd = trout_sdslot_switchvdd,
};
int __init trout_init_mmc(unsigned int sys_rev)
{
sdslot_vreg_enabled = 0;
vreg_sdslot = vreg_get(0, "gp6");
if (IS_ERR(vreg_sdslot))
return PTR_ERR(vreg_sdslot);
irq_set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1);
if (!opt_disable_sdcard)
msm_add_sdcc(2, &trout_sdslot_data,
TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 0);
else
printk(KERN_INFO "trout: SD-Card interface disabled\n");
return 0;
}

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arch/arm/mach-msm/board-trout-panel.c Normal file
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/* linux/arch/arm/mach-msm/board-trout-mddi.c
** Author: Brian Swetland <swetland@google.com>
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/leds.h>
#include <linux/err.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/system_info.h>
#include <linux/platform_data/video-msm_fb.h>
#include <mach/vreg.h>
#include "board-trout.h"
#include "proc_comm.h"
#include "clock-pcom.h"
#include "devices.h"
#define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255
#define MDDI_CLIENT_CORE_BASE 0x108000
#define LCD_CONTROL_BLOCK_BASE 0x110000
#define SPI_BLOCK_BASE 0x120000
#define I2C_BLOCK_BASE 0x130000
#define PWM_BLOCK_BASE 0x140000
#define GPIO_BLOCK_BASE 0x150000
#define SYSTEM_BLOCK1_BASE 0x160000
#define SYSTEM_BLOCK2_BASE 0x170000
#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
#define SYSCLKENA (MDDI_CLIENT_CORE_BASE|0x2C)
#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
#define V_VDDE2E_VDD2_GPIO 0
#define MDDI_RST_N 82
#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
#define START (LCD_CONTROL_BLOCK_BASE|0x08)
#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
#define SSICTL (SPI_BLOCK_BASE|0x00)
#define SSITIME (SPI_BLOCK_BASE|0x04)
#define SSITX (SPI_BLOCK_BASE|0x08)
#define SSIRX (SPI_BLOCK_BASE|0x0C)
#define SSIINTC (SPI_BLOCK_BASE|0x10)
#define SSIINTS (SPI_BLOCK_BASE|0x14)
#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
#define SSIID (SPI_BLOCK_BASE|0x20)
#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
#define GPIODATA (GPIO_BLOCK_BASE|0x00)
#define GPIODIR (GPIO_BLOCK_BASE|0x04)
#define GPIOIS (GPIO_BLOCK_BASE|0x08)
#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
#define GPIOIE (GPIO_BLOCK_BASE|0x14)
#define GPIORIS (GPIO_BLOCK_BASE|0x18)
#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
#define GPIOIC (GPIO_BLOCK_BASE|0x20)
#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
#define GPIOPC (GPIO_BLOCK_BASE|0x28)
#define GPIOID (GPIO_BLOCK_BASE|0x30)
#define SPI_WRITE(reg, val) \
{ SSITX, 0x00010000 | (((reg) & 0xff) << 8) | ((val) & 0xff) }, \
{ 0, 5 },
#define SPI_WRITE1(reg) \
{ SSITX, (reg) & 0xff }, \
{ 0, 5 },
struct mddi_table {
uint32_t reg;
uint32_t value;
};
static struct mddi_table mddi_toshiba_init_table[] = {
{ DPSET0, 0x09e90046 },
{ DPSET1, 0x00000118 },
{ DPSUS, 0x00000000 },
{ DPRUN, 0x00000001 },
{ 1, 14 }, /* msleep 14 */
{ SYSCKENA, 0x00000001 },
{ CLKENB, 0x0000A1EF }, /* # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK) */
{ GPIODATA, 0x02000200 }, /* # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 */
{ GPIODIR, 0x000030D }, /* 24D # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output) */
{ GPIOSEL, 0/*0x00000173*/}, /* # SYS.GPIOSEL # GPIO port multiplexing control */
{ GPIOPC, 0x03C300C0 }, /* # GPI .GPIOPC # GPIO2,3 PD cut */
{ WKREQ, 0x00000000 }, /* # SYS.WKREQ # Wake-up request event is VSYNC alignment */
{ GPIOIBE, 0x000003FF },
{ GPIOIS, 0x00000000 },
{ GPIOIC, 0x000003FF },
{ GPIOIE, 0x00000000 },
{ GPIODATA, 0x00040004 }, /* # GPI .GPIODATA # eDRAM VD supply */
{ 1, 1 }, /* msleep 1 */
{ GPIODATA, 0x02040004 }, /* # GPI .GPIODATA # eDRAM VD supply */
{ DRAMPWR, 0x00000001 }, /* eDRAM power */
};
#define GPIOSEL_VWAKEINT (1U << 0)
#define INTMASK_VWAKEOUT (1U << 0)
static int trout_new_backlight = 1;
static struct vreg *vreg_mddi_1v5;
static struct vreg *vreg_lcm_2v85;
static void trout_process_mddi_table(struct msm_mddi_client_data *client_data,
struct mddi_table *table, size_t count)
{
int i;
for (i = 0; i < count; i++) {
uint32_t reg = table[i].reg;
uint32_t value = table[i].value;
if (reg == 0)
udelay(value);
else if (reg == 1)
msleep(value);
else
client_data->remote_write(client_data, value, reg);
}
}
static int trout_mddi_toshiba_client_init(
struct msm_mddi_bridge_platform_data *bridge_data,
struct msm_mddi_client_data *client_data)
{
int panel_id;
client_data->auto_hibernate(client_data, 0);
trout_process_mddi_table(client_data, mddi_toshiba_init_table,
ARRAY_SIZE(mddi_toshiba_init_table));
client_data->auto_hibernate(client_data, 1);
panel_id = (client_data->remote_read(client_data, GPIODATA) >> 4) & 3;
if (panel_id > 1) {
printk(KERN_WARNING "unknown panel id at mddi_enable\n");
return -1;
}
return 0;
}
static int trout_mddi_toshiba_client_uninit(
struct msm_mddi_bridge_platform_data *bridge_data,
struct msm_mddi_client_data *client_data)
{
return 0;
}
static struct resource resources_msm_fb[] = {
{
.start = MSM_FB_BASE,
.end = MSM_FB_BASE + MSM_FB_SIZE,
.flags = IORESOURCE_MEM,
},
};
struct msm_mddi_bridge_platform_data toshiba_client_data = {
.init = trout_mddi_toshiba_client_init,
.uninit = trout_mddi_toshiba_client_uninit,
.fb_data = {
.xres = 320,
.yres = 480,
.width = 45,
.height = 67,
.output_format = 0,
},
};
static struct msm_mddi_platform_data mddi_pdata = {
.clk_rate = 122880000,
.fb_resource = resources_msm_fb,
.num_clients = 1,
.client_platform_data = {
{
.product_id = (0xd263 << 16 | 0),
.name = "mddi_c_d263_0000",
.id = 0,
.client_data = &toshiba_client_data,
.clk_rate = 0,
},
},
};
int __init trout_init_panel(void)
{
int rc;
if (!machine_is_trout())
return 0;
vreg_mddi_1v5 = vreg_get(0, "gp2");
if (IS_ERR(vreg_mddi_1v5))
return PTR_ERR(vreg_mddi_1v5);
vreg_lcm_2v85 = vreg_get(0, "gp4");
if (IS_ERR(vreg_lcm_2v85))
return PTR_ERR(vreg_lcm_2v85);
trout_new_backlight = system_rev >= 5;
if (trout_new_backlight) {
uint32_t config = PCOM_GPIO_CFG(27, 0, GPIO_OUTPUT,
GPIO_NO_PULL, GPIO_8MA);
msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
} else {
uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT,
GPIO_NO_PULL, GPIO_8MA);
uint32_t id = P_GP_CLK;
uint32_t rate = 19200000;
msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
if (id < 0)
pr_err("trout_init_panel: set clock rate failed\n");
}
rc = platform_device_register(&msm_device_mdp);
if (rc)
return rc;
msm_device_mddi0.dev.platform_data = &mddi_pdata;
return platform_device_register(&msm_device_mddi0);
}
device_initcall(trout_init_panel);

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/* linux/arch/arm/mach-msm/board-trout.c
*
* Copyright (C) 2009 Google, Inc.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clkdev.h>
#include <linux/memblock.h>
#include <asm/system_info.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/setup.h>
#include <mach/hardware.h>
#include <mach/msm_iomap.h>
#include "devices.h"
#include "board-trout.h"
#include "common.h"
extern int trout_init_mmc(unsigned int);
static struct platform_device *devices[] __initdata = {
&msm_clock_7x01a,
&msm_device_gpio_7201,
&msm_device_uart3,
&msm_device_smd,
&msm_device_nand,
&msm_device_hsusb,
&msm_device_i2c,
};
static void __init trout_init_early(void)
{
arch_ioremap_caller = __msm_ioremap_caller;
}
static void __init trout_init_irq(void)
{
msm_init_irq();
}
static void __init trout_fixup(struct tag *tags, char **cmdline)
{
memblock_add(PHYS_OFFSET, 101*SZ_1M);
}
static void __init trout_init(void)
{
int rc;
platform_add_devices(devices, ARRAY_SIZE(devices));
if (IS_ENABLED(CONFIG_MMC)) {
rc = trout_init_mmc(system_rev);
if (rc)
pr_crit("MMC init failure (%d)\n", rc);
}
}
static struct map_desc trout_io_desc[] __initdata = {
{
.virtual = (unsigned long)TROUT_CPLD_BASE,
.pfn = __phys_to_pfn(TROUT_CPLD_START),
.length = TROUT_CPLD_SIZE,
.type = MT_DEVICE_NONSHARED
}
};
static void __init trout_map_io(void)
{
msm_map_common_io();
iotable_init(trout_io_desc, ARRAY_SIZE(trout_io_desc));
#if defined(CONFIG_DEBUG_MSM_UART) && (CONFIG_DEBUG_UART_PHYS == 0xa9c00000)
/* route UART3 to the "H2W" extended usb connector */
writeb(0x80, TROUT_CPLD_BASE + 0x00);
#endif
}
static void __init trout_init_late(void)
{
smd_debugfs_init();
}
MACHINE_START(TROUT, "HTC Dream")
.atag_offset = 0x100,
.fixup = trout_fixup,
.map_io = trout_map_io,
.init_early = trout_init_early,
.init_irq = trout_init_irq,
.init_machine = trout_init,
.init_late = trout_init_late,
.init_time = msm7x01_timer_init,
MACHINE_END

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arch/arm/mach-msm/board-trout.h Normal file
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/* linux/arch/arm/mach-msm/board-trout.h
** Author: Brian Swetland <swetland@google.com>
*/
#ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
#define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
#include "common.h"
#define MSM_SMI_BASE 0x00000000
#define MSM_SMI_SIZE 0x00800000
#define MSM_EBI_BASE 0x10000000
#define MSM_EBI_SIZE 0x06e00000
#define MSM_PMEM_GPU0_BASE 0x00000000
#define MSM_PMEM_GPU0_SIZE 0x00700000
#define MSM_PMEM_MDP_BASE 0x02000000
#define MSM_PMEM_MDP_SIZE 0x00800000
#define MSM_PMEM_ADSP_BASE 0x02800000
#define MSM_PMEM_ADSP_SIZE 0x00800000
#define MSM_PMEM_CAMERA_BASE 0x03000000
#define MSM_PMEM_CAMERA_SIZE 0x00800000
#define MSM_FB_BASE 0x03800000
#define MSM_FB_SIZE 0x00100000
#define MSM_LINUX_BASE MSM_EBI_BASE
#define MSM_LINUX_SIZE 0x06500000
#define MSM_PMEM_GPU1_SIZE 0x800000
#define MSM_PMEM_GPU1_BASE (MSM_RAM_CONSOLE_BASE - MSM_PMEM_GPU1_SIZE)
#define MSM_RAM_CONSOLE_BASE (MSM_EBI_BASE + 0x6d00000)
#define MSM_RAM_CONSOLE_SIZE (128 * SZ_1K)
#if (MSM_FB_BASE + MSM_FB_SIZE) >= (MSM_PMEM_GPU1_BASE)
#error invalid memory map
#endif
#define DECLARE_MSM_IOMAP
#include <mach/msm_iomap.h>
#define TROUT_4_BALL_UP_0 1
#define TROUT_4_BALL_LEFT_0 18
#define TROUT_4_BALL_DOWN_0 57
#define TROUT_4_BALL_RIGHT_0 91
#define TROUT_5_BALL_UP_0 94
#define TROUT_5_BALL_LEFT_0 18
#define TROUT_5_BALL_DOWN_0 90
#define TROUT_5_BALL_RIGHT_0 19
#define TROUT_POWER_KEY 20
#define TROUT_4_TP_LS_EN 19
#define TROUT_5_TP_LS_EN 1
#define TROUT_CPLD_BASE IOMEM(0xE8100000)
#define TROUT_CPLD_START 0x98000000
#define TROUT_CPLD_SIZE SZ_4K
#define TROUT_GPIO_CABLE_IN1 (83)
#define TROUT_GPIO_CABLE_IN2 (49)
#define TROUT_GPIO_START (128)
#define TROUT_GPIO_INT_MASK0_REG (0x0c)
#define TROUT_GPIO_INT_STAT0_REG (0x0e)
#define TROUT_GPIO_INT_MASK1_REG (0x14)
#define TROUT_GPIO_INT_STAT1_REG (0x10)
#define TROUT_GPIO_HAPTIC_PWM (28)
#define TROUT_GPIO_PS_HOLD (25)
#define TROUT_GPIO_MISC2_BASE (TROUT_GPIO_START + 0x00)
#define TROUT_GPIO_MISC3_BASE (TROUT_GPIO_START + 0x08)
#define TROUT_GPIO_MISC4_BASE (TROUT_GPIO_START + 0x10)
#define TROUT_GPIO_MISC5_BASE (TROUT_GPIO_START + 0x18)
#define TROUT_GPIO_INT2_BASE (TROUT_GPIO_START + 0x20)
#define TROUT_GPIO_MISC1_BASE (TROUT_GPIO_START + 0x28)
#define TROUT_GPIO_VIRTUAL_BASE (TROUT_GPIO_START + 0x30)
#define TROUT_GPIO_INT5_BASE (TROUT_GPIO_START + 0x48)
#define TROUT_GPIO_CHARGER_EN (TROUT_GPIO_MISC2_BASE + 0)
#define TROUT_GPIO_ISET (TROUT_GPIO_MISC2_BASE + 1)
#define TROUT_GPIO_H2W_DAT_DIR (TROUT_GPIO_MISC2_BASE + 2)
#define TROUT_GPIO_H2W_CLK_DIR (TROUT_GPIO_MISC2_BASE + 3)
#define TROUT_GPIO_H2W_DAT_GPO (TROUT_GPIO_MISC2_BASE + 4)
#define TROUT_GPIO_H2W_CLK_GPO (TROUT_GPIO_MISC2_BASE + 5)
#define TROUT_GPIO_H2W_SEL0 (TROUT_GPIO_MISC2_BASE + 6)
#define TROUT_GPIO_H2W_SEL1 (TROUT_GPIO_MISC2_BASE + 7)
#define TROUT_GPIO_SPOTLIGHT_EN (TROUT_GPIO_MISC3_BASE + 0)
#define TROUT_GPIO_FLASH_EN (TROUT_GPIO_MISC3_BASE + 1)
#define TROUT_GPIO_I2C_PULL (TROUT_GPIO_MISC3_BASE + 2)
#define TROUT_GPIO_TP_I2C_PULL (TROUT_GPIO_MISC3_BASE + 3)
#define TROUT_GPIO_TP_EN (TROUT_GPIO_MISC3_BASE + 4)
#define TROUT_GPIO_JOG_EN (TROUT_GPIO_MISC3_BASE + 5)
#define TROUT_GPIO_UI_LED_EN (TROUT_GPIO_MISC3_BASE + 6)
#define TROUT_GPIO_QTKEY_LED_EN (TROUT_GPIO_MISC3_BASE + 7)
#define TROUT_GPIO_VCM_PWDN (TROUT_GPIO_MISC4_BASE + 0)
#define TROUT_GPIO_USB_H2W_SW (TROUT_GPIO_MISC4_BASE + 1)
#define TROUT_GPIO_COMPASS_RST_N (TROUT_GPIO_MISC4_BASE + 2)
#define TROUT_GPIO_HAPTIC_EN_UP (TROUT_GPIO_MISC4_BASE + 3)
#define TROUT_GPIO_HAPTIC_EN_MAIN (TROUT_GPIO_MISC4_BASE + 4)
#define TROUT_GPIO_USB_PHY_RST_N (TROUT_GPIO_MISC4_BASE + 5)
#define TROUT_GPIO_WIFI_PA_RESETX (TROUT_GPIO_MISC4_BASE + 6)
#define TROUT_GPIO_WIFI_EN (TROUT_GPIO_MISC4_BASE + 7)
#define TROUT_GPIO_BT_32K_EN (TROUT_GPIO_MISC5_BASE + 0)
#define TROUT_GPIO_MAC_32K_EN (TROUT_GPIO_MISC5_BASE + 1)
#define TROUT_GPIO_MDDI_32K_EN (TROUT_GPIO_MISC5_BASE + 2)
#define TROUT_GPIO_COMPASS_32K_EN (TROUT_GPIO_MISC5_BASE + 3)
#define TROUT_GPIO_NAVI_ACT_N (TROUT_GPIO_INT2_BASE + 0)
#define TROUT_GPIO_COMPASS_IRQ (TROUT_GPIO_INT2_BASE + 1)
#define TROUT_GPIO_SLIDING_DET (TROUT_GPIO_INT2_BASE + 2)
#define TROUT_GPIO_AUD_HSMIC_DET_N (TROUT_GPIO_INT2_BASE + 3)
#define TROUT_GPIO_SD_DOOR_N (TROUT_GPIO_INT2_BASE + 4)
#define TROUT_GPIO_CAM_BTN_STEP1_N (TROUT_GPIO_INT2_BASE + 5)
#define TROUT_GPIO_CAM_BTN_STEP2_N (TROUT_GPIO_INT2_BASE + 6)
#define TROUT_GPIO_TP_ATT_N (TROUT_GPIO_INT2_BASE + 7)
#define TROUT_GPIO_BANK0_FIRST_INT_SOURCE (TROUT_GPIO_NAVI_ACT_N)
#define TROUT_GPIO_BANK0_LAST_INT_SOURCE (TROUT_GPIO_TP_ATT_N)
#define TROUT_GPIO_H2W_DAT_GPI (TROUT_GPIO_MISC1_BASE + 0)
#define TROUT_GPIO_H2W_CLK_GPI (TROUT_GPIO_MISC1_BASE + 1)
#define TROUT_GPIO_CPLD128_VER_0 (TROUT_GPIO_MISC1_BASE + 4)
#define TROUT_GPIO_CPLD128_VER_1 (TROUT_GPIO_MISC1_BASE + 5)
#define TROUT_GPIO_CPLD128_VER_2 (TROUT_GPIO_MISC1_BASE + 6)
#define TROUT_GPIO_CPLD128_VER_3 (TROUT_GPIO_MISC1_BASE + 7)
#define TROUT_GPIO_SDMC_CD_N (TROUT_GPIO_VIRTUAL_BASE + 0)
#define TROUT_GPIO_END (TROUT_GPIO_SDMC_CD_N)
#define TROUT_GPIO_BANK1_FIRST_INT_SOURCE (TROUT_GPIO_SDMC_CD_N)
#define TROUT_GPIO_BANK1_LAST_INT_SOURCE (TROUT_GPIO_SDMC_CD_N)
#define TROUT_GPIO_VIRTUAL_TO_REAL_OFFSET \
(TROUT_GPIO_INT5_BASE - TROUT_GPIO_VIRTUAL_BASE)
#define TROUT_INT_START (NR_MSM_IRQS + NR_GPIO_IRQS)
#define TROUT_INT_BANK0_COUNT (8)
#define TROUT_INT_BANK1_START (TROUT_INT_START + TROUT_INT_BANK0_COUNT)
#define TROUT_INT_BANK1_COUNT (1)
#define TROUT_INT_END (TROUT_INT_START + TROUT_INT_BANK0_COUNT + \
TROUT_INT_BANK1_COUNT - 1)
#define TROUT_GPIO_TO_INT(n) (((n) <= TROUT_GPIO_BANK0_LAST_INT_SOURCE) ? \
(TROUT_INT_START - TROUT_GPIO_BANK0_FIRST_INT_SOURCE + (n)) : \
(TROUT_INT_BANK1_START - TROUT_GPIO_BANK1_FIRST_INT_SOURCE + (n)))
#define TROUT_INT_TO_BANK(n) ((n - TROUT_INT_START) / TROUT_INT_BANK0_COUNT)
#define TROUT_INT_TO_MASK(n) (1U << ((n - TROUT_INT_START) & 7))
#define TROUT_BANK_TO_MASK_REG(bank) \
(bank ? TROUT_GPIO_INT_MASK1_REG : TROUT_GPIO_INT_MASK0_REG)
#define TROUT_BANK_TO_STAT_REG(bank) \
(bank ? TROUT_GPIO_INT_STAT1_REG : TROUT_GPIO_INT_STAT0_REG)
#endif /* GUARD */

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arch/arm/mach-msm/clock-pcom.c Normal file
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/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <mach/clk.h>
#include "proc_comm.h"
#include "clock.h"
#include "clock-pcom.h"
struct clk_pcom {
unsigned id;
unsigned long flags;
struct msm_clk msm_clk;
};
static inline struct clk_pcom *to_clk_pcom(struct clk_hw *hw)
{
return container_of(to_msm_clk(hw), struct clk_pcom, msm_clk);
}
static int pc_clk_enable(struct clk_hw *hw)
{
unsigned id = to_clk_pcom(hw)->id;
int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
if (rc < 0)
return rc;
else
return (int)id < 0 ? -EINVAL : 0;
}
static void pc_clk_disable(struct clk_hw *hw)
{
unsigned id = to_clk_pcom(hw)->id;
msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
}
static int pc_clk_reset(struct clk_hw *hw, enum clk_reset_action action)
{
int rc;
unsigned id = to_clk_pcom(hw)->id;
if (action == CLK_RESET_ASSERT)
rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_ASSERT, &id, NULL);
else
rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_DEASSERT, &id, NULL);
if (rc < 0)
return rc;
else
return (int)id < 0 ? -EINVAL : 0;
}
static int pc_clk_set_rate(struct clk_hw *hw, unsigned long new_rate,
unsigned long p_rate)
{
struct clk_pcom *p = to_clk_pcom(hw);
unsigned id = p->id, rate = new_rate;
int rc;
/*
* The rate _might_ be rounded off to the nearest KHz value by the
* remote function. So a return value of 0 doesn't necessarily mean
* that the exact rate was set successfully.
*/
if (p->flags & CLKFLAG_MIN)
rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
else
rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
if (rc < 0)
return rc;
else
return (int)id < 0 ? -EINVAL : 0;
}
static unsigned long pc_clk_recalc_rate(struct clk_hw *hw, unsigned long p_rate)
{
unsigned id = to_clk_pcom(hw)->id;
if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
return 0;
else
return id;
}
static int pc_clk_is_enabled(struct clk_hw *hw)
{
unsigned id = to_clk_pcom(hw)->id;
if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
return 0;
else
return id;
}
static long pc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *p_rate)
{
/* Not really supported; pc_clk_set_rate() does rounding on it's own. */
return rate;
}
static struct clk_ops clk_ops_pcom = {
.enable = pc_clk_enable,
.disable = pc_clk_disable,
.set_rate = pc_clk_set_rate,
.recalc_rate = pc_clk_recalc_rate,
.is_enabled = pc_clk_is_enabled,
.round_rate = pc_clk_round_rate,
};
static int msm_clock_pcom_probe(struct platform_device *pdev)
{
const struct pcom_clk_pdata *pdata = pdev->dev.platform_data;
int i, ret;
for (i = 0; i < pdata->num_lookups; i++) {
const struct clk_pcom_desc *desc = &pdata->lookup[i];
struct clk *c;
struct clk_pcom *p;
struct clk_hw *hw;
struct clk_init_data init;
p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
if (!p)
return -ENOMEM;
p->id = desc->id;
p->flags = desc->flags;
p->msm_clk.reset = pc_clk_reset;
hw = &p->msm_clk.hw;
hw->init = &init;
init.name = desc->name;
init.ops = &clk_ops_pcom;
init.num_parents = 0;
init.flags = CLK_IS_ROOT;
if (!(p->flags & CLKFLAG_AUTO_OFF))
init.flags |= CLK_IGNORE_UNUSED;
c = devm_clk_register(&pdev->dev, hw);
ret = clk_register_clkdev(c, desc->con, desc->dev);
if (ret)
return ret;
}
return 0;
}
static struct platform_driver msm_clock_pcom_driver = {
.probe = msm_clock_pcom_probe,
.driver = {
.name = "msm-clock-pcom",
.owner = THIS_MODULE,
},
};
module_platform_driver(msm_clock_pcom_driver);
MODULE_LICENSE("GPL v2");

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/*
* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H
#define __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H
/* clock IDs used by the modem processor */
#define P_ACPU_CLK 0 /* Applications processor clock */
#define P_ADM_CLK 1 /* Applications data mover clock */
#define P_ADSP_CLK 2 /* ADSP clock */
#define P_EBI1_CLK 3 /* External bus interface 1 clock */
#define P_EBI2_CLK 4 /* External bus interface 2 clock */
#define P_ECODEC_CLK 5 /* External CODEC clock */
#define P_EMDH_CLK 6 /* External MDDI host clock */
#define P_GP_CLK 7 /* General purpose clock */
#define P_GRP_3D_CLK 8 /* Graphics clock */
#define P_I2C_CLK 9 /* I2C clock */
#define P_ICODEC_RX_CLK 10 /* Internal CODEX RX clock */
#define P_ICODEC_TX_CLK 11 /* Internal CODEX TX clock */
#define P_IMEM_CLK 12 /* Internal graphics memory clock */
#define P_MDC_CLK 13 /* MDDI client clock */
#define P_MDP_CLK 14 /* Mobile display processor clock */
#define P_PBUS_CLK 15 /* Peripheral bus clock */
#define P_PCM_CLK 16 /* PCM clock */
#define P_PMDH_CLK 17 /* Primary MDDI host clock */
#define P_SDAC_CLK 18 /* Stereo DAC clock */
#define P_SDC1_CLK 19 /* Secure Digital Card clocks */
#define P_SDC1_P_CLK 20
#define P_SDC2_CLK 21
#define P_SDC2_P_CLK 22
#define P_SDC3_CLK 23
#define P_SDC3_P_CLK 24
#define P_SDC4_CLK 25
#define P_SDC4_P_CLK 26
#define P_TSIF_CLK 27 /* Transport Stream Interface clocks */
#define P_TSIF_REF_CLK 28
#define P_TV_DAC_CLK 29 /* TV clocks */
#define P_TV_ENC_CLK 30
#define P_UART1_CLK 31 /* UART clocks */
#define P_UART2_CLK 32
#define P_UART3_CLK 33
#define P_UART1DM_CLK 34
#define P_UART2DM_CLK 35
#define P_USB_HS_CLK 36 /* High speed USB core clock */
#define P_USB_HS_P_CLK 37 /* High speed USB pbus clock */
#define P_USB_OTG_CLK 38 /* Full speed USB clock */
#define P_VDC_CLK 39 /* Video controller clock */
#define P_VFE_MDC_CLK 40 /* Camera / Video Front End clock */
#define P_VFE_CLK 41 /* VFE MDDI client clock */
#define P_MDP_LCDC_PCLK_CLK 42
#define P_MDP_LCDC_PAD_PCLK_CLK 43
#define P_MDP_VSYNC_CLK 44
#define P_SPI_CLK 45
#define P_VFE_AXI_CLK 46
#define P_USB_HS2_CLK 47 /* High speed USB 2 core clock */
#define P_USB_HS2_P_CLK 48 /* High speed USB 2 pbus clock */
#define P_USB_HS3_CLK 49 /* High speed USB 3 core clock */
#define P_USB_HS3_P_CLK 50 /* High speed USB 3 pbus clock */
#define P_GRP_3D_P_CLK 51 /* Graphics pbus clock */
#define P_USB_PHY_CLK 52 /* USB PHY clock */
#define P_USB_HS_CORE_CLK 53 /* High speed USB 1 core clock */
#define P_USB_HS2_CORE_CLK 54 /* High speed USB 2 core clock */
#define P_USB_HS3_CORE_CLK 55 /* High speed USB 3 core clock */
#define P_CAM_M_CLK 56
#define P_CAMIF_PAD_P_CLK 57
#define P_GRP_2D_CLK 58
#define P_GRP_2D_P_CLK 59
#define P_I2S_CLK 60
#define P_JPEG_CLK 61
#define P_JPEG_P_CLK 62
#define P_LPA_CODEC_CLK 63
#define P_LPA_CORE_CLK 64
#define P_LPA_P_CLK 65
#define P_MDC_IO_CLK 66
#define P_MDC_P_CLK 67
#define P_MFC_CLK 68
#define P_MFC_DIV2_CLK 69
#define P_MFC_P_CLK 70
#define P_QUP_I2C_CLK 71
#define P_ROTATOR_IMEM_CLK 72
#define P_ROTATOR_P_CLK 73
#define P_VFE_CAMIF_CLK 74
#define P_VFE_P_CLK 75
#define P_VPE_CLK 76
#define P_I2C_2_CLK 77
#define P_MI2S_CODEC_RX_S_CLK 78
#define P_MI2S_CODEC_RX_M_CLK 79
#define P_MI2S_CODEC_TX_S_CLK 80
#define P_MI2S_CODEC_TX_M_CLK 81
#define P_PMDH_P_CLK 82
#define P_EMDH_P_CLK 83
#define P_SPI_P_CLK 84
#define P_TSIF_P_CLK 85
#define P_MDP_P_CLK 86
#define P_SDAC_M_CLK 87
#define P_MI2S_S_CLK 88
#define P_MI2S_M_CLK 89
#define P_AXI_ROTATOR_CLK 90
#define P_HDMI_CLK 91
#define P_CSI0_CLK 92
#define P_CSI0_VFE_CLK 93
#define P_CSI0_P_CLK 94
#define P_CSI1_CLK 95
#define P_CSI1_VFE_CLK 96
#define P_CSI1_P_CLK 97
#define P_GSBI_CLK 98
#define P_GSBI_P_CLK 99
#define P_CE_CLK 100 /* Crypto engine */
#define P_CODEC_SSBI_CLK 101
#define P_NR_CLKS 102
struct clk_pcom_desc {
unsigned id;
const char *name;
const char *con;
const char *dev;
unsigned long flags;
};
struct pcom_clk_pdata {
struct clk_pcom_desc *lookup;
u32 num_lookups;
};
#define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) { \
.id = P_##clk_id, \
.name = #clk_id, \
.con = clk_name, \
.dev = clk_dev, \
.flags = clk_flags, \
}
#endif

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/* arch/arm/mach-msm/clock.c
*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include "clock.h"
int clk_reset(struct clk *clk, enum clk_reset_action action)
{
struct clk_hw *hw = __clk_get_hw(clk);
struct msm_clk *m = to_msm_clk(hw);
return m->reset(hw, action);
}
EXPORT_SYMBOL(clk_reset);

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arch/arm/mach-msm/clock.h Normal file
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/* arch/arm/mach-msm/clock.h
*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ARCH_ARM_MACH_MSM_CLOCK_H
#define __ARCH_ARM_MACH_MSM_CLOCK_H
#include <linux/clk-provider.h>
#include <mach/clk.h>
#define CLK_FIRST_AVAILABLE_FLAG 0x00000100
#define CLKFLAG_AUTO_OFF 0x00000200
#define CLKFLAG_MIN 0x00000400
#define CLKFLAG_MAX 0x00000800
#define OFF CLKFLAG_AUTO_OFF
#define CLK_MIN CLKFLAG_MIN
#define CLK_MAX CLKFLAG_MAX
#define CLK_MINMAX (CLK_MIN | CLK_MAX)
struct msm_clk {
int (*reset)(struct clk_hw *hw, enum clk_reset_action action);
struct clk_hw hw;
};
static inline struct msm_clk *to_msm_clk(struct clk_hw *hw)
{
return container_of(hw, struct msm_clk, hw);
}
#endif

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/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_COMMON_H
#define __MACH_COMMON_H
extern void msm7x01_timer_init(void);
extern void msm7x30_timer_init(void);
extern void qsd8x50_timer_init(void);
extern void msm_map_common_io(void);
extern void msm_map_msm7x30_io(void);
extern void msm_map_qsd8x50_io(void);
extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
unsigned int mtype, void *caller);
struct msm_mmc_platform_data;
extern void msm_add_devices(void);
extern void msm_init_irq(void);
extern void msm_init_gpio(void);
extern int msm_add_sdcc(unsigned int controller,
struct msm_mmc_platform_data *plat,
unsigned int stat_irq, unsigned long stat_irq_flags);
#if defined(CONFIG_MSM_SMD) && defined(CONFIG_DEBUG_FS)
extern int smd_debugfs_init(void);
#else
static inline int smd_debugfs_init(void) { return 0; }
#endif
#endif

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arch/arm/mach-msm/devices-msm7x00.c Normal file
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/* linux/arch/arm/mach-msm/devices.c
*
* Copyright (C) 2008 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/clkdev.h>
#include <mach/irqs.h>
#include <mach/msm_iomap.h>
#include "devices.h"
#include <asm/mach/flash.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include "clock.h"
#include "clock-pcom.h"
#include <linux/platform_data/mmc-msm_sdcc.h>
static struct resource msm_gpio_resources[] = {
{
.start = 32 + 0,
.end = 32 + 0,
.flags = IORESOURCE_IRQ,
},
{
.start = 32 + 1,
.end = 32 + 1,
.flags = IORESOURCE_IRQ,
},
{
.start = 0xa9200800,
.end = 0xa9200800 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
.name = "gpio1"
},
{
.start = 0xa9300C00,
.end = 0xa9300C00 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
.name = "gpio2"
},
};
struct platform_device msm_device_gpio_7201 = {
.name = "gpio-msm-7201",
.num_resources = ARRAY_SIZE(msm_gpio_resources),
.resource = msm_gpio_resources,
};
static struct resource resources_uart1[] = {
{
.start = INT_UART1,
.end = INT_UART1,
.flags = IORESOURCE_IRQ,
},
{
.start = MSM_UART1_PHYS,
.end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1,
.flags = IORESOURCE_MEM,
.name = "uart_resource"
},
};
static struct resource resources_uart2[] = {
{
.start = INT_UART2,
.end = INT_UART2,
.flags = IORESOURCE_IRQ,
},
{
.start = MSM_UART2_PHYS,
.end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
.flags = IORESOURCE_MEM,
.name = "uart_resource"
},
};
static struct resource resources_uart3[] = {
{
.start = INT_UART3,
.end = INT_UART3,
.flags = IORESOURCE_IRQ,
},
{
.start = MSM_UART3_PHYS,
.end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
.flags = IORESOURCE_MEM,
.name = "uart_resource"
},
};
struct platform_device msm_device_uart1 = {
.name = "msm_serial",
.id = 0,
.num_resources = ARRAY_SIZE(resources_uart1),
.resource = resources_uart1,
};
struct platform_device msm_device_uart2 = {
.name = "msm_serial",
.id = 1,
.num_resources = ARRAY_SIZE(resources_uart2),
.resource = resources_uart2,
};
struct platform_device msm_device_uart3 = {
.name = "msm_serial",
.id = 2,
.num_resources = ARRAY_SIZE(resources_uart3),
.resource = resources_uart3,
};
static struct resource resources_i2c[] = {
{
.start = MSM_I2C_PHYS,
.end = MSM_I2C_PHYS + MSM_I2C_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = INT_PWB_I2C,
.end = INT_PWB_I2C,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device msm_device_i2c = {
.name = "msm_i2c",
.id = 0,
.num_resources = ARRAY_SIZE(resources_i2c),
.resource = resources_i2c,
};
static struct resource resources_hsusb[] = {
{
.start = MSM_HSUSB_PHYS,
.end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
.flags = IORESOURCE_MEM,
},
{
.start = INT_USB_HS,
.end = INT_USB_HS,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device msm_device_hsusb = {
.name = "msm_hsusb",
.id = -1,
.num_resources = ARRAY_SIZE(resources_hsusb),
.resource = resources_hsusb,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
struct flash_platform_data msm_nand_data = {
.parts = NULL,
.nr_parts = 0,
};
static struct resource resources_nand[] = {
[0] = {
.start = 7,
.end = 7,
.flags = IORESOURCE_DMA,
},
};
struct platform_device msm_device_nand = {
.name = "msm_nand",
.id = -1,
.num_resources = ARRAY_SIZE(resources_nand),
.resource = resources_nand,
.dev = {
.platform_data = &msm_nand_data,
},
};
struct platform_device msm_device_smd = {
.name = "msm_smd",
.id = -1,
};
static struct resource resources_sdc1[] = {
{
.start = MSM_SDC1_PHYS,
.end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = INT_SDC1_0,
.end = INT_SDC1_0,
.flags = IORESOURCE_IRQ,
.name = "cmd_irq",
},
{
.flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
.name = "status_irq"
},
{
.start = 8,
.end = 8,
.flags = IORESOURCE_DMA,
},
};
static struct resource resources_sdc2[] = {
{
.start = MSM_SDC2_PHYS,
.end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = INT_SDC2_0,
.end = INT_SDC2_0,
.flags = IORESOURCE_IRQ,
.name = "cmd_irq",
},
{
.flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
.name = "status_irq"
},
{
.start = 8,
.end = 8,
.flags = IORESOURCE_DMA,
},
};
static struct resource resources_sdc3[] = {
{
.start = MSM_SDC3_PHYS,
.end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = INT_SDC3_0,
.end = INT_SDC3_0,
.flags = IORESOURCE_IRQ,
.name = "cmd_irq",
},
{
.flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
.name = "status_irq"
},
{
.start = 8,
.end = 8,
.flags = IORESOURCE_DMA,
},
};
static struct resource resources_sdc4[] = {
{
.start = MSM_SDC4_PHYS,
.end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = INT_SDC4_0,
.end = INT_SDC4_0,
.flags = IORESOURCE_IRQ,
.name = "cmd_irq",
},
{
.flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
.name = "status_irq"
},
{
.start = 8,
.end = 8,
.flags = IORESOURCE_DMA,
},
};
struct platform_device msm_device_sdc1 = {
.name = "msm_sdcc",
.id = 1,
.num_resources = ARRAY_SIZE(resources_sdc1),
.resource = resources_sdc1,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
struct platform_device msm_device_sdc2 = {
.name = "msm_sdcc",
.id = 2,
.num_resources = ARRAY_SIZE(resources_sdc2),
.resource = resources_sdc2,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
struct platform_device msm_device_sdc3 = {
.name = "msm_sdcc",
.id = 3,
.num_resources = ARRAY_SIZE(resources_sdc3),
.resource = resources_sdc3,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
struct platform_device msm_device_sdc4 = {
.name = "msm_sdcc",
.id = 4,
.num_resources = ARRAY_SIZE(resources_sdc4),
.resource = resources_sdc4,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
static struct platform_device *msm_sdcc_devices[] __initdata = {
&msm_device_sdc1,
&msm_device_sdc2,
&msm_device_sdc3,
&msm_device_sdc4,
};
int __init msm_add_sdcc(unsigned int controller,
struct msm_mmc_platform_data *plat,
unsigned int stat_irq, unsigned long stat_irq_flags)
{
struct platform_device *pdev;
struct resource *res;
if (controller < 1 || controller > 4)
return -EINVAL;
pdev = msm_sdcc_devices[controller-1];
pdev->dev.platform_data = plat;
res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
if (!res)
return -EINVAL;
else if (stat_irq) {
res->start = res->end = stat_irq;
res->flags &= ~IORESOURCE_DISABLED;
res->flags |= stat_irq_flags;
}
return platform_device_register(pdev);
}
static struct resource resources_mddi0[] = {
{
.start = MSM_PMDH_PHYS,
.end = MSM_PMDH_PHYS + MSM_PMDH_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = INT_MDDI_PRI,
.end = INT_MDDI_PRI,
.flags = IORESOURCE_IRQ,
},
};
static struct resource resources_mddi1[] = {
{
.start = MSM_EMDH_PHYS,
.end = MSM_EMDH_PHYS + MSM_EMDH_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = INT_MDDI_EXT,
.end = INT_MDDI_EXT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device msm_device_mddi0 = {
.name = "msm_mddi",
.id = 0,
.num_resources = ARRAY_SIZE(resources_mddi0),
.resource = resources_mddi0,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
struct platform_device msm_device_mddi1 = {
.name = "msm_mddi",
.id = 1,
.num_resources = ARRAY_SIZE(resources_mddi1),
.resource = resources_mddi1,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
static struct resource resources_mdp[] = {
{
.start = MSM_MDP_PHYS,
.end = MSM_MDP_PHYS + MSM_MDP_SIZE - 1,
.name = "mdp",
.flags = IORESOURCE_MEM
},
{
.start = INT_MDP,
.end = INT_MDP,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device msm_device_mdp = {
.name = "msm_mdp",
.id = 0,
.num_resources = ARRAY_SIZE(resources_mdp),
.resource = resources_mdp,
};
static struct clk_pcom_desc msm_clocks_7x01a[] = {
CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0),
CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, 0),
CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0),
CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0),
CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF),
CLK_PCOM("gp_clk", GP_CLK, NULL, 0),
CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, OFF),
CLK_PCOM("i2c_clk", I2C_CLK, "msm_i2c.0", 0),
CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0),
CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0),
CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0),
CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF),
CLK_PCOM("pbus_clk", PBUS_CLK, NULL, 0),
CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0),
CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX),
CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF),
CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF),
CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF),
CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF),
CLK_PCOM("sdc_clk", SDC3_CLK, "msm_sdcc.3", OFF),
CLK_PCOM("sdc_pclk", SDC3_P_CLK, "msm_sdcc.3", OFF),
CLK_PCOM("sdc_clk", SDC4_CLK, "msm_sdcc.4", OFF),
CLK_PCOM("sdc_pclk", SDC4_P_CLK, "msm_sdcc.4", OFF),
CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0),
CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0),
CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0),
CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0),
CLK_PCOM("core", UART1_CLK, "msm_serial.0", OFF),
CLK_PCOM("core", UART2_CLK, "msm_serial.1", 0),
CLK_PCOM("core", UART3_CLK, "msm_serial.2", OFF),
CLK_PCOM("uart1dm_clk", UART1DM_CLK, NULL, OFF),
CLK_PCOM("uart2dm_clk", UART2DM_CLK, NULL, 0),
CLK_PCOM("usb_hs_clk", USB_HS_CLK, "msm_hsusb", OFF),
CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, "msm_hsusb", OFF),
CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0),
CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF ),
CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF),
CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF),
};
static struct pcom_clk_pdata msm_clock_7x01a_pdata = {
.lookup = msm_clocks_7x01a,
.num_lookups = ARRAY_SIZE(msm_clocks_7x01a),
};
struct platform_device msm_clock_7x01a = {
.name = "msm-clock-pcom",
.dev.platform_data = &msm_clock_7x01a_pdata,
};

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/*
* Copyright (C) 2008 Google, Inc.
* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/clkdev.h>
#include <mach/irqs.h>
#include <mach/msm_iomap.h>
#include <mach/dma.h>
#include "devices.h"
#include "smd_private.h"
#include "common.h"
#include <asm/mach/flash.h>
#include "clock.h"
#include "clock-pcom.h"
#include <linux/platform_data/mmc-msm_sdcc.h>
static struct resource msm_gpio_resources[] = {
{
.start = 32 + 18,
.end = 32 + 18,
.flags = IORESOURCE_IRQ,
},
{
.start = 32 + 19,
.end = 32 + 19,
.flags = IORESOURCE_IRQ,
},
{
.start = 0xac001000,
.end = 0xac001000 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
.name = "gpio1"
},
{
.start = 0xac101400,
.end = 0xac101400 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
.name = "gpio2"
},
};
struct platform_device msm_device_gpio_7x30 = {
.name = "gpio-msm-7x30",
.num_resources = ARRAY_SIZE(msm_gpio_resources),
.resource = msm_gpio_resources,
};
static struct resource resources_uart2[] = {
{
.start = INT_UART2,
.end = INT_UART2,
.flags = IORESOURCE_IRQ,
},
{
.start = MSM_UART2_PHYS,
.end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
.flags = IORESOURCE_MEM,
.name = "uart_resource"
},
};
struct platform_device msm_device_uart2 = {
.name = "msm_serial",
.id = 1,
.num_resources = ARRAY_SIZE(resources_uart2),
.resource = resources_uart2,
};
struct platform_device msm_device_smd = {
.name = "msm_smd",
.id = -1,
};
static struct resource resources_otg[] = {
{
.start = MSM_HSUSB_PHYS,
.end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
.flags = IORESOURCE_MEM,
},
{
.start = INT_USB_HS,
.end = INT_USB_HS,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device msm_device_otg = {
.name = "msm_otg",
.id = -1,
.num_resources = ARRAY_SIZE(resources_otg),
.resource = resources_otg,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
static struct resource resources_hsusb[] = {
{
.start = MSM_HSUSB_PHYS,
.end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
.flags = IORESOURCE_MEM,
},
{
.start = INT_USB_HS,
.end = INT_USB_HS,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device msm_device_hsusb = {
.name = "msm_hsusb",
.id = -1,
.num_resources = ARRAY_SIZE(resources_hsusb),
.resource = resources_hsusb,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
static u64 dma_mask = 0xffffffffULL;
static struct resource resources_hsusb_host[] = {
{
.start = MSM_HSUSB_PHYS,
.end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
.flags = IORESOURCE_MEM,
},
{
.start = INT_USB_HS,
.end = INT_USB_HS,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device msm_device_hsusb_host = {
.name = "msm_hsusb_host",
.id = -1,
.num_resources = ARRAY_SIZE(resources_hsusb_host),
.resource = resources_hsusb_host,
.dev = {
.dma_mask = &dma_mask,
.coherent_dma_mask = 0xffffffffULL,
},
};
static struct clk_pcom_desc msm_clocks_7x30[] = {
CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0),
CLK_PCOM("cam_m_clk", CAM_M_CLK, NULL, 0),
CLK_PCOM("camif_pad_pclk", CAMIF_PAD_P_CLK, NULL, OFF),
CLK_PCOM("ce_clk", CE_CLK, NULL, 0),
CLK_PCOM("codec_ssbi_clk", CODEC_SSBI_CLK, NULL, 0),
CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN),
CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0),
CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX),
CLK_PCOM("emdh_pclk", EMDH_P_CLK, NULL, OFF),
CLK_PCOM("gp_clk", GP_CLK, NULL, 0),
CLK_PCOM("grp_2d_clk", GRP_2D_CLK, NULL, 0),
CLK_PCOM("grp_2d_pclk", GRP_2D_P_CLK, NULL, 0),
CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0),
CLK_PCOM("grp_pclk", GRP_3D_P_CLK, NULL, 0),
CLK_PCOM("hdmi_clk", HDMI_CLK, NULL, 0),
CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
CLK_PCOM("jpeg_clk", JPEG_CLK, NULL, OFF),
CLK_PCOM("jpeg_pclk", JPEG_P_CLK, NULL, OFF),
CLK_PCOM("lpa_codec_clk", LPA_CODEC_CLK, NULL, 0),
CLK_PCOM("lpa_core_clk", LPA_CORE_CLK, NULL, 0),
CLK_PCOM("lpa_pclk", LPA_P_CLK, NULL, 0),
CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0),
CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX),
CLK_PCOM("mddi_pclk", PMDH_P_CLK, NULL, 0),
CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF),
CLK_PCOM("mdp_pclk", MDP_P_CLK, NULL, 0),
CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0),
CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0),
CLK_PCOM("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, 0),
CLK_PCOM("mfc_clk", MFC_CLK, NULL, 0),
CLK_PCOM("mfc_div2_clk", MFC_DIV2_CLK, NULL, 0),
CLK_PCOM("mfc_pclk", MFC_P_CLK, NULL, 0),
CLK_PCOM("mi2s_m_clk", MI2S_M_CLK, NULL, 0),
CLK_PCOM("mi2s_s_clk", MI2S_S_CLK, NULL, 0),
CLK_PCOM("mi2s_codec_rx_m_clk", MI2S_CODEC_RX_M_CLK, NULL, 0),
CLK_PCOM("mi2s_codec_rx_s_clk", MI2S_CODEC_RX_S_CLK, NULL, 0),
CLK_PCOM("mi2s_codec_tx_m_clk", MI2S_CODEC_TX_M_CLK, NULL, 0),
CLK_PCOM("mi2s_codec_tx_s_clk", MI2S_CODEC_TX_S_CLK, NULL, 0),
CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN),
CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0),
CLK_PCOM("rotator_clk", AXI_ROTATOR_CLK, NULL, 0),
CLK_PCOM("rotator_imem_clk", ROTATOR_IMEM_CLK, NULL, OFF),
CLK_PCOM("rotator_pclk", ROTATOR_P_CLK, NULL, OFF),
CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
CLK_PCOM("spi_clk", SPI_CLK, NULL, 0),
CLK_PCOM("spi_pclk", SPI_P_CLK, NULL, 0),
CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0),
CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0),
CLK_PCOM("core", UART2_CLK, "msm_serial.1", 0),
CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0),
CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF),
CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF),
CLK_PCOM("usb_hs_core_clk", USB_HS_CORE_CLK, NULL, OFF),
CLK_PCOM("usb_hs2_clk", USB_HS2_CLK, NULL, OFF),
CLK_PCOM("usb_hs2_pclk", USB_HS2_P_CLK, NULL, OFF),
CLK_PCOM("usb_hs2_core_clk", USB_HS2_CORE_CLK, NULL, OFF),
CLK_PCOM("usb_hs3_clk", USB_HS3_CLK, NULL, OFF),
CLK_PCOM("usb_hs3_pclk", USB_HS3_P_CLK, NULL, OFF),
CLK_PCOM("usb_hs3_core_clk", USB_HS3_CORE_CLK, NULL, OFF),
CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF | CLK_MIN),
CLK_PCOM("vfe_camif_clk", VFE_CAMIF_CLK, NULL, 0),
CLK_PCOM("vfe_clk", VFE_CLK, NULL, 0),
CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, 0),
CLK_PCOM("vfe_pclk", VFE_P_CLK, NULL, OFF),
CLK_PCOM("vpe_clk", VPE_CLK, NULL, 0),
/* 7x30 v2 hardware only. */
CLK_PCOM("csi_clk", CSI0_CLK, NULL, 0),
CLK_PCOM("csi_pclk", CSI0_P_CLK, NULL, 0),
CLK_PCOM("csi_vfe_clk", CSI0_VFE_CLK, NULL, 0),
};
static struct pcom_clk_pdata msm_clock_7x30_pdata = {
.lookup = msm_clocks_7x30,
.num_lookups = ARRAY_SIZE(msm_clocks_7x30),
};
struct platform_device msm_clock_7x30 = {
.name = "msm-clock-pcom",
.dev.platform_data = &msm_clock_7x30_pdata,
};

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arch/arm/mach-msm/devices-qsd8x50.c Normal file
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/*
* Copyright (C) 2008 Google, Inc.
* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/clkdev.h>
#include <linux/dma-mapping.h>
#include <mach/irqs.h>
#include <mach/msm_iomap.h>
#include <mach/dma.h>
#include "devices.h"
#include "common.h"
#include <asm/mach/flash.h>
#include <linux/platform_data/mmc-msm_sdcc.h>
#include "clock.h"
#include "clock-pcom.h"
static struct resource msm_gpio_resources[] = {
{
.start = 64 + 165 + 9,
.end = 64 + 165 + 9,
.flags = IORESOURCE_IRQ,
},
{
.start = 64 + 165 + 10,
.end = 64 + 165 + 10,
.flags = IORESOURCE_IRQ,
},
{
.start = 0xa9000800,
.end = 0xa9000800 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
.name = "gpio1"
},
{
.start = 0xa9100C00,
.end = 0xa9100C00 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
.name = "gpio2"
},
};
struct platform_device msm_device_gpio_8x50 = {
.name = "gpio-msm-8x50",
.num_resources = ARRAY_SIZE(msm_gpio_resources),
.resource = msm_gpio_resources,
};
static struct resource resources_uart3[] = {
{
.start = INT_UART3,
.end = INT_UART3,
.flags = IORESOURCE_IRQ,
},
{
.start = MSM_UART3_PHYS,
.end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
.flags = IORESOURCE_MEM,
.name = "uart_resource"
},
};
struct platform_device msm_device_uart3 = {
.name = "msm_serial",
.id = 2,
.num_resources = ARRAY_SIZE(resources_uart3),
.resource = resources_uart3,
};
struct platform_device msm_device_smd = {
.name = "msm_smd",
.id = -1,
};
static struct resource resources_otg[] = {
{
.start = MSM_HSUSB_PHYS,
.end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
.flags = IORESOURCE_MEM,
},
{
.start = INT_USB_HS,
.end = INT_USB_HS,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device msm_device_otg = {
.name = "msm_otg",
.id = -1,
.num_resources = ARRAY_SIZE(resources_otg),
.resource = resources_otg,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
static struct resource resources_hsusb[] = {
{
.start = MSM_HSUSB_PHYS,
.end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
.flags = IORESOURCE_MEM,
},
{
.start = INT_USB_HS,
.end = INT_USB_HS,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device msm_device_hsusb = {
.name = "msm_hsusb",
.id = -1,
.num_resources = ARRAY_SIZE(resources_hsusb),
.resource = resources_hsusb,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
static u64 dma_mask = 0xffffffffULL;
static struct resource resources_hsusb_host[] = {
{
.start = MSM_HSUSB_PHYS,
.end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
.flags = IORESOURCE_MEM,
},
{
.start = INT_USB_HS,
.end = INT_USB_HS,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device msm_device_hsusb_host = {
.name = "msm_hsusb_host",
.id = -1,
.num_resources = ARRAY_SIZE(resources_hsusb_host),
.resource = resources_hsusb_host,
.dev = {
.dma_mask = &dma_mask,
.coherent_dma_mask = 0xffffffffULL,
},
};
static struct resource resources_sdc1[] = {
{
.start = MSM_SDC1_PHYS,
.end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = INT_SDC1_0,
.end = INT_SDC1_0,
.flags = IORESOURCE_IRQ,
.name = "cmd_irq",
},
{
.flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
.name = "status_irq"
},
{
.start = 8,
.end = 8,
.flags = IORESOURCE_DMA,
},
};
static struct resource resources_sdc2[] = {
{
.start = MSM_SDC2_PHYS,
.end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = INT_SDC2_0,
.end = INT_SDC2_0,
.flags = IORESOURCE_IRQ,
.name = "cmd_irq",
},
{
.flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
.name = "status_irq"
},
{
.start = 8,
.end = 8,
.flags = IORESOURCE_DMA,
},
};
static struct resource resources_sdc3[] = {
{
.start = MSM_SDC3_PHYS,
.end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = INT_SDC3_0,
.end = INT_SDC3_0,
.flags = IORESOURCE_IRQ,
.name = "cmd_irq",
},
{
.flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
.name = "status_irq"
},
{
.start = 8,
.end = 8,
.flags = IORESOURCE_DMA,
},
};
static struct resource resources_sdc4[] = {
{
.start = MSM_SDC4_PHYS,
.end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = INT_SDC4_0,
.end = INT_SDC4_0,
.flags = IORESOURCE_IRQ,
.name = "cmd_irq",
},
{
.flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
.name = "status_irq"
},
{
.start = 8,
.end = 8,
.flags = IORESOURCE_DMA,
},
};
struct platform_device msm_device_sdc1 = {
.name = "msm_sdcc",
.id = 1,
.num_resources = ARRAY_SIZE(resources_sdc1),
.resource = resources_sdc1,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
struct platform_device msm_device_sdc2 = {
.name = "msm_sdcc",
.id = 2,
.num_resources = ARRAY_SIZE(resources_sdc2),
.resource = resources_sdc2,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
struct platform_device msm_device_sdc3 = {
.name = "msm_sdcc",
.id = 3,
.num_resources = ARRAY_SIZE(resources_sdc3),
.resource = resources_sdc3,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
struct platform_device msm_device_sdc4 = {
.name = "msm_sdcc",
.id = 4,
.num_resources = ARRAY_SIZE(resources_sdc4),
.resource = resources_sdc4,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
static struct platform_device *msm_sdcc_devices[] __initdata = {
&msm_device_sdc1,
&msm_device_sdc2,
&msm_device_sdc3,
&msm_device_sdc4,
};
int __init msm_add_sdcc(unsigned int controller,
struct msm_mmc_platform_data *plat,
unsigned int stat_irq, unsigned long stat_irq_flags)
{
struct platform_device *pdev;
struct resource *res;
if (controller < 1 || controller > 4)
return -EINVAL;
pdev = msm_sdcc_devices[controller-1];
pdev->dev.platform_data = plat;
res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
if (!res)
return -EINVAL;
else if (stat_irq) {
res->start = res->end = stat_irq;
res->flags &= ~IORESOURCE_DISABLED;
res->flags |= stat_irq_flags;
}
return platform_device_register(pdev);
}
static struct clk_pcom_desc msm_clocks_8x50[] = {
CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
CLK_PCOM("ce_clk", CE_CLK, NULL, 0),
CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN),
CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0),
CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0),
CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX),
CLK_PCOM("gp_clk", GP_CLK, NULL, 0),
CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0),
CLK_PCOM("i2c_clk", I2C_CLK, NULL, 0),
CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0),
CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0),
CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0),
CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX),
CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF),
CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0),
CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0),
CLK_PCOM("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, 0),
CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN),
CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0),
CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF),
CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF),
CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF),
CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF),
CLK_PCOM("sdc_clk", SDC3_CLK, "msm_sdcc.3", OFF),
CLK_PCOM("sdc_pclk", SDC3_P_CLK, "msm_sdcc.3", OFF),
CLK_PCOM("sdc_clk", SDC4_CLK, "msm_sdcc.4", OFF),
CLK_PCOM("sdc_pclk", SDC4_P_CLK, "msm_sdcc.4", OFF),
CLK_PCOM("spi_clk", SPI_CLK, NULL, 0),
CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0),
CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0),
CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0),
CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0),
CLK_PCOM("core", UART1_CLK, NULL, OFF),
CLK_PCOM("core", UART2_CLK, NULL, 0),
CLK_PCOM("core", UART3_CLK, "msm_serial.2", OFF),
CLK_PCOM("uartdm_clk", UART1DM_CLK, NULL, OFF),
CLK_PCOM("uartdm_clk", UART2DM_CLK, NULL, 0),
CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF),
CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF),
CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0),
CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF | CLK_MIN),
CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF),
CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF),
CLK_PCOM("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF),
CLK_PCOM("usb_hs2_clk", USB_HS2_CLK, NULL, OFF),
CLK_PCOM("usb_hs2_pclk", USB_HS2_P_CLK, NULL, OFF),
CLK_PCOM("usb_hs3_clk", USB_HS3_CLK, NULL, OFF),
CLK_PCOM("usb_hs3_pclk", USB_HS3_P_CLK, NULL, OFF),
CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0),
};
static struct pcom_clk_pdata msm_clock_8x50_pdata = {
.lookup = msm_clocks_8x50,
.num_lookups = ARRAY_SIZE(msm_clocks_8x50),
};
struct platform_device msm_clock_8x50 = {
.name = "msm-clock-pcom",
.dev.platform_data = &msm_clock_8x50_pdata,
};

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/* linux/arch/arm/mach-msm/devices.h
*
* Copyright (C) 2008 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ARCH_ARM_MACH_MSM_DEVICES_H
#define __ARCH_ARM_MACH_MSM_DEVICES_H
extern struct platform_device msm_device_gpio_7201;
extern struct platform_device msm_device_gpio_7x30;
extern struct platform_device msm_device_gpio_8x50;
extern struct platform_device msm_device_uart1;
extern struct platform_device msm_device_uart2;
extern struct platform_device msm_device_uart3;
extern struct platform_device msm8960_device_uart_gsbi2;
extern struct platform_device msm8960_device_uart_gsbi5;
extern struct platform_device msm_device_sdc1;
extern struct platform_device msm_device_sdc2;
extern struct platform_device msm_device_sdc3;
extern struct platform_device msm_device_sdc4;
extern struct platform_device msm_device_hsusb;
extern struct platform_device msm_device_otg;
extern struct platform_device msm_device_hsusb_host;
extern struct platform_device msm_device_i2c;
extern struct platform_device msm_device_smd;
extern struct platform_device msm_device_nand;
extern struct platform_device msm_device_mddi0;
extern struct platform_device msm_device_mddi1;
extern struct platform_device msm_device_mdp;
extern struct platform_device msm_clock_7x01a;
extern struct platform_device msm_clock_7x30;
extern struct platform_device msm_clock_8x50;
#endif

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/* linux/arch/arm/mach-msm/dma.c
*
* Copyright (C) 2007 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/completion.h>
#include <linux/module.h>
#include <mach/dma.h>
#include <mach/msm_iomap.h>
#define MSM_DMOV_CHANNEL_COUNT 16
#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2))
#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
#if defined(CONFIG_ARCH_MSM7X30)
#define DMOV_SD_AARM DMOV_SD2
#else
#define DMOV_SD_AARM DMOV_SD3
#endif
#define DMOV_CMD_PTR(ch) DMOV_SD_AARM(0x000, ch)
#define DMOV_RSLT(ch) DMOV_SD_AARM(0x040, ch)
#define DMOV_FLUSH0(ch) DMOV_SD_AARM(0x080, ch)
#define DMOV_FLUSH1(ch) DMOV_SD_AARM(0x0C0, ch)
#define DMOV_FLUSH2(ch) DMOV_SD_AARM(0x100, ch)
#define DMOV_FLUSH3(ch) DMOV_SD_AARM(0x140, ch)
#define DMOV_FLUSH4(ch) DMOV_SD_AARM(0x180, ch)
#define DMOV_FLUSH5(ch) DMOV_SD_AARM(0x1C0, ch)
#define DMOV_STATUS(ch) DMOV_SD_AARM(0x200, ch)
#define DMOV_ISR DMOV_SD_AARM(0x380, 0)
#define DMOV_CONFIG(ch) DMOV_SD_AARM(0x300, ch)
enum {
MSM_DMOV_PRINT_ERRORS = 1,
MSM_DMOV_PRINT_IO = 2,
MSM_DMOV_PRINT_FLOW = 4
};
static DEFINE_SPINLOCK(msm_dmov_lock);
static struct clk *msm_dmov_clk;
static unsigned int channel_active;
static struct list_head ready_commands[MSM_DMOV_CHANNEL_COUNT];
static struct list_head active_commands[MSM_DMOV_CHANNEL_COUNT];
unsigned int msm_dmov_print_mask = MSM_DMOV_PRINT_ERRORS;
#define MSM_DMOV_DPRINTF(mask, format, args...) \
do { \
if ((mask) & msm_dmov_print_mask) \
printk(KERN_ERR format, args); \
} while (0)
#define PRINT_ERROR(format, args...) \
MSM_DMOV_DPRINTF(MSM_DMOV_PRINT_ERRORS, format, args);
#define PRINT_IO(format, args...) \
MSM_DMOV_DPRINTF(MSM_DMOV_PRINT_IO, format, args);
#define PRINT_FLOW(format, args...) \
MSM_DMOV_DPRINTF(MSM_DMOV_PRINT_FLOW, format, args);
void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful)
{
writel((graceful << 31), DMOV_FLUSH0(id));
}
EXPORT_SYMBOL_GPL(msm_dmov_stop_cmd);
void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd)
{
unsigned long irq_flags;
unsigned int status;
spin_lock_irqsave(&msm_dmov_lock, irq_flags);
if (!channel_active)
clk_enable(msm_dmov_clk);
dsb();
status = readl(DMOV_STATUS(id));
if (list_empty(&ready_commands[id]) &&
(status & DMOV_STATUS_CMD_PTR_RDY)) {
#if 0
if (list_empty(&active_commands[id])) {
PRINT_FLOW("msm_dmov_enqueue_cmd(%d), enable interrupt\n", id);
writel(DMOV_CONFIG_IRQ_EN, DMOV_CONFIG(id));
}
#endif
if (cmd->execute_func)
cmd->execute_func(cmd);
PRINT_IO("msm_dmov_enqueue_cmd(%d), start command, status %x\n", id, status);
list_add_tail(&cmd->list, &active_commands[id]);
if (!channel_active)
enable_irq(INT_ADM_AARM);
channel_active |= 1U << id;
writel(cmd->cmdptr, DMOV_CMD_PTR(id));
} else {
if (!channel_active)
clk_disable(msm_dmov_clk);
if (list_empty(&active_commands[id]))
PRINT_ERROR("msm_dmov_enqueue_cmd(%d), error datamover stalled, status %x\n", id, status);
PRINT_IO("msm_dmov_enqueue_cmd(%d), enqueue command, status %x\n", id, status);
list_add_tail(&cmd->list, &ready_commands[id]);
}
spin_unlock_irqrestore(&msm_dmov_lock, irq_flags);
}
EXPORT_SYMBOL_GPL(msm_dmov_enqueue_cmd);
struct msm_dmov_exec_cmdptr_cmd {
struct msm_dmov_cmd dmov_cmd;
struct completion complete;
unsigned id;
unsigned int result;
struct msm_dmov_errdata err;
};
static void
dmov_exec_cmdptr_complete_func(struct msm_dmov_cmd *_cmd,
unsigned int result,
struct msm_dmov_errdata *err)
{
struct msm_dmov_exec_cmdptr_cmd *cmd = container_of(_cmd, struct msm_dmov_exec_cmdptr_cmd, dmov_cmd);
cmd->result = result;
if (result != 0x80000002 && err)
memcpy(&cmd->err, err, sizeof(struct msm_dmov_errdata));
complete(&cmd->complete);
}
int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr)
{
struct msm_dmov_exec_cmdptr_cmd cmd;
PRINT_FLOW("dmov_exec_cmdptr(%d, %x)\n", id, cmdptr);
cmd.dmov_cmd.cmdptr = cmdptr;
cmd.dmov_cmd.complete_func = dmov_exec_cmdptr_complete_func;
cmd.dmov_cmd.execute_func = NULL;
cmd.id = id;
init_completion(&cmd.complete);
msm_dmov_enqueue_cmd(id, &cmd.dmov_cmd);
wait_for_completion(&cmd.complete);
if (cmd.result != 0x80000002) {
PRINT_ERROR("dmov_exec_cmdptr(%d): ERROR, result: %x\n", id, cmd.result);
PRINT_ERROR("dmov_exec_cmdptr(%d): flush: %x %x %x %x\n",
id, cmd.err.flush[0], cmd.err.flush[1], cmd.err.flush[2], cmd.err.flush[3]);
return -EIO;
}
PRINT_FLOW("dmov_exec_cmdptr(%d, %x) done\n", id, cmdptr);
return 0;
}
static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id)
{
unsigned int int_status, mask, id;
unsigned long irq_flags;
unsigned int ch_status;
unsigned int ch_result;
struct msm_dmov_cmd *cmd;
spin_lock_irqsave(&msm_dmov_lock, irq_flags);
int_status = readl(DMOV_ISR); /* read and clear interrupt */
PRINT_FLOW("msm_datamover_irq_handler: DMOV_ISR %x\n", int_status);
while (int_status) {
mask = int_status & -int_status;
id = fls(mask) - 1;
PRINT_FLOW("msm_datamover_irq_handler %08x %08x id %d\n", int_status, mask, id);
int_status &= ~mask;
ch_status = readl(DMOV_STATUS(id));
if (!(ch_status & DMOV_STATUS_RSLT_VALID)) {
PRINT_FLOW("msm_datamover_irq_handler id %d, result not valid %x\n", id, ch_status);
continue;
}
do {
ch_result = readl(DMOV_RSLT(id));
if (list_empty(&active_commands[id])) {
PRINT_ERROR("msm_datamover_irq_handler id %d, got result "
"with no active command, status %x, result %x\n",
id, ch_status, ch_result);
cmd = NULL;
} else
cmd = list_entry(active_commands[id].next, typeof(*cmd), list);
PRINT_FLOW("msm_datamover_irq_handler id %d, status %x, result %x\n", id, ch_status, ch_result);
if (ch_result & DMOV_RSLT_DONE) {
PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n",
id, ch_status);
PRINT_IO("msm_datamover_irq_handler id %d, got result "
"for %p, result %x\n", id, cmd, ch_result);
if (cmd) {
list_del(&cmd->list);
dsb();
cmd->complete_func(cmd, ch_result, NULL);
}
}
if (ch_result & DMOV_RSLT_FLUSH) {
struct msm_dmov_errdata errdata;
errdata.flush[0] = readl(DMOV_FLUSH0(id));
errdata.flush[1] = readl(DMOV_FLUSH1(id));
errdata.flush[2] = readl(DMOV_FLUSH2(id));
errdata.flush[3] = readl(DMOV_FLUSH3(id));
errdata.flush[4] = readl(DMOV_FLUSH4(id));
errdata.flush[5] = readl(DMOV_FLUSH5(id));
PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
PRINT_FLOW("msm_datamover_irq_handler id %d, flush, result %x, flush0 %x\n", id, ch_result, errdata.flush[0]);
if (cmd) {
list_del(&cmd->list);
dsb();
cmd->complete_func(cmd, ch_result, &errdata);
}
}
if (ch_result & DMOV_RSLT_ERROR) {
struct msm_dmov_errdata errdata;
errdata.flush[0] = readl(DMOV_FLUSH0(id));
errdata.flush[1] = readl(DMOV_FLUSH1(id));
errdata.flush[2] = readl(DMOV_FLUSH2(id));
errdata.flush[3] = readl(DMOV_FLUSH3(id));
errdata.flush[4] = readl(DMOV_FLUSH4(id));
errdata.flush[5] = readl(DMOV_FLUSH5(id));
PRINT_ERROR("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
PRINT_ERROR("msm_datamover_irq_handler id %d, error, result %x, flush0 %x\n", id, ch_result, errdata.flush[0]);
if (cmd) {
list_del(&cmd->list);
dsb();
cmd->complete_func(cmd, ch_result, &errdata);
}
/* this does not seem to work, once we get an error */
/* the datamover will no longer accept commands */
writel(0, DMOV_FLUSH0(id));
}
ch_status = readl(DMOV_STATUS(id));
PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) {
cmd = list_entry(ready_commands[id].next, typeof(*cmd), list);
list_move_tail(&cmd->list, &active_commands[id]);
if (cmd->execute_func)
cmd->execute_func(cmd);
PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id);
writel(cmd->cmdptr, DMOV_CMD_PTR(id));
}
} while (ch_status & DMOV_STATUS_RSLT_VALID);
if (list_empty(&active_commands[id]) && list_empty(&ready_commands[id]))
channel_active &= ~(1U << id);
PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
}
if (!channel_active) {
disable_irq_nosync(INT_ADM_AARM);
clk_disable(msm_dmov_clk);
}
spin_unlock_irqrestore(&msm_dmov_lock, irq_flags);
return IRQ_HANDLED;
}
static int __init msm_init_datamover(void)
{
int i;
int ret;
struct clk *clk;
for (i = 0; i < MSM_DMOV_CHANNEL_COUNT; i++) {
INIT_LIST_HEAD(&ready_commands[i]);
INIT_LIST_HEAD(&active_commands[i]);
writel(DMOV_CONFIG_IRQ_EN | DMOV_CONFIG_FORCE_TOP_PTR_RSLT | DMOV_CONFIG_FORCE_FLUSH_RSLT, DMOV_CONFIG(i));
}
clk = clk_get(NULL, "adm_clk");
if (IS_ERR(clk))
return PTR_ERR(clk);
clk_prepare(clk);
msm_dmov_clk = clk;
ret = request_irq(INT_ADM_AARM, msm_datamover_irq_handler, 0, "msmdatamover", NULL);
if (ret)
return ret;
disable_irq(INT_ADM_AARM);
return 0;
}
module_init(msm_init_datamover);

51
arch/arm/mach-msm/gpiomux-8x50.c Normal file
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/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#include "gpiomux.h"
#if defined(CONFIG_MMC_MSM) || defined(CONFIG_MMC_MSM_MODULE)
#define SDCC_DAT_0_3_CMD_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_UP\
| GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA)
#define SDCC_CLK_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_NONE\
| GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA)
#else
#define SDCC_DAT_0_3_CMD_ACTV_CFG 0
#define SDCC_CLK_ACTV_CFG 0
#endif
#define SDC1_SUSPEND_CONFIG (GPIOMUX_VALID | GPIOMUX_PULL_DOWN\
| GPIOMUX_FUNC_GPIO | GPIOMUX_DRV_2MA)
struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
[86] = { /* UART3 RX */
.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
GPIOMUX_FUNC_1 | GPIOMUX_VALID,
},
[87] = { /* UART3 TX */
.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
GPIOMUX_FUNC_1 | GPIOMUX_VALID,
},
/* SDC1 data[3:0] & CMD */
[51 ... 55] = {
.active = SDCC_DAT_0_3_CMD_ACTV_CFG,
.suspended = SDC1_SUSPEND_CONFIG
},
/* SDC1 CLK */
[56] = {
.active = SDCC_CLK_ACTV_CFG,
.suspended = SDC1_SUSPEND_CONFIG
},
};

67
arch/arm/mach-msm/gpiomux-v1.h Normal file
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/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_V1_H
#define __ARCH_ARM_MACH_MSM_GPIOMUX_V1_H
#if defined(CONFIG_ARCH_MSM7X30)
#define GPIOMUX_NGPIOS 182
#elif defined(CONFIG_ARCH_QSD8X50)
#define GPIOMUX_NGPIOS 165
#else
#define GPIOMUX_NGPIOS 133
#endif
typedef u32 gpiomux_config_t;
enum {
GPIOMUX_DRV_2MA = 0UL << 17,
GPIOMUX_DRV_4MA = 1UL << 17,
GPIOMUX_DRV_6MA = 2UL << 17,
GPIOMUX_DRV_8MA = 3UL << 17,
GPIOMUX_DRV_10MA = 4UL << 17,
GPIOMUX_DRV_12MA = 5UL << 17,
GPIOMUX_DRV_14MA = 6UL << 17,
GPIOMUX_DRV_16MA = 7UL << 17,
};
enum {
GPIOMUX_FUNC_GPIO = 0UL,
GPIOMUX_FUNC_1 = 1UL,
GPIOMUX_FUNC_2 = 2UL,
GPIOMUX_FUNC_3 = 3UL,
GPIOMUX_FUNC_4 = 4UL,
GPIOMUX_FUNC_5 = 5UL,
GPIOMUX_FUNC_6 = 6UL,
GPIOMUX_FUNC_7 = 7UL,
GPIOMUX_FUNC_8 = 8UL,
GPIOMUX_FUNC_9 = 9UL,
GPIOMUX_FUNC_A = 10UL,
GPIOMUX_FUNC_B = 11UL,
GPIOMUX_FUNC_C = 12UL,
GPIOMUX_FUNC_D = 13UL,
GPIOMUX_FUNC_E = 14UL,
GPIOMUX_FUNC_F = 15UL,
};
enum {
GPIOMUX_PULL_NONE = 0UL << 15,
GPIOMUX_PULL_DOWN = 1UL << 15,
GPIOMUX_PULL_KEEPER = 2UL << 15,
GPIOMUX_PULL_UP = 3UL << 15,
};
#endif

111
arch/arm/mach-msm/gpiomux.c Normal file
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/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#include <linux/module.h>
#include <linux/spinlock.h>
#include "gpiomux.h"
#include "proc_comm.h"
static DEFINE_SPINLOCK(gpiomux_lock);
static void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val)
{
unsigned tlmm_config = (val & ~GPIOMUX_CTL_MASK) |
((gpio & 0x3ff) << 4);
unsigned tlmm_disable = 0;
int rc;
rc = msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX,
&tlmm_config, &tlmm_disable);
if (rc)
pr_err("%s: unexpected proc_comm failure %d: %08x %08x\n",
__func__, rc, tlmm_config, tlmm_disable);
}
int msm_gpiomux_write(unsigned gpio,
gpiomux_config_t active,
gpiomux_config_t suspended)
{
struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
unsigned long irq_flags;
gpiomux_config_t setting;
if (gpio >= GPIOMUX_NGPIOS)
return -EINVAL;
spin_lock_irqsave(&gpiomux_lock, irq_flags);
if (active & GPIOMUX_VALID)
cfg->active = active;
if (suspended & GPIOMUX_VALID)
cfg->suspended = suspended;
setting = cfg->ref ? active : suspended;
if (setting & GPIOMUX_VALID)
__msm_gpiomux_write(gpio, setting);
spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
return 0;
}
EXPORT_SYMBOL(msm_gpiomux_write);
int msm_gpiomux_get(unsigned gpio)
{
struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
unsigned long irq_flags;
if (gpio >= GPIOMUX_NGPIOS)
return -EINVAL;
spin_lock_irqsave(&gpiomux_lock, irq_flags);
if (cfg->ref++ == 0 && cfg->active & GPIOMUX_VALID)
__msm_gpiomux_write(gpio, cfg->active);
spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
return 0;
}
EXPORT_SYMBOL(msm_gpiomux_get);
int msm_gpiomux_put(unsigned gpio)
{
struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
unsigned long irq_flags;
if (gpio >= GPIOMUX_NGPIOS)
return -EINVAL;
spin_lock_irqsave(&gpiomux_lock, irq_flags);
BUG_ON(cfg->ref == 0);
if (--cfg->ref == 0 && cfg->suspended & GPIOMUX_VALID)
__msm_gpiomux_write(gpio, cfg->suspended);
spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
return 0;
}
EXPORT_SYMBOL(msm_gpiomux_put);
static int __init gpiomux_init(void)
{
unsigned n;
for (n = 0; n < GPIOMUX_NGPIOS; ++n) {
msm_gpiomux_configs[n].ref = 0;
if (!(msm_gpiomux_configs[n].suspended & GPIOMUX_VALID))
continue;
__msm_gpiomux_write(n, msm_gpiomux_configs[n].suspended);
}
return 0;
}
postcore_initcall(gpiomux_init);

84
arch/arm/mach-msm/gpiomux.h Normal file
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/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_H
#define __ARCH_ARM_MACH_MSM_GPIOMUX_H
#include <linux/bitops.h>
#include <linux/errno.h>
#include <mach/msm_gpiomux.h>
#include "gpiomux-v1.h"
/**
* struct msm_gpiomux_config: gpiomux settings for one gpio line.
*
* A complete gpiomux config is the bitwise-or of a drive-strength,
* function, and pull. For functions other than GPIO, the OE
* is hard-wired according to the function. For GPIO mode,
* OE is controlled by gpiolib.
*
* Available settings differ by target; see the gpiomux header
* specific to your target arch for available configurations.
*
* @active: The configuration to be installed when the line is
* active, or its reference count is > 0.
* @suspended: The configuration to be installed when the line
* is suspended, or its reference count is 0.
* @ref: The reference count of the line. For internal use of
* the gpiomux framework only.
*/
struct msm_gpiomux_config {
gpiomux_config_t active;
gpiomux_config_t suspended;
unsigned ref;
};
/**
* @GPIOMUX_VALID: If set, the config field contains 'good data'.
* The absence of this bit will prevent the gpiomux
* system from applying the configuration under all
* circumstances.
*/
enum {
GPIOMUX_VALID = BIT(sizeof(gpiomux_config_t) * BITS_PER_BYTE - 1),
GPIOMUX_CTL_MASK = GPIOMUX_VALID,
};
#ifdef CONFIG_MSM_GPIOMUX
/* Each architecture must provide its own instance of this table.
* To avoid having gpiomux manage any given gpio, one or both of
* the entries can avoid setting GPIOMUX_VALID - the absence
* of that flag will prevent the configuration from being applied
* during state transitions.
*/
extern struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS];
/* Install a new configuration to the gpio line. To avoid overwriting
* a configuration, leave the VALID bit out.
*/
int msm_gpiomux_write(unsigned gpio,
gpiomux_config_t active,
gpiomux_config_t suspended);
#else
static inline int msm_gpiomux_write(unsigned gpio,
gpiomux_config_t active,
gpiomux_config_t suspended)
{
return -ENOSYS;
}
#endif
#endif

31
arch/arm/mach-msm/include/mach/clk.h Normal file
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/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_CLK_H
#define __MACH_CLK_H
/* Magic rate value for use with PM QOS to request the board's maximum
* supported AXI rate. PM QOS will only pass positive s32 rate values
* through to the clock driver, so INT_MAX is used.
*/
#define MSM_AXI_MAX_FREQ LONG_MAX
enum clk_reset_action {
CLK_RESET_DEASSERT = 0,
CLK_RESET_ASSERT = 1
};
struct clk;
/* Assert/Deassert reset to a hardware block associated with a clock */
int clk_reset(struct clk *clk, enum clk_reset_action action);
#endif

151
arch/arm/mach-msm/include/mach/dma.h Normal file
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/* linux/include/asm-arm/arch-msm/dma.h
*
* Copyright (C) 2007 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_MSM_DMA_H
#include <linux/list.h>
struct msm_dmov_errdata {
uint32_t flush[6];
};
struct msm_dmov_cmd {
struct list_head list;
unsigned int cmdptr;
void (*complete_func)(struct msm_dmov_cmd *cmd,
unsigned int result,
struct msm_dmov_errdata *err);
void (*execute_func)(struct msm_dmov_cmd *cmd);
void *data;
};
#ifndef CONFIG_ARCH_MSM8X60
void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
#else
static inline
void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) { }
static inline
void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful) { }
static inline
int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) { return -EIO; }
#endif
#define DMOV_CMD_LIST (0 << 29) /* does not work */
#define DMOV_CMD_PTR_LIST (1 << 29) /* works */
#define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */
#define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */
#define DMOV_CMD_ADDR(addr) ((addr) >> 3)
#define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */
#define DMOV_RSLT_ERROR (1 << 3)
#define DMOV_RSLT_FLUSH (1 << 2)
#define DMOV_RSLT_DONE (1 << 1) /* top pointer done */
#define DMOV_RSLT_USER (1 << 0) /* command with FR force result */
#define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29))
#define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3)
#define DMOV_STATUS_RSLT_VALID (1 << 1)
#define DMOV_STATUS_CMD_PTR_RDY (1 << 0)
#define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2)
#define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1)
#define DMOV_CONFIG_IRQ_EN (1 << 0)
/* channel assignments */
#define DMOV_NAND_CHAN 7
#define DMOV_NAND_CRCI_CMD 5
#define DMOV_NAND_CRCI_DATA 4
#define DMOV_SDC1_CHAN 8
#define DMOV_SDC1_CRCI 6
#define DMOV_SDC2_CHAN 8
#define DMOV_SDC2_CRCI 7
#define DMOV_TSIF_CHAN 10
#define DMOV_TSIF_CRCI 10
#define DMOV_USB_CHAN 11
/* no client rate control ifc (eg, ram) */
#define DMOV_NONE_CRCI 0
/* If the CMD_PTR register has CMD_PTR_LIST selected, the data mover
* is going to walk a list of 32bit pointers as described below. Each
* pointer points to a *array* of dmov_s, etc structs. The last pointer
* in the list is marked with CMD_PTR_LP. The last struct in each array
* is marked with CMD_LC (see below).
*/
#define CMD_PTR_ADDR(addr) ((addr) >> 3)
#define CMD_PTR_LP (1 << 31) /* last pointer */
#define CMD_PTR_PT (3 << 29) /* ? */
/* Single Item Mode */
typedef struct {
unsigned cmd;
unsigned src;
unsigned dst;
unsigned len;
} dmov_s;
/* Scatter/Gather Mode */
typedef struct {
unsigned cmd;
unsigned src_dscr;
unsigned dst_dscr;
unsigned _reserved;
} dmov_sg;
/* Box mode */
typedef struct {
uint32_t cmd;
uint32_t src_row_addr;
uint32_t dst_row_addr;
uint32_t src_dst_len;
uint32_t num_rows;
uint32_t row_offset;
} dmov_box;
/* bits for the cmd field of the above structures */
#define CMD_LC (1 << 31) /* last command */
#define CMD_FR (1 << 22) /* force result -- does not work? */
#define CMD_OCU (1 << 21) /* other channel unblock */
#define CMD_OCB (1 << 20) /* other channel block */
#define CMD_TCB (1 << 19) /* ? */
#define CMD_DAH (1 << 18) /* destination address hold -- does not work?*/
#define CMD_SAH (1 << 17) /* source address hold -- does not work? */
#define CMD_MODE_SINGLE (0 << 0) /* dmov_s structure used */
#define CMD_MODE_SG (1 << 0) /* untested */
#define CMD_MODE_IND_SG (2 << 0) /* untested */
#define CMD_MODE_BOX (3 << 0) /* untested */
#define CMD_DST_SWAP_BYTES (1 << 14) /* exchange each byte n with byte n+1 */
#define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */
#define CMD_DST_SWAP_WORDS (1 << 16) /* exchange each word n with word n+1 */
#define CMD_SRC_SWAP_BYTES (1 << 11) /* exchange each byte n with byte n+1 */
#define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */
#define CMD_SRC_SWAP_WORDS (1 << 13) /* exchange each word n with word n+1 */
#define CMD_DST_CRCI(n) (((n) & 15) << 7)
#define CMD_SRC_CRCI(n) (((n) & 15) << 3)
#endif

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/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#if !defined(CONFIG_ARM_GIC)
#include <mach/msm_iomap.h>
.macro get_irqnr_preamble, base, tmp
@ enable imprecise aborts
cpsie a
mov \base, #MSM_VIC_BASE
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
@ 0xD0 has irq# or old irq# if the irq has been handled
@ 0xD4 has irq# or -1 if none pending *but* if you just
@ read 0xD4 you never get the first irq for some reason
ldr \irqnr, [\base, #0xD0]
ldr \irqnr, [\base, #0xD4]
cmp \irqnr, #0xffffffff
.endm
#endif

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/* arch/arm/mach-msm/include/mach/hardware.h
*
* Copyright (C) 2007 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_MSM_HARDWARE_H
#endif

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/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*/
#ifndef __ASM_ARCH_MSM_IRQS_7X00_H
#define __ASM_ARCH_MSM_IRQS_7X00_H
/* MSM ARM11 Interrupt Numbers */
/* See 80-VE113-1 A, pp219-221 */
#define INT_A9_M2A_0 0
#define INT_A9_M2A_1 1
#define INT_A9_M2A_2 2
#define INT_A9_M2A_3 3
#define INT_A9_M2A_4 4
#define INT_A9_M2A_5 5
#define INT_A9_M2A_6 6
#define INT_GP_TIMER_EXP 7
#define INT_DEBUG_TIMER_EXP 8
#define INT_UART1 9
#define INT_UART2 10
#define INT_UART3 11
#define INT_UART1_RX 12
#define INT_UART2_RX 13
#define INT_UART3_RX 14
#define INT_USB_OTG 15
#define INT_MDDI_PRI 16
#define INT_MDDI_EXT 17
#define INT_MDDI_CLIENT 18
#define INT_MDP 19
#define INT_GRAPHICS 20
#define INT_ADM_AARM 21
#define INT_ADSP_A11 22
#define INT_ADSP_A9_A11 23
#define INT_SDC1_0 24
#define INT_SDC1_1 25
#define INT_SDC2_0 26
#define INT_SDC2_1 27
#define INT_KEYSENSE 28
#define INT_TCHSCRN_SSBI 29
#define INT_TCHSCRN1 30
#define INT_TCHSCRN2 31
#define INT_GPIO_GROUP1 (32 + 0)
#define INT_GPIO_GROUP2 (32 + 1)
#define INT_PWB_I2C (32 + 2)
#define INT_SOFTRESET (32 + 3)
#define INT_NAND_WR_ER_DONE (32 + 4)
#define INT_NAND_OP_DONE (32 + 5)
#define INT_PBUS_ARM11 (32 + 6)
#define INT_AXI_MPU_SMI (32 + 7)
#define INT_AXI_MPU_EBI1 (32 + 8)
#define INT_AD_HSSD (32 + 9)
#define INT_ARM11_PMU (32 + 10)
#define INT_ARM11_DMA (32 + 11)
#define INT_TSIF_IRQ (32 + 12)
#define INT_UART1DM_IRQ (32 + 13)
#define INT_UART1DM_RX (32 + 14)
#define INT_USB_HS (32 + 15)
#define INT_SDC3_0 (32 + 16)
#define INT_SDC3_1 (32 + 17)
#define INT_SDC4_0 (32 + 18)
#define INT_SDC4_1 (32 + 19)
#define INT_UART2DM_RX (32 + 20)
#define INT_UART2DM_IRQ (32 + 21)
/* 22-31 are reserved */
#define NR_MSM_IRQS 64
#define NR_GPIO_IRQS 122
#define NR_BOARD_IRQS 64
#endif

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/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_MSM_IRQS_7X30_H
#define __ASM_ARCH_MSM_IRQS_7X30_H
/* MSM ACPU Interrupt Numbers */
#define INT_DEBUG_TIMER_EXP 0
#define INT_GPT0_TIMER_EXP 1
#define INT_GPT1_TIMER_EXP 2
#define INT_WDT0_ACCSCSSBARK 3
#define INT_WDT1_ACCSCSSBARK 4
#define INT_AVS_SVIC 5
#define INT_AVS_SVIC_SW_DONE 6
#define INT_SC_DBG_RX_FULL 7
#define INT_SC_DBG_TX_EMPTY 8
#define INT_ARM11_PM 9
#define INT_AVS_REQ_DOWN 10
#define INT_AVS_REQ_UP 11
#define INT_SC_ACG 12
/* SCSS_VICFIQSTS0[13:15] are RESERVED */
#define INT_L2_SVICCPUIRPTREQ 16
#define INT_L2_SVICDMANSIRPTREQ 17
#define INT_L2_SVICDMASIRPTREQ 18
#define INT_L2_SVICSLVIRPTREQ 19
#define INT_AD5A_MPROC_APPS_0 20
#define INT_AD5A_MPROC_APPS_1 21
#define INT_A9_M2A_0 22
#define INT_A9_M2A_1 23
#define INT_A9_M2A_2 24
#define INT_A9_M2A_3 25
#define INT_A9_M2A_4 26
#define INT_A9_M2A_5 27
#define INT_A9_M2A_6 28
#define INT_A9_M2A_7 29
#define INT_A9_M2A_8 30
#define INT_A9_M2A_9 31
#define INT_AXI_EBI1_SC (32 + 0)
#define INT_IMEM_ERR (32 + 1)
#define INT_AXI_EBI0_SC (32 + 2)
#define INT_PBUS_SC_IRQC (32 + 3)
#define INT_PERPH_BUS_BPM (32 + 4)
#define INT_CC_TEMP_SENSE (32 + 5)
#define INT_UXMC_EBI0 (32 + 6)
#define INT_UXMC_EBI1 (32 + 7)
#define INT_EBI2_OP_DONE (32 + 8)
#define INT_EBI2_WR_ER_DONE (32 + 9)
#define INT_TCSR_SPSS_CE (32 + 10)
#define INT_EMDH (32 + 11)
#define INT_PMDH (32 + 12)
#define INT_MDC (32 + 13)
#define INT_MIDI_TO_SUPSS (32 + 14)
#define INT_LPA_2 (32 + 15)
#define INT_GPIO_GROUP1_SECURE (32 + 16)
#define INT_GPIO_GROUP2_SECURE (32 + 17)
#define INT_GPIO_GROUP1 (32 + 18)
#define INT_GPIO_GROUP2 (32 + 19)
#define INT_MPRPH_SOFTRESET (32 + 20)
#define INT_PWB_I2C (32 + 21)
#define INT_PWB_I2C_2 (32 + 22)
#define INT_TSSC_SAMPLE (32 + 23)
#define INT_TSSC_PENUP (32 + 24)
#define INT_TCHSCRN_SSBI (32 + 25)
#define INT_FM_RDS (32 + 26)
#define INT_KEYSENSE (32 + 27)
#define INT_USB_OTG_HS (32 + 28)
#define INT_USB_OTG_HS2 (32 + 29)
#define INT_USB_OTG_HS3 (32 + 30)
#define INT_CSI (32 + 31)
#define INT_SPI_OUTPUT (64 + 0)
#define INT_SPI_INPUT (64 + 1)
#define INT_SPI_ERROR (64 + 2)
#define INT_UART1 (64 + 3)
#define INT_UART1_RX (64 + 4)
#define INT_UART2 (64 + 5)
#define INT_UART2_RX (64 + 6)
#define INT_UART3 (64 + 7)
#define INT_UART3_RX (64 + 8)
#define INT_UART1DM_IRQ (64 + 9)
#define INT_UART1DM_RX (64 + 10)
#define INT_UART2DM_IRQ (64 + 11)
#define INT_UART2DM_RX (64 + 12)
#define INT_TSIF (64 + 13)
#define INT_ADM_SC1 (64 + 14)
#define INT_ADM_SC2 (64 + 15)
#define INT_MDP (64 + 16)
#define INT_VPE (64 + 17)
#define INT_GRP_2D (64 + 18)
#define INT_GRP_3D (64 + 19)
#define INT_ROTATOR (64 + 20)
#define INT_MFC720 (64 + 21)
#define INT_JPEG (64 + 22)
#define INT_VFE (64 + 23)
#define INT_TV_ENC (64 + 24)
#define INT_PMIC_SSBI (64 + 25)
#define INT_MPM_1 (64 + 26)
#define INT_TCSR_SPSS_SAMPLE (64 + 27)
#define INT_TCSR_SPSS_PENUP (64 + 28)
#define INT_MPM_2 (64 + 29)
#define INT_SDC1_0 (64 + 30)
#define INT_SDC1_1 (64 + 31)
#define INT_SDC3_0 (96 + 0)
#define INT_SDC3_1 (96 + 1)
#define INT_SDC2_0 (96 + 2)
#define INT_SDC2_1 (96 + 3)
#define INT_SDC4_0 (96 + 4)
#define INT_SDC4_1 (96 + 5)
#define INT_PWB_QUP_IN (96 + 6)
#define INT_PWB_QUP_OUT (96 + 7)
#define INT_PWB_QUP_ERR (96 + 8)
#define INT_SCSS_WDT0_BITE (96 + 9)
/* SCSS_VICFIQSTS3[10:31] are RESERVED */
/* Retrofit universal macro names */
#define INT_ADM_AARM INT_ADM_SC2
#define INT_USB_HS INT_USB_OTG_HS
#define INT_USB_OTG INT_USB_OTG_HS
#define INT_TCHSCRN1 INT_TSSC_SAMPLE
#define INT_TCHSCRN2 INT_TSSC_PENUP
#define INT_GP_TIMER_EXP INT_GPT0_TIMER_EXP
#define INT_ADSP_A11 INT_AD5A_MPROC_APPS_0
#define INT_ADSP_A9_A11 INT_AD5A_MPROC_APPS_1
#define INT_MDDI_EXT INT_EMDH
#define INT_MDDI_PRI INT_PMDH
#define INT_MDDI_CLIENT INT_MDC
#define INT_NAND_WR_ER_DONE INT_EBI2_WR_ER_DONE
#define INT_NAND_OP_DONE INT_EBI2_OP_DONE
#define NR_MSM_IRQS 128
#define NR_GPIO_IRQS 182
#define PMIC8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
#define NR_PMIC8058_GPIO_IRQS 40
#define NR_PMIC8058_MPP_IRQS 12
#define NR_PMIC8058_MISC_IRQS 8
#define NR_PMIC8058_IRQS (NR_PMIC8058_GPIO_IRQS +\
NR_PMIC8058_MPP_IRQS +\
NR_PMIC8058_MISC_IRQS)
#define NR_BOARD_IRQS NR_PMIC8058_IRQS
#endif /* __ASM_ARCH_MSM_IRQS_7X30_H */

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/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_MSM_IRQS_8XXX_H
#define __ASM_ARCH_MSM_IRQS_8XXX_H
/* MSM ACPU Interrupt Numbers */
#define INT_A9_M2A_0 0
#define INT_A9_M2A_1 1
#define INT_A9_M2A_2 2
#define INT_A9_M2A_3 3
#define INT_A9_M2A_4 4
#define INT_A9_M2A_5 5
#define INT_A9_M2A_6 6
#define INT_GP_TIMER_EXP 7
#define INT_DEBUG_TIMER_EXP 8
#define INT_SIRC_0 9
#define INT_SDC3_0 10
#define INT_SDC3_1 11
#define INT_SDC4_0 12
#define INT_SDC4_1 13
#define INT_AD6_EXT_VFR 14
#define INT_USB_OTG 15
#define INT_MDDI_PRI 16
#define INT_MDDI_EXT 17
#define INT_MDDI_CLIENT 18
#define INT_MDP 19
#define INT_GRAPHICS 20
#define INT_ADM_AARM 21
#define INT_ADSP_A11 22
#define INT_ADSP_A9_A11 23
#define INT_SDC1_0 24
#define INT_SDC1_1 25
#define INT_SDC2_0 26
#define INT_SDC2_1 27
#define INT_KEYSENSE 28
#define INT_TCHSCRN_SSBI 29
#define INT_TCHSCRN1 30
#define INT_TCHSCRN2 31
#define INT_TCSR_MPRPH_SC1 (32 + 0)
#define INT_USB_FS2 (32 + 1)
#define INT_PWB_I2C (32 + 2)
#define INT_SOFTRESET (32 + 3)
#define INT_NAND_WR_ER_DONE (32 + 4)
#define INT_NAND_OP_DONE (32 + 5)
#define INT_TCSR_MPRPH_SC2 (32 + 6)
#define INT_OP_PEN (32 + 7)
#define INT_AD_HSSD (32 + 8)
#define INT_ARM11_PM (32 + 9)
#define INT_SDMA_NON_SECURE (32 + 10)
#define INT_TSIF_IRQ (32 + 11)
#define INT_UART1DM_IRQ (32 + 12)
#define INT_UART1DM_RX (32 + 13)
#define INT_SDMA_SECURE (32 + 14)
#define INT_SI2S_SLAVE (32 + 15)
#define INT_SC_I2CPU (32 + 16)
#define INT_SC_DBG_RDTRFULL (32 + 17)
#define INT_SC_DBG_WDTRFULL (32 + 18)
#define INT_SCPLL_CTL_DONE (32 + 19)
#define INT_UART2DM_IRQ (32 + 20)
#define INT_UART2DM_RX (32 + 21)
#define INT_VDC_MEC (32 + 22)
#define INT_VDC_DB (32 + 23)
#define INT_VDC_AXI (32 + 24)
#define INT_VFE (32 + 25)
#define INT_USB_HS (32 + 26)
#define INT_AUDIO_OUT0 (32 + 27)
#define INT_AUDIO_OUT1 (32 + 28)
#define INT_CRYPTO (32 + 29)
#define INT_AD6M_IDLE (32 + 30)
#define INT_SIRC_1 (32 + 31)
#define NR_GPIO_IRQS 165
#define NR_MSM_IRQS 64
#define NR_BOARD_IRQS 64
#endif

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/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_MSM_IRQS_H
#define __ASM_ARCH_MSM_IRQS_H
#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
#if defined(CONFIG_ARCH_MSM7X30)
#include "irqs-7x30.h"
#elif defined(CONFIG_ARCH_QSD8X50)
#include "irqs-8x50.h"
#include "sirc.h"
#elif defined(CONFIG_ARCH_MSM_ARM11)
#include "irqs-7x00.h"
#else
#error "Unknown architecture specification"
#endif
#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n))
#define MSM_INT_TO_REG(base, irq) (base + irq / 32)
#endif

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arch/arm/mach-msm/include/mach/msm_gpiomux.h Normal file
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/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _LINUX_MSM_GPIOMUX_H
#define _LINUX_MSM_GPIOMUX_H
#ifdef CONFIG_MSM_GPIOMUX
/* Increment a gpio's reference count, possibly activating the line. */
int __must_check msm_gpiomux_get(unsigned gpio);
/* Decrement a gpio's reference count, possibly suspending the line. */
int msm_gpiomux_put(unsigned gpio);
#else
static inline int __must_check msm_gpiomux_get(unsigned gpio)
{
return -ENOSYS;
}
static inline int msm_gpiomux_put(unsigned gpio)
{
return -ENOSYS;
}
#endif
#endif /* _LINUX_MSM_GPIOMUX_H */

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/* arch/arm/mach-msm/include/mach/msm_iomap.h
*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* The MSM peripherals are spread all over across 768MB of physical
* space, which makes just having a simple IO_ADDRESS macro to slide
* them into the right virtual location rough. Instead, we will
* provide a master phys->virt mapping for peripherals here.
*
*/
#ifndef __ASM_ARCH_MSM_IOMAP_7X00_H
#define __ASM_ARCH_MSM_IOMAP_7X00_H
#include <asm/sizes.h>
/* Physical base address and size of peripherals.
* Ordered by the virtual base addresses they will be mapped at.
*
* MSM_VIC_BASE must be an value that can be loaded via a "mov"
* instruction, otherwise entry-macro.S will not compile.
*
* If you add or remove entries here, you'll want to edit the
* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
* changes.
*
*/
#define MSM_VIC_BASE IOMEM(0xE0000000)
#define MSM_VIC_PHYS 0xC0000000
#define MSM_VIC_SIZE SZ_4K
#define MSM7X00_CSR_PHYS 0xC0100000
#define MSM7X00_CSR_SIZE SZ_4K
#define MSM_DMOV_BASE IOMEM(0xE0002000)
#define MSM_DMOV_PHYS 0xA9700000
#define MSM_DMOV_SIZE SZ_4K
#define MSM7X00_GPIO1_PHYS 0xA9200000
#define MSM7X00_GPIO1_SIZE SZ_4K
#define MSM7X00_GPIO2_PHYS 0xA9300000
#define MSM7X00_GPIO2_SIZE SZ_4K
#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
#define MSM_CLK_CTL_PHYS 0xA8600000
#define MSM_CLK_CTL_SIZE SZ_4K
#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
#define MSM_SHARED_RAM_PHYS 0x01F00000
#define MSM_SHARED_RAM_SIZE SZ_1M
#define MSM_UART1_PHYS 0xA9A00000
#define MSM_UART1_SIZE SZ_4K
#define MSM_UART2_PHYS 0xA9B00000
#define MSM_UART2_SIZE SZ_4K
#define MSM_UART3_PHYS 0xA9C00000
#define MSM_UART3_SIZE SZ_4K
#define MSM_SDC1_PHYS 0xA0400000
#define MSM_SDC1_SIZE SZ_4K
#define MSM_SDC2_PHYS 0xA0500000
#define MSM_SDC2_SIZE SZ_4K
#define MSM_SDC3_PHYS 0xA0600000
#define MSM_SDC3_SIZE SZ_4K
#define MSM_SDC4_PHYS 0xA0700000
#define MSM_SDC4_SIZE SZ_4K
#define MSM_I2C_PHYS 0xA9900000
#define MSM_I2C_SIZE SZ_4K
#define MSM_HSUSB_PHYS 0xA0800000
#define MSM_HSUSB_SIZE SZ_4K
#define MSM_PMDH_PHYS 0xAA600000
#define MSM_PMDH_SIZE SZ_4K
#define MSM_EMDH_PHYS 0xAA700000
#define MSM_EMDH_SIZE SZ_4K
#define MSM_MDP_PHYS 0xAA200000
#define MSM_MDP_SIZE 0x000F0000
#define MSM_MDC_PHYS 0xAA500000
#define MSM_MDC_SIZE SZ_1M
#define MSM_AD5_PHYS 0xAC000000
#define MSM_AD5_SIZE (SZ_1M*13)
#endif

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arch/arm/mach-msm/include/mach/msm_iomap-7x30.h Normal file
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/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* The MSM peripherals are spread all over across 768MB of physical
* space, which makes just having a simple IO_ADDRESS macro to slide
* them into the right virtual location rough. Instead, we will
* provide a master phys->virt mapping for peripherals here.
*
*/
#ifndef __ASM_ARCH_MSM_IOMAP_7X30_H
#define __ASM_ARCH_MSM_IOMAP_7X30_H
/* Physical base address and size of peripherals.
* Ordered by the virtual base addresses they will be mapped at.
*
* MSM_VIC_BASE must be an value that can be loaded via a "mov"
* instruction, otherwise entry-macro.S will not compile.
*
* If you add or remove entries here, you'll want to edit the
* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
* changes.
*
*/
#define MSM_VIC_BASE IOMEM(0xE0000000)
#define MSM_VIC_PHYS 0xC0080000
#define MSM_VIC_SIZE SZ_4K
#define MSM7X30_CSR_PHYS 0xC0100000
#define MSM7X30_CSR_SIZE SZ_4K
#define MSM_DMOV_BASE IOMEM(0xE0002000)
#define MSM_DMOV_PHYS 0xAC400000
#define MSM_DMOV_SIZE SZ_4K
#define MSM7X30_GPIO1_PHYS 0xAC001000
#define MSM7X30_GPIO1_SIZE SZ_4K
#define MSM7X30_GPIO2_PHYS 0xAC101000
#define MSM7X30_GPIO2_SIZE SZ_4K
#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
#define MSM_CLK_CTL_PHYS 0xAB800000
#define MSM_CLK_CTL_SIZE SZ_4K
#define MSM_CLK_CTL_SH2_BASE IOMEM(0xE0006000)
#define MSM_CLK_CTL_SH2_PHYS 0xABA01000
#define MSM_CLK_CTL_SH2_SIZE SZ_4K
#define MSM_ACC_BASE IOMEM(0xE0007000)
#define MSM_ACC_PHYS 0xC0101000
#define MSM_ACC_SIZE SZ_4K
#define MSM_SAW_BASE IOMEM(0xE0008000)
#define MSM_SAW_PHYS 0xC0102000
#define MSM_SAW_SIZE SZ_4K
#define MSM_GCC_BASE IOMEM(0xE0009000)
#define MSM_GCC_PHYS 0xC0182000
#define MSM_GCC_SIZE SZ_4K
#define MSM_TCSR_BASE IOMEM(0xE000A000)
#define MSM_TCSR_PHYS 0xAB600000
#define MSM_TCSR_SIZE SZ_4K
#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
#define MSM_SHARED_RAM_PHYS 0x00100000
#define MSM_SHARED_RAM_SIZE SZ_1M
#define MSM_UART1_PHYS 0xACA00000
#define MSM_UART1_SIZE SZ_4K
#define MSM_UART2_PHYS 0xACB00000
#define MSM_UART2_SIZE SZ_4K
#define MSM_UART3_PHYS 0xACC00000
#define MSM_UART3_SIZE SZ_4K
#define MSM_MDC_BASE IOMEM(0xE0200000)
#define MSM_MDC_PHYS 0xAA500000
#define MSM_MDC_SIZE SZ_1M
#define MSM_AD5_BASE IOMEM(0xE0300000)
#define MSM_AD5_PHYS 0xA7000000
#define MSM_AD5_SIZE (SZ_1M*13)
#define MSM_HSUSB_PHYS 0xA3600000
#define MSM_HSUSB_SIZE SZ_1K
#endif

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arch/arm/mach-msm/include/mach/msm_iomap-8x50.h Normal file
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/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* The MSM peripherals are spread all over across 768MB of physical
* space, which makes just having a simple IO_ADDRESS macro to slide
* them into the right virtual location rough. Instead, we will
* provide a master phys->virt mapping for peripherals here.
*
*/
#ifndef __ASM_ARCH_MSM_IOMAP_8X50_H
#define __ASM_ARCH_MSM_IOMAP_8X50_H
/* Physical base address and size of peripherals.
* Ordered by the virtual base addresses they will be mapped at.
*
* MSM_VIC_BASE must be an value that can be loaded via a "mov"
* instruction, otherwise entry-macro.S will not compile.
*
* If you add or remove entries here, you'll want to edit the
* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
* changes.
*
*/
#define MSM_VIC_BASE IOMEM(0xE0000000)
#define MSM_VIC_PHYS 0xAC000000
#define MSM_VIC_SIZE SZ_4K
#define QSD8X50_CSR_PHYS 0xAC100000
#define QSD8X50_CSR_SIZE SZ_4K
#define MSM_DMOV_BASE IOMEM(0xE0002000)
#define MSM_DMOV_PHYS 0xA9700000
#define MSM_DMOV_SIZE SZ_4K
#define QSD8X50_GPIO1_PHYS 0xA9000000
#define QSD8X50_GPIO1_SIZE SZ_4K
#define QSD8X50_GPIO2_PHYS 0xA9100000
#define QSD8X50_GPIO2_SIZE SZ_4K
#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
#define MSM_CLK_CTL_PHYS 0xA8600000
#define MSM_CLK_CTL_SIZE SZ_4K
#define MSM_SIRC_BASE IOMEM(0xE1006000)
#define MSM_SIRC_PHYS 0xAC200000
#define MSM_SIRC_SIZE SZ_4K
#define MSM_SCPLL_BASE IOMEM(0xE1007000)
#define MSM_SCPLL_PHYS 0xA8800000
#define MSM_SCPLL_SIZE SZ_4K
#ifdef CONFIG_MSM_SOC_REV_A
#define MSM_SMI_BASE 0xE0000000
#else
#define MSM_SMI_BASE 0x00000000
#endif
#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
#define MSM_SHARED_RAM_PHYS (MSM_SMI_BASE + 0x00100000)
#define MSM_SHARED_RAM_SIZE SZ_1M
#define MSM_UART1_PHYS 0xA9A00000
#define MSM_UART1_SIZE SZ_4K
#define MSM_UART2_PHYS 0xA9B00000
#define MSM_UART2_SIZE SZ_4K
#define MSM_UART3_PHYS 0xA9C00000
#define MSM_UART3_SIZE SZ_4K
#define MSM_MDC_BASE IOMEM(0xE0200000)
#define MSM_MDC_PHYS 0xAA500000
#define MSM_MDC_SIZE SZ_1M
#define MSM_AD5_BASE IOMEM(0xE0300000)
#define MSM_AD5_PHYS 0xAC000000
#define MSM_AD5_SIZE (SZ_1M*13)
#define MSM_I2C_SIZE SZ_4K
#define MSM_I2C_PHYS 0xA9900000
#define MSM_HSUSB_PHYS 0xA0800000
#define MSM_HSUSB_SIZE SZ_1K
#define MSM_NAND_PHYS 0xA0A00000
#define MSM_TSIF_PHYS (0xa0100000)
#define MSM_TSIF_SIZE (0x200)
#define MSM_TSSC_PHYS 0xAA300000
#define MSM_UART1DM_PHYS 0xA0200000
#define MSM_UART2DM_PHYS 0xA0900000
#define MSM_SDC1_PHYS 0xA0300000
#define MSM_SDC1_SIZE SZ_4K
#define MSM_SDC2_PHYS 0xA0400000
#define MSM_SDC2_SIZE SZ_4K
#define MSM_SDC3_PHYS 0xA0500000
#define MSM_SDC3_SIZE SZ_4K
#define MSM_SDC4_PHYS 0xA0600000
#define MSM_SDC4_SIZE SZ_4K
#endif

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arch/arm/mach-msm/include/mach/msm_iomap.h Normal file
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/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* The MSM peripherals are spread all over across 768MB of physical
* space, which makes just having a simple IO_ADDRESS macro to slide
* them into the right virtual location rough. Instead, we will
* provide a master phys->virt mapping for peripherals here.
*
*/
#ifndef __ASM_ARCH_MSM_IOMAP_H
#define __ASM_ARCH_MSM_IOMAP_H
#include <asm/sizes.h>
/* Physical base address and size of peripherals.
* Ordered by the virtual base addresses they will be mapped at.
*
* MSM_VIC_BASE must be an value that can be loaded via a "mov"
* instruction, otherwise entry-macro.S will not compile.
*
* If you add or remove entries here, you'll want to edit the
* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
* changes.
*
*/
#if defined(CONFIG_ARCH_MSM7X30)
#include "msm_iomap-7x30.h"
#elif defined(CONFIG_ARCH_QSD8X50)
#include "msm_iomap-8x50.h"
#else
#include "msm_iomap-7x00.h"
#endif
/* Virtual addresses shared across all MSM targets. */
#define MSM_CSR_BASE IOMEM(0xE0001000)
#define MSM_GPIO1_BASE IOMEM(0xE0003000)
#define MSM_GPIO2_BASE IOMEM(0xE0004000)
#endif

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arch/arm/mach-msm/include/mach/msm_smd.h Normal file
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/* linux/include/asm-arm/arch-msm/msm_smd.h
*
* Copyright (C) 2007 Google, Inc.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_MSM_SMD_H
#define __ASM_ARCH_MSM_SMD_H
typedef struct smd_channel smd_channel_t;
extern int (*msm_check_for_modem_crash)(void);
/* warning: notify() may be called before open returns */
int smd_open(const char *name, smd_channel_t **ch, void *priv,
void (*notify)(void *priv, unsigned event));
#define SMD_EVENT_DATA 1
#define SMD_EVENT_OPEN 2
#define SMD_EVENT_CLOSE 3
int smd_close(smd_channel_t *ch);
/* passing a null pointer for data reads and discards */
int smd_read(smd_channel_t *ch, void *data, int len);
/* Write to stream channels may do a partial write and return
** the length actually written.
** Write to packet channels will never do a partial write --
** it will return the requested length written or an error.
*/
int smd_write(smd_channel_t *ch, const void *data, int len);
int smd_write_atomic(smd_channel_t *ch, const void *data, int len);
int smd_write_avail(smd_channel_t *ch);
int smd_read_avail(smd_channel_t *ch);
/* Returns the total size of the current packet being read.
** Returns 0 if no packets available or a stream channel.
*/
int smd_cur_packet_size(smd_channel_t *ch);
/* used for tty unthrottling and the like -- causes the notify()
** callback to be called from the same lock context as is used
** when it is called from channel updates
*/
void smd_kick(smd_channel_t *ch);
#if 0
/* these are interruptable waits which will block you until the specified
** number of bytes are readable or writable.
*/
int smd_wait_until_readable(smd_channel_t *ch, int bytes);
int smd_wait_until_writable(smd_channel_t *ch, int bytes);
#endif
typedef enum {
SMD_PORT_DS = 0,
SMD_PORT_DIAG,
SMD_PORT_RPC_CALL,
SMD_PORT_RPC_REPLY,
SMD_PORT_BT,
SMD_PORT_CONTROL,
SMD_PORT_MEMCPY_SPARE1,
SMD_PORT_DATA1,
SMD_PORT_DATA2,
SMD_PORT_DATA3,
SMD_PORT_DATA4,
SMD_PORT_DATA5,
SMD_PORT_DATA6,
SMD_PORT_DATA7,
SMD_PORT_DATA8,
SMD_PORT_DATA9,
SMD_PORT_DATA10,
SMD_PORT_DATA11,
SMD_PORT_DATA12,
SMD_PORT_DATA13,
SMD_PORT_DATA14,
SMD_PORT_DATA15,
SMD_PORT_DATA16,
SMD_PORT_DATA17,
SMD_PORT_DATA18,
SMD_PORT_DATA19,
SMD_PORT_DATA20,
SMD_PORT_GPS_NMEA,
SMD_PORT_BRIDGE_1,
SMD_PORT_BRIDGE_2,
SMD_PORT_BRIDGE_3,
SMD_PORT_BRIDGE_4,
SMD_PORT_BRIDGE_5,
SMD_PORT_LOOPBACK,
SMD_PORT_CS_APPS_MODEM,
SMD_PORT_CS_APPS_DSP,
SMD_PORT_CS_MODEM_DSP,
SMD_NUM_PORTS,
} smd_port_id_type;
#endif

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/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_MSM_SIRC_H
#define __ASM_ARCH_MSM_SIRC_H
struct sirc_regs_t {
void *int_enable;
void *int_enable_clear;
void *int_enable_set;
void *int_type;
void *int_polarity;
void *int_clear;
};
struct sirc_cascade_regs {
void *int_status;
unsigned int cascade_irq;
};
void msm_init_sirc(void);
void msm_sirc_enter_sleep(void);
void msm_sirc_exit_sleep(void);
#if defined(CONFIG_ARCH_MSM_SCORPION)
#include <mach/msm_iomap.h>
/*
* Secondary interrupt controller interrupts
*/
#define FIRST_SIRC_IRQ (NR_MSM_IRQS + NR_GPIO_IRQS)
#define INT_UART1 (FIRST_SIRC_IRQ + 0)
#define INT_UART2 (FIRST_SIRC_IRQ + 1)
#define INT_UART3 (FIRST_SIRC_IRQ + 2)
#define INT_UART1_RX (FIRST_SIRC_IRQ + 3)
#define INT_UART2_RX (FIRST_SIRC_IRQ + 4)
#define INT_UART3_RX (FIRST_SIRC_IRQ + 5)
#define INT_SPI_INPUT (FIRST_SIRC_IRQ + 6)
#define INT_SPI_OUTPUT (FIRST_SIRC_IRQ + 7)
#define INT_SPI_ERROR (FIRST_SIRC_IRQ + 8)
#define INT_GPIO_GROUP1 (FIRST_SIRC_IRQ + 9)
#define INT_GPIO_GROUP2 (FIRST_SIRC_IRQ + 10)
#define INT_GPIO_GROUP1_SECURE (FIRST_SIRC_IRQ + 11)
#define INT_GPIO_GROUP2_SECURE (FIRST_SIRC_IRQ + 12)
#define INT_AVS_SVIC (FIRST_SIRC_IRQ + 13)
#define INT_AVS_REQ_UP (FIRST_SIRC_IRQ + 14)
#define INT_AVS_REQ_DOWN (FIRST_SIRC_IRQ + 15)
#define INT_PBUS_ERR (FIRST_SIRC_IRQ + 16)
#define INT_AXI_ERR (FIRST_SIRC_IRQ + 17)
#define INT_SMI_ERR (FIRST_SIRC_IRQ + 18)
#define INT_EBI1_ERR (FIRST_SIRC_IRQ + 19)
#define INT_IMEM_ERR (FIRST_SIRC_IRQ + 20)
#define INT_TEMP_SENSOR (FIRST_SIRC_IRQ + 21)
#define INT_TV_ENC (FIRST_SIRC_IRQ + 22)
#define INT_GRP2D (FIRST_SIRC_IRQ + 23)
#define INT_GSBI_QUP (FIRST_SIRC_IRQ + 24)
#define INT_SC_ACG (FIRST_SIRC_IRQ + 25)
#define INT_WDT0 (FIRST_SIRC_IRQ + 26)
#define INT_WDT1 (FIRST_SIRC_IRQ + 27)
#if defined(CONFIG_MSM_SOC_REV_A)
#define NR_SIRC_IRQS 28
#define SIRC_MASK 0x0FFFFFFF
#else
#define NR_SIRC_IRQS 23
#define SIRC_MASK 0x007FFFFF
#endif
#define LAST_SIRC_IRQ (FIRST_SIRC_IRQ + NR_SIRC_IRQS - 1)
#define SPSS_SIRC_INT_SELECT (MSM_SIRC_BASE + 0x00)
#define SPSS_SIRC_INT_ENABLE (MSM_SIRC_BASE + 0x04)
#define SPSS_SIRC_INT_ENABLE_CLEAR (MSM_SIRC_BASE + 0x08)
#define SPSS_SIRC_INT_ENABLE_SET (MSM_SIRC_BASE + 0x0C)
#define SPSS_SIRC_INT_TYPE (MSM_SIRC_BASE + 0x10)
#define SPSS_SIRC_INT_POLARITY (MSM_SIRC_BASE + 0x14)
#define SPSS_SIRC_SECURITY (MSM_SIRC_BASE + 0x18)
#define SPSS_SIRC_IRQ_STATUS (MSM_SIRC_BASE + 0x1C)
#define SPSS_SIRC_IRQ1_STATUS (MSM_SIRC_BASE + 0x20)
#define SPSS_SIRC_RAW_STATUS (MSM_SIRC_BASE + 0x24)
#define SPSS_SIRC_INT_CLEAR (MSM_SIRC_BASE + 0x28)
#define SPSS_SIRC_SOFT_INT (MSM_SIRC_BASE + 0x2C)
#endif
#endif

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arch/arm/mach-msm/include/mach/vreg.h Normal file
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/* linux/include/asm-arm/arch-msm/vreg.h
*
* Copyright (C) 2008 Google, Inc.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ARCH_ARM_MACH_MSM_VREG_H
#define __ARCH_ARM_MACH_MSM_VREG_H
struct vreg;
struct vreg *vreg_get(struct device *dev, const char *id);
void vreg_put(struct vreg *vreg);
int vreg_enable(struct vreg *vreg);
int vreg_disable(struct vreg *vreg);
int vreg_set_level(struct vreg *vreg, unsigned mv);
#endif

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/* arch/arm/mach-msm/io.c
*
* MSM7K, QSD io support
*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/export.h>
#include <mach/hardware.h>
#include <asm/page.h>
#include <mach/msm_iomap.h>
#include <asm/mach/map.h>
#include "common.h"
#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \
.virtual = (unsigned long) MSM_##name##_BASE, \
.pfn = __phys_to_pfn(chip##_##name##_PHYS), \
.length = chip##_##name##_SIZE, \
.type = mem_type, \
}
#define MSM_DEVICE_TYPE(name, mem_type) \
MSM_CHIP_DEVICE_TYPE(name, MSM, mem_type)
#define MSM_CHIP_DEVICE(name, chip) \
MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE)
#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
#if defined(CONFIG_ARCH_MSM7X00A)
static struct map_desc msm_io_desc[] __initdata = {
MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED),
MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED),
MSM_DEVICE_TYPE(DMOV, MT_DEVICE_NONSHARED),
MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED),
MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED),
MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED),
{
.virtual = (unsigned long) MSM_SHARED_RAM_BASE,
.pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
.length = MSM_SHARED_RAM_SIZE,
.type = MT_DEVICE,
},
#if defined(CONFIG_DEBUG_MSM_UART)
{
/* Must be last: virtual and pfn filled in by debug_ll_addr() */
.length = SZ_4K,
.type = MT_DEVICE_NONSHARED,
}
#endif
};
void __init msm_map_common_io(void)
{
size_t size = ARRAY_SIZE(msm_io_desc);
/* Make sure the peripheral register window is closed, since
* we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which
* pages are peripheral interface or not.
*/
asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
#if defined(CONFIG_DEBUG_MSM_UART)
#ifdef CONFIG_MMU
debug_ll_addr(&msm_io_desc[size - 1].pfn,
&msm_io_desc[size - 1].virtual);
#endif
msm_io_desc[size - 1].pfn = __phys_to_pfn(msm_io_desc[size - 1].pfn);
#endif
iotable_init(msm_io_desc, size);
}
#endif
#ifdef CONFIG_ARCH_QSD8X50
static struct map_desc qsd8x50_io_desc[] __initdata = {
MSM_DEVICE(VIC),
MSM_CHIP_DEVICE(CSR, QSD8X50),
MSM_DEVICE(DMOV),
MSM_CHIP_DEVICE(GPIO1, QSD8X50),
MSM_CHIP_DEVICE(GPIO2, QSD8X50),
MSM_DEVICE(CLK_CTL),
MSM_DEVICE(SIRC),
MSM_DEVICE(SCPLL),
MSM_DEVICE(AD5),
MSM_DEVICE(MDC),
{
.virtual = (unsigned long) MSM_SHARED_RAM_BASE,
.pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
.length = MSM_SHARED_RAM_SIZE,
.type = MT_DEVICE,
},
};
void __init msm_map_qsd8x50_io(void)
{
debug_ll_io_init();
iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc));
}
#endif /* CONFIG_ARCH_QSD8X50 */
#ifdef CONFIG_ARCH_MSM7X30
static struct map_desc msm7x30_io_desc[] __initdata = {
MSM_DEVICE(VIC),
MSM_CHIP_DEVICE(CSR, MSM7X30),
MSM_DEVICE(DMOV),
MSM_CHIP_DEVICE(GPIO1, MSM7X30),
MSM_CHIP_DEVICE(GPIO2, MSM7X30),
MSM_DEVICE(CLK_CTL),
MSM_DEVICE(CLK_CTL_SH2),
MSM_DEVICE(AD5),
MSM_DEVICE(MDC),
MSM_DEVICE(ACC),
MSM_DEVICE(SAW),
MSM_DEVICE(GCC),
MSM_DEVICE(TCSR),
{
.virtual = (unsigned long) MSM_SHARED_RAM_BASE,
.pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
.length = MSM_SHARED_RAM_SIZE,
.type = MT_DEVICE,
},
};
void __init msm_map_msm7x30_io(void)
{
debug_ll_io_init();
iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc));
}
#endif /* CONFIG_ARCH_MSM7X30 */
#ifdef CONFIG_ARCH_MSM7X00A
void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
unsigned int mtype, void *caller)
{
if (mtype == MT_DEVICE) {
/* The peripherals in the 88000000 - D0000000 range
* are only accessible by type MT_DEVICE_NONSHARED.
* Adjust mtype as necessary to make this "just work."
*/
if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000))
mtype = MT_DEVICE_NONSHARED;
}
return __arm_ioremap_caller(phys_addr, size, mtype, caller);
}
#endif

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/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/ptrace.h>
#include <linux/timer.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/cacheflush.h>
#include <mach/hardware.h>
#include <mach/msm_iomap.h>
#include "smd_private.h"
enum {
IRQ_DEBUG_SLEEP_INT_TRIGGER = 1U << 0,
IRQ_DEBUG_SLEEP_INT = 1U << 1,
IRQ_DEBUG_SLEEP_ABORT = 1U << 2,
IRQ_DEBUG_SLEEP = 1U << 3,
IRQ_DEBUG_SLEEP_REQUEST = 1U << 4,
};
static int msm_irq_debug_mask;
module_param_named(debug_mask, msm_irq_debug_mask, int,
S_IRUGO | S_IWUSR | S_IWGRP);
#define VIC_REG(off) (MSM_VIC_BASE + (off))
#define VIC_INT_TO_REG_ADDR(base, irq) (base + (irq / 32) * 4)
#define VIC_INT_TO_REG_INDEX(irq) ((irq >> 5) & 3)
#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
#define VIC_INT_SELECT2 VIC_REG(0x0008) /* 1: FIQ, 0: IRQ */
#define VIC_INT_SELECT3 VIC_REG(0x000C) /* 1: FIQ, 0: IRQ */
#define VIC_INT_EN0 VIC_REG(0x0010)
#define VIC_INT_EN1 VIC_REG(0x0014)
#define VIC_INT_EN2 VIC_REG(0x0018)
#define VIC_INT_EN3 VIC_REG(0x001C)
#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
#define VIC_INT_ENCLEAR2 VIC_REG(0x0028)
#define VIC_INT_ENCLEAR3 VIC_REG(0x002C)
#define VIC_INT_ENSET0 VIC_REG(0x0030)
#define VIC_INT_ENSET1 VIC_REG(0x0034)
#define VIC_INT_ENSET2 VIC_REG(0x0038)
#define VIC_INT_ENSET3 VIC_REG(0x003C)
#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
#define VIC_INT_TYPE2 VIC_REG(0x0048) /* 1: EDGE, 0: LEVEL */
#define VIC_INT_TYPE3 VIC_REG(0x004C) /* 1: EDGE, 0: LEVEL */
#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
#define VIC_INT_POLARITY2 VIC_REG(0x0058) /* 1: NEG, 0: POS */
#define VIC_INT_POLARITY3 VIC_REG(0x005C) /* 1: NEG, 0: POS */
#define VIC_NO_PEND_VAL VIC_REG(0x0060)
#if defined(CONFIG_ARCH_MSM_SCORPION)
#define VIC_NO_PEND_VAL_FIQ VIC_REG(0x0064)
#define VIC_INT_MASTEREN VIC_REG(0x0068) /* 1: IRQ, 2: FIQ */
#define VIC_CONFIG VIC_REG(0x006C) /* 1: USE SC VIC */
#else
#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */
#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */
#endif
#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
#define VIC_IRQ_STATUS2 VIC_REG(0x0088)
#define VIC_IRQ_STATUS3 VIC_REG(0x008C)
#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
#define VIC_FIQ_STATUS2 VIC_REG(0x0098)
#define VIC_FIQ_STATUS3 VIC_REG(0x009C)
#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
#define VIC_RAW_STATUS2 VIC_REG(0x00A8)
#define VIC_RAW_STATUS3 VIC_REG(0x00AC)
#define VIC_INT_CLEAR0 VIC_REG(0x00B0)
#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
#define VIC_INT_CLEAR2 VIC_REG(0x00B8)
#define VIC_INT_CLEAR3 VIC_REG(0x00BC)
#define VIC_SOFTINT0 VIC_REG(0x00C0)
#define VIC_SOFTINT1 VIC_REG(0x00C4)
#define VIC_SOFTINT2 VIC_REG(0x00C8)
#define VIC_SOFTINT3 VIC_REG(0x00CC)
#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
#if defined(CONFIG_ARCH_MSM_SCORPION)
#define VIC_FIQ_VEC_RD VIC_REG(0x00DC)
#define VIC_FIQ_VEC_PEND_RD VIC_REG(0x00E0)
#define VIC_FIQ_VEC_WR VIC_REG(0x00E4)
#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E8)
#define VIC_IRQ_IN_STACK VIC_REG(0x00EC)
#define VIC_FIQ_IN_SERVICE VIC_REG(0x00F0)
#define VIC_FIQ_IN_STACK VIC_REG(0x00F4)
#define VIC_TEST_BUS_SEL VIC_REG(0x00F8)
#define VIC_IRQ_CTRL_CONFIG VIC_REG(0x00FC)
#else
#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0)
#define VIC_IRQ_IN_STACK VIC_REG(0x00E4)
#define VIC_TEST_BUS_SEL VIC_REG(0x00E8)
#endif
#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
#define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4))
#if defined(CONFIG_ARCH_MSM7X30)
#define VIC_NUM_REGS 4
#else
#define VIC_NUM_REGS 2
#endif
#if VIC_NUM_REGS == 2
#define DPRINT_REGS(base_reg, format, ...) \
printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__, \
readl(base_reg ## 0), readl(base_reg ## 1))
#define DPRINT_ARRAY(array, format, ...) \
printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__, \
array[0], array[1])
#elif VIC_NUM_REGS == 4
#define DPRINT_REGS(base_reg, format, ...) \
printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__, \
readl(base_reg ## 0), readl(base_reg ## 1), \
readl(base_reg ## 2), readl(base_reg ## 3))
#define DPRINT_ARRAY(array, format, ...) \
printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__, \
array[0], array[1], \
array[2], array[3])
#else
#error "VIC_NUM_REGS set to illegal value"
#endif
static uint32_t msm_irq_smsm_wake_enable[2];
static struct {
uint32_t int_en[2];
uint32_t int_type;
uint32_t int_polarity;
uint32_t int_select;
} msm_irq_shadow_reg[VIC_NUM_REGS];
static uint32_t msm_irq_idle_disable[VIC_NUM_REGS];
#define SMSM_FAKE_IRQ (0xff)
static uint8_t msm_irq_to_smsm[NR_IRQS] = {
[INT_MDDI_EXT] = 1,
[INT_MDDI_PRI] = 2,
[INT_MDDI_CLIENT] = 3,
[INT_USB_OTG] = 4,
[INT_PWB_I2C] = 5,
[INT_SDC1_0] = 6,
[INT_SDC1_1] = 7,
[INT_SDC2_0] = 8,
[INT_SDC2_1] = 9,
[INT_ADSP_A9_A11] = 10,
[INT_UART1] = 11,
[INT_UART2] = 12,
[INT_UART3] = 13,
[INT_UART1_RX] = 14,
[INT_UART2_RX] = 15,
[INT_UART3_RX] = 16,
[INT_UART1DM_IRQ] = 17,
[INT_UART1DM_RX] = 18,
[INT_KEYSENSE] = 19,
#if !defined(CONFIG_ARCH_MSM7X30)
[INT_AD_HSSD] = 20,
#endif
[INT_NAND_WR_ER_DONE] = 21,
[INT_NAND_OP_DONE] = 22,
[INT_TCHSCRN1] = 23,
[INT_TCHSCRN2] = 24,
[INT_TCHSCRN_SSBI] = 25,
[INT_USB_HS] = 26,
[INT_UART2DM_RX] = 27,
[INT_UART2DM_IRQ] = 28,
[INT_SDC4_1] = 29,
[INT_SDC4_0] = 30,
[INT_SDC3_1] = 31,
[INT_SDC3_0] = 32,
/* fake wakeup interrupts */
[INT_GPIO_GROUP1] = SMSM_FAKE_IRQ,
[INT_GPIO_GROUP2] = SMSM_FAKE_IRQ,
[INT_A9_M2A_0] = SMSM_FAKE_IRQ,
[INT_A9_M2A_1] = SMSM_FAKE_IRQ,
[INT_A9_M2A_5] = SMSM_FAKE_IRQ,
[INT_GP_TIMER_EXP] = SMSM_FAKE_IRQ,
[INT_DEBUG_TIMER_EXP] = SMSM_FAKE_IRQ,
[INT_ADSP_A11] = SMSM_FAKE_IRQ,
#ifdef CONFIG_ARCH_QSD8X50
[INT_SIRC_0] = SMSM_FAKE_IRQ,
[INT_SIRC_1] = SMSM_FAKE_IRQ,
#endif
};
static inline void msm_irq_write_all_regs(void __iomem *base, unsigned int val)
{
int i;
for (i = 0; i < VIC_NUM_REGS; i++)
writel(val, base + (i * 4));
}
static void msm_irq_ack(struct irq_data *d)
{
void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_CLEAR0, d->irq);
writel(1 << (d->irq & 31), reg);
}
static void msm_irq_mask(struct irq_data *d)
{
void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENCLEAR0, d->irq);
unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
uint32_t mask = 1UL << (d->irq & 31);
int smsm_irq = msm_irq_to_smsm[d->irq];
msm_irq_shadow_reg[index].int_en[0] &= ~mask;
writel(mask, reg);
if (smsm_irq == 0)
msm_irq_idle_disable[index] &= ~mask;
else {
mask = 1UL << (smsm_irq - 1);
msm_irq_smsm_wake_enable[0] &= ~mask;
}
}
static void msm_irq_unmask(struct irq_data *d)
{
void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, d->irq);
unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
uint32_t mask = 1UL << (d->irq & 31);
int smsm_irq = msm_irq_to_smsm[d->irq];
msm_irq_shadow_reg[index].int_en[0] |= mask;
writel(mask, reg);
if (smsm_irq == 0)
msm_irq_idle_disable[index] |= mask;
else {
mask = 1UL << (smsm_irq - 1);
msm_irq_smsm_wake_enable[0] |= mask;
}
}
static int msm_irq_set_wake(struct irq_data *d, unsigned int on)
{
unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
uint32_t mask = 1UL << (d->irq & 31);
int smsm_irq = msm_irq_to_smsm[d->irq];
if (smsm_irq == 0) {
printk(KERN_ERR "msm_irq_set_wake: bad wakeup irq %d\n", d->irq);
return -EINVAL;
}
if (on)
msm_irq_shadow_reg[index].int_en[1] |= mask;
else
msm_irq_shadow_reg[index].int_en[1] &= ~mask;
if (smsm_irq == SMSM_FAKE_IRQ)
return 0;
mask = 1UL << (smsm_irq - 1);
if (on)
msm_irq_smsm_wake_enable[1] |= mask;
else
msm_irq_smsm_wake_enable[1] &= ~mask;
return 0;
}
static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
void __iomem *treg = VIC_INT_TO_REG_ADDR(VIC_INT_TYPE0, d->irq);
void __iomem *preg = VIC_INT_TO_REG_ADDR(VIC_INT_POLARITY0, d->irq);
unsigned index = VIC_INT_TO_REG_INDEX(d->irq);
int b = 1 << (d->irq & 31);
uint32_t polarity;
uint32_t type;
polarity = msm_irq_shadow_reg[index].int_polarity;
if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
polarity |= b;
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
polarity &= ~b;
writel(polarity, preg);
msm_irq_shadow_reg[index].int_polarity = polarity;
type = msm_irq_shadow_reg[index].int_type;
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
type |= b;
__irq_set_handler_locked(d->irq, handle_edge_irq);
}
if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
type &= ~b;
__irq_set_handler_locked(d->irq, handle_level_irq);
}
writel(type, treg);
msm_irq_shadow_reg[index].int_type = type;
return 0;
}
static struct irq_chip msm_irq_chip = {
.name = "msm",
.irq_disable = msm_irq_mask,
.irq_ack = msm_irq_ack,
.irq_mask = msm_irq_mask,
.irq_unmask = msm_irq_unmask,
.irq_set_wake = msm_irq_set_wake,
.irq_set_type = msm_irq_set_type,
};
void __init msm_init_irq(void)
{
unsigned n;
/* select level interrupts */
msm_irq_write_all_regs(VIC_INT_TYPE0, 0);
/* select highlevel interrupts */
msm_irq_write_all_regs(VIC_INT_POLARITY0, 0);
/* select IRQ for all INTs */
msm_irq_write_all_regs(VIC_INT_SELECT0, 0);
/* disable all INTs */
msm_irq_write_all_regs(VIC_INT_EN0, 0);
/* don't use vic */
writel(0, VIC_CONFIG);
/* enable interrupt controller */
writel(3, VIC_INT_MASTEREN);
for (n = 0; n < NR_MSM_IRQS; n++) {
irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
set_irq_flags(n, IRQF_VALID);
}
}

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/* linux/arch/arm/mach-msm/irq.c
*
* Copyright (C) 2007 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/ptrace.h>
#include <linux/timer.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/msm_iomap.h>
#define VIC_REG(off) (MSM_VIC_BASE + (off))
#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
#define VIC_INT_EN0 VIC_REG(0x0010)
#define VIC_INT_EN1 VIC_REG(0x0014)
#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
#define VIC_INT_ENSET0 VIC_REG(0x0030)
#define VIC_INT_ENSET1 VIC_REG(0x0034)
#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
#define VIC_NO_PEND_VAL VIC_REG(0x0060)
#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */
#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */
#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
#define VIC_INT_CLEAR0 VIC_REG(0x00B0)
#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
#define VIC_SOFTINT0 VIC_REG(0x00C0)
#define VIC_SOFTINT1 VIC_REG(0x00C4)
#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0)
#define VIC_IRQ_IN_STACK VIC_REG(0x00E4)
#define VIC_TEST_BUS_SEL VIC_REG(0x00E8)
#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
#define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4))
static void msm_irq_ack(struct irq_data *d)
{
void __iomem *reg = VIC_INT_CLEAR0 + ((d->irq & 32) ? 4 : 0);
writel(1 << (d->irq & 31), reg);
}
static void msm_irq_mask(struct irq_data *d)
{
void __iomem *reg = VIC_INT_ENCLEAR0 + ((d->irq & 32) ? 4 : 0);
writel(1 << (d->irq & 31), reg);
}
static void msm_irq_unmask(struct irq_data *d)
{
void __iomem *reg = VIC_INT_ENSET0 + ((d->irq & 32) ? 4 : 0);
writel(1 << (d->irq & 31), reg);
}
static int msm_irq_set_wake(struct irq_data *d, unsigned int on)
{
return -EINVAL;
}
static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
void __iomem *treg = VIC_INT_TYPE0 + ((d->irq & 32) ? 4 : 0);
void __iomem *preg = VIC_INT_POLARITY0 + ((d->irq & 32) ? 4 : 0);
int b = 1 << (d->irq & 31);
if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
writel(readl(preg) | b, preg);
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
writel(readl(preg) & (~b), preg);
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
writel(readl(treg) | b, treg);
__irq_set_handler_locked(d->irq, handle_edge_irq);
}
if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
writel(readl(treg) & (~b), treg);
__irq_set_handler_locked(d->irq, handle_level_irq);
}
return 0;
}
static struct irq_chip msm_irq_chip = {
.name = "msm",
.irq_ack = msm_irq_ack,
.irq_mask = msm_irq_mask,
.irq_unmask = msm_irq_unmask,
.irq_set_wake = msm_irq_set_wake,
.irq_set_type = msm_irq_set_type,
};
void __init msm_init_irq(void)
{
unsigned n;
/* select level interrupts */
writel(0, VIC_INT_TYPE0);
writel(0, VIC_INT_TYPE1);
/* select highlevel interrupts */
writel(0, VIC_INT_POLARITY0);
writel(0, VIC_INT_POLARITY1);
/* select IRQ for all INTs */
writel(0, VIC_INT_SELECT0);
writel(0, VIC_INT_SELECT1);
/* disable all INTs */
writel(0, VIC_INT_EN0);
writel(0, VIC_INT_EN1);
/* don't use 1136 vic */
writel(0, VIC_CONFIG);
/* enable interrupt controller */
writel(1, VIC_INT_MASTEREN);
for (n = 0; n < NR_MSM_IRQS; n++) {
irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
set_irq_flags(n, IRQF_VALID);
}
}

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/* arch/arm/mach-msm/last_radio_log.c
*
* Extract the log from a modem crash though SMEM
*
* Copyright (C) 2007 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/fs.h>
#include <linux/proc_fs.h>
#include <linux/uaccess.h>
#include "smd_private.h"
static void *radio_log_base;
static size_t radio_log_size;
extern void *smem_item(unsigned id, unsigned *size);
static ssize_t last_radio_log_read(struct file *file, char __user *buf,
size_t len, loff_t *offset)
{
return simple_read_from_buffer(buf, len, offset,
radio_log_base, radio_log_size);
}
static struct file_operations last_radio_log_fops = {
.read = last_radio_log_read,
.llseek = default_llseek,
};
void msm_init_last_radio_log(struct module *owner)
{
struct proc_dir_entry *entry;
if (last_radio_log_fops.owner) {
pr_err("%s: already claimed\n", __func__);
return;
}
radio_log_base = smem_item(SMEM_CLKREGIM_BSP, &radio_log_size);
if (!radio_log_base) {
pr_err("%s: could not retrieve SMEM_CLKREGIM_BSP\n", __func__);
return;
}
entry = proc_create("last_radio_log", S_IRUGO, NULL,
&last_radio_log_fops);
if (!entry) {
pr_err("%s: could not create proc entry for radio log\n",
__func__);
return;
}
pr_err("%s: last radio log is %d bytes long\n", __func__,
radio_log_size);
last_radio_log_fops.owner = owner;
proc_set_size(entry, radio_log_size);
}
EXPORT_SYMBOL(msm_init_last_radio_log);

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/* arch/arm/mach-msm/proc_comm.c
*
* Copyright (C) 2007-2008 Google, Inc.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <mach/msm_iomap.h>
#include "proc_comm.h"
static inline void msm_a2m_int(uint32_t irq)
{
#if defined(CONFIG_ARCH_MSM7X30)
writel(1 << irq, MSM_GCC_BASE + 0x8);
#else
writel(1, MSM_CSR_BASE + 0x400 + (irq * 4));
#endif
}
static inline void notify_other_proc_comm(void)
{
msm_a2m_int(6);
}
#define APP_COMMAND 0x00
#define APP_STATUS 0x04
#define APP_DATA1 0x08
#define APP_DATA2 0x0C
#define MDM_COMMAND 0x10
#define MDM_STATUS 0x14
#define MDM_DATA1 0x18
#define MDM_DATA2 0x1C
static DEFINE_SPINLOCK(proc_comm_lock);
/* The higher level SMD support will install this to
* provide a way to check for and handle modem restart.
*/
int (*msm_check_for_modem_crash)(void);
/* Poll for a state change, checking for possible
* modem crashes along the way (so we don't wait
* forever while the ARM9 is blowing up).
*
* Return an error in the event of a modem crash and
* restart so the msm_proc_comm() routine can restart
* the operation from the beginning.
*/
static int proc_comm_wait_for(void __iomem *addr, unsigned value)
{
for (;;) {
if (readl(addr) == value)
return 0;
if (msm_check_for_modem_crash)
if (msm_check_for_modem_crash())
return -EAGAIN;
}
}
int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2)
{
void __iomem *base = MSM_SHARED_RAM_BASE;
unsigned long flags;
int ret;
spin_lock_irqsave(&proc_comm_lock, flags);
for (;;) {
if (proc_comm_wait_for(base + MDM_STATUS, PCOM_READY))
continue;
writel(cmd, base + APP_COMMAND);
writel(data1 ? *data1 : 0, base + APP_DATA1);
writel(data2 ? *data2 : 0, base + APP_DATA2);
notify_other_proc_comm();
if (proc_comm_wait_for(base + APP_COMMAND, PCOM_CMD_DONE))
continue;
if (readl(base + APP_STATUS) != PCOM_CMD_FAIL) {
if (data1)
*data1 = readl(base + APP_DATA1);
if (data2)
*data2 = readl(base + APP_DATA2);
ret = 0;
} else {
ret = -EIO;
}
break;
}
writel(PCOM_CMD_IDLE, base + APP_COMMAND);
spin_unlock_irqrestore(&proc_comm_lock, flags);
return ret;
}
/*
* We need to wait for the ARM9 to at least partially boot
* up before we can continue. Since the ARM9 does resource
* allocation, if we dont' wait we could end up crashing or in
* and unknown state. This function should be called early to
* wait on the ARM9.
*/
void proc_comm_boot_wait(void)
{
void __iomem *base = MSM_SHARED_RAM_BASE;
proc_comm_wait_for(base + MDM_STATUS, PCOM_READY);
}

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/* arch/arm/mach-msm/proc_comm.h
*
* Copyright (c) 2007 QUALCOMM Incorporated
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _ARCH_ARM_MACH_MSM_PROC_COMM_H_
#define _ARCH_ARM_MACH_MSM_PROC_COMM_H_
#include <linux/init.h>
enum {
PCOM_CMD_IDLE = 0x0,
PCOM_CMD_DONE,
PCOM_RESET_APPS,
PCOM_RESET_CHIP,
PCOM_CONFIG_NAND_MPU,
PCOM_CONFIG_USB_CLKS,
PCOM_GET_POWER_ON_STATUS,
PCOM_GET_WAKE_UP_STATUS,
PCOM_GET_BATT_LEVEL,
PCOM_CHG_IS_CHARGING,
PCOM_POWER_DOWN,
PCOM_USB_PIN_CONFIG,
PCOM_USB_PIN_SEL,
PCOM_SET_RTC_ALARM,
PCOM_NV_READ,
PCOM_NV_WRITE,
PCOM_GET_UUID_HIGH,
PCOM_GET_UUID_LOW,
PCOM_GET_HW_ENTROPY,
PCOM_RPC_GPIO_TLMM_CONFIG_REMOTE,
PCOM_CLKCTL_RPC_ENABLE,
PCOM_CLKCTL_RPC_DISABLE,
PCOM_CLKCTL_RPC_RESET,
PCOM_CLKCTL_RPC_SET_FLAGS,
PCOM_CLKCTL_RPC_SET_RATE,
PCOM_CLKCTL_RPC_MIN_RATE,
PCOM_CLKCTL_RPC_MAX_RATE,
PCOM_CLKCTL_RPC_RATE,
PCOM_CLKCTL_RPC_PLL_REQUEST,
PCOM_CLKCTL_RPC_ENABLED,
PCOM_VREG_SWITCH,
PCOM_VREG_SET_LEVEL,
PCOM_GPIO_TLMM_CONFIG_GROUP,
PCOM_GPIO_TLMM_UNCONFIG_GROUP,
PCOM_NV_WRITE_BYTES_4_7,
PCOM_CONFIG_DISP,
PCOM_GET_FTM_BOOT_COUNT,
PCOM_RPC_GPIO_TLMM_CONFIG_EX,
PCOM_PM_MPP_CONFIG,
PCOM_GPIO_IN,
PCOM_GPIO_OUT,
PCOM_RESET_MODEM,
PCOM_RESET_CHIP_IMM,
PCOM_PM_VID_EN,
PCOM_VREG_PULLDOWN,
PCOM_GET_MODEM_VERSION,
PCOM_CLK_REGIME_SEC_RESET,
PCOM_CLK_REGIME_SEC_RESET_ASSERT,
PCOM_CLK_REGIME_SEC_RESET_DEASSERT,
PCOM_CLK_REGIME_SEC_PLL_REQUEST_WRP,
PCOM_CLK_REGIME_SEC_ENABLE,
PCOM_CLK_REGIME_SEC_DISABLE,
PCOM_CLK_REGIME_SEC_IS_ON,
PCOM_CLK_REGIME_SEC_SEL_CLK_INV,
PCOM_CLK_REGIME_SEC_SEL_CLK_SRC,
PCOM_CLK_REGIME_SEC_SEL_CLK_DIV,
PCOM_CLK_REGIME_SEC_ICODEC_CLK_ENABLE,
PCOM_CLK_REGIME_SEC_ICODEC_CLK_DISABLE,
PCOM_CLK_REGIME_SEC_SEL_SPEED,
PCOM_CLK_REGIME_SEC_CONFIG_GP_CLK_WRP,
PCOM_CLK_REGIME_SEC_CONFIG_MDH_CLK_WRP,
PCOM_CLK_REGIME_SEC_USB_XTAL_ON,
PCOM_CLK_REGIME_SEC_USB_XTAL_OFF,
PCOM_CLK_REGIME_SEC_SET_QDSP_DME_MODE,
PCOM_CLK_REGIME_SEC_SWITCH_ADSP_CLK,
PCOM_CLK_REGIME_SEC_GET_MAX_ADSP_CLK_KHZ,
PCOM_CLK_REGIME_SEC_GET_I2C_CLK_KHZ,
PCOM_CLK_REGIME_SEC_MSM_GET_CLK_FREQ_KHZ,
PCOM_CLK_REGIME_SEC_SEL_VFE_SRC,
PCOM_CLK_REGIME_SEC_MSM_SEL_CAMCLK,
PCOM_CLK_REGIME_SEC_MSM_SEL_LCDCLK,
PCOM_CLK_REGIME_SEC_VFE_RAIL_OFF,
PCOM_CLK_REGIME_SEC_VFE_RAIL_ON,
PCOM_CLK_REGIME_SEC_GRP_RAIL_OFF,
PCOM_CLK_REGIME_SEC_GRP_RAIL_ON,
PCOM_CLK_REGIME_SEC_VDC_RAIL_OFF,
PCOM_CLK_REGIME_SEC_VDC_RAIL_ON,
PCOM_CLK_REGIME_SEC_LCD_CTRL,
PCOM_CLK_REGIME_SEC_REGISTER_FOR_CPU_RESOURCE,
PCOM_CLK_REGIME_SEC_DEREGISTER_FOR_CPU_RESOURCE,
PCOM_CLK_REGIME_SEC_RESOURCE_REQUEST_WRP,
PCOM_CLK_REGIME_MSM_SEC_SEL_CLK_OWNER,
PCOM_CLK_REGIME_SEC_DEVMAN_REQUEST_WRP,
PCOM_GPIO_CONFIG,
PCOM_GPIO_CONFIGURE_GROUP,
PCOM_GPIO_TLMM_SET_PORT,
PCOM_GPIO_TLMM_CONFIG_EX,
PCOM_SET_FTM_BOOT_COUNT,
PCOM_RESERVED0,
PCOM_RESERVED1,
PCOM_CUSTOMER_CMD1,
PCOM_CUSTOMER_CMD2,
PCOM_CUSTOMER_CMD3,
PCOM_CLK_REGIME_ENTER_APPSBL_CHG_MODE,
PCOM_CLK_REGIME_EXIT_APPSBL_CHG_MODE,
PCOM_CLK_REGIME_SEC_RAIL_DISABLE,
PCOM_CLK_REGIME_SEC_RAIL_ENABLE,
PCOM_CLK_REGIME_SEC_RAIL_CONTROL,
PCOM_SET_SW_WATCHDOG_STATE,
PCOM_PM_MPP_CONFIG_DIGITAL_INPUT,
PCOM_PM_MPP_CONFIG_I_SINK,
PCOM_RESERVED_101,
PCOM_MSM_HSUSB_PHY_RESET,
PCOM_GET_BATT_MV_LEVEL,
PCOM_CHG_USB_IS_PC_CONNECTED,
PCOM_CHG_USB_IS_CHARGER_CONNECTED,
PCOM_CHG_USB_IS_DISCONNECTED,
PCOM_CHG_USB_IS_AVAILABLE,
PCOM_CLK_REGIME_SEC_MSM_SEL_FREQ,
PCOM_CLK_REGIME_SEC_SET_PCLK_AXI_POLICY,
PCOM_CLKCTL_RPC_RESET_ASSERT,
PCOM_CLKCTL_RPC_RESET_DEASSERT,
PCOM_CLKCTL_RPC_RAIL_ON,
PCOM_CLKCTL_RPC_RAIL_OFF,
PCOM_CLKCTL_RPC_RAIL_ENABLE,
PCOM_CLKCTL_RPC_RAIL_DISABLE,
PCOM_CLKCTL_RPC_RAIL_CONTROL,
PCOM_CLKCTL_RPC_MIN_MSMC1,
PCOM_NUM_CMDS,
};
enum {
PCOM_INVALID_STATUS = 0x0,
PCOM_READY,
PCOM_CMD_RUNNING,
PCOM_CMD_SUCCESS,
PCOM_CMD_FAIL,
PCOM_CMD_FAIL_FALSE_RETURNED,
PCOM_CMD_FAIL_CMD_OUT_OF_BOUNDS_SERVER,
PCOM_CMD_FAIL_CMD_OUT_OF_BOUNDS_CLIENT,
PCOM_CMD_FAIL_CMD_UNREGISTERED,
PCOM_CMD_FAIL_CMD_LOCKED,
PCOM_CMD_FAIL_SERVER_NOT_YET_READY,
PCOM_CMD_FAIL_BAD_DESTINATION,
PCOM_CMD_FAIL_SERVER_RESET,
PCOM_CMD_FAIL_SMSM_NOT_INIT,
PCOM_CMD_FAIL_PROC_COMM_BUSY,
PCOM_CMD_FAIL_PROC_COMM_NOT_INIT,
};
/* List of VREGs that support the Pull Down Resistor setting. */
enum vreg_pdown_id {
PM_VREG_PDOWN_MSMA_ID,
PM_VREG_PDOWN_MSMP_ID,
PM_VREG_PDOWN_MSME1_ID, /* Not supported in Panoramix */
PM_VREG_PDOWN_MSMC1_ID, /* Not supported in PM6620 */
PM_VREG_PDOWN_MSMC2_ID, /* Supported in PM7500 only */
PM_VREG_PDOWN_GP3_ID, /* Supported in PM7500 only */
PM_VREG_PDOWN_MSME2_ID, /* Supported in PM7500 and Panoramix only */
PM_VREG_PDOWN_GP4_ID, /* Supported in PM7500 only */
PM_VREG_PDOWN_GP1_ID, /* Supported in PM7500 only */
PM_VREG_PDOWN_TCXO_ID,
PM_VREG_PDOWN_PA_ID,
PM_VREG_PDOWN_RFTX_ID,
PM_VREG_PDOWN_RFRX1_ID,
PM_VREG_PDOWN_RFRX2_ID,
PM_VREG_PDOWN_SYNT_ID,
PM_VREG_PDOWN_WLAN_ID,
PM_VREG_PDOWN_USB_ID,
PM_VREG_PDOWN_MMC_ID,
PM_VREG_PDOWN_RUIM_ID,
PM_VREG_PDOWN_MSMC0_ID, /* Supported in PM6610 only */
PM_VREG_PDOWN_GP2_ID, /* Supported in PM7500 only */
PM_VREG_PDOWN_GP5_ID, /* Supported in PM7500 only */
PM_VREG_PDOWN_GP6_ID, /* Supported in PM7500 only */
PM_VREG_PDOWN_RF_ID,
PM_VREG_PDOWN_RF_VCO_ID,
PM_VREG_PDOWN_MPLL_ID,
PM_VREG_PDOWN_S2_ID,
PM_VREG_PDOWN_S3_ID,
PM_VREG_PDOWN_RFUBM_ID,
/* new for HAN */
PM_VREG_PDOWN_RF1_ID,
PM_VREG_PDOWN_RF2_ID,
PM_VREG_PDOWN_RFA_ID,
PM_VREG_PDOWN_CDC2_ID,
PM_VREG_PDOWN_RFTX2_ID,
PM_VREG_PDOWN_USIM_ID,
PM_VREG_PDOWN_USB2P6_ID,
PM_VREG_PDOWN_USB3P3_ID,
PM_VREG_PDOWN_INVALID_ID,
/* backward compatible enums only */
PM_VREG_PDOWN_CAM_ID = PM_VREG_PDOWN_GP1_ID,
PM_VREG_PDOWN_MDDI_ID = PM_VREG_PDOWN_GP2_ID,
PM_VREG_PDOWN_RUIM2_ID = PM_VREG_PDOWN_GP3_ID,
PM_VREG_PDOWN_AUX_ID = PM_VREG_PDOWN_GP4_ID,
PM_VREG_PDOWN_AUX2_ID = PM_VREG_PDOWN_GP5_ID,
PM_VREG_PDOWN_BT_ID = PM_VREG_PDOWN_GP6_ID,
PM_VREG_PDOWN_MSME_ID = PM_VREG_PDOWN_MSME1_ID,
PM_VREG_PDOWN_MSMC_ID = PM_VREG_PDOWN_MSMC1_ID,
PM_VREG_PDOWN_RFA1_ID = PM_VREG_PDOWN_RFRX2_ID,
PM_VREG_PDOWN_RFA2_ID = PM_VREG_PDOWN_RFTX2_ID,
PM_VREG_PDOWN_XO_ID = PM_VREG_PDOWN_TCXO_ID
};
enum {
PCOM_CLKRGM_APPS_RESET_USB_PHY = 34,
PCOM_CLKRGM_APPS_RESET_USBH = 37,
};
/* gpio info for PCOM_RPC_GPIO_TLMM_CONFIG_EX */
#define GPIO_ENABLE 0
#define GPIO_DISABLE 1
#define GPIO_INPUT 0
#define GPIO_OUTPUT 1
#define GPIO_NO_PULL 0
#define GPIO_PULL_DOWN 1
#define GPIO_KEEPER 2
#define GPIO_PULL_UP 3
#define GPIO_2MA 0
#define GPIO_4MA 1
#define GPIO_6MA 2
#define GPIO_8MA 3
#define GPIO_10MA 4
#define GPIO_12MA 5
#define GPIO_14MA 6
#define GPIO_16MA 7
#define PCOM_GPIO_CFG(gpio, func, dir, pull, drvstr) \
((((gpio) & 0x3FF) << 4) | \
((func) & 0xf) | \
(((dir) & 0x1) << 14) | \
(((pull) & 0x3) << 15) | \
(((drvstr) & 0xF) << 17))
int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2);
void proc_comm_boot_wait(void);
#endif

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arch/arm/mach-msm/sirc.c Normal file
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/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <asm/irq.h>
static unsigned int int_enable;
static unsigned int wake_enable;
static struct sirc_regs_t sirc_regs = {
.int_enable = SPSS_SIRC_INT_ENABLE,
.int_enable_clear = SPSS_SIRC_INT_ENABLE_CLEAR,
.int_enable_set = SPSS_SIRC_INT_ENABLE_SET,
.int_type = SPSS_SIRC_INT_TYPE,
.int_polarity = SPSS_SIRC_INT_POLARITY,
.int_clear = SPSS_SIRC_INT_CLEAR,
};
static struct sirc_cascade_regs sirc_reg_table[] = {
{
.int_status = SPSS_SIRC_IRQ_STATUS,
.cascade_irq = INT_SIRC_0,
}
};
/* Mask off the given interrupt. Keep the int_enable mask in sync with
the enable reg, so it can be restored after power collapse. */
static void sirc_irq_mask(struct irq_data *d)
{
unsigned int mask;
mask = 1 << (d->irq - FIRST_SIRC_IRQ);
writel(mask, sirc_regs.int_enable_clear);
int_enable &= ~mask;
return;
}
/* Unmask the given interrupt. Keep the int_enable mask in sync with
the enable reg, so it can be restored after power collapse. */
static void sirc_irq_unmask(struct irq_data *d)
{
unsigned int mask;
mask = 1 << (d->irq - FIRST_SIRC_IRQ);
writel(mask, sirc_regs.int_enable_set);
int_enable |= mask;
return;
}
static void sirc_irq_ack(struct irq_data *d)
{
unsigned int mask;
mask = 1 << (d->irq - FIRST_SIRC_IRQ);
writel(mask, sirc_regs.int_clear);
return;
}
static int sirc_irq_set_wake(struct irq_data *d, unsigned int on)
{
unsigned int mask;
/* Used to set the interrupt enable mask during power collapse. */
mask = 1 << (d->irq - FIRST_SIRC_IRQ);
if (on)
wake_enable |= mask;
else
wake_enable &= ~mask;
return 0;
}
static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
unsigned int mask;
unsigned int val;
mask = 1 << (d->irq - FIRST_SIRC_IRQ);
val = readl(sirc_regs.int_polarity);
if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING))
val |= mask;
else
val &= ~mask;
writel(val, sirc_regs.int_polarity);
val = readl(sirc_regs.int_type);
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
val |= mask;
__irq_set_handler_locked(d->irq, handle_edge_irq);
} else {
val &= ~mask;
__irq_set_handler_locked(d->irq, handle_level_irq);
}
writel(val, sirc_regs.int_type);
return 0;
}
/* Finds the pending interrupt on the passed cascade irq and redrives it */
static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned int reg = 0;
unsigned int sirq;
unsigned int status;
while ((reg < ARRAY_SIZE(sirc_reg_table)) &&
(sirc_reg_table[reg].cascade_irq != irq))
reg++;
status = readl(sirc_reg_table[reg].int_status);
status &= SIRC_MASK;
if (status == 0)
return;
for (sirq = 0;
(sirq < NR_SIRC_IRQS) && ((status & (1U << sirq)) == 0);
sirq++)
;
generic_handle_irq(sirq+FIRST_SIRC_IRQ);
desc->irq_data.chip->irq_ack(&desc->irq_data);
}
static struct irq_chip sirc_irq_chip = {
.name = "sirc",
.irq_ack = sirc_irq_ack,
.irq_mask = sirc_irq_mask,
.irq_unmask = sirc_irq_unmask,
.irq_set_wake = sirc_irq_set_wake,
.irq_set_type = sirc_irq_set_type,
};
void __init msm_init_sirc(void)
{
int i;
int_enable = 0;
wake_enable = 0;
for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) {
irq_set_chip_and_handler(i, &sirc_irq_chip, handle_edge_irq);
set_irq_flags(i, IRQF_VALID);
}
for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) {
irq_set_chained_handler(sirc_reg_table[i].cascade_irq,
sirc_irq_handler);
irq_set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
}
return;
}

1035
arch/arm/mach-msm/smd.c Normal file
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311
arch/arm/mach-msm/smd_debug.c Normal file
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/* arch/arm/mach-msm/smd_debug.c
*
* Copyright (C) 2007 Google, Inc.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/debugfs.h>
#include <linux/list.h>
#include <mach/msm_iomap.h>
#include "smd_private.h"
#if defined(CONFIG_DEBUG_FS)
static char *chstate(unsigned n)
{
switch (n) {
case SMD_SS_CLOSED:
return "CLOSED";
case SMD_SS_OPENING:
return "OPENING";
case SMD_SS_OPENED:
return "OPENED";
case SMD_SS_FLUSHING:
return "FLUSHING";
case SMD_SS_CLOSING:
return "CLOSING";
case SMD_SS_RESET:
return "RESET";
case SMD_SS_RESET_OPENING:
return "ROPENING";
default:
return "UNKNOWN";
}
}
static int dump_ch(char *buf, int max, struct smd_channel *ch)
{
volatile struct smd_half_channel *s = ch->send;
volatile struct smd_half_channel *r = ch->recv;
return scnprintf(
buf, max,
"ch%02d:"
" %8s(%05d/%05d) %c%c%c%c%c%c%c <->"
" %8s(%05d/%05d) %c%c%c%c%c%c%c '%s'\n", ch->n,
chstate(s->state), s->tail, s->head,
s->fDSR ? 'D' : 'd',
s->fCTS ? 'C' : 'c',
s->fCD ? 'C' : 'c',
s->fRI ? 'I' : 'i',
s->fHEAD ? 'W' : 'w',
s->fTAIL ? 'R' : 'r',
s->fSTATE ? 'S' : 's',
chstate(r->state), r->tail, r->head,
r->fDSR ? 'D' : 'd',
r->fCTS ? 'R' : 'r',
r->fCD ? 'C' : 'c',
r->fRI ? 'I' : 'i',
r->fHEAD ? 'W' : 'w',
r->fTAIL ? 'R' : 'r',
r->fSTATE ? 'S' : 's',
ch->name
);
}
static int debug_read_stat(char *buf, int max)
{
char *msg;
int i = 0;
msg = smem_find(ID_DIAG_ERR_MSG, SZ_DIAG_ERR_MSG);
if (raw_smsm_get_state(SMSM_STATE_MODEM) & SMSM_RESET)
i += scnprintf(buf + i, max - i,
"smsm: ARM9 HAS CRASHED\n");
i += scnprintf(buf + i, max - i, "smsm: a9: %08x a11: %08x\n",
raw_smsm_get_state(SMSM_STATE_MODEM),
raw_smsm_get_state(SMSM_STATE_APPS));
#ifdef CONFIG_ARCH_MSM_SCORPION
i += scnprintf(buf + i, max - i, "smsm dem: apps: %08x modem: %08x "
"qdsp6: %08x power: %08x time: %08x\n",
raw_smsm_get_state(SMSM_STATE_APPS_DEM),
raw_smsm_get_state(SMSM_STATE_MODEM_DEM),
raw_smsm_get_state(SMSM_STATE_QDSP6_DEM),
raw_smsm_get_state(SMSM_STATE_POWER_MASTER_DEM),
raw_smsm_get_state(SMSM_STATE_TIME_MASTER_DEM));
#endif
if (msg) {
msg[SZ_DIAG_ERR_MSG - 1] = 0;
i += scnprintf(buf + i, max - i, "diag: '%s'\n", msg);
}
return i;
}
static int debug_read_mem(char *buf, int max)
{
unsigned n;
struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE;
struct smem_heap_entry *toc = shared->heap_toc;
int i = 0;
i += scnprintf(buf + i, max - i,
"heap: init=%d free=%d remain=%d\n",
shared->heap_info.initialized,
shared->heap_info.free_offset,
shared->heap_info.heap_remaining);
for (n = 0; n < SMEM_NUM_ITEMS; n++) {
if (toc[n].allocated == 0)
continue;
i += scnprintf(buf + i, max - i,
"%04d: offset %08x size %08x\n",
n, toc[n].offset, toc[n].size);
}
return i;
}
static int debug_read_ch(char *buf, int max)
{
struct smd_channel *ch;
unsigned long flags;
int i = 0;
spin_lock_irqsave(&smd_lock, flags);
list_for_each_entry(ch, &smd_ch_list_dsp, ch_list)
i += dump_ch(buf + i, max - i, ch);
list_for_each_entry(ch, &smd_ch_list_modem, ch_list)
i += dump_ch(buf + i, max - i, ch);
list_for_each_entry(ch, &smd_ch_closed_list, ch_list)
i += dump_ch(buf + i, max - i, ch);
spin_unlock_irqrestore(&smd_lock, flags);
return i;
}
static int debug_read_version(char *buf, int max)
{
struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE;
unsigned version = shared->version[VERSION_MODEM];
return sprintf(buf, "%d.%d\n", version >> 16, version & 0xffff);
}
static int debug_read_build_id(char *buf, int max)
{
unsigned size;
void *data;
data = smem_item(SMEM_HW_SW_BUILD_ID, &size);
if (!data)
return 0;
if (size >= max)
size = max;
memcpy(buf, data, size);
return size;
}
static int debug_read_alloc_tbl(char *buf, int max)
{
struct smd_alloc_elm *shared;
int n, i = 0;
shared = smem_find(ID_CH_ALLOC_TBL, sizeof(*shared) * 64);
for (n = 0; n < 64; n++) {
if (shared[n].ref_count == 0)
continue;
i += scnprintf(buf + i, max - i,
"%03d: %-20s cid=%02d type=%03d "
"kind=%02d ref_count=%d\n",
n, shared[n].name, shared[n].cid,
shared[n].ctype & 0xff,
(shared[n].ctype >> 8) & 0xf,
shared[n].ref_count);
}
return i;
}
#define DEBUG_BUFMAX 4096
static char debug_buffer[DEBUG_BUFMAX];
static ssize_t debug_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
int (*fill)(char *buf, int max) = file->private_data;
int bsize = fill(debug_buffer, DEBUG_BUFMAX);
return simple_read_from_buffer(buf, count, ppos, debug_buffer, bsize);
}
static const struct file_operations debug_ops = {
.read = debug_read,
.open = simple_open,
.llseek = default_llseek,
};
static void debug_create(const char *name, umode_t mode,
struct dentry *dent,
int (*fill)(char *buf, int max))
{
debugfs_create_file(name, mode, dent, fill, &debug_ops);
}
int __init smd_debugfs_init(void)
{
struct dentry *dent;
dent = debugfs_create_dir("smd", 0);
if (IS_ERR(dent))
return 1;
debug_create("ch", 0444, dent, debug_read_ch);
debug_create("stat", 0444, dent, debug_read_stat);
debug_create("mem", 0444, dent, debug_read_mem);
debug_create("version", 0444, dent, debug_read_version);
debug_create("tbl", 0444, dent, debug_read_alloc_tbl);
debug_create("build", 0444, dent, debug_read_build_id);
return 0;
}
#endif
#define MAX_NUM_SLEEP_CLIENTS 64
#define MAX_SLEEP_NAME_LEN 8
#define NUM_GPIO_INT_REGISTERS 6
#define GPIO_SMEM_NUM_GROUPS 2
#define GPIO_SMEM_MAX_PC_INTERRUPTS 8
struct tramp_gpio_save {
unsigned int enable;
unsigned int detect;
unsigned int polarity;
};
struct tramp_gpio_smem {
uint16_t num_fired[GPIO_SMEM_NUM_GROUPS];
uint16_t fired[GPIO_SMEM_NUM_GROUPS][GPIO_SMEM_MAX_PC_INTERRUPTS];
uint32_t enabled[NUM_GPIO_INT_REGISTERS];
uint32_t detection[NUM_GPIO_INT_REGISTERS];
uint32_t polarity[NUM_GPIO_INT_REGISTERS];
};
void smsm_print_sleep_info(void)
{
unsigned long flags;
uint32_t *ptr;
#ifndef CONFIG_ARCH_MSM_SCORPION
struct tramp_gpio_smem *gpio;
struct smsm_interrupt_info *int_info;
#endif
spin_lock_irqsave(&smem_lock, flags);
ptr = smem_alloc(SMEM_SMSM_SLEEP_DELAY, sizeof(*ptr));
if (ptr)
pr_info("SMEM_SMSM_SLEEP_DELAY: %x\n", *ptr);
ptr = smem_alloc(SMEM_SMSM_LIMIT_SLEEP, sizeof(*ptr));
if (ptr)
pr_info("SMEM_SMSM_LIMIT_SLEEP: %x\n", *ptr);
ptr = smem_alloc(SMEM_SLEEP_POWER_COLLAPSE_DISABLED, sizeof(*ptr));
if (ptr)
pr_info("SMEM_SLEEP_POWER_COLLAPSE_DISABLED: %x\n", *ptr);
#ifndef CONFIG_ARCH_MSM_SCORPION
int_info = smem_alloc(SMEM_SMSM_INT_INFO, sizeof(*int_info));
if (int_info)
pr_info("SMEM_SMSM_INT_INFO %x %x %x\n",
int_info->interrupt_mask,
int_info->pending_interrupts,
int_info->wakeup_reason);
gpio = smem_alloc(SMEM_GPIO_INT, sizeof(*gpio));
if (gpio) {
int i;
for (i = 0; i < NUM_GPIO_INT_REGISTERS; i++)
pr_info("SMEM_GPIO_INT: %d: e %x d %x p %x\n",
i, gpio->enabled[i], gpio->detection[i],
gpio->polarity[i]);
for (i = 0; i < GPIO_SMEM_NUM_GROUPS; i++)
pr_info("SMEM_GPIO_INT: %d: f %d: %d %d...\n",
i, gpio->num_fired[i], gpio->fired[i][0],
gpio->fired[i][1]);
}
#else
#endif
spin_unlock_irqrestore(&smem_lock, flags);
}

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arch/arm/mach-msm/smd_private.h Normal file
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/* arch/arm/mach-msm/smd_private.h
*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2007 QUALCOMM Incorporated
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
#define _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/list.h>
#include <linux/io.h>
#include <mach/msm_iomap.h>
struct smem_heap_info {
unsigned initialized;
unsigned free_offset;
unsigned heap_remaining;
unsigned reserved;
};
struct smem_heap_entry {
unsigned allocated;
unsigned offset;
unsigned size;
unsigned reserved;
};
struct smem_proc_comm {
unsigned command;
unsigned status;
unsigned data1;
unsigned data2;
};
#define PC_APPS 0
#define PC_MODEM 1
#define VERSION_SMD 0
#define VERSION_QDSP6 4
#define VERSION_APPS_SBL 6
#define VERSION_MODEM_SBL 7
#define VERSION_APPS 8
#define VERSION_MODEM 9
struct smem_shared {
struct smem_proc_comm proc_comm[4];
unsigned version[32];
struct smem_heap_info heap_info;
struct smem_heap_entry heap_toc[512];
};
#define SMSM_V1_SIZE (sizeof(unsigned) * 8)
#define SMSM_V2_SIZE (sizeof(unsigned) * 4)
#ifdef CONFIG_MSM_SMD_PKG3
struct smsm_interrupt_info {
uint32_t interrupt_mask;
uint32_t pending_interrupts;
uint32_t wakeup_reason;
};
#else
#define DEM_MAX_PORT_NAME_LEN (20)
struct msm_dem_slave_data {
uint32_t sleep_time;
uint32_t interrupt_mask;
uint32_t resources_used;
uint32_t reserved1;
uint32_t wakeup_reason;
uint32_t pending_interrupts;
uint32_t rpc_prog;
uint32_t rpc_proc;
char smd_port_name[DEM_MAX_PORT_NAME_LEN];
uint32_t reserved2;
};
#endif
#define SZ_DIAG_ERR_MSG 0xC8
#define ID_DIAG_ERR_MSG SMEM_DIAG_ERR_MESSAGE
#define ID_SMD_CHANNELS SMEM_SMD_BASE_ID
#define ID_SHARED_STATE SMEM_SMSM_SHARED_STATE
#define ID_CH_ALLOC_TBL SMEM_CHANNEL_ALLOC_TBL
#define SMSM_INIT 0x00000001
#define SMSM_SMDINIT 0x00000008
#define SMSM_RPCINIT 0x00000020
#define SMSM_RESET 0x00000040
#define SMSM_RSA 0x00000080
#define SMSM_RUN 0x00000100
#define SMSM_PWRC 0x00000200
#define SMSM_TIMEWAIT 0x00000400
#define SMSM_TIMEINIT 0x00000800
#define SMSM_PWRC_EARLY_EXIT 0x00001000
#define SMSM_WFPI 0x00002000
#define SMSM_SLEEP 0x00004000
#define SMSM_SLEEPEXIT 0x00008000
#define SMSM_APPS_REBOOT 0x00020000
#define SMSM_SYSTEM_POWER_DOWN 0x00040000
#define SMSM_SYSTEM_REBOOT 0x00080000
#define SMSM_SYSTEM_DOWNLOAD 0x00100000
#define SMSM_PWRC_SUSPEND 0x00200000
#define SMSM_APPS_SHUTDOWN 0x00400000
#define SMSM_SMD_LOOPBACK 0x00800000
#define SMSM_RUN_QUIET 0x01000000
#define SMSM_MODEM_WAIT 0x02000000
#define SMSM_MODEM_BREAK 0x04000000
#define SMSM_MODEM_CONTINUE 0x08000000
#define SMSM_UNKNOWN 0x80000000
#define SMSM_WKUP_REASON_RPC 0x00000001
#define SMSM_WKUP_REASON_INT 0x00000002
#define SMSM_WKUP_REASON_GPIO 0x00000004
#define SMSM_WKUP_REASON_TIMER 0x00000008
#define SMSM_WKUP_REASON_ALARM 0x00000010
#define SMSM_WKUP_REASON_RESET 0x00000020
#ifdef CONFIG_ARCH_MSM7X00A
enum smsm_state_item {
SMSM_STATE_APPS = 1,
SMSM_STATE_MODEM = 3,
SMSM_STATE_COUNT,
};
#else
enum smsm_state_item {
SMSM_STATE_APPS,
SMSM_STATE_MODEM,
SMSM_STATE_HEXAGON,
SMSM_STATE_APPS_DEM,
SMSM_STATE_MODEM_DEM,
SMSM_STATE_QDSP6_DEM,
SMSM_STATE_POWER_MASTER_DEM,
SMSM_STATE_TIME_MASTER_DEM,
SMSM_STATE_COUNT,
};
#endif
void *smem_alloc(unsigned id, unsigned size);
int smsm_change_state(enum smsm_state_item item, uint32_t clear_mask, uint32_t set_mask);
uint32_t smsm_get_state(enum smsm_state_item item);
int smsm_set_sleep_duration(uint32_t delay);
void smsm_print_sleep_info(void);
#define SMEM_NUM_SMD_CHANNELS 64
typedef enum {
/* fixed items */
SMEM_PROC_COMM = 0,
SMEM_HEAP_INFO,
SMEM_ALLOCATION_TABLE,
SMEM_VERSION_INFO,
SMEM_HW_RESET_DETECT,
SMEM_AARM_WARM_BOOT,
SMEM_DIAG_ERR_MESSAGE,
SMEM_SPINLOCK_ARRAY,
SMEM_MEMORY_BARRIER_LOCATION,
/* dynamic items */
SMEM_AARM_PARTITION_TABLE,
SMEM_AARM_BAD_BLOCK_TABLE,
SMEM_RESERVE_BAD_BLOCKS,
SMEM_WM_UUID,
SMEM_CHANNEL_ALLOC_TBL,
SMEM_SMD_BASE_ID,
SMEM_SMEM_LOG_IDX = SMEM_SMD_BASE_ID + SMEM_NUM_SMD_CHANNELS,
SMEM_SMEM_LOG_EVENTS,
SMEM_SMEM_STATIC_LOG_IDX,
SMEM_SMEM_STATIC_LOG_EVENTS,
SMEM_SMEM_SLOW_CLOCK_SYNC,
SMEM_SMEM_SLOW_CLOCK_VALUE,
SMEM_BIO_LED_BUF,
SMEM_SMSM_SHARED_STATE,
SMEM_SMSM_INT_INFO,
SMEM_SMSM_SLEEP_DELAY,
SMEM_SMSM_LIMIT_SLEEP,
SMEM_SLEEP_POWER_COLLAPSE_DISABLED,
SMEM_KEYPAD_KEYS_PRESSED,
SMEM_KEYPAD_STATE_UPDATED,
SMEM_KEYPAD_STATE_IDX,
SMEM_GPIO_INT,
SMEM_MDDI_LCD_IDX,
SMEM_MDDI_HOST_DRIVER_STATE,
SMEM_MDDI_LCD_DISP_STATE,
SMEM_LCD_CUR_PANEL,
SMEM_MARM_BOOT_SEGMENT_INFO,
SMEM_AARM_BOOT_SEGMENT_INFO,
SMEM_SLEEP_STATIC,
SMEM_SCORPION_FREQUENCY,
SMEM_SMD_PROFILES,
SMEM_TSSC_BUSY,
SMEM_HS_SUSPEND_FILTER_INFO,
SMEM_BATT_INFO,
SMEM_APPS_BOOT_MODE,
SMEM_VERSION_FIRST,
SMEM_VERSION_LAST = SMEM_VERSION_FIRST + 24,
SMEM_OSS_RRCASN1_BUF1,
SMEM_OSS_RRCASN1_BUF2,
SMEM_ID_VENDOR0,
SMEM_ID_VENDOR1,
SMEM_ID_VENDOR2,
SMEM_HW_SW_BUILD_ID,
SMEM_SMD_BLOCK_PORT_BASE_ID,
SMEM_SMD_BLOCK_PORT_PROC0_HEAP = SMEM_SMD_BLOCK_PORT_BASE_ID + SMEM_NUM_SMD_CHANNELS,
SMEM_SMD_BLOCK_PORT_PROC1_HEAP = SMEM_SMD_BLOCK_PORT_PROC0_HEAP + SMEM_NUM_SMD_CHANNELS,
SMEM_I2C_MUTEX = SMEM_SMD_BLOCK_PORT_PROC1_HEAP + SMEM_NUM_SMD_CHANNELS,
SMEM_SCLK_CONVERSION,
SMEM_SMD_SMSM_INTR_MUX,
SMEM_SMSM_CPU_INTR_MASK,
SMEM_APPS_DEM_SLAVE_DATA,
SMEM_QDSP6_DEM_SLAVE_DATA,
SMEM_CLKREGIM_BSP,
SMEM_CLKREGIM_SOURCES,
SMEM_SMD_FIFO_BASE_ID,
SMEM_USABLE_RAM_PARTITION_TABLE = SMEM_SMD_FIFO_BASE_ID + SMEM_NUM_SMD_CHANNELS,
SMEM_POWER_ON_STATUS_INFO,
SMEM_DAL_AREA,
SMEM_SMEM_LOG_POWER_IDX,
SMEM_SMEM_LOG_POWER_WRAP,
SMEM_SMEM_LOG_POWER_EVENTS,
SMEM_ERR_CRASH_LOG,
SMEM_ERR_F3_TRACE_LOG,
SMEM_NUM_ITEMS,
} smem_mem_type;
#define SMD_SS_CLOSED 0x00000000
#define SMD_SS_OPENING 0x00000001
#define SMD_SS_OPENED 0x00000002
#define SMD_SS_FLUSHING 0x00000003
#define SMD_SS_CLOSING 0x00000004
#define SMD_SS_RESET 0x00000005
#define SMD_SS_RESET_OPENING 0x00000006
#define SMD_BUF_SIZE 8192
#define SMD_CHANNELS 64
#define SMD_HEADER_SIZE 20
struct smd_alloc_elm {
char name[20];
uint32_t cid;
uint32_t ctype;
uint32_t ref_count;
};
struct smd_half_channel {
unsigned state;
unsigned char fDSR;
unsigned char fCTS;
unsigned char fCD;
unsigned char fRI;
unsigned char fHEAD;
unsigned char fTAIL;
unsigned char fSTATE;
unsigned char fUNUSED;
unsigned tail;
unsigned head;
} __attribute__(( aligned(4), packed ));
/* Only used on SMD package v3 on msm7201a */
struct smd_shared_v1 {
struct smd_half_channel ch0;
unsigned char data0[SMD_BUF_SIZE];
struct smd_half_channel ch1;
unsigned char data1[SMD_BUF_SIZE];
};
/* Used on SMD package v4 */
struct smd_shared_v2 {
struct smd_half_channel ch0;
struct smd_half_channel ch1;
};
struct smd_channel {
volatile struct smd_half_channel *send;
volatile struct smd_half_channel *recv;
unsigned char *send_data;
unsigned char *recv_data;
unsigned fifo_mask;
unsigned fifo_size;
unsigned current_packet;
unsigned n;
struct list_head ch_list;
void *priv;
void (*notify)(void *priv, unsigned flags);
int (*read)(struct smd_channel *ch, void *data, int len);
int (*write)(struct smd_channel *ch, const void *data, int len);
int (*read_avail)(struct smd_channel *ch);
int (*write_avail)(struct smd_channel *ch);
void (*update_state)(struct smd_channel *ch);
unsigned last_state;
void (*notify_other_cpu)(void);
unsigned type;
char name[32];
struct platform_device pdev;
};
#define SMD_TYPE_MASK 0x0FF
#define SMD_TYPE_APPS_MODEM 0x000
#define SMD_TYPE_APPS_DSP 0x001
#define SMD_TYPE_MODEM_DSP 0x002
#define SMD_KIND_MASK 0xF00
#define SMD_KIND_UNKNOWN 0x000
#define SMD_KIND_STREAM 0x100
#define SMD_KIND_PACKET 0x200
extern struct list_head smd_ch_closed_list;
extern struct list_head smd_ch_list_modem;
extern struct list_head smd_ch_list_dsp;
extern spinlock_t smd_lock;
extern spinlock_t smem_lock;
void *smem_find(unsigned id, unsigned size);
void *smem_item(unsigned id, unsigned *size);
uint32_t raw_smsm_get_state(enum smsm_state_item item);
extern void msm_init_last_radio_log(struct module *);
#ifdef CONFIG_MSM_SMD_PKG3
/*
* This allocator assumes an SMD Package v3 which only exists on
* MSM7x00 SoC's.
*/
static inline int _smd_alloc_channel(struct smd_channel *ch)
{
struct smd_shared_v1 *shared1;
shared1 = smem_alloc(ID_SMD_CHANNELS + ch->n, sizeof(*shared1));
if (!shared1) {
pr_err("smd_alloc_channel() cid %d does not exist\n", ch->n);
return -1;
}
ch->send = &shared1->ch0;
ch->recv = &shared1->ch1;
ch->send_data = shared1->data0;
ch->recv_data = shared1->data1;
ch->fifo_size = SMD_BUF_SIZE;
return 0;
}
#else
/*
* This allocator assumes an SMD Package v4, the most common
* and the default.
*/
static inline int _smd_alloc_channel(struct smd_channel *ch)
{
struct smd_shared_v2 *shared2;
void *buffer;
unsigned buffer_sz;
shared2 = smem_alloc(SMEM_SMD_BASE_ID + ch->n, sizeof(*shared2));
buffer = smem_item(SMEM_SMD_FIFO_BASE_ID + ch->n, &buffer_sz);
if (!buffer)
return -1;
/* buffer must be a power-of-two size */
if (buffer_sz & (buffer_sz - 1))
return -1;
buffer_sz /= 2;
ch->send = &shared2->ch0;
ch->recv = &shared2->ch1;
ch->send_data = buffer;
ch->recv_data = buffer + buffer_sz;
ch->fifo_size = buffer_sz;
return 0;
}
#endif /* CONFIG_MSM_SMD_PKG3 */
#if defined(CONFIG_ARCH_MSM7X30)
static inline void msm_a2m_int(uint32_t irq)
{
writel(1 << irq, MSM_GCC_BASE + 0x8);
}
#else
static inline void msm_a2m_int(uint32_t irq)
{
writel(1, MSM_CSR_BASE + 0x400 + (irq * 4));
}
#endif /* CONFIG_ARCH_MSM7X30 */
#endif

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arch/arm/mach-msm/vreg.c Normal file
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/* arch/arm/mach-msm/vreg.c
*
* Copyright (C) 2008 Google, Inc.
* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/debugfs.h>
#include <linux/module.h>
#include <linux/string.h>
#include <mach/vreg.h>
#include "proc_comm.h"
struct vreg {
const char *name;
unsigned id;
int status;
unsigned refcnt;
};
#define VREG(_name, _id, _status, _refcnt) \
{ .name = _name, .id = _id, .status = _status, .refcnt = _refcnt }
static struct vreg vregs[] = {
VREG("msma", 0, 0, 0),
VREG("msmp", 1, 0, 0),
VREG("msme1", 2, 0, 0),
VREG("msmc1", 3, 0, 0),
VREG("msmc2", 4, 0, 0),
VREG("gp3", 5, 0, 0),
VREG("msme2", 6, 0, 0),
VREG("gp4", 7, 0, 0),
VREG("gp1", 8, 0, 0),
VREG("tcxo", 9, 0, 0),
VREG("pa", 10, 0, 0),
VREG("rftx", 11, 0, 0),
VREG("rfrx1", 12, 0, 0),
VREG("rfrx2", 13, 0, 0),
VREG("synt", 14, 0, 0),
VREG("wlan", 15, 0, 0),
VREG("usb", 16, 0, 0),
VREG("boost", 17, 0, 0),
VREG("mmc", 18, 0, 0),
VREG("ruim", 19, 0, 0),
VREG("msmc0", 20, 0, 0),
VREG("gp2", 21, 0, 0),
VREG("gp5", 22, 0, 0),
VREG("gp6", 23, 0, 0),
VREG("rf", 24, 0, 0),
VREG("rf_vco", 26, 0, 0),
VREG("mpll", 27, 0, 0),
VREG("s2", 28, 0, 0),
VREG("s3", 29, 0, 0),
VREG("rfubm", 30, 0, 0),
VREG("ncp", 31, 0, 0),
VREG("gp7", 32, 0, 0),
VREG("gp8", 33, 0, 0),
VREG("gp9", 34, 0, 0),
VREG("gp10", 35, 0, 0),
VREG("gp11", 36, 0, 0),
VREG("gp12", 37, 0, 0),
VREG("gp13", 38, 0, 0),
VREG("gp14", 39, 0, 0),
VREG("gp15", 40, 0, 0),
VREG("gp16", 41, 0, 0),
VREG("gp17", 42, 0, 0),
VREG("s4", 43, 0, 0),
VREG("usb2", 44, 0, 0),
VREG("wlan2", 45, 0, 0),
VREG("xo_out", 46, 0, 0),
VREG("lvsw0", 47, 0, 0),
VREG("lvsw1", 48, 0, 0),
};
struct vreg *vreg_get(struct device *dev, const char *id)
{
int n;
for (n = 0; n < ARRAY_SIZE(vregs); n++) {
if (!strcmp(vregs[n].name, id))
return vregs + n;
}
return ERR_PTR(-ENOENT);
}
void vreg_put(struct vreg *vreg)
{
}
int vreg_enable(struct vreg *vreg)
{
unsigned id = vreg->id;
unsigned enable = 1;
if (vreg->refcnt == 0)
vreg->status = msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable);
if ((vreg->refcnt < UINT_MAX) && (!vreg->status))
vreg->refcnt++;
return vreg->status;
}
int vreg_disable(struct vreg *vreg)
{
unsigned id = vreg->id;
unsigned enable = 0;
if (!vreg->refcnt)
return 0;
if (vreg->refcnt == 1)
vreg->status = msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable);
if (!vreg->status)
vreg->refcnt--;
return vreg->status;
}
int vreg_set_level(struct vreg *vreg, unsigned mv)
{
unsigned id = vreg->id;
vreg->status = msm_proc_comm(PCOM_VREG_SET_LEVEL, &id, &mv);
return vreg->status;
}
#if defined(CONFIG_DEBUG_FS)
static int vreg_debug_set(void *data, u64 val)
{
struct vreg *vreg = data;
switch (val) {
case 0:
vreg_disable(vreg);
break;
case 1:
vreg_enable(vreg);
break;
default:
vreg_set_level(vreg, val);
break;
}
return 0;
}
static int vreg_debug_get(void *data, u64 *val)
{
struct vreg *vreg = data;
if (!vreg->status)
*val = 0;
else
*val = 1;
return 0;
}
static int vreg_debug_count_set(void *data, u64 val)
{
struct vreg *vreg = data;
if (val > UINT_MAX)
val = UINT_MAX;
vreg->refcnt = val;
return 0;
}
static int vreg_debug_count_get(void *data, u64 *val)
{
struct vreg *vreg = data;
*val = vreg->refcnt;
return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(vreg_fops, vreg_debug_get, vreg_debug_set, "%llu\n");
DEFINE_SIMPLE_ATTRIBUTE(vreg_count_fops, vreg_debug_count_get,
vreg_debug_count_set, "%llu\n");
static int __init vreg_debug_init(void)
{
struct dentry *dent;
int n;
char name[32];
const char *refcnt_name = "_refcnt";
dent = debugfs_create_dir("vreg", 0);
if (IS_ERR(dent))
return 0;
for (n = 0; n < ARRAY_SIZE(vregs); n++) {
(void) debugfs_create_file(vregs[n].name, 0644,
dent, vregs + n, &vreg_fops);
strlcpy(name, vregs[n].name, sizeof(name));
strlcat(name, refcnt_name, sizeof(name));
(void) debugfs_create_file(name, 0644,
dent, vregs + n, &vreg_count_fops);
}
return 0;
}
device_initcall(vreg_debug_init);
#endif