mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
430
arch/arm/mach-mv78xx0/common.c
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430
arch/arm/mach-mv78xx0/common.c
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/*
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* arch/arm/mach-mv78xx0/common.c
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*
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* Core functions for Marvell MV78xx0 SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/ata_platform.h>
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#include <linux/clk-provider.h>
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#include <linux/ethtool.h>
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#include <asm/hardware/cache-feroceon-l2.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <mach/mv78xx0.h>
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#include <mach/bridge-regs.h>
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#include <linux/platform_data/usb-ehci-orion.h>
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#include <linux/platform_data/mtd-orion_nand.h>
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#include <plat/time.h>
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#include <plat/common.h>
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#include <plat/addr-map.h>
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#include "common.h"
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static int get_tclk(void);
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/*****************************************************************************
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* Common bits
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****************************************************************************/
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int mv78xx0_core_index(void)
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{
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u32 extra;
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/*
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* Read Extra Features register.
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*/
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__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
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return !!(extra & 0x00004000);
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}
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static int get_hclk(void)
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{
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int hclk;
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/*
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* HCLK tick rate is configured by DEV_D[7:5] pins.
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*/
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switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
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case 0:
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hclk = 166666667;
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break;
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case 1:
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hclk = 200000000;
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break;
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case 2:
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hclk = 266666667;
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break;
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case 3:
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hclk = 333333333;
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break;
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case 4:
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hclk = 400000000;
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break;
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default:
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panic("unknown HCLK PLL setting: %.8x\n",
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readl(SAMPLE_AT_RESET_LOW));
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}
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return hclk;
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}
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static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
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{
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u32 cfg;
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/*
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* Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
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* PCLK/L2CLK by bits [19:14].
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*/
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if (core_index == 0) {
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cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
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} else {
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cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
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}
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/*
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* Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
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* ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
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*/
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*pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
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/*
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* Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
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* ratio (1, 2, 3).
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*/
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*l2clk = *pclk / (((cfg >> 4) & 3) + 1);
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}
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static int get_tclk(void)
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{
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int tclk_freq;
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/*
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* TCLK tick rate is configured by DEV_A[2:0] strap pins.
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*/
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switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
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case 1:
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tclk_freq = 166666667;
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break;
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case 3:
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tclk_freq = 200000000;
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break;
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default:
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panic("unknown TCLK PLL setting: %.8x\n",
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readl(SAMPLE_AT_RESET_HIGH));
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}
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return tclk_freq;
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}
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/*****************************************************************************
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* I/O Address Mapping
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****************************************************************************/
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static struct map_desc mv78xx0_io_desc[] __initdata = {
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{
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.virtual = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
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.pfn = 0,
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.length = MV78XX0_CORE_REGS_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long) MV78XX0_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
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.length = MV78XX0_REGS_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init mv78xx0_map_io(void)
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{
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unsigned long phys;
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/*
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* Map the right set of per-core registers depending on
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* which core we are running on.
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*/
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if (mv78xx0_core_index() == 0) {
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phys = MV78XX0_CORE0_REGS_PHYS_BASE;
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} else {
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phys = MV78XX0_CORE1_REGS_PHYS_BASE;
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}
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mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
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iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
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}
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/*****************************************************************************
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* CLK tree
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****************************************************************************/
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static struct clk *tclk;
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static void __init clk_init(void)
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{
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tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
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get_tclk());
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orion_clkdev_init(tclk);
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}
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/*****************************************************************************
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* EHCI
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****************************************************************************/
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void __init mv78xx0_ehci0_init(void)
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{
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orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
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}
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/*****************************************************************************
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* EHCI1
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****************************************************************************/
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void __init mv78xx0_ehci1_init(void)
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{
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orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
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}
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/*****************************************************************************
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* EHCI2
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****************************************************************************/
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void __init mv78xx0_ehci2_init(void)
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{
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orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
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}
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/*****************************************************************************
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* GE00
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****************************************************************************/
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void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
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{
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orion_ge00_init(eth_data,
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GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
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IRQ_MV78XX0_GE_ERR,
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MV643XX_TX_CSUM_DEFAULT_LIMIT);
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}
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/*****************************************************************************
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* GE01
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****************************************************************************/
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void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
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{
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orion_ge01_init(eth_data,
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GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
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NO_IRQ,
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MV643XX_TX_CSUM_DEFAULT_LIMIT);
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}
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/*****************************************************************************
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* GE10
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****************************************************************************/
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void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
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{
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u32 dev, rev;
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/*
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* On the Z0, ge10 and ge11 are internally connected back
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* to back, and not brought out.
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*/
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mv78xx0_pcie_id(&dev, &rev);
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if (dev == MV78X00_Z0_DEV_ID) {
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eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
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eth_data->speed = SPEED_1000;
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eth_data->duplex = DUPLEX_FULL;
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}
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orion_ge10_init(eth_data,
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GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
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NO_IRQ);
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}
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/*****************************************************************************
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* GE11
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****************************************************************************/
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void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
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{
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u32 dev, rev;
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/*
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* On the Z0, ge10 and ge11 are internally connected back
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* to back, and not brought out.
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*/
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mv78xx0_pcie_id(&dev, &rev);
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if (dev == MV78X00_Z0_DEV_ID) {
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eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
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eth_data->speed = SPEED_1000;
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eth_data->duplex = DUPLEX_FULL;
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}
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orion_ge11_init(eth_data,
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GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
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NO_IRQ);
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}
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/*****************************************************************************
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* I2C
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****************************************************************************/
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void __init mv78xx0_i2c_init(void)
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{
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orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
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orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
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}
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/*****************************************************************************
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* SATA
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****************************************************************************/
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void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
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{
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orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
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}
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/*****************************************************************************
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* UART0
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****************************************************************************/
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void __init mv78xx0_uart0_init(void)
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{
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orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
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IRQ_MV78XX0_UART_0, tclk);
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}
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/*****************************************************************************
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* UART1
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****************************************************************************/
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void __init mv78xx0_uart1_init(void)
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{
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orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
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IRQ_MV78XX0_UART_1, tclk);
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}
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/*****************************************************************************
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* UART2
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****************************************************************************/
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void __init mv78xx0_uart2_init(void)
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{
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orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
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IRQ_MV78XX0_UART_2, tclk);
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}
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/*****************************************************************************
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* UART3
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****************************************************************************/
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void __init mv78xx0_uart3_init(void)
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{
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orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
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IRQ_MV78XX0_UART_3, tclk);
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}
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/*****************************************************************************
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* Time handling
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****************************************************************************/
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void __init mv78xx0_init_early(void)
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{
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orion_time_set_base(TIMER_VIRT_BASE);
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if (mv78xx0_core_index() == 0)
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mvebu_mbus_init("marvell,mv78xx0-mbus",
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BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ,
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DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ);
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else
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mvebu_mbus_init("marvell,mv78xx0-mbus",
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BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ,
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DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ);
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}
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void __init_refok mv78xx0_timer_init(void)
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{
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orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
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IRQ_MV78XX0_TIMER_1, get_tclk());
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}
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/*****************************************************************************
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* General
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****************************************************************************/
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static char * __init mv78xx0_id(void)
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{
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u32 dev, rev;
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mv78xx0_pcie_id(&dev, &rev);
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if (dev == MV78X00_Z0_DEV_ID) {
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if (rev == MV78X00_REV_Z0)
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return "MV78X00-Z0";
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else
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return "MV78X00-Rev-Unsupported";
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} else if (dev == MV78100_DEV_ID) {
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if (rev == MV78100_REV_A0)
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return "MV78100-A0";
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else if (rev == MV78100_REV_A1)
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return "MV78100-A1";
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else
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return "MV78100-Rev-Unsupported";
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} else if (dev == MV78200_DEV_ID) {
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if (rev == MV78100_REV_A0)
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return "MV78200-A0";
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else
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return "MV78200-Rev-Unsupported";
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} else {
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return "Device-Unknown";
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}
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}
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static int __init is_l2_writethrough(void)
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{
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return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
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}
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void __init mv78xx0_init(void)
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{
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int core_index;
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int hclk;
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int pclk;
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int l2clk;
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core_index = mv78xx0_core_index();
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hclk = get_hclk();
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get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
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printk(KERN_INFO "%s ", mv78xx0_id());
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printk("core #%d, ", core_index);
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printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
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printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
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printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
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printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
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#ifdef CONFIG_CACHE_FEROCEON_L2
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feroceon_l2_init(is_l2_writethrough());
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#endif
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/* Setup root of clk tree */
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clk_init();
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}
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void mv78xx0_restart(enum reboot_mode mode, const char *cmd)
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{
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/*
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* Enable soft reset to assert RSTOUTn.
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*/
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writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
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/*
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* Assert soft reset.
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*/
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writel(SOFT_RESET, SYSTEM_SOFT_RESET);
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while (1)
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;
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}
|
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