mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 09:22:44 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
37
arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
Normal file
37
arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
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@ -0,0 +1,37 @@
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/*
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* arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_BRIDGE_REGS_H
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#define __ASM_ARCH_BRIDGE_REGS_H
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#include <mach/mv78xx0.h>
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#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
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#define L2_WRITETHROUGH 0x00020000
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
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#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
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#define SOFT_RESET 0x00000001
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
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#define IRQ_CAUSE_ERR_OFF 0x0000
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#define IRQ_CAUSE_LOW_OFF 0x0004
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#define IRQ_CAUSE_HIGH_OFF 0x0008
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#define IRQ_MASK_ERR_OFF 0x000c
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#define IRQ_MASK_LOW_OFF 0x0010
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#define IRQ_MASK_HIGH_OFF 0x0014
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
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#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
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#endif
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41
arch/arm/mach-mv78xx0/include/mach/entry-macro.S
Normal file
41
arch/arm/mach-mv78xx0/include/mach/entry-macro.S
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@ -0,0 +1,41 @@
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/*
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* arch/arm/mach-mv78xx0/include/mach/entry-macro.S
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*
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* Low-level IRQ helper macros for Marvell MV78xx0 platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/bridge-regs.h>
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =IRQ_VIRT_BASE
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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@ check low interrupts
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ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
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ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
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mov \irqnr, #31
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ands \irqstat, \irqstat, \tmp
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bne 1001f
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@ if no low interrupts set, check high interrupts
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ldr \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
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ldr \tmp, [\base, #IRQ_MASK_HIGH_OFF]
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mov \irqnr, #63
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ands \irqstat, \irqstat, \tmp
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bne 1001f
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@ if no high interrupts set, check error interrupts
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ldr \irqstat, [\base, #IRQ_CAUSE_ERR_OFF]
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ldr \tmp, [\base, #IRQ_MASK_ERR_OFF]
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mov \irqnr, #95
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ands \irqstat, \irqstat, \tmp
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@ find first active interrupt source
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1001: clzne \irqstat, \irqstat
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subne \irqnr, \irqnr, \irqstat
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.endm
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14
arch/arm/mach-mv78xx0/include/mach/hardware.h
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14
arch/arm/mach-mv78xx0/include/mach/hardware.h
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@ -0,0 +1,14 @@
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/*
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* arch/arm/mach-mv78xx0/include/mach/hardware.h
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include "mv78xx0.h"
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#endif
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94
arch/arm/mach-mv78xx0/include/mach/irqs.h
Normal file
94
arch/arm/mach-mv78xx0/include/mach/irqs.h
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@ -0,0 +1,94 @@
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/*
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* arch/arm/mach-mv78xx0/include/mach/irqs.h
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*
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* IRQ definitions for Marvell MV78xx0 SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_IRQS_H
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#define __ASM_ARCH_IRQS_H
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/*
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* MV78xx0 Low Interrupt Controller
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*/
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#define IRQ_MV78XX0_ERR 0
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#define IRQ_MV78XX0_SPI 1
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#define IRQ_MV78XX0_I2C_0 2
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#define IRQ_MV78XX0_I2C_1 3
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#define IRQ_MV78XX0_IDMA_0 4
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#define IRQ_MV78XX0_IDMA_1 5
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#define IRQ_MV78XX0_IDMA_2 6
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#define IRQ_MV78XX0_IDMA_3 7
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#define IRQ_MV78XX0_TIMER_0 8
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#define IRQ_MV78XX0_TIMER_1 9
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#define IRQ_MV78XX0_TIMER_2 10
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#define IRQ_MV78XX0_TIMER_3 11
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#define IRQ_MV78XX0_UART_0 12
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#define IRQ_MV78XX0_UART_1 13
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#define IRQ_MV78XX0_UART_2 14
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#define IRQ_MV78XX0_UART_3 15
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#define IRQ_MV78XX0_USB_0 16
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#define IRQ_MV78XX0_USB_1 17
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#define IRQ_MV78XX0_USB_2 18
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#define IRQ_MV78XX0_CRYPTO 19
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#define IRQ_MV78XX0_SDIO_0 20
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#define IRQ_MV78XX0_SDIO_1 21
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#define IRQ_MV78XX0_XOR_0 22
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#define IRQ_MV78XX0_XOR_1 23
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#define IRQ_MV78XX0_I2S_0 24
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#define IRQ_MV78XX0_I2S_1 25
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#define IRQ_MV78XX0_SATA 26
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#define IRQ_MV78XX0_TDMI 27
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/*
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* MV78xx0 High Interrupt Controller
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*/
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#define IRQ_MV78XX0_PCIE_00 32
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#define IRQ_MV78XX0_PCIE_01 33
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#define IRQ_MV78XX0_PCIE_02 34
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#define IRQ_MV78XX0_PCIE_03 35
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#define IRQ_MV78XX0_PCIE_10 36
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#define IRQ_MV78XX0_PCIE_11 37
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#define IRQ_MV78XX0_PCIE_12 38
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#define IRQ_MV78XX0_PCIE_13 39
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#define IRQ_MV78XX0_GE00_SUM 40
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#define IRQ_MV78XX0_GE00_RX 41
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#define IRQ_MV78XX0_GE00_TX 42
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#define IRQ_MV78XX0_GE00_MISC 43
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#define IRQ_MV78XX0_GE01_SUM 44
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#define IRQ_MV78XX0_GE01_RX 45
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#define IRQ_MV78XX0_GE01_TX 46
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#define IRQ_MV78XX0_GE01_MISC 47
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#define IRQ_MV78XX0_GE10_SUM 48
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#define IRQ_MV78XX0_GE10_RX 49
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#define IRQ_MV78XX0_GE10_TX 50
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#define IRQ_MV78XX0_GE10_MISC 51
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#define IRQ_MV78XX0_GE11_SUM 52
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#define IRQ_MV78XX0_GE11_RX 53
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#define IRQ_MV78XX0_GE11_TX 54
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#define IRQ_MV78XX0_GE11_MISC 55
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#define IRQ_MV78XX0_GPIO_0_7 56
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#define IRQ_MV78XX0_GPIO_8_15 57
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#define IRQ_MV78XX0_GPIO_16_23 58
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#define IRQ_MV78XX0_GPIO_24_31 59
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#define IRQ_MV78XX0_DB_IN 60
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#define IRQ_MV78XX0_DB_OUT 61
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/*
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* MV78xx0 Error Interrupt Controller
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*/
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#define IRQ_MV78XX0_GE_ERR 70
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/*
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* MV78XX0 General Purpose Pins
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*/
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#define IRQ_MV78XX0_GPIO_START 96
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#define NR_GPIO_IRQS 32
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#define NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
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#endif
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127
arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
Normal file
127
arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
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@ -0,0 +1,127 @@
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/*
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* arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
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*
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* Generic definitions for Marvell MV78xx0 SoC flavors:
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* MV781x0 and MV782x0.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_MV78XX0_H
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#define __ASM_ARCH_MV78XX0_H
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/*
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* Marvell MV78xx0 address maps.
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*
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* phys
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* c0000000 PCIe Memory space
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* f0800000 PCIe #0 I/O space
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* f0900000 PCIe #1 I/O space
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* f0a00000 PCIe #2 I/O space
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* f0b00000 PCIe #3 I/O space
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* f0c00000 PCIe #4 I/O space
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* f0d00000 PCIe #5 I/O space
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* f0e00000 PCIe #6 I/O space
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* f0f00000 PCIe #7 I/O space
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* f1000000 on-chip peripheral registers
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*
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* virt phys size
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* fe400000 f102x000 16K core-specific peripheral registers
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* fee00000 f0800000 64K PCIe #0 I/O space
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* fee10000 f0900000 64K PCIe #1 I/O space
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* fee20000 f0a00000 64K PCIe #2 I/O space
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* fee30000 f0b00000 64K PCIe #3 I/O space
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* fee40000 f0c00000 64K PCIe #4 I/O space
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* fee50000 f0d00000 64K PCIe #5 I/O space
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* fee60000 f0e00000 64K PCIe #6 I/O space
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* fee70000 f0f00000 64K PCIe #7 I/O space
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* fd000000 f1000000 1M on-chip peripheral registers
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*/
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#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
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#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
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#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
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#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
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#define MV78XX0_CORE_REGS_SIZE SZ_16K
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#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
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#define MV78XX0_PCIE_IO_SIZE SZ_1M
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#define MV78XX0_REGS_PHYS_BASE 0xf1000000
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#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000)
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#define MV78XX0_REGS_SIZE SZ_1M
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#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
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#define MV78XX0_PCIE_MEM_SIZE 0x30000000
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/*
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* Core-specific peripheral registers.
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*/
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#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
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#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE)
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#define BRIDGE_WINS_CPU0_BASE (MV78XX0_CORE0_REGS_PHYS_BASE)
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#define BRIDGE_WINS_CPU1_BASE (MV78XX0_CORE1_REGS_PHYS_BASE)
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#define BRIDGE_WINS_SZ (0xA000)
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/*
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* Register Map
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*/
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#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000)
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#define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000)
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#define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500)
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#define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570)
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#define DDR_WINDOW_CPU_SZ (0x20)
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#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000)
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#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000)
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#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030)
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#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034)
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#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
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#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
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#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100)
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#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
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#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
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#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
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#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
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#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200)
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#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200)
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#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300)
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#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300)
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#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000)
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#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000)
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#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000)
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#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000)
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#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000)
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#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000)
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#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000)
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#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000)
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#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000)
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#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000)
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#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000)
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#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000)
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#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000)
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#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000)
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#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000)
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#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000)
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/*
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* Supported devices and revisions.
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*/
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#define MV78X00_Z0_DEV_ID 0x6381
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#define MV78X00_REV_Z0 1
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#define MV78100_DEV_ID 0x7810
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#define MV78100_REV_A0 1
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#define MV78100_REV_A1 2
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#define MV78200_DEV_ID 0x7820
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#define MV78200_REV_A0 1
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#endif
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46
arch/arm/mach-mv78xx0/include/mach/uncompress.h
Normal file
46
arch/arm/mach-mv78xx0/include/mach/uncompress.h
Normal file
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@ -0,0 +1,46 @@
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/*
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||||
* arch/arm/mach-mv78xx0/include/mach/uncompress.h
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||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
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#include <linux/serial_reg.h>
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#include <mach/mv78xx0.h>
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#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
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static void putc(const char c)
|
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{
|
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unsigned char *base = SERIAL_BASE;
|
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int i;
|
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|
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for (i = 0; i < 0x1000; i++) {
|
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if (base[UART_LSR << 2] & UART_LSR_THRE)
|
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break;
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barrier();
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}
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base[UART_TX << 2] = c;
|
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}
|
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static void flush(void)
|
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{
|
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unsigned char *base = SERIAL_BASE;
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unsigned char mask;
|
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int i;
|
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|
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mask = UART_LSR_TEMT | UART_LSR_THRE;
|
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|
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for (i = 0; i < 0x1000; i++) {
|
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if ((base[UART_LSR << 2] & mask) == mask)
|
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break;
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barrier();
|
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}
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}
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|
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/*
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||||
* nothing to do
|
||||
*/
|
||||
#define arch_decomp_setup()
|
||||
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