mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 09:22:44 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
37
arch/arm/mach-orion5x/include/mach/bridge-regs.h
Normal file
37
arch/arm/mach-orion5x/include/mach/bridge-regs.h
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@ -0,0 +1,37 @@
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/*
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* arch/arm/mach-orion5x/include/mach/bridge-regs.h
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*
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* Orion CPU Bridge Registers
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_BRIDGE_REGS_H
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#define __ASM_ARCH_BRIDGE_REGS_H
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#include <mach/orion5x.h>
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#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
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#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
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#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
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#define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
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#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
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#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
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#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
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#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
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#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300)
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#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300)
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#endif
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25
arch/arm/mach-orion5x/include/mach/entry-macro.S
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25
arch/arm/mach-orion5x/include/mach/entry-macro.S
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/*
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* arch/arm/mach-orion5x/include/mach/entry-macro.S
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*
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* Low-level IRQ helper macros for Orion platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/bridge-regs.h>
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =MAIN_IRQ_CAUSE
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqstat, [\base, #0] @ main cause
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ldr \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask
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mov \irqnr, #0 @ default irqnr
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@ find cause bits that are unmasked
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ands \irqstat, \irqstat, \tmp @ clear Z flag if any
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clzne \irqnr, \irqstat @ calc irqnr
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rsbne \irqnr, \irqnr, #31
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.endm
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14
arch/arm/mach-orion5x/include/mach/hardware.h
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14
arch/arm/mach-orion5x/include/mach/hardware.h
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/*
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* arch/arm/mach-orion5x/include/mach/hardware.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include "orion5x.h"
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#endif
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60
arch/arm/mach-orion5x/include/mach/irqs.h
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60
arch/arm/mach-orion5x/include/mach/irqs.h
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/*
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* arch/arm/mach-orion5x/include/mach/irqs.h
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*
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* IRQ definitions for Orion SoC
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_IRQS_H
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#define __ASM_ARCH_IRQS_H
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/*
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* Orion Main Interrupt Controller
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*/
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#define IRQ_ORION5X_BRIDGE 0
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#define IRQ_ORION5X_DOORBELL_H2C 1
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#define IRQ_ORION5X_DOORBELL_C2H 2
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#define IRQ_ORION5X_UART0 3
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#define IRQ_ORION5X_UART1 4
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#define IRQ_ORION5X_I2C 5
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#define IRQ_ORION5X_GPIO_0_7 6
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#define IRQ_ORION5X_GPIO_8_15 7
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#define IRQ_ORION5X_GPIO_16_23 8
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#define IRQ_ORION5X_GPIO_24_31 9
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#define IRQ_ORION5X_PCIE0_ERR 10
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#define IRQ_ORION5X_PCIE0_INT 11
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#define IRQ_ORION5X_USB1_CTRL 12
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#define IRQ_ORION5X_DEV_BUS_ERR 14
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#define IRQ_ORION5X_PCI_ERR 15
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#define IRQ_ORION5X_USB_BR_ERR 16
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#define IRQ_ORION5X_USB0_CTRL 17
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#define IRQ_ORION5X_ETH_RX 18
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#define IRQ_ORION5X_ETH_TX 19
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#define IRQ_ORION5X_ETH_MISC 20
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#define IRQ_ORION5X_ETH_SUM 21
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#define IRQ_ORION5X_ETH_ERR 22
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#define IRQ_ORION5X_IDMA_ERR 23
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#define IRQ_ORION5X_IDMA_0 24
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#define IRQ_ORION5X_IDMA_1 25
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#define IRQ_ORION5X_IDMA_2 26
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#define IRQ_ORION5X_IDMA_3 27
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#define IRQ_ORION5X_CESA 28
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#define IRQ_ORION5X_SATA 29
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#define IRQ_ORION5X_XOR0 30
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#define IRQ_ORION5X_XOR1 31
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/*
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* Orion General Purpose Pins
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*/
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#define IRQ_ORION5X_GPIO_START 32
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#define NR_GPIO_IRQS 32
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#define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)
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#endif
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146
arch/arm/mach-orion5x/include/mach/orion5x.h
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146
arch/arm/mach-orion5x/include/mach/orion5x.h
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/*
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* arch/arm/mach-orion5x/include/mach/orion5x.h
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*
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* Generic definitions of Orion SoC flavors:
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* Orion-1, Orion-VoIP, Orion-NAS, Orion-2, and Orion-1-90.
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_ORION5X_H
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#define __ASM_ARCH_ORION5X_H
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/*****************************************************************************
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* Orion Address Maps
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*
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* phys
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* e0000000 PCIe MEM space
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* e8000000 PCI MEM space
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* f0000000 PCIe WA space (Orion-1/Orion-NAS only)
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* f1000000 on-chip peripheral registers
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* f2000000 PCIe I/O space
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* f2100000 PCI I/O space
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* f2200000 SRAM dedicated for the crypto unit
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* f4000000 device bus mappings (boot)
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* fa000000 device bus mappings (cs0)
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* fa800000 device bus mappings (cs2)
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* fc000000 device bus mappings (cs0/cs1)
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*
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* virt phys size
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* fe000000 f1000000 1M on-chip peripheral registers
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* fee00000 f2000000 64K PCIe I/O space
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* fee10000 f2100000 64K PCI I/O space
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* fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
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****************************************************************************/
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#define ORION5X_REGS_PHYS_BASE 0xf1000000
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#define ORION5X_REGS_VIRT_BASE IOMEM(0xfe000000)
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#define ORION5X_REGS_SIZE SZ_1M
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#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
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#define ORION5X_PCIE_IO_BUS_BASE 0x00000000
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#define ORION5X_PCIE_IO_SIZE SZ_64K
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#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
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#define ORION5X_PCI_IO_BUS_BASE 0x00010000
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#define ORION5X_PCI_IO_SIZE SZ_64K
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#define ORION5X_SRAM_PHYS_BASE (0xf2200000)
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#define ORION5X_SRAM_SIZE SZ_8K
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/* Relevant only for Orion-1/Orion-NAS */
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#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
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#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
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#define ORION5X_PCIE_WA_SIZE SZ_16M
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#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
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#define ORION5X_PCIE_MEM_SIZE SZ_128M
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#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000
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#define ORION5X_PCI_MEM_SIZE SZ_128M
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/*******************************************************************************
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* Orion Registers Map
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******************************************************************************/
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#define ORION5X_DDR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x00000)
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#define ORION5X_DDR_WINS_BASE (ORION5X_DDR_PHYS_BASE + 0x1500)
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#define ORION5X_DDR_WINS_SZ (0x10)
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#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000)
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#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000)
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#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000)
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#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x))
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#define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100)
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#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x0600)
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#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x1000)
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#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2000)
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#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2000)
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#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2100)
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#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2100)
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#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000)
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#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000)
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#define ORION5X_BRIDGE_WINS_BASE (ORION5X_BRIDGE_PHYS_BASE)
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#define ORION5X_BRIDGE_WINS_SZ (0x80)
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#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000)
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#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x40000)
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#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x50000)
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#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x50000)
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#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x60900)
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#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x60900)
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#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x70000)
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#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x70000)
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#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x80000)
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#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x80000)
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#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x90000)
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#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0xa0000)
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#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0xa0000)
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/*******************************************************************************
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* Device Bus Registers
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******************************************************************************/
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#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000)
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#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004)
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#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050)
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#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008)
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#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010)
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#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c)
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#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460)
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#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464)
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#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c)
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#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0)
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#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0)
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#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4)
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/*******************************************************************************
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* Supported Devices & Revisions
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******************************************************************************/
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/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
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#define MV88F5181_DEV_ID 0x5181
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#define MV88F5181_REV_B1 3
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#define MV88F5181L_REV_A0 8
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#define MV88F5181L_REV_A1 9
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/* Orion-NAS (88F5182) */
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#define MV88F5182_DEV_ID 0x5182
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#define MV88F5182_REV_A2 2
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/* Orion-2 (88F5281) */
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#define MV88F5281_DEV_ID 0x5281
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#define MV88F5281_REV_D0 4
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#define MV88F5281_REV_D1 5
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#define MV88F5281_REV_D2 6
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/* Orion-1-90 (88F6183) */
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#define MV88F6183_DEV_ID 0x6183
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#define MV88F6183_REV_B0 3
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#endif
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48
arch/arm/mach-orion5x/include/mach/uncompress.h
Normal file
48
arch/arm/mach-orion5x/include/mach/uncompress.h
Normal file
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@ -0,0 +1,48 @@
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/*
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* arch/arm/mach-orion5x/include/mach/uncompress.h
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*
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* Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
|
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/serial_reg.h>
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#include <mach/orion5x.h>
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#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
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static void putc(const char c)
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{
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unsigned char *base = SERIAL_BASE;
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int i;
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for (i = 0; i < 0x1000; i++) {
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if (base[UART_LSR << 2] & UART_LSR_THRE)
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break;
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barrier();
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}
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base[UART_TX << 2] = c;
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}
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static void flush(void)
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{
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unsigned char *base = SERIAL_BASE;
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unsigned char mask;
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int i;
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mask = UART_LSR_TEMT | UART_LSR_THRE;
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for (i = 0; i < 0x1000; i++) {
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if ((base[UART_LSR << 2] & mask) == mask)
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break;
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barrier();
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}
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}
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/*
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* nothing to do
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||||
*/
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||||
#define arch_decomp_setup()
|
||||
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