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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
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214
arch/arm/mach-s3c24xx/include/mach/dma.h Normal file
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/* arch/arm/mach-s3c2410/include/mach/dma.h
*
* Copyright (C) 2003-2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Samsung S3C24XX DMA support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H __FILE__
#include <linux/device.h>
#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
/* We use `virtual` dma channels to hide the fact we have only a limited
* number of DMA channels, and not of all of them (dependent on the device)
* can be attached to any DMA source. We therefore let the DMA core handle
* the allocation of hardware channels to clients.
*/
enum dma_ch {
DMACH_XD0 = 0,
DMACH_XD1,
DMACH_SDI,
DMACH_SPI0,
DMACH_SPI1,
DMACH_UART0,
DMACH_UART1,
DMACH_UART2,
DMACH_TIMER,
DMACH_I2S_IN,
DMACH_I2S_OUT,
DMACH_PCM_IN,
DMACH_PCM_OUT,
DMACH_MIC_IN,
DMACH_USB_EP1,
DMACH_USB_EP2,
DMACH_USB_EP3,
DMACH_USB_EP4,
DMACH_UART0_SRC2, /* s3c2412 second uart sources */
DMACH_UART1_SRC2,
DMACH_UART2_SRC2,
DMACH_UART3, /* s3c2443 has extra uart */
DMACH_UART3_SRC2,
DMACH_SPI0_TX, /* s3c2443/2416/2450 hsspi0 */
DMACH_SPI0_RX, /* s3c2443/2416/2450 hsspi0 */
DMACH_SPI1_TX, /* s3c2443/2450 hsspi1 */
DMACH_SPI1_RX, /* s3c2443/2450 hsspi1 */
DMACH_MAX, /* the end entry */
};
static inline bool samsung_dma_has_circular(void)
{
return false;
}
static inline bool samsung_dma_is_dmadev(void)
{
return false;
}
#include <plat/dma.h>
#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
/* we have 4 dma channels */
#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
#define S3C_DMA_CHANNELS (4)
#else
#define S3C_DMA_CHANNELS (6)
#endif
/* types */
enum s3c2410_dma_state {
S3C2410_DMA_IDLE,
S3C2410_DMA_RUNNING,
S3C2410_DMA_PAUSED
};
/* enum s3c2410_dma_loadst
*
* This represents the state of the DMA engine, wrt to the loaded / running
* transfers. Since we don't have any way of knowing exactly the state of
* the DMA transfers, we need to know the state to make decisions on whether
* we can
*
* S3C2410_DMA_NONE
*
* There are no buffers loaded (the channel should be inactive)
*
* S3C2410_DMA_1LOADED
*
* There is one buffer loaded, however it has not been confirmed to be
* loaded by the DMA engine. This may be because the channel is not
* yet running, or the DMA driver decided that it was too costly to
* sit and wait for it to happen.
*
* S3C2410_DMA_1RUNNING
*
* The buffer has been confirmed running, and not finisged
*
* S3C2410_DMA_1LOADED_1RUNNING
*
* There is a buffer waiting to be loaded by the DMA engine, and one
* currently running.
*/
enum s3c2410_dma_loadst {
S3C2410_DMALOAD_NONE,
S3C2410_DMALOAD_1LOADED,
S3C2410_DMALOAD_1RUNNING,
S3C2410_DMALOAD_1LOADED_1RUNNING,
};
/* flags */
#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
* waiting for reloads */
#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
#define S3C2410_DMAF_CIRCULAR (1 << 2) /* no circular dma support */
/* dma buffer */
struct s3c2410_dma_buf;
/* s3c2410_dma_buf
*
* internally used buffer structure to describe a queued or running
* buffer.
*/
struct s3c2410_dma_buf {
struct s3c2410_dma_buf *next;
int magic; /* magic */
int size; /* buffer size in bytes */
dma_addr_t data; /* start of DMA data */
dma_addr_t ptr; /* where the DMA got to [1] */
void *id; /* client's id */
};
/* [1] is this updated for both recv/send modes? */
struct s3c2410_dma_stats {
unsigned long loads;
unsigned long timeout_longest;
unsigned long timeout_shortest;
unsigned long timeout_avg;
unsigned long timeout_failed;
};
struct s3c2410_dma_map;
/* struct s3c2410_dma_chan
*
* full state information for each DMA channel
*/
struct s3c2410_dma_chan {
/* channel state flags and information */
unsigned char number; /* number of this dma channel */
unsigned char in_use; /* channel allocated */
unsigned char irq_claimed; /* irq claimed for channel */
unsigned char irq_enabled; /* irq enabled for channel */
unsigned char xfer_unit; /* size of an transfer */
/* channel state */
enum s3c2410_dma_state state;
enum s3c2410_dma_loadst load_state;
struct s3c2410_dma_client *client;
/* channel configuration */
enum dma_data_direction source;
enum dma_ch req_ch;
unsigned long dev_addr;
unsigned long load_timeout;
unsigned int flags; /* channel flags */
struct s3c24xx_dma_map *map; /* channel hw maps */
/* channel's hardware position and configuration */
void __iomem *regs; /* channels registers */
void __iomem *addr_reg; /* data address register */
unsigned int irq; /* channel irq */
unsigned long dcon; /* default value of DCON */
/* driver handles */
s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
s3c2410_dma_opfn_t op_fn; /* channel op callback */
/* stats gathering */
struct s3c2410_dma_stats *stats;
struct s3c2410_dma_stats stats_store;
/* buffer list and information */
struct s3c2410_dma_buf *curr; /* current dma buffer */
struct s3c2410_dma_buf *next; /* next buffer to load */
struct s3c2410_dma_buf *end; /* end of queue */
/* system device */
struct device dev;
};
typedef unsigned long dma_device_t;
#endif /* __ASM_ARCH_DMA_H */

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arch/arm/mach-s3c24xx/include/mach/fb.h Normal file
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#include <plat/fb-s3c2410.h>

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arch/arm/mach-s3c24xx/include/mach/gpio-samsung.h Normal file
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/*
* Copyright (c) 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - GPIO lib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* some boards require extra gpio capacity to support external
* devices that need GPIO.
*/
#ifndef GPIO_SAMSUNG_S3C24XX_H
#define GPIO_SAMSUNG_S3C24XX_H
/*
* GPIO sizes for various SoCs:
*
* 2410 2412 2440 2443 2416
* 2442
* ---- ---- ---- ---- ----
* A 23 22 25 16 27
* B 11 11 11 11 11
* C 16 16 16 16 16
* D 16 16 16 16 16
* E 16 16 16 16 16
* F 8 8 8 8 8
* G 16 16 16 16 8
* H 11 11 11 15 15
* J -- -- 13 16 --
* K -- -- -- -- 16
* L -- -- -- 15 14
* M -- -- -- 2 2
*/
/* GPIO bank sizes */
#define S3C2410_GPIO_A_NR (32)
#define S3C2410_GPIO_B_NR (32)
#define S3C2410_GPIO_C_NR (32)
#define S3C2410_GPIO_D_NR (32)
#define S3C2410_GPIO_E_NR (32)
#define S3C2410_GPIO_F_NR (32)
#define S3C2410_GPIO_G_NR (32)
#define S3C2410_GPIO_H_NR (32)
#define S3C2410_GPIO_J_NR (32) /* technically 16. */
#define S3C2410_GPIO_K_NR (32) /* technically 16. */
#define S3C2410_GPIO_L_NR (32) /* technically 15. */
#define S3C2410_GPIO_M_NR (32) /* technically 2. */
#if CONFIG_S3C_GPIO_SPACE != 0
#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment
#endif
#define S3C2410_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
#ifndef __ASSEMBLY__
enum s3c_gpio_number {
S3C2410_GPIO_A_START = 0,
S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H),
S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J),
S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K),
S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L),
};
#endif /* __ASSEMBLY__ */
/* S3C2410 GPIO number definitions. */
#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr))
#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr))
#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr))
#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr))
#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr))
#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr))
#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr))
#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr))
#define S3C2410_GPJ(_nr) (S3C2410_GPIO_J_START + (_nr))
#define S3C2410_GPK(_nr) (S3C2410_GPIO_K_START + (_nr))
#define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr))
#define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr))
#ifdef CONFIG_CPU_S3C244X
#define S3C_GPIO_END (S3C2410_GPJ(0) + 32)
#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
#define S3C_GPIO_END (S3C2410_GPM(0) + 32)
#else
#define S3C_GPIO_END (S3C2410_GPH(0) + 32)
#endif
#endif /* GPIO_SAMSUNG_S3C24XX_H */

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arch/arm/mach-s3c24xx/include/mach/hardware.h Normal file
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/*
* Copyright (c) 2003 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - hardware
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#ifndef __ASSEMBLY__
extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
#endif /* __ASSEMBLY__ */
#include <asm/sizes.h>
#include <mach/map.h>
#endif /* __ASM_ARCH_HARDWARE_H */

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arch/arm/mach-s3c24xx/include/mach/io.h Normal file
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/*
* arch/arm/mach-s3c2410/include/mach/io.h
* from arch/arm/mach-rpc/include/mach/io.h
*
* Copyright (C) 1997 Russell King
* (C) 2003 Simtec Electronics
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <mach/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
* We use two different types of addressing - PC style addresses, and ARM
* addresses. PC style accesses the PC hardware with the normal PC IO
* addresses, eg 0x3f8 for serial#1. ARM addresses are above A28
* and are translated to the start of IO. Note that all addresses are
* not shifted left!
*/
#define __PORT_PCIO(x) ((x) < (1<<28))
#define PCIO_BASE (S3C24XX_VA_ISA_WORD)
#define PCIO_BASE_b (S3C24XX_VA_ISA_BYTE)
#define PCIO_BASE_w (S3C24XX_VA_ISA_WORD)
#define PCIO_BASE_l (S3C24XX_VA_ISA_WORD)
/*
* Dynamic IO functions - let the compiler
* optimize the expressions
*/
#define DECLARE_DYN_OUT(sz,fnsuffix,instr) \
static inline void __out##fnsuffix (unsigned int val, unsigned int port) \
{ \
unsigned long temp; \
__asm__ __volatile__( \
"cmp %2, #(1<<28)\n\t" \
"mov %0, %2\n\t" \
"addcc %0, %0, %3\n\t" \
"str" instr " %1, [%0, #0 ] @ out" #fnsuffix \
: "=&r" (temp) \
: "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \
: "cc"); \
}
#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
static inline unsigned sz __in##fnsuffix (unsigned int port) \
{ \
unsigned long temp, value; \
__asm__ __volatile__( \
"cmp %2, #(1<<28)\n\t" \
"mov %0, %2\n\t" \
"addcc %0, %0, %3\n\t" \
"ldr" instr " %1, [%0, #0 ] @ in" #fnsuffix \
: "=&r" (temp), "=r" (value) \
: "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \
: "cc"); \
return (unsigned sz)value; \
}
static inline void __iomem *__ioaddr (unsigned long port)
{
return __PORT_PCIO(port) ? (PCIO_BASE + port) : (void __iomem *)port;
}
#define DECLARE_IO(sz,fnsuffix,instr) \
DECLARE_DYN_IN(sz,fnsuffix,instr) \
DECLARE_DYN_OUT(sz,fnsuffix,instr)
DECLARE_IO(char,b,"b")
DECLARE_IO(short,w,"h")
DECLARE_IO(int,l,"")
#undef DECLARE_IO
#undef DECLARE_DYN_IN
/*
* Constant address IO functions
*
* These have to be macros for the 'J' constraint to work -
* +/-4096 immediate operand.
*/
#define __outbc(value,port) \
({ \
if (__PORT_PCIO((port))) \
__asm__ __volatile__( \
"strb %0, [%1, %2] @ outbc" \
: : "r" (value), "r" (PCIO_BASE), "Jr" ((port))); \
else \
__asm__ __volatile__( \
"strb %0, [%1, #0] @ outbc" \
: : "r" (value), "r" ((port))); \
})
#define __inbc(port) \
({ \
unsigned char result; \
if (__PORT_PCIO((port))) \
__asm__ __volatile__( \
"ldrb %0, [%1, %2] @ inbc" \
: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
else \
__asm__ __volatile__( \
"ldrb %0, [%1, #0] @ inbc" \
: "=r" (result) : "r" ((port))); \
result; \
})
#define __outwc(value,port) \
({ \
unsigned long v = value; \
if (__PORT_PCIO((port))) { \
if ((port) < 256 && (port) > -256) \
__asm__ __volatile__( \
"strh %0, [%1, %2] @ outwc" \
: : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
else if ((port) > 0) \
__asm__ __volatile__( \
"strh %0, [%1, %2] @ outwc" \
: : "r" (v), \
"r" (PCIO_BASE + ((port) & ~0xff)), \
"Jr" (((port) & 0xff))); \
else \
__asm__ __volatile__( \
"strh %0, [%1, #0] @ outwc" \
: : "r" (v), \
"r" (PCIO_BASE + (port))); \
} else \
__asm__ __volatile__( \
"strh %0, [%1, #0] @ outwc" \
: : "r" (v), "r" ((port))); \
})
#define __inwc(port) \
({ \
unsigned short result; \
if (__PORT_PCIO((port))) { \
if ((port) < 256 && (port) > -256 ) \
__asm__ __volatile__( \
"ldrh %0, [%1, %2] @ inwc" \
: "=r" (result) \
: "r" (PCIO_BASE), \
"Jr" ((port))); \
else if ((port) > 0) \
__asm__ __volatile__( \
"ldrh %0, [%1, %2] @ inwc" \
: "=r" (result) \
: "r" (PCIO_BASE + ((port) & ~0xff)), \
"Jr" (((port) & 0xff))); \
else \
__asm__ __volatile__( \
"ldrh %0, [%1, #0] @ inwc" \
: "=r" (result) \
: "r" (PCIO_BASE + ((port)))); \
} else \
__asm__ __volatile__( \
"ldrh %0, [%1, #0] @ inwc" \
: "=r" (result) : "r" ((port))); \
result; \
})
#define __outlc(value,port) \
({ \
unsigned long v = value; \
if (__PORT_PCIO((port))) \
__asm__ __volatile__( \
"str %0, [%1, %2] @ outlc" \
: : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
else \
__asm__ __volatile__( \
"str %0, [%1, #0] @ outlc" \
: : "r" (v), "r" ((port))); \
})
#define __inlc(port) \
({ \
unsigned long result; \
if (__PORT_PCIO((port))) \
__asm__ __volatile__( \
"ldr %0, [%1, %2] @ inlc" \
: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
else \
__asm__ __volatile__( \
"ldr %0, [%1, #0] @ inlc" \
: "=r" (result) : "r" ((port))); \
result; \
})
#define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)(port)))
#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p))
#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p))
#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l)
#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l)
#define insl(p,d,l) __raw_readsl(__ioaddr(p),d,l)
#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l)
#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l)
#define outsl(p,d,l) __raw_writesl(__ioaddr(p),d,l)
#endif

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arch/arm/mach-s3c24xx/include/mach/irqs.h Normal file
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/* arch/arm/mach-s3c2410/include/mach/irqs.h
*
* Copyright (c) 2003-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H __FILE__
/* we keep the first set of CPU IRQs out of the range of
* the ISA space, so that the PC104 has them to itself
* and we don't end up having to do horrible things to the
* standard ISA drivers....
*/
#define S3C2410_CPUIRQ_OFFSET (16)
#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET)
/* main cpu interrupts */
#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */
#define IRQ_EINT1 S3C2410_IRQ(1)
#define IRQ_EINT2 S3C2410_IRQ(2)
#define IRQ_EINT3 S3C2410_IRQ(3)
#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */
#define IRQ_EINT8t23 S3C2410_IRQ(5)
#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */
#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */
#define IRQ_BATT_FLT S3C2410_IRQ(7)
#define IRQ_TICK S3C2410_IRQ(8) /* 24 */
#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */
#define IRQ_TIMER0 S3C2410_IRQ(10)
#define IRQ_TIMER1 S3C2410_IRQ(11)
#define IRQ_TIMER2 S3C2410_IRQ(12)
#define IRQ_TIMER3 S3C2410_IRQ(13)
#define IRQ_TIMER4 S3C2410_IRQ(14)
#define IRQ_UART2 S3C2410_IRQ(15)
#define IRQ_LCD S3C2410_IRQ(16) /* 32 */
#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */
#define IRQ_DMA1 S3C2410_IRQ(18)
#define IRQ_DMA2 S3C2410_IRQ(19)
#define IRQ_DMA3 S3C2410_IRQ(20)
#define IRQ_SDI S3C2410_IRQ(21)
#define IRQ_SPI0 S3C2410_IRQ(22)
#define IRQ_UART1 S3C2410_IRQ(23)
#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */
#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */
#define IRQ_USBD S3C2410_IRQ(25)
#define IRQ_USBH S3C2410_IRQ(26)
#define IRQ_IIC S3C2410_IRQ(27)
#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */
#define IRQ_SPI1 S3C2410_IRQ(29)
#define IRQ_RTC S3C2410_IRQ(30)
#define IRQ_ADCPARENT S3C2410_IRQ(31)
/* interrupts generated from the external interrupts sources */
#define IRQ_EINT0_2412 S3C2410_IRQ(32)
#define IRQ_EINT1_2412 S3C2410_IRQ(33)
#define IRQ_EINT2_2412 S3C2410_IRQ(34)
#define IRQ_EINT3_2412 S3C2410_IRQ(35)
#define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */
#define IRQ_EINT5 S3C2410_IRQ(37)
#define IRQ_EINT6 S3C2410_IRQ(38)
#define IRQ_EINT7 S3C2410_IRQ(39)
#define IRQ_EINT8 S3C2410_IRQ(40)
#define IRQ_EINT9 S3C2410_IRQ(41)
#define IRQ_EINT10 S3C2410_IRQ(42)
#define IRQ_EINT11 S3C2410_IRQ(43)
#define IRQ_EINT12 S3C2410_IRQ(44)
#define IRQ_EINT13 S3C2410_IRQ(45)
#define IRQ_EINT14 S3C2410_IRQ(46)
#define IRQ_EINT15 S3C2410_IRQ(47)
#define IRQ_EINT16 S3C2410_IRQ(48)
#define IRQ_EINT17 S3C2410_IRQ(49)
#define IRQ_EINT18 S3C2410_IRQ(50)
#define IRQ_EINT19 S3C2410_IRQ(51)
#define IRQ_EINT20 S3C2410_IRQ(52) /* 68 */
#define IRQ_EINT21 S3C2410_IRQ(53)
#define IRQ_EINT22 S3C2410_IRQ(54)
#define IRQ_EINT23 S3C2410_IRQ(55)
#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
#define IRQ_LCD_FIFO S3C2410_IRQ(56)
#define IRQ_LCD_FRAME S3C2410_IRQ(57)
/* IRQs for the interal UARTs, and ADC
* these need to be ordered in number of appearance in the
* SUBSRC mask register
*/
#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+58)
#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 74 */
#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1)
#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2)
#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 77 */
#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4)
#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5)
#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 80 */
#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7)
#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8)
#define IRQ_TC S3C2410_IRQSUB(9)
#define IRQ_ADC S3C2410_IRQSUB(10)
/* extra irqs for s3c2412 */
#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21)
#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13)
#define IRQ_S3C2412_CF S3C2410_IRQSUB(14)
#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5)
#define IRQ_S3C2416_DMA S3C2410_IRQ(17)
#define IRQ_S3C2416_UART3 S3C2410_IRQ(18)
#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20)
#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21)
#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15)
#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16)
#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17)
#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18)
#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19)
#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20)
#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21)
#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22)
#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23)
#define IRQ_S32416_WDT S3C2410_IRQSUB(27)
#define IRQ_S32416_AC97 S3C2410_IRQSUB(28)
/* second interrupt-register of s3c2416/s3c2450 */
#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 58 + 29)
#define IRQ_S3C2416_2D S3C2416_IRQ(0)
#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1)
#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2)
#define IRQ_S3C2416_RESERVED3 S3C2416_IRQ(3)
#define IRQ_S3C2416_PCM0 S3C2416_IRQ(4)
#define IRQ_S3C2416_PCM1 S3C2416_IRQ(5)
#define IRQ_S3C2416_I2S0 S3C2416_IRQ(6)
#define IRQ_S3C2416_I2S1 S3C2416_IRQ(7)
/* extra irqs for s3c2440 */
#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */
#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */
#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13)
#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14)
/* irqs for s3c2443 */
#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */
#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */
#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */
#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */
#define IRQ_HSMMC0 IRQ_S3C2416_HSMMC0
#define IRQ_HSMMC1 IRQ_S3C2443_HSMMC
#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15)
#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16)
#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17)
#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18)
#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19)
#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20)
#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21)
#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22)
#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23)
/* UART3 */
#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24)
#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25)
#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26)
#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27)
#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28)
#if defined(CONFIG_CPU_S3C2416)
#define NR_IRQS (IRQ_S3C2416_I2S1 + 1)
#else
#define NR_IRQS (IRQ_S3C2443_AC97 + 1)
#endif
/* compatibility define. */
#define IRQ_UART3 IRQ_S3C2443_UART3
#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3
#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3
#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3
#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3
#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2
#ifdef CONFIG_CPU_S3C2440
#define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97
#else
#define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97
#endif
/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
#define FIQ_START IRQ_EINT0
#endif /* __ASM_ARCH_IRQ_H */

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/* arch/arm/mach-s3c2410/include/mach/map.h
*
* Copyright (c) 2003 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H
#include <plat/map-base.h>
/*
* S3C2410 UART offset is 0x4000 but the other SoCs are 0x400.
* So need to define it, and here is to avoid redefinition warning.
*/
#define S3C_UART_OFFSET (0x4000)
#include <plat/map-s3c.h>
/*
* interrupt controller is the first thing we put in, to make
* the assembly code for the irq detection easier
*/
#define S3C2410_PA_IRQ (0x4A000000)
#define S3C24XX_SZ_IRQ SZ_1M
/* memory controller registers */
#define S3C2410_PA_MEMCTRL (0x48000000)
#define S3C24XX_SZ_MEMCTRL SZ_1M
/* UARTs */
#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
/* Timers */
#define S3C2410_PA_TIMER (0x51000000)
#define S3C24XX_SZ_TIMER SZ_1M
/* Clock and Power management */
#define S3C24XX_SZ_CLKPWR SZ_1M
/* USB Device port */
#define S3C2410_PA_USBDEV (0x52000000)
#define S3C24XX_SZ_USBDEV SZ_1M
/* Watchdog */
#define S3C2410_PA_WATCHDOG (0x53000000)
#define S3C24XX_SZ_WATCHDOG SZ_1M
/* Standard size definitions for peripheral blocks. */
#define S3C24XX_SZ_UART SZ_1M
#define S3C24XX_SZ_IIS SZ_1M
#define S3C24XX_SZ_ADC SZ_1M
#define S3C24XX_SZ_SPI SZ_1M
#define S3C24XX_SZ_SDI SZ_1M
#define S3C24XX_SZ_NAND SZ_1M
#define S3C24XX_SZ_GPIO SZ_1M
/* USB host controller */
#define S3C2410_PA_USBHOST (0x49000000)
/* S3C2416/S3C2443/S3C2450 High-Speed USB Gadget */
#define S3C2416_PA_HSUDC (0x49800000)
#define S3C2416_SZ_HSUDC (SZ_4K)
/* DMA controller */
#define S3C2410_PA_DMA (0x4B000000)
#define S3C24XX_SZ_DMA SZ_1M
/* Clock and Power management */
#define S3C2410_PA_CLKPWR (0x4C000000)
/* LCD controller */
#define S3C2410_PA_LCD (0x4D000000)
#define S3C24XX_SZ_LCD SZ_1M
/* NAND flash controller */
#define S3C2410_PA_NAND (0x4E000000)
/* IIC hardware controller */
#define S3C2410_PA_IIC (0x54000000)
/* IIS controller */
#define S3C2410_PA_IIS (0x55000000)
/* RTC */
#define S3C2410_PA_RTC (0x57000000)
#define S3C24XX_SZ_RTC SZ_1M
/* ADC */
#define S3C2410_PA_ADC (0x58000000)
/* SPI */
#define S3C2410_PA_SPI (0x59000000)
#define S3C2443_PA_SPI0 (0x52000000)
#define S3C2443_PA_SPI1 S3C2410_PA_SPI
/* SDI */
#define S3C2410_PA_SDI (0x5A000000)
/* CAMIF */
#define S3C2440_PA_CAMIF (0x4F000000)
#define S3C2440_SZ_CAMIF SZ_1M
/* AC97 */
#define S3C2440_PA_AC97 (0x5B000000)
#define S3C2440_SZ_AC97 SZ_1M
/* S3C2443/S3C2416 High-speed SD/MMC */
#define S3C2443_PA_HSMMC (0x4A800000)
#define S3C2416_PA_HSMMC0 (0x4AC00000)
#define S3C2443_PA_FB (0x4C800000)
/* S3C2412 memory and IO controls */
#define S3C2412_PA_SSMC (0x4F000000)
#define S3C2412_PA_EBI (0x48800000)
/* physical addresses of all the chip-select areas */
#define S3C2410_CS0 (0x00000000)
#define S3C2410_CS1 (0x08000000)
#define S3C2410_CS2 (0x10000000)
#define S3C2410_CS3 (0x18000000)
#define S3C2410_CS4 (0x20000000)
#define S3C2410_CS5 (0x28000000)
#define S3C2410_CS6 (0x30000000)
#define S3C2410_CS7 (0x38000000)
#define S3C2410_SDRAM_PA (S3C2410_CS6)
/* Use a single interface for common resources between S3C24XX cpus */
#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
#define S3C24XX_PA_DMA S3C2410_PA_DMA
#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
#define S3C24XX_PA_LCD S3C2410_PA_LCD
#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
#define S3C24XX_PA_IIS S3C2410_PA_IIS
#define S3C24XX_PA_RTC S3C2410_PA_RTC
#define S3C24XX_PA_ADC S3C2410_PA_ADC
#define S3C24XX_PA_SPI S3C2410_PA_SPI
#define S3C24XX_PA_SPI1 (S3C2410_PA_SPI + S3C2410_SPI1)
#define S3C24XX_PA_SDI S3C2410_PA_SDI
#define S3C24XX_PA_NAND S3C2410_PA_NAND
#define S3C_PA_FB S3C2443_PA_FB
#define S3C_PA_IIC S3C2410_PA_IIC
#define S3C_PA_UART S3C24XX_PA_UART
#define S3C_PA_USBHOST S3C2410_PA_USBHOST
#define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0
#define S3C_PA_HSMMC1 S3C2443_PA_HSMMC
#define S3C_PA_WDT S3C2410_PA_WATCHDOG
#define S3C_PA_NAND S3C24XX_PA_NAND
#define S3C_PA_SPI0 S3C2443_PA_SPI0
#define S3C_PA_SPI1 S3C2443_PA_SPI1
#define SAMSUNG_PA_TIMER S3C2410_PA_TIMER
#endif /* __ASM_ARCH_MAP_H */

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/* linux/arch/arm/mach-s3c2410/include/pm-core.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C24xx - PM core support for arch/arm/plat-s3c/pm.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
static inline void s3c_pm_debug_init_uart(void)
{
unsigned long tmp = __raw_readl(S3C2410_CLKCON);
/* re-start uart clocks */
tmp |= S3C2410_CLKCON_UART0;
tmp |= S3C2410_CLKCON_UART1;
tmp |= S3C2410_CLKCON_UART2;
__raw_writel(tmp, S3C2410_CLKCON);
udelay(10);
}
static inline void s3c_pm_arch_prepare_irqs(void)
{
__raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
__raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
/* ack any outstanding external interrupts before we go to sleep */
__raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
__raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
__raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
}
static inline void s3c_pm_arch_stop_clocks(void)
{
__raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
}
static void s3c_pm_show_resume_irqs(int start, unsigned long which,
unsigned long mask);
static inline void s3c_pm_arch_show_resume_irqs(void)
{
S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n",
__raw_readl(S3C2410_SRCPND),
__raw_readl(S3C2410_EINTPEND));
s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
s3c_irqwake_intmask);
s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
s3c_irqwake_eintmask);
}
static inline void s3c_pm_arch_update_uart(void __iomem *regs,
struct pm_uart_save *save)
{
}
static inline void s3c_pm_restored_gpios(void) { }
static inline void samsung_pm_saved_gpios(void) { }

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/* arch/arm/mach-s3c2410/include/mach/regs-clock.h
*
* Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2410 clock register definitions
*/
#ifndef __ASM_ARM_REGS_CLOCK
#define __ASM_ARM_REGS_CLOCK
#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
#define S3C2410_LOCKTIME S3C2410_CLKREG(0x00)
#define S3C2410_MPLLCON S3C2410_CLKREG(0x04)
#define S3C2410_UPLLCON S3C2410_CLKREG(0x08)
#define S3C2410_CLKCON S3C2410_CLKREG(0x0C)
#define S3C2410_CLKSLOW S3C2410_CLKREG(0x10)
#define S3C2410_CLKDIVN S3C2410_CLKREG(0x14)
#define S3C2410_CLKCON_IDLE (1<<2)
#define S3C2410_CLKCON_POWER (1<<3)
#define S3C2410_CLKCON_NAND (1<<4)
#define S3C2410_CLKCON_LCDC (1<<5)
#define S3C2410_CLKCON_USBH (1<<6)
#define S3C2410_CLKCON_USBD (1<<7)
#define S3C2410_CLKCON_PWMT (1<<8)
#define S3C2410_CLKCON_SDI (1<<9)
#define S3C2410_CLKCON_UART0 (1<<10)
#define S3C2410_CLKCON_UART1 (1<<11)
#define S3C2410_CLKCON_UART2 (1<<12)
#define S3C2410_CLKCON_GPIO (1<<13)
#define S3C2410_CLKCON_RTC (1<<14)
#define S3C2410_CLKCON_ADC (1<<15)
#define S3C2410_CLKCON_IIC (1<<16)
#define S3C2410_CLKCON_IIS (1<<17)
#define S3C2410_CLKCON_SPI (1<<18)
#define S3C2410_CLKDIVN_PDIVN (1<<0)
#define S3C2410_CLKDIVN_HDIVN (1<<1)
#define S3C2410_CLKSLOW_UCLK_OFF (1<<7)
#define S3C2410_CLKSLOW_MPLL_OFF (1<<5)
#define S3C2410_CLKSLOW_SLOW (1<<4)
#define S3C2410_CLKSLOW_SLOWVAL(x) (x)
#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
/* extra registers */
#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18)
#define S3C2440_CLKCON_CAMERA (1<<19)
#define S3C2440_CLKCON_AC97 (1<<20)
#define S3C2440_CLKDIVN_PDIVN (1<<0)
#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1)
#define S3C2440_CLKDIVN_HDIVN_1 (0<<1)
#define S3C2440_CLKDIVN_HDIVN_2 (1<<1)
#define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1)
#define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1)
#define S3C2440_CLKDIVN_UCLK (1<<3)
#define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0)
#define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4)
#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8)
#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
#define S3C2440_CAMDIVN_DVSEN (1<<12)
#define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5)
#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
#define S3C2412_OSCSET S3C2410_CLKREG(0x18)
#define S3C2412_CLKSRC S3C2410_CLKREG(0x1C)
#define S3C2412_PLLCON_OFF (1<<20)
#define S3C2412_CLKDIVN_PDIVN (1<<2)
#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0)
#define S3C2412_CLKDIVN_ARMDIVN (1<<3)
#define S3C2412_CLKDIVN_DVSEN (1<<4)
#define S3C2412_CLKDIVN_HALFHCLK (1<<5)
#define S3C2412_CLKDIVN_USB48DIV (1<<6)
#define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8)
#define S3C2412_CLKDIVN_UARTDIV_SHIFT (8)
#define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12)
#define S3C2412_CLKDIVN_I2SDIV_SHIFT (12)
#define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16)
#define S3C2412_CLKDIVN_CAMDIV_SHIFT (16)
#define S3C2412_CLKCON_WDT (1<<28)
#define S3C2412_CLKCON_SPI (1<<27)
#define S3C2412_CLKCON_IIS (1<<26)
#define S3C2412_CLKCON_IIC (1<<25)
#define S3C2412_CLKCON_ADC (1<<24)
#define S3C2412_CLKCON_RTC (1<<23)
#define S3C2412_CLKCON_GPIO (1<<22)
#define S3C2412_CLKCON_UART2 (1<<21)
#define S3C2412_CLKCON_UART1 (1<<20)
#define S3C2412_CLKCON_UART0 (1<<19)
#define S3C2412_CLKCON_SDI (1<<18)
#define S3C2412_CLKCON_PWMT (1<<17)
#define S3C2412_CLKCON_USBD (1<<16)
#define S3C2412_CLKCON_CAMCLK (1<<15)
#define S3C2412_CLKCON_UARTCLK (1<<14)
/* missing 13 */
#define S3C2412_CLKCON_USB_HOST48 (1<<12)
#define S3C2412_CLKCON_USB_DEV48 (1<<11)
#define S3C2412_CLKCON_HCLKdiv2 (1<<10)
#define S3C2412_CLKCON_HCLKx2 (1<<9)
#define S3C2412_CLKCON_SDRAM (1<<8)
/* missing 7 */
#define S3C2412_CLKCON_USBH S3C2410_CLKCON_USBH
#define S3C2412_CLKCON_LCDC S3C2410_CLKCON_LCDC
#define S3C2412_CLKCON_NAND S3C2410_CLKCON_NAND
#define S3C2412_CLKCON_DMA3 (1<<3)
#define S3C2412_CLKCON_DMA2 (1<<2)
#define S3C2412_CLKCON_DMA1 (1<<1)
#define S3C2412_CLKCON_DMA0 (1<<0)
/* clock sourec controls */
#define S3C2412_CLKSRC_EXTCLKDIV_MASK (7 << 0)
#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT (0)
#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV (1<<3)
#define S3C2412_CLKSRC_MSYSCLK_MPLL (1<<4)
#define S3C2412_CLKSRC_USYSCLK_UPLL (1<<5)
#define S3C2412_CLKSRC_UARTCLK_MPLL (1<<8)
#define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9)
#define S3C2412_CLKSRC_USBCLK_HCLK (1<<10)
#define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11)
#define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12)
#define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14)
#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
#define S3C2416_CLKDIV2 S3C2410_CLKREG(0x28)
#endif /* __ASM_ARM_REGS_CLOCK */

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/* arch/arm/mach-s3c2410/include/mach/regs-gpio.h
*
* Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2410 GPIO register definitions
*/
#ifndef __ASM_ARCH_REGS_GPIO_H
#define __ASM_ARCH_REGS_GPIO_H
#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
/* general configuration options */
#define S3C2410_GPIO_LEAVE (0xFFFFFFFF)
#define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */
#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1)
#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */
#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */
#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */
/* register address for the GPIO registers.
* S3C24XX_GPIOREG2 is for the second set of registers in the
* GPIO which move between s3c2410 and s3c2412 type systems */
#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
/* configure GPIO ports A..G */
/* port A - S3C2410: 22bits, zero in bit X makes pin X output
* 1 makes port special function, this is default
*/
#define S3C2410_GPACON S3C2410_GPIOREG(0x00)
#define S3C2410_GPADAT S3C2410_GPIOREG(0x04)
#define S3C2410_GPA0_ADDR0 (1<<0)
#define S3C2410_GPA1_ADDR16 (1<<1)
#define S3C2410_GPA2_ADDR17 (1<<2)
#define S3C2410_GPA3_ADDR18 (1<<3)
#define S3C2410_GPA4_ADDR19 (1<<4)
#define S3C2410_GPA5_ADDR20 (1<<5)
#define S3C2410_GPA6_ADDR21 (1<<6)
#define S3C2410_GPA7_ADDR22 (1<<7)
#define S3C2410_GPA8_ADDR23 (1<<8)
#define S3C2410_GPA9_ADDR24 (1<<9)
#define S3C2410_GPA10_ADDR25 (1<<10)
#define S3C2410_GPA11_ADDR26 (1<<11)
#define S3C2410_GPA12_nGCS1 (1<<12)
#define S3C2410_GPA13_nGCS2 (1<<13)
#define S3C2410_GPA14_nGCS3 (1<<14)
#define S3C2410_GPA15_nGCS4 (1<<15)
#define S3C2410_GPA16_nGCS5 (1<<16)
#define S3C2410_GPA17_CLE (1<<17)
#define S3C2410_GPA18_ALE (1<<18)
#define S3C2410_GPA19_nFWE (1<<19)
#define S3C2410_GPA20_nFRE (1<<20)
#define S3C2410_GPA21_nRSTOUT (1<<21)
#define S3C2410_GPA22_nFCE (1<<22)
/* 0x08 and 0x0c are reserved on S3C2410 */
/* S3C2410:
* GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
* 00 = input, 01 = output, 10=special function, 11=reserved
* bit 0,1 = pin 0, 2,3= pin 1...
*
* CPBUP = pull up resistor control, 1=disabled, 0=enabled
*/
#define S3C2410_GPBCON S3C2410_GPIOREG(0x10)
#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14)
#define S3C2410_GPBUP S3C2410_GPIOREG(0x18)
/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
#define S3C2410_GPB0_TOUT0 (0x02 << 0)
#define S3C2410_GPB1_TOUT1 (0x02 << 2)
#define S3C2410_GPB2_TOUT2 (0x02 << 4)
#define S3C2410_GPB3_TOUT3 (0x02 << 6)
#define S3C2410_GPB4_TCLK0 (0x02 << 8)
#define S3C2410_GPB4_MASK (0x03 << 8)
#define S3C2410_GPB5_nXBACK (0x02 << 10)
#define S3C2443_GPB5_XBACK (0x03 << 10)
#define S3C2410_GPB6_nXBREQ (0x02 << 12)
#define S3C2443_GPB6_XBREQ (0x03 << 12)
#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
#define S3C2443_GPB7_XDACK1 (0x03 << 14)
#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
#define S3C2443_GPB9_XDACK0 (0x03 << 18)
#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
#define S3C2443_GPB10_XDREQ0 (0x03 << 20)
#define S3C2410_GPB_PUPDIS(x) (1<<(x))
/* Port C consits of 16 GPIO/Special function
*
* almost identical setup to port b, but the special functions are mostly
* to do with the video system's sync/etc.
*/
#define S3C2410_GPCCON S3C2410_GPIOREG(0x20)
#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)
#define S3C2410_GPCUP S3C2410_GPIOREG(0x28)
#define S3C2410_GPC0_LEND (0x02 << 0)
#define S3C2410_GPC1_VCLK (0x02 << 2)
#define S3C2410_GPC2_VLINE (0x02 << 4)
#define S3C2410_GPC3_VFRAME (0x02 << 6)
#define S3C2410_GPC4_VM (0x02 << 8)
#define S3C2410_GPC5_LCDVF0 (0x02 << 10)
#define S3C2410_GPC6_LCDVF1 (0x02 << 12)
#define S3C2410_GPC7_LCDVF2 (0x02 << 14)
#define S3C2410_GPC8_VD0 (0x02 << 16)
#define S3C2410_GPC9_VD1 (0x02 << 18)
#define S3C2410_GPC10_VD2 (0x02 << 20)
#define S3C2410_GPC11_VD3 (0x02 << 22)
#define S3C2410_GPC12_VD4 (0x02 << 24)
#define S3C2410_GPC13_VD5 (0x02 << 26)
#define S3C2410_GPC14_VD6 (0x02 << 28)
#define S3C2410_GPC15_VD7 (0x02 << 30)
#define S3C2410_GPC_PUPDIS(x) (1<<(x))
/*
* S3C2410: Port D consists of 16 GPIO/Special function
*
* almost identical setup to port b, but the special functions are mostly
* to do with the video system's data.
*
* almost identical setup to port c
*/
#define S3C2410_GPDCON S3C2410_GPIOREG(0x30)
#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34)
#define S3C2410_GPDUP S3C2410_GPIOREG(0x38)
#define S3C2410_GPD0_VD8 (0x02 << 0)
#define S3C2442_GPD0_nSPICS1 (0x03 << 0)
#define S3C2410_GPD1_VD9 (0x02 << 2)
#define S3C2442_GPD1_SPICLK1 (0x03 << 2)
#define S3C2410_GPD2_VD10 (0x02 << 4)
#define S3C2410_GPD3_VD11 (0x02 << 6)
#define S3C2410_GPD4_VD12 (0x02 << 8)
#define S3C2410_GPD5_VD13 (0x02 << 10)
#define S3C2410_GPD6_VD14 (0x02 << 12)
#define S3C2410_GPD7_VD15 (0x02 << 14)
#define S3C2410_GPD8_VD16 (0x02 << 16)
#define S3C2440_GPD8_SPIMISO1 (0x03 << 16)
#define S3C2410_GPD9_VD17 (0x02 << 18)
#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18)
#define S3C2410_GPD10_VD18 (0x02 << 20)
#define S3C2440_GPD10_SPICLK1 (0x03 << 20)
#define S3C2410_GPD11_VD19 (0x02 << 22)
#define S3C2410_GPD12_VD20 (0x02 << 24)
#define S3C2410_GPD13_VD21 (0x02 << 26)
#define S3C2410_GPD14_VD22 (0x02 << 28)
#define S3C2410_GPD14_nSS1 (0x03 << 28)
#define S3C2410_GPD15_VD23 (0x02 << 30)
#define S3C2410_GPD15_nSS0 (0x03 << 30)
#define S3C2410_GPD_PUPDIS(x) (1<<(x))
/* S3C2410:
* Port E consists of 16 GPIO/Special function
*
* again, the same as port B, but dealing with I2S, SDI, and
* more miscellaneous functions
*
* GPIO / interrupt inputs
*/
#define S3C2410_GPECON S3C2410_GPIOREG(0x40)
#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44)
#define S3C2410_GPEUP S3C2410_GPIOREG(0x48)
#define S3C2410_GPE0_I2SLRCK (0x02 << 0)
#define S3C2443_GPE0_AC_nRESET (0x03 << 0)
#define S3C2410_GPE0_MASK (0x03 << 0)
#define S3C2410_GPE1_I2SSCLK (0x02 << 2)
#define S3C2443_GPE1_AC_SYNC (0x03 << 2)
#define S3C2410_GPE1_MASK (0x03 << 2)
#define S3C2410_GPE2_CDCLK (0x02 << 4)
#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
#define S3C2410_GPE3_I2SSDI (0x02 << 6)
#define S3C2443_GPE3_AC_SDI (0x03 << 6)
#define S3C2410_GPE3_nSS0 (0x03 << 6)
#define S3C2410_GPE3_MASK (0x03 << 6)
#define S3C2410_GPE4_I2SSDO (0x02 << 8)
#define S3C2443_GPE4_AC_SDO (0x03 << 8)
#define S3C2410_GPE4_I2SSDI (0x03 << 8)
#define S3C2410_GPE4_MASK (0x03 << 8)
#define S3C2410_GPE5_SDCLK (0x02 << 10)
#define S3C2443_GPE5_SD1_CLK (0x02 << 10)
#define S3C2443_GPE5_AC_BITCLK (0x03 << 10)
#define S3C2410_GPE6_SDCMD (0x02 << 12)
#define S3C2443_GPE6_SD1_CMD (0x02 << 12)
#define S3C2443_GPE6_AC_SDI (0x03 << 12)
#define S3C2410_GPE7_SDDAT0 (0x02 << 14)
#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)
#define S3C2443_GPE7_AC_SDO (0x03 << 14)
#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
#define S3C2443_GPE8_AC_SYNC (0x03 << 16)
#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
#define S3C2443_GPE9_AC_nRESET (0x03 << 18)
#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
#define S3C2410_GPE13_SPICLK0 (0x02 << 26)
#define S3C2410_GPE14_IICSCL (0x02 << 28)
#define S3C2410_GPE14_MASK (0x03 << 28)
#define S3C2410_GPE15_IICSDA (0x02 << 30)
#define S3C2410_GPE15_MASK (0x03 << 30)
#define S3C2440_GPE0_ACSYNC (0x03 << 0)
#define S3C2440_GPE1_ACBITCLK (0x03 << 2)
#define S3C2440_GPE2_ACRESET (0x03 << 4)
#define S3C2440_GPE3_ACIN (0x03 << 6)
#define S3C2440_GPE4_ACOUT (0x03 << 8)
#define S3C2410_GPE_PUPDIS(x) (1<<(x))
/* S3C2410:
* Port F consists of 8 GPIO/Special function
*
* GPIO / interrupt inputs
*
* GPFCON has 2 bits for each of the input pins on port F
* 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
*
* pull up works like all other ports.
*
* GPIO/serial/misc pins
*/
#define S3C2410_GPFCON S3C2410_GPIOREG(0x50)
#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54)
#define S3C2410_GPFUP S3C2410_GPIOREG(0x58)
#define S3C2410_GPF0_EINT0 (0x02 << 0)
#define S3C2410_GPF1_EINT1 (0x02 << 2)
#define S3C2410_GPF2_EINT2 (0x02 << 4)
#define S3C2410_GPF3_EINT3 (0x02 << 6)
#define S3C2410_GPF4_EINT4 (0x02 << 8)
#define S3C2410_GPF5_EINT5 (0x02 << 10)
#define S3C2410_GPF6_EINT6 (0x02 << 12)
#define S3C2410_GPF7_EINT7 (0x02 << 14)
#define S3C2410_GPF_PUPDIS(x) (1<<(x))
/* S3C2410:
* Port G consists of 8 GPIO/IRQ/Special function
*
* GPGCON has 2 bits for each of the input pins on port G
* 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
*
* pull up works like all other ports.
*/
#define S3C2410_GPGCON S3C2410_GPIOREG(0x60)
#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)
#define S3C2410_GPGUP S3C2410_GPIOREG(0x68)
#define S3C2410_GPG0_EINT8 (0x02 << 0)
#define S3C2410_GPG1_EINT9 (0x02 << 2)
#define S3C2410_GPG2_EINT10 (0x02 << 4)
#define S3C2410_GPG2_nSS0 (0x03 << 4)
#define S3C2410_GPG3_EINT11 (0x02 << 6)
#define S3C2410_GPG3_nSS1 (0x03 << 6)
#define S3C2410_GPG4_EINT12 (0x02 << 8)
#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
#define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
#define S3C2410_GPG5_EINT13 (0x02 << 10)
#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */
#define S3C2410_GPG6_EINT14 (0x02 << 12)
#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
#define S3C2410_GPG7_EINT15 (0x02 << 14)
#define S3C2410_GPG7_SPICLK1 (0x03 << 14)
#define S3C2410_GPG8_EINT16 (0x02 << 16)
#define S3C2410_GPG9_EINT17 (0x02 << 18)
#define S3C2410_GPG10_EINT18 (0x02 << 20)
#define S3C2410_GPG11_EINT19 (0x02 << 22)
#define S3C2410_GPG11_TCLK1 (0x03 << 22)
#define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
#define S3C2410_GPG12_EINT20 (0x02 << 24)
#define S3C2410_GPG12_XMON (0x03 << 24)
#define S3C2442_GPG12_nSPICS0 (0x03 << 24)
#define S3C2443_GPG12_nINPACK (0x03 << 24)
#define S3C2410_GPG13_EINT21 (0x02 << 26)
#define S3C2410_GPG13_nXPON (0x03 << 26)
#define S3C2443_GPG13_CF_nREG (0x03 << 26)
#define S3C2410_GPG14_EINT22 (0x02 << 28)
#define S3C2410_GPG14_YMON (0x03 << 28)
#define S3C2443_GPG14_CF_RESET (0x03 << 28)
#define S3C2410_GPG15_EINT23 (0x02 << 30)
#define S3C2410_GPG15_nYPON (0x03 << 30)
#define S3C2443_GPG15_CF_PWR (0x03 << 30)
#define S3C2410_GPG_PUPDIS(x) (1<<(x))
/* Port H consists of11 GPIO/serial/Misc pins
*
* GPHCON has 2 bits for each of the input pins on port H
* 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
*
* pull up works like all other ports.
*/
#define S3C2410_GPHCON S3C2410_GPIOREG(0x70)
#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)
#define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
#define S3C2410_GPH0_nCTS0 (0x02 << 0)
#define S3C2416_GPH0_TXD0 (0x02 << 0)
#define S3C2410_GPH1_nRTS0 (0x02 << 2)
#define S3C2416_GPH1_RXD0 (0x02 << 2)
#define S3C2410_GPH2_TXD0 (0x02 << 4)
#define S3C2416_GPH2_TXD1 (0x02 << 4)
#define S3C2410_GPH3_RXD0 (0x02 << 6)
#define S3C2416_GPH3_RXD1 (0x02 << 6)
#define S3C2410_GPH4_TXD1 (0x02 << 8)
#define S3C2416_GPH4_TXD2 (0x02 << 8)
#define S3C2410_GPH5_RXD1 (0x02 << 10)
#define S3C2416_GPH5_RXD2 (0x02 << 10)
#define S3C2410_GPH6_TXD2 (0x02 << 12)
#define S3C2416_GPH6_TXD3 (0x02 << 12)
#define S3C2410_GPH6_nRTS1 (0x03 << 12)
#define S3C2416_GPH6_nRTS2 (0x03 << 12)
#define S3C2410_GPH7_RXD2 (0x02 << 14)
#define S3C2416_GPH7_RXD3 (0x02 << 14)
#define S3C2410_GPH7_nCTS1 (0x03 << 14)
#define S3C2416_GPH7_nCTS2 (0x03 << 14)
#define S3C2410_GPH8_UCLK (0x02 << 16)
#define S3C2416_GPH8_nCTS0 (0x02 << 16)
#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
#define S3C2442_GPH9_nSPICS0 (0x03 << 18)
#define S3C2416_GPH9_nRTS0 (0x02 << 18)
#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
#define S3C2416_GPH10_nCTS1 (0x02 << 20)
#define S3C2416_GPH11_nRTS1 (0x02 << 22)
#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24)
#define S3C2416_GPH13_CLKOUT0 (0x02 << 26)
#define S3C2416_GPH14_CLKOUT1 (0x02 << 28)
/* The S3C2412 and S3C2413 move the GPJ register set to after
* GPH, which means all registers after 0x80 are now offset by 0x10
* for the 2412/2413 from the 2410/2440/2442
*/
/*
* Port J consists of 13 GPIO/Camera pins. GPJCON has 2 bits
* for each of the pins on port J.
* 00 - input, 01 output, 10 - camera
*
* Pull up works like all other ports.
*/
#define S3C2413_GPJCON S3C2410_GPIOREG(0x80)
#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84)
#define S3C2413_GPJUP S3C2410_GPIOREG(0x88)
#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C)
/* S3C2443 and above */
#define S3C2440_GPJCON S3C2410_GPIOREG(0xD0)
#define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4)
#define S3C2440_GPJUP S3C2410_GPIOREG(0xD8)
#define S3C2443_GPKCON S3C2410_GPIOREG(0xE0)
#define S3C2443_GPKDAT S3C2410_GPIOREG(0xE4)
#define S3C2443_GPKUP S3C2410_GPIOREG(0xE8)
#define S3C2443_GPLCON S3C2410_GPIOREG(0xF0)
#define S3C2443_GPLDAT S3C2410_GPIOREG(0xF4)
#define S3C2443_GPLUP S3C2410_GPIOREG(0xF8)
#define S3C2443_GPMCON S3C2410_GPIOREG(0x100)
#define S3C2443_GPMDAT S3C2410_GPIOREG(0x104)
#define S3C2443_GPMUP S3C2410_GPIOREG(0x108)
/* miscellaneous control */
#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
/* see clock.h for dclk definitions */
/* pullup control on databus */
#define S3C2410_MISCCR_SPUCR_HEN (0<<0)
#define S3C2410_MISCCR_SPUCR_HDIS (1<<0)
#define S3C2410_MISCCR_SPUCR_LEN (0<<1)
#define S3C2410_MISCCR_SPUCR_LDIS (1<<1)
#define S3C2410_MISCCR_USBDEV (0<<3)
#define S3C2410_MISCCR_USBHOST (1<<3)
#define S3C2410_MISCCR_CLK0_MPLL (0<<4)
#define S3C2410_MISCCR_CLK0_UPLL (1<<4)
#define S3C2410_MISCCR_CLK0_FCLK (2<<4)
#define S3C2410_MISCCR_CLK0_HCLK (3<<4)
#define S3C2410_MISCCR_CLK0_PCLK (4<<4)
#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
#define S3C2410_MISCCR_CLK0_MASK (7<<4)
#define S3C2412_MISCCR_CLK0_RTC (2<<4)
#define S3C2410_MISCCR_CLK1_MPLL (0<<8)
#define S3C2410_MISCCR_CLK1_UPLL (1<<8)
#define S3C2410_MISCCR_CLK1_FCLK (2<<8)
#define S3C2410_MISCCR_CLK1_HCLK (3<<8)
#define S3C2410_MISCCR_CLK1_PCLK (4<<8)
#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
#define S3C2410_MISCCR_CLK1_MASK (7<<8)
#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8)
#define S3C2410_MISCCR_USBSUSPND0 (1<<12)
#define S3C2416_MISCCR_SEL_SUSPND (1<<12)
#define S3C2410_MISCCR_USBSUSPND1 (1<<13)
#define S3C2410_MISCCR_nRSTCON (1<<16)
#define S3C2410_MISCCR_nEN_SCLK0 (1<<17)
#define S3C2410_MISCCR_nEN_SCLK1 (1<<18)
#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */
#define S3C2410_MISCCR_SDSLEEP (7<<17)
#define S3C2416_MISCCR_FLT_I2C (1<<24)
#define S3C2416_MISCCR_HSSPI_EN2 (1<<31)
/* external interrupt control... */
/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
* S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
* S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
*
* note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
*
* Samsung datasheet p9-25
*/
#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)
#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
#define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88)
#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
/* interrupt filtering conrrol for EINT16..EINT23 */
#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)
#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)
#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)
#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)
#define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94)
#define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98)
#define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C)
#define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0)
/* values for interrupt filtering */
#define S3C2410_EINTFLT_PCLK (0x00)
#define S3C2410_EINTFLT_EXTCLK (1<<7)
#define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f)
/* removed EINTxxxx defs from here, not meant for this */
/* GSTATUS have miscellaneous information in them
*
* These move between s3c2410 and s3c2412 style systems.
*/
#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)
#define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0)
#define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4)
#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)
#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)
#define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC)
#define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0)
#define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4)
#define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8)
#define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC)
#define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC)
#define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0)
#define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4)
#define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8)
#define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC)
#define S3C2410_GSTATUS0_nWAIT (1<<3)
#define S3C2410_GSTATUS0_NCON (1<<2)
#define S3C2410_GSTATUS0_RnB (1<<1)
#define S3C2410_GSTATUS0_nBATTFLT (1<<0)
#define S3C2410_GSTATUS1_IDMASK (0xffff0000)
#define S3C2410_GSTATUS1_2410 (0x32410000)
#define S3C2410_GSTATUS1_2412 (0x32412001)
#define S3C2410_GSTATUS1_2416 (0x32416003)
#define S3C2410_GSTATUS1_2440 (0x32440000)
#define S3C2410_GSTATUS1_2442 (0x32440aaa)
/* some 2416 CPUs report this value also */
#define S3C2410_GSTATUS1_2450 (0x32450003)
#define S3C2410_GSTATUS2_WTRESET (1<<2)
#define S3C2410_GSTATUS2_OFFRESET (1<<1)
#define S3C2410_GSTATUS2_PONRESET (1<<0)
/* 2412/2413 sleep configuration registers */
#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)
#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C)
#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C)
#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C)
#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C)
#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C)
/* definitions for each pin bit */
#define S3C2412_GPIO_SLPCON_LOW ( 0x00 )
#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 )
#define S3C2412_GPIO_SLPCON_IN ( 0x02 )
#define S3C2412_GPIO_SLPCON_PULL ( 0x03 )
#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2))
#define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2))
#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2))
#define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2))
#define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */
#define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2))
#define S3C2412_SLPCON_ALL_LOW (0x0)
#define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444)
#define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888)
#define S3C2412_SLPCON_ALL_PULL (0x33333333)
#endif /* __ASM_ARCH_REGS_GPIO_H */

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/* arch/arm/mach-s3c2410/include/mach/regs-irq.h
*
* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ___ASM_ARCH_REGS_IRQ_H
#define ___ASM_ARCH_REGS_IRQ_H
/* interrupt controller */
#define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ)
#define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO)
#define S3C24XX_EINTREG(x) ((x) + S3C24XX_VA_GPIO2)
#define S3C2410_SRCPND S3C2410_IRQREG(0x000)
#define S3C2410_INTMOD S3C2410_IRQREG(0x004)
#define S3C2410_INTMSK S3C2410_IRQREG(0x008)
#define S3C2410_PRIORITY S3C2410_IRQREG(0x00C)
#define S3C2410_INTPND S3C2410_IRQREG(0x010)
#define S3C2410_INTOFFSET S3C2410_IRQREG(0x014)
#define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018)
#define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C)
#define S3C2416_PRIORITY_MODE1 S3C2410_IRQREG(0x030)
#define S3C2416_PRIORITY_UPDATE1 S3C2410_IRQREG(0x034)
#define S3C2416_SRCPND2 S3C2410_IRQREG(0x040)
#define S3C2416_INTMOD2 S3C2410_IRQREG(0x044)
#define S3C2416_INTMSK2 S3C2410_IRQREG(0x048)
#define S3C2416_INTPND2 S3C2410_IRQREG(0x050)
#define S3C2416_INTOFFSET2 S3C2410_IRQREG(0x054)
#define S3C2416_PRIORITY_MODE2 S3C2410_IRQREG(0x070)
#define S3C2416_PRIORITY_UPDATE2 S3C2410_IRQREG(0x074)
/* mask: 0=enable, 1=disable
* 1 bit EINT, 4=EINT4, 23=EINT23
* EINT0,1,2,3 are not handled here.
*/
#define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4)
#define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8)
#define S3C2412_EINTMASK S3C2410_EINTREG(0x0B4)
#define S3C2412_EINTPEND S3C2410_EINTREG(0X0B8)
#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4)
#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8)
#endif /* ___ASM_ARCH_REGS_IRQ_H */

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/* arch/arm/mach-s3c2410/include/mach/regs-lcd.h
*
* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ___ASM_ARCH_REGS_LCD_H
#define ___ASM_ARCH_REGS_LCD_H
#define S3C2410_LCDREG(x) (x)
/* LCD control registers */
#define S3C2410_LCDCON1 S3C2410_LCDREG(0x00)
#define S3C2410_LCDCON2 S3C2410_LCDREG(0x04)
#define S3C2410_LCDCON3 S3C2410_LCDREG(0x08)
#define S3C2410_LCDCON4 S3C2410_LCDREG(0x0C)
#define S3C2410_LCDCON5 S3C2410_LCDREG(0x10)
#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8)
#define S3C2410_LCDCON1_MMODE (1<<7)
#define S3C2410_LCDCON1_DSCAN4 (0<<5)
#define S3C2410_LCDCON1_STN4 (1<<5)
#define S3C2410_LCDCON1_STN8 (2<<5)
#define S3C2410_LCDCON1_TFT (3<<5)
#define S3C2410_LCDCON1_STN1BPP (0<<1)
#define S3C2410_LCDCON1_STN2GREY (1<<1)
#define S3C2410_LCDCON1_STN4GREY (2<<1)
#define S3C2410_LCDCON1_STN8BPP (3<<1)
#define S3C2410_LCDCON1_STN12BPP (4<<1)
#define S3C2410_LCDCON1_TFT1BPP (8<<1)
#define S3C2410_LCDCON1_TFT2BPP (9<<1)
#define S3C2410_LCDCON1_TFT4BPP (10<<1)
#define S3C2410_LCDCON1_TFT8BPP (11<<1)
#define S3C2410_LCDCON1_TFT16BPP (12<<1)
#define S3C2410_LCDCON1_TFT24BPP (13<<1)
#define S3C2410_LCDCON1_ENVID (1)
#define S3C2410_LCDCON1_MODEMASK 0x1E
#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14)
#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF)
#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F)
#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8)
#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
/* LDCCON4 changes for STN mode on the S3C2412 */
#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF)
#define S3C2410_LCDCON5_BPP24BL (1<<12)
#define S3C2410_LCDCON5_FRM565 (1<<11)
#define S3C2410_LCDCON5_INVVCLK (1<<10)
#define S3C2410_LCDCON5_INVVLINE (1<<9)
#define S3C2410_LCDCON5_INVVFRAME (1<<8)
#define S3C2410_LCDCON5_INVVD (1<<7)
#define S3C2410_LCDCON5_INVVDEN (1<<6)
#define S3C2410_LCDCON5_INVPWREN (1<<5)
#define S3C2410_LCDCON5_INVLEND (1<<4)
#define S3C2410_LCDCON5_PWREN (1<<3)
#define S3C2410_LCDCON5_ENLEND (1<<2)
#define S3C2410_LCDCON5_BSWP (1<<1)
#define S3C2410_LCDCON5_HWSWP (1<<0)
/* framebuffer start addressed */
#define S3C2410_LCDSADDR1 S3C2410_LCDREG(0x14)
#define S3C2410_LCDSADDR2 S3C2410_LCDREG(0x18)
#define S3C2410_LCDSADDR3 S3C2410_LCDREG(0x1C)
#define S3C2410_LCDBANK(x) ((x) << 21)
#define S3C2410_LCDBASEU(x) (x)
#define S3C2410_OFFSIZE(x) ((x) << 11)
#define S3C2410_PAGEWIDTH(x) (x)
/* colour lookup and miscellaneous controls */
#define S3C2410_REDLUT S3C2410_LCDREG(0x20)
#define S3C2410_GREENLUT S3C2410_LCDREG(0x24)
#define S3C2410_BLUELUT S3C2410_LCDREG(0x28)
#define S3C2410_DITHMODE S3C2410_LCDREG(0x4C)
#define S3C2410_TPAL S3C2410_LCDREG(0x50)
#define S3C2410_TPAL_EN (1<<24)
/* interrupt info */
#define S3C2410_LCDINTPND S3C2410_LCDREG(0x54)
#define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58)
#define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C)
#define S3C2410_LCDINT_FIWSEL (1<<2)
#define S3C2410_LCDINT_FRSYNC (1<<1)
#define S3C2410_LCDINT_FICNT (1<<0)
/* s3c2442 extra stn registers */
#define S3C2442_REDLUT S3C2410_LCDREG(0x20)
#define S3C2442_GREENLUT S3C2410_LCDREG(0x24)
#define S3C2442_BLUELUT S3C2410_LCDREG(0x28)
#define S3C2442_DITHMODE S3C2410_LCDREG(0x20)
#define S3C2410_LPCSEL S3C2410_LCDREG(0x60)
#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4))
/* S3C2412 registers */
#define S3C2412_TPAL S3C2410_LCDREG(0x20)
#define S3C2412_LCDINTPND S3C2410_LCDREG(0x24)
#define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28)
#define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C)
#define S3C2412_TCONSEL S3C2410_LCDREG(0x30)
#define S3C2412_LCDCON6 S3C2410_LCDREG(0x34)
#define S3C2412_LCDCON7 S3C2410_LCDREG(0x38)
#define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C)
#define S3C2412_LCDCON9 S3C2410_LCDREG(0x40)
#define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4))
#define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4))
#define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4))
#define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4))
/* general registers */
/* base of the LCD registers, where INTPND, INTSRC and then INTMSK
* are available. */
#define S3C2410_LCDINTBASE S3C2410_LCDREG(0x54)
#define S3C2412_LCDINTBASE S3C2410_LCDREG(0x24)
#define S3C24XX_LCDINTPND (0x00)
#define S3C24XX_LCDSRCPND (0x04)
#define S3C24XX_LCDINTMSK (0x08)
#endif /* ___ASM_ARCH_REGS_LCD_H */

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/* arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
*
* Copyright (c) 2007 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2443 clock register definitions
*/
#ifndef __ASM_ARM_REGS_S3C2443_CLOCK
#define __ASM_ARM_REGS_S3C2443_CLOCK
#define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
#define S3C2443_PLLCON_MDIVSHIFT 16
#define S3C2443_PLLCON_PDIVSHIFT 8
#define S3C2443_PLLCON_SDIVSHIFT 0
#define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1)
#define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1)
#define S3C2443_PLLCON_SDIVMASK (3)
#define S3C2443_MPLLCON S3C2443_CLKREG(0x10)
#define S3C2443_EPLLCON S3C2443_CLKREG(0x18)
#define S3C2443_CLKSRC S3C2443_CLKREG(0x20)
#define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24)
#define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28)
#define S3C2443_HCLKCON S3C2443_CLKREG(0x30)
#define S3C2443_PCLKCON S3C2443_CLKREG(0x34)
#define S3C2443_SCLKCON S3C2443_CLKREG(0x38)
#define S3C2443_PWRMODE S3C2443_CLKREG(0x40)
#define S3C2443_SWRST S3C2443_CLKREG(0x44)
#define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50)
#define S3C2443_SYSID S3C2443_CLKREG(0x5C)
#define S3C2443_PWRCFG S3C2443_CLKREG(0x60)
#define S3C2443_RSTCON S3C2443_CLKREG(0x64)
#define S3C2443_PHYCTRL S3C2443_CLKREG(0x80)
#define S3C2443_PHYPWR S3C2443_CLKREG(0x84)
#define S3C2443_URSTCON S3C2443_CLKREG(0x88)
#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C)
#define S3C2443_PLLCON_OFF (1<<24)
#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7)
#define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7)
#define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7)
#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7)
#define S3C2443_CLKSRC_EPLLREF_MASK (3<<7)
#define S3C2443_CLKSRC_EXTCLK_DIV (1<<3)
#define S3C2443_CLKDIV0_HALF_HCLK (1<<3)
#define S3C2443_CLKDIV0_HALF_PCLK (1<<2)
#define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0)
#define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6)
#define S3C2443_CLKDIV0_EXTDIV_SHIFT (6)
#define S3C2443_CLKDIV0_PREDIV_MASK (3<<4)
#define S3C2443_CLKDIV0_PREDIV_SHIFT (4)
#define S3C2416_CLKDIV0_ARMDIV_MASK (7 << 9)
#define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9)
#define S3C2443_CLKDIV0_ARMDIV_SHIFT (9)
#define S3C2443_CLKDIV0_ARMDIV_1 (0<<9)
#define S3C2443_CLKDIV0_ARMDIV_2 (8<<9)
#define S3C2443_CLKDIV0_ARMDIV_3 (2<<9)
#define S3C2443_CLKDIV0_ARMDIV_4 (9<<9)
#define S3C2443_CLKDIV0_ARMDIV_6 (10<<9)
#define S3C2443_CLKDIV0_ARMDIV_8 (11<<9)
#define S3C2443_CLKDIV0_ARMDIV_12 (13<<9)
#define S3C2443_CLKDIV0_ARMDIV_16 (15<<9)
/* S3C2443_CLKDIV1 removed, only used in clock.c code */
#define S3C2443_CLKCON_NAND
#define S3C2443_HCLKCON_DMA0 (1<<0)
#define S3C2443_HCLKCON_DMA1 (1<<1)
#define S3C2443_HCLKCON_DMA2 (1<<2)
#define S3C2443_HCLKCON_DMA3 (1<<3)
#define S3C2443_HCLKCON_DMA4 (1<<4)
#define S3C2443_HCLKCON_DMA5 (1<<5)
#define S3C2443_HCLKCON_CAMIF (1<<8)
#define S3C2443_HCLKCON_LCDC (1<<9)
#define S3C2443_HCLKCON_USBH (1<<11)
#define S3C2443_HCLKCON_USBD (1<<12)
#define S3C2416_HCLKCON_HSMMC0 (1<<15)
#define S3C2443_HCLKCON_HSMMC (1<<16)
#define S3C2443_HCLKCON_CFC (1<<17)
#define S3C2443_HCLKCON_SSMC (1<<18)
#define S3C2443_HCLKCON_DRAMC (1<<19)
#define S3C2443_PCLKCON_UART0 (1<<0)
#define S3C2443_PCLKCON_UART1 (1<<1)
#define S3C2443_PCLKCON_UART2 (1<<2)
#define S3C2443_PCLKCON_UART3 (1<<3)
#define S3C2443_PCLKCON_IIC (1<<4)
#define S3C2443_PCLKCON_SDI (1<<5)
#define S3C2443_PCLKCON_HSSPI (1<<6)
#define S3C2443_PCLKCON_ADC (1<<7)
#define S3C2443_PCLKCON_AC97 (1<<8)
#define S3C2443_PCLKCON_IIS (1<<9)
#define S3C2443_PCLKCON_PWMT (1<<10)
#define S3C2443_PCLKCON_WDT (1<<11)
#define S3C2443_PCLKCON_RTC (1<<12)
#define S3C2443_PCLKCON_GPIO (1<<13)
#define S3C2443_PCLKCON_SPI0 (1<<14)
#define S3C2443_PCLKCON_SPI1 (1<<15)
#define S3C2443_SCLKCON_DDRCLK (1<<16)
#define S3C2443_SCLKCON_SSMCCLK (1<<15)
#define S3C2443_SCLKCON_HSSPICLK (1<<14)
#define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13)
#define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12)
#define S3C2443_SCLKCON_CAMCLK (1<<11)
#define S3C2443_SCLKCON_DISPCLK (1<<10)
#define S3C2443_SCLKCON_I2SCLK (1<<9)
#define S3C2443_SCLKCON_UARTCLK (1<<8)
#define S3C2443_SCLKCON_USBHOST (1<<1)
#define S3C2443_PWRCFG_SLEEP (1<<15)
#define S3C2443_PWRCFG_USBPHY (1 << 4)
#define S3C2443_URSTCON_FUNCRST (1 << 2)
#define S3C2443_URSTCON_PHYRST (1 << 0)
#define S3C2443_PHYCTRL_CLKSEL (1 << 3)
#define S3C2443_PHYCTRL_EXTCLK (1 << 2)
#define S3C2443_PHYCTRL_PLLSEL (1 << 1)
#define S3C2443_PHYCTRL_DSPORT (1 << 0)
#define S3C2443_PHYPWR_COMMON_ON (1 << 31)
#define S3C2443_PHYPWR_ANALOG_PD (1 << 4)
#define S3C2443_PHYPWR_PLL_REFCLK (1 << 3)
#define S3C2443_PHYPWR_XO_ON (1 << 2)
#define S3C2443_PHYPWR_PLL_PWRDN (1 << 1)
#define S3C2443_PHYPWR_FSUSPEND (1 << 0)
#define S3C2443_UCLKCON_DETECT_VBUS (1 << 31)
#define S3C2443_UCLKCON_FUNC_CLKEN (1 << 2)
#define S3C2443_UCLKCON_TCLKEN (1 << 0)
#include <asm/div64.h>
static inline unsigned int
s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk)
{
unsigned int mdiv, pdiv, sdiv;
uint64_t fvco;
mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
mdiv &= S3C2443_PLLCON_MDIVMASK;
pdiv &= S3C2443_PLLCON_PDIVMASK;
sdiv &= S3C2443_PLLCON_SDIVMASK;
fvco = (uint64_t)baseclk * (2 * (mdiv + 8));
do_div(fvco, pdiv << sdiv);
return (unsigned int)fvco;
}
static inline unsigned int
s3c2443_get_epll(unsigned int pllval, unsigned int baseclk)
{
unsigned int mdiv, pdiv, sdiv;
uint64_t fvco;
mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
mdiv &= S3C2443_PLLCON_MDIVMASK;
pdiv &= S3C2443_PLLCON_PDIVMASK;
sdiv &= S3C2443_PLLCON_SDIVMASK;
fvco = (uint64_t)baseclk * (mdiv + 8);
do_div(fvco, (pdiv + 2) << sdiv);
return (unsigned int)fvco;
}
#endif /* __ASM_ARM_REGS_S3C2443_CLOCK */

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arch/arm/mach-s3c24xx/include/mach/rtc-core.h Normal file
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/*
* Copyright (c) 2011 Heiko Stuebner <heiko@sntech.de>
*
* Samsung RTC Controller core functions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __RTC_CORE_H
#define __RTC_CORE_H __FILE__
/* These functions are only for use with the core support code, such as
* the cpu specific initialisation code
*/
extern struct platform_device s3c_device_rtc;
/* re-define device name depending on support. */
static inline void s3c_rtc_setname(char *name)
{
s3c_device_rtc.name = name;
}
#endif /* __RTC_CORE_H */

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arch/arm/mach-s3c24xx/include/mach/s3c2412.h Normal file
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/*
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_H
#define __ARCH_ARM_REGS_S3C24XX_S3C2412_H __FILE__
#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
#define S3C2412_REFRESH S3C2412_MEMREG(0x10)
#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x4)
#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x0)
#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_H */