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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-09 01:28:05 -04:00
Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
244
arch/arm/mach-s3c64xx/pl080.c
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244
arch/arm/mach-s3c64xx/pl080.c
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/*
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* Samsung's S3C64XX generic DMA support using amba-pl08x driver.
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*
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* Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/pl080.h>
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#include <linux/amba/pl08x.h>
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#include <linux/of.h>
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#include <mach/irqs.h>
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#include <mach/map.h>
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#include "regs-sys.h"
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static int pl08x_get_xfer_signal(const struct pl08x_channel_data *cd)
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{
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return cd->min_signal;
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}
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static void pl08x_put_xfer_signal(const struct pl08x_channel_data *cd, int ch)
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{
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}
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/*
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* DMA0
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*/
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static struct pl08x_channel_data s3c64xx_dma0_info[] = {
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{
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.bus_id = "uart0_tx",
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.min_signal = 0,
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.max_signal = 0,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "uart0_rx",
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.min_signal = 1,
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.max_signal = 1,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "uart1_tx",
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.min_signal = 2,
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.max_signal = 2,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "uart1_rx",
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.min_signal = 3,
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.max_signal = 3,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "uart2_tx",
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.min_signal = 4,
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.max_signal = 4,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "uart2_rx",
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.min_signal = 5,
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.max_signal = 5,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "uart3_tx",
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.min_signal = 6,
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.max_signal = 6,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "uart3_rx",
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.min_signal = 7,
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.max_signal = 7,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "pcm0_tx",
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.min_signal = 8,
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.max_signal = 8,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "pcm0_rx",
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.min_signal = 9,
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.max_signal = 9,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "i2s0_tx",
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.min_signal = 10,
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.max_signal = 10,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "i2s0_rx",
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.min_signal = 11,
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.max_signal = 11,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "spi0_tx",
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.min_signal = 12,
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.max_signal = 12,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "spi0_rx",
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.min_signal = 13,
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.max_signal = 13,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "i2s2_tx",
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.min_signal = 14,
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.max_signal = 14,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "i2s2_rx",
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.min_signal = 15,
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.max_signal = 15,
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.periph_buses = PL08X_AHB2,
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}
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};
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struct pl08x_platform_data s3c64xx_dma0_plat_data = {
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.memcpy_channel = {
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.bus_id = "memcpy",
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.cctl_memcpy =
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(PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT |
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PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT |
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PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT |
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PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT |
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PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE |
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PL080_CONTROL_PROT_SYS),
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},
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.lli_buses = PL08X_AHB1,
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.mem_buses = PL08X_AHB1,
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.get_xfer_signal = pl08x_get_xfer_signal,
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.put_xfer_signal = pl08x_put_xfer_signal,
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.slave_channels = s3c64xx_dma0_info,
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.num_slave_channels = ARRAY_SIZE(s3c64xx_dma0_info),
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};
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static AMBA_AHB_DEVICE(s3c64xx_dma0, "dma-pl080s.0", 0,
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0x75000000, {IRQ_DMA0}, &s3c64xx_dma0_plat_data);
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/*
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* DMA1
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*/
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static struct pl08x_channel_data s3c64xx_dma1_info[] = {
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{
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.bus_id = "pcm1_tx",
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.min_signal = 0,
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.max_signal = 0,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "pcm1_rx",
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.min_signal = 1,
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.max_signal = 1,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "i2s1_tx",
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.min_signal = 2,
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.max_signal = 2,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "i2s1_rx",
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.min_signal = 3,
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.max_signal = 3,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "spi1_tx",
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.min_signal = 4,
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.max_signal = 4,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "spi1_rx",
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.min_signal = 5,
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.max_signal = 5,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ac97_out",
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.min_signal = 6,
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.max_signal = 6,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ac97_in",
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.min_signal = 7,
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.max_signal = 7,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ac97_mic",
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.min_signal = 8,
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.max_signal = 8,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "pwm",
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.min_signal = 9,
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.max_signal = 9,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "irda",
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.min_signal = 10,
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.max_signal = 10,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "external",
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.min_signal = 11,
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.max_signal = 11,
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.periph_buses = PL08X_AHB2,
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},
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};
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struct pl08x_platform_data s3c64xx_dma1_plat_data = {
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.memcpy_channel = {
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.bus_id = "memcpy",
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.cctl_memcpy =
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(PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT |
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PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT |
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PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT |
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PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT |
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PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE |
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PL080_CONTROL_PROT_SYS),
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},
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.lli_buses = PL08X_AHB1,
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.mem_buses = PL08X_AHB1,
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.get_xfer_signal = pl08x_get_xfer_signal,
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.put_xfer_signal = pl08x_put_xfer_signal,
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.slave_channels = s3c64xx_dma1_info,
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.num_slave_channels = ARRAY_SIZE(s3c64xx_dma1_info),
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};
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static AMBA_AHB_DEVICE(s3c64xx_dma1, "dma-pl080s.1", 0,
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0x75100000, {IRQ_DMA1}, &s3c64xx_dma1_plat_data);
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static int __init s3c64xx_pl080_init(void)
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{
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/* Set all DMA configuration to be DMA, not SDMA */
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writel(0xffffff, S3C64XX_SDMA_SEL);
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if (of_have_populated_dt())
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return 0;
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amba_device_register(&s3c64xx_dma0_device, &iomem_resource);
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amba_device_register(&s3c64xx_dma1_device, &iomem_resource);
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return 0;
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}
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arch_initcall(s3c64xx_pl080_init);
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