mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
34
arch/arm/mach-s5pv210/Kconfig
Normal file
34
arch/arm/mach-s5pv210/Kconfig
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@ -0,0 +1,34 @@
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# arch/arm/mach-s5pv210/Kconfig
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#
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# Copyright (c) 2010 Samsung Electronics Co., Ltd.
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# http://www.samsung.com/
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#
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# Licensed under GPLv2
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# Configuration options for the S5PV210/S5PC110
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config ARCH_S5PV210
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bool "Samsung S5PV210/S5PC110" if ARCH_MULTI_V7
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select ARCH_HAS_HOLES_MEMORYMODEL
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select ARCH_REQUIRE_GPIOLIB
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select ARM_VIC
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select CLKSRC_SAMSUNG_PWM
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select COMMON_CLK_SAMSUNG
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select HAVE_S3C2410_I2C if I2C
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select HAVE_S3C2410_WATCHDOG if WATCHDOG
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select HAVE_S3C_RTC if RTC_CLASS
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select PINCTRL
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select PINCTRL_EXYNOS
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help
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Samsung S5PV210/S5PC110 series based systems
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if ARCH_S5PV210
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config CPU_S5PV210
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def_bool y
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select ARM_AMBA
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select PL330_DMA if DMADEVICES
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help
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Enable S5PV210 CPU support
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endif
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16
arch/arm/mach-s5pv210/Makefile
Normal file
16
arch/arm/mach-s5pv210/Makefile
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@ -0,0 +1,16 @@
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# arch/arm/mach-s5pv210/Makefile
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#
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# Copyright (c) 2010 Samsung Electronics Co., Ltd.
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# http://www.samsung.com/
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#
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# Licensed under GPLv2
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ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include
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# Core
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obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
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# machine support
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obj-y += s5pv210.o
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23
arch/arm/mach-s5pv210/common.h
Normal file
23
arch/arm/mach-s5pv210/common.h
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@ -0,0 +1,23 @@
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/*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Common Header for S5PV210 machines
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_MACH_S5PV210_COMMON_H
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#define __ARCH_ARM_MACH_S5PV210_COMMON_H
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#ifdef CONFIG_PM_SLEEP
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u32 exynos_get_eint_wake_mask(void);
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void s5pv210_cpu_resume(void);
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void s5pv210_pm_init(void);
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#else
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static inline void s5pv210_pm_init(void) {}
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#endif
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#endif /* __ARCH_ARM_MACH_S5PV210_COMMON_H */
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179
arch/arm/mach-s5pv210/pm.c
Normal file
179
arch/arm/mach-s5pv210/pm.c
Normal file
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@ -0,0 +1,179 @@
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/* linux/arch/arm/mach-s5pv210/pm.c
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*
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* Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5PV210 - Power Management support
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*
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* Based on arch/arm/mach-s3c2410/pm.c
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/syscore_ops.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/suspend.h>
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#include <plat/pm-common.h>
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#include "common.h"
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#include "regs-clock.h"
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static struct sleep_save s5pv210_core_save[] = {
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/* Clock ETC */
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SAVE_ITEM(S5P_MDNIE_SEL),
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};
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/*
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* VIC wake-up support (TODO)
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*/
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static u32 s5pv210_irqwake_intmask = 0xffffffff;
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/*
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* Suspend helpers.
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*/
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static int s5pv210_cpu_suspend(unsigned long arg)
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{
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unsigned long tmp;
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/* issue the standby signal into the pm unit. Note, we
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* issue a write-buffer drain just in case */
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tmp = 0;
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asm("b 1f\n\t"
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".align 5\n\t"
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"1:\n\t"
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"mcr p15, 0, %0, c7, c10, 5\n\t"
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"mcr p15, 0, %0, c7, c10, 4\n\t"
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"wfi" : : "r" (tmp));
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pr_info("Failed to suspend the system\n");
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return 1; /* Aborting suspend */
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}
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static void s5pv210_pm_prepare(void)
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{
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unsigned int tmp;
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/* Set wake-up mask registers */
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__raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
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__raw_writel(s5pv210_irqwake_intmask, S5P_WAKEUP_MASK);
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/* ensure at least INFORM0 has the resume address */
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__raw_writel(virt_to_phys(s5pv210_cpu_resume), S5P_INFORM0);
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tmp = __raw_readl(S5P_SLEEP_CFG);
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tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
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__raw_writel(tmp, S5P_SLEEP_CFG);
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/* WFI for SLEEP mode configuration by SYSCON */
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tmp = __raw_readl(S5P_PWR_CFG);
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tmp &= S5P_CFG_WFI_CLEAN;
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tmp |= S5P_CFG_WFI_SLEEP;
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__raw_writel(tmp, S5P_PWR_CFG);
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/* SYSCON interrupt handling disable */
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tmp = __raw_readl(S5P_OTHERS);
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tmp |= S5P_OTHER_SYSC_INTOFF;
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__raw_writel(tmp, S5P_OTHERS);
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s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
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}
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/*
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* Suspend operations.
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*/
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static int s5pv210_suspend_enter(suspend_state_t state)
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{
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int ret;
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s3c_pm_debug_init();
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S3C_PMDBG("%s: suspending the system...\n", __func__);
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S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
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s5pv210_irqwake_intmask, exynos_get_eint_wake_mask());
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if (s5pv210_irqwake_intmask == -1U
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&& exynos_get_eint_wake_mask() == -1U) {
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pr_err("%s: No wake-up sources!\n", __func__);
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pr_err("%s: Aborting sleep\n", __func__);
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return -EINVAL;
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}
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s3c_pm_save_uarts();
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s5pv210_pm_prepare();
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flush_cache_all();
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s3c_pm_check_store();
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ret = cpu_suspend(0, s5pv210_cpu_suspend);
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if (ret)
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return ret;
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s3c_pm_restore_uarts();
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S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
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__raw_readl(S5P_WAKEUP_STAT));
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s3c_pm_check_restore();
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S3C_PMDBG("%s: resuming the system...\n", __func__);
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return 0;
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}
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static int s5pv210_suspend_prepare(void)
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{
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s3c_pm_check_prepare();
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return 0;
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}
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static void s5pv210_suspend_finish(void)
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{
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s3c_pm_check_cleanup();
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}
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static const struct platform_suspend_ops s5pv210_suspend_ops = {
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.enter = s5pv210_suspend_enter,
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.prepare = s5pv210_suspend_prepare,
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.finish = s5pv210_suspend_finish,
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.valid = suspend_valid_only_mem,
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};
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/*
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* Syscore operations used to delay restore of certain registers.
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*/
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static void s5pv210_pm_resume(void)
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{
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u32 tmp;
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tmp = __raw_readl(S5P_OTHERS);
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tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF |\
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S5P_OTHERS_RET_MMC | S5P_OTHERS_RET_UART);
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__raw_writel(tmp , S5P_OTHERS);
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s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
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}
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static struct syscore_ops s5pv210_pm_syscore_ops = {
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.resume = s5pv210_pm_resume,
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};
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/*
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* Initialization entry point.
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*/
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void __init s5pv210_pm_init(void)
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{
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register_syscore_ops(&s5pv210_pm_syscore_ops);
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suspend_set_ops(&s5pv210_suspend_ops);
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}
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201
arch/arm/mach-s5pv210/regs-clock.h
Normal file
201
arch/arm/mach-s5pv210/regs-clock.h
Normal file
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@ -0,0 +1,201 @@
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/*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5PV210 - Clock register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
|
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_CLOCK_H
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#define __ASM_ARCH_REGS_CLOCK_H __FILE__
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#include <plat/map-base.h>
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#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
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#define S5P_APLL_LOCK S5P_CLKREG(0x00)
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#define S5P_MPLL_LOCK S5P_CLKREG(0x08)
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#define S5P_EPLL_LOCK S5P_CLKREG(0x10)
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#define S5P_VPLL_LOCK S5P_CLKREG(0x20)
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#define S5P_APLL_CON S5P_CLKREG(0x100)
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#define S5P_MPLL_CON S5P_CLKREG(0x108)
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#define S5P_EPLL_CON S5P_CLKREG(0x110)
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#define S5P_EPLL_CON1 S5P_CLKREG(0x114)
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#define S5P_VPLL_CON S5P_CLKREG(0x120)
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#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
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#define S5P_CLK_SRC1 S5P_CLKREG(0x204)
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#define S5P_CLK_SRC2 S5P_CLKREG(0x208)
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#define S5P_CLK_SRC3 S5P_CLKREG(0x20C)
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#define S5P_CLK_SRC4 S5P_CLKREG(0x210)
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#define S5P_CLK_SRC5 S5P_CLKREG(0x214)
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#define S5P_CLK_SRC6 S5P_CLKREG(0x218)
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#define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x280)
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#define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x284)
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#define S5P_CLK_DIV0 S5P_CLKREG(0x300)
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#define S5P_CLK_DIV1 S5P_CLKREG(0x304)
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#define S5P_CLK_DIV2 S5P_CLKREG(0x308)
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#define S5P_CLK_DIV3 S5P_CLKREG(0x30C)
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#define S5P_CLK_DIV4 S5P_CLKREG(0x310)
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#define S5P_CLK_DIV5 S5P_CLKREG(0x314)
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#define S5P_CLK_DIV6 S5P_CLKREG(0x318)
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#define S5P_CLK_DIV7 S5P_CLKREG(0x31C)
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|
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#define S5P_CLKGATE_MAIN0 S5P_CLKREG(0x400)
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#define S5P_CLKGATE_MAIN1 S5P_CLKREG(0x404)
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#define S5P_CLKGATE_MAIN2 S5P_CLKREG(0x408)
|
||||
|
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#define S5P_CLKGATE_PERI0 S5P_CLKREG(0x420)
|
||||
#define S5P_CLKGATE_PERI1 S5P_CLKREG(0x424)
|
||||
|
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#define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x440)
|
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#define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x444)
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||||
#define S5P_CLKGATE_IP0 S5P_CLKREG(0x460)
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#define S5P_CLKGATE_IP1 S5P_CLKREG(0x464)
|
||||
#define S5P_CLKGATE_IP2 S5P_CLKREG(0x468)
|
||||
#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C)
|
||||
#define S5P_CLKGATE_IP4 S5P_CLKREG(0x470)
|
||||
|
||||
#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x480)
|
||||
#define S5P_CLKGATE_BUS0 S5P_CLKREG(0x484)
|
||||
#define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488)
|
||||
#define S5P_CLK_OUT S5P_CLKREG(0x500)
|
||||
|
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/* DIV/MUX STATUS */
|
||||
#define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1000)
|
||||
#define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1004)
|
||||
#define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1100)
|
||||
#define S5P_CLKMUX_STAT1 S5P_CLKREG(0x1104)
|
||||
|
||||
/* CLKSRC0 */
|
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#define S5P_CLKSRC0_MUX200_SHIFT (16)
|
||||
#define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT)
|
||||
#define S5P_CLKSRC0_MUX166_MASK (0x1<<20)
|
||||
#define S5P_CLKSRC0_MUX133_MASK (0x1<<24)
|
||||
|
||||
/* CLKSRC2 */
|
||||
#define S5P_CLKSRC2_G3D_SHIFT (0)
|
||||
#define S5P_CLKSRC2_G3D_MASK (0x3 << S5P_CLKSRC2_G3D_SHIFT)
|
||||
#define S5P_CLKSRC2_MFC_SHIFT (4)
|
||||
#define S5P_CLKSRC2_MFC_MASK (0x3 << S5P_CLKSRC2_MFC_SHIFT)
|
||||
|
||||
/* CLKSRC6*/
|
||||
#define S5P_CLKSRC6_ONEDRAM_SHIFT (24)
|
||||
#define S5P_CLKSRC6_ONEDRAM_MASK (0x3 << S5P_CLKSRC6_ONEDRAM_SHIFT)
|
||||
|
||||
/* CLKDIV0 */
|
||||
#define S5P_CLKDIV0_APLL_SHIFT (0)
|
||||
#define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT)
|
||||
#define S5P_CLKDIV0_A2M_SHIFT (4)
|
||||
#define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT)
|
||||
#define S5P_CLKDIV0_HCLK200_SHIFT (8)
|
||||
#define S5P_CLKDIV0_HCLK200_MASK (0x7 << S5P_CLKDIV0_HCLK200_SHIFT)
|
||||
#define S5P_CLKDIV0_PCLK100_SHIFT (12)
|
||||
#define S5P_CLKDIV0_PCLK100_MASK (0x7 << S5P_CLKDIV0_PCLK100_SHIFT)
|
||||
#define S5P_CLKDIV0_HCLK166_SHIFT (16)
|
||||
#define S5P_CLKDIV0_HCLK166_MASK (0xF << S5P_CLKDIV0_HCLK166_SHIFT)
|
||||
#define S5P_CLKDIV0_PCLK83_SHIFT (20)
|
||||
#define S5P_CLKDIV0_PCLK83_MASK (0x7 << S5P_CLKDIV0_PCLK83_SHIFT)
|
||||
#define S5P_CLKDIV0_HCLK133_SHIFT (24)
|
||||
#define S5P_CLKDIV0_HCLK133_MASK (0xF << S5P_CLKDIV0_HCLK133_SHIFT)
|
||||
#define S5P_CLKDIV0_PCLK66_SHIFT (28)
|
||||
#define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT)
|
||||
|
||||
/* CLKDIV2 */
|
||||
#define S5P_CLKDIV2_G3D_SHIFT (0)
|
||||
#define S5P_CLKDIV2_G3D_MASK (0xF << S5P_CLKDIV2_G3D_SHIFT)
|
||||
#define S5P_CLKDIV2_MFC_SHIFT (4)
|
||||
#define S5P_CLKDIV2_MFC_MASK (0xF << S5P_CLKDIV2_MFC_SHIFT)
|
||||
|
||||
/* CLKDIV6 */
|
||||
#define S5P_CLKDIV6_ONEDRAM_SHIFT (28)
|
||||
#define S5P_CLKDIV6_ONEDRAM_MASK (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT)
|
||||
|
||||
#define S5P_SWRESET S5P_CLKREG(0x2000)
|
||||
|
||||
#define S5P_ARM_MCS_CON S5P_CLKREG(0x6100)
|
||||
|
||||
/* Registers related to power management */
|
||||
#define S5P_PWR_CFG S5P_CLKREG(0xC000)
|
||||
#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004)
|
||||
#define S5P_WAKEUP_MASK S5P_CLKREG(0xC008)
|
||||
#define S5P_PWR_MODE S5P_CLKREG(0xC00C)
|
||||
#define S5P_NORMAL_CFG S5P_CLKREG(0xC010)
|
||||
#define S5P_IDLE_CFG S5P_CLKREG(0xC020)
|
||||
#define S5P_STOP_CFG S5P_CLKREG(0xC030)
|
||||
#define S5P_STOP_MEM_CFG S5P_CLKREG(0xC034)
|
||||
#define S5P_SLEEP_CFG S5P_CLKREG(0xC040)
|
||||
|
||||
#define S5P_OSC_FREQ S5P_CLKREG(0xC100)
|
||||
#define S5P_OSC_STABLE S5P_CLKREG(0xC104)
|
||||
#define S5P_PWR_STABLE S5P_CLKREG(0xC108)
|
||||
#define S5P_MTC_STABLE S5P_CLKREG(0xC110)
|
||||
#define S5P_CLAMP_STABLE S5P_CLKREG(0xC114)
|
||||
|
||||
#define S5P_WAKEUP_STAT S5P_CLKREG(0xC200)
|
||||
#define S5P_BLK_PWR_STAT S5P_CLKREG(0xC204)
|
||||
|
||||
#define S5P_OTHERS S5P_CLKREG(0xE000)
|
||||
#define S5P_OM_STAT S5P_CLKREG(0xE100)
|
||||
#define S5P_HDMI_PHY_CONTROL S5P_CLKREG(0xE804)
|
||||
#define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C)
|
||||
#define S5P_DAC_PHY_CONTROL S5P_CLKREG(0xE810)
|
||||
|
||||
#define S5P_INFORM0 S5P_CLKREG(0xF000)
|
||||
#define S5P_INFORM1 S5P_CLKREG(0xF004)
|
||||
#define S5P_INFORM2 S5P_CLKREG(0xF008)
|
||||
#define S5P_INFORM3 S5P_CLKREG(0xF00C)
|
||||
#define S5P_INFORM4 S5P_CLKREG(0xF010)
|
||||
#define S5P_INFORM5 S5P_CLKREG(0xF014)
|
||||
#define S5P_INFORM6 S5P_CLKREG(0xF018)
|
||||
#define S5P_INFORM7 S5P_CLKREG(0xF01C)
|
||||
|
||||
#define S5P_RST_STAT S5P_CLKREG(0xA000)
|
||||
#define S5P_OSC_CON S5P_CLKREG(0x8000)
|
||||
#define S5P_MDNIE_SEL S5P_CLKREG(0x7008)
|
||||
#define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200)
|
||||
#define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204)
|
||||
|
||||
#define S5P_IDLE_CFG_TL_MASK (3 << 30)
|
||||
#define S5P_IDLE_CFG_TM_MASK (3 << 28)
|
||||
#define S5P_IDLE_CFG_TL_ON (2 << 30)
|
||||
#define S5P_IDLE_CFG_TM_ON (2 << 28)
|
||||
#define S5P_IDLE_CFG_DIDLE (1 << 0)
|
||||
|
||||
#define S5P_CFG_WFI_CLEAN (~(3 << 8))
|
||||
#define S5P_CFG_WFI_IDLE (1 << 8)
|
||||
#define S5P_CFG_WFI_STOP (2 << 8)
|
||||
#define S5P_CFG_WFI_SLEEP (3 << 8)
|
||||
|
||||
#define S5P_OTHER_SYS_INT 24
|
||||
#define S5P_OTHER_STA_TYPE 23
|
||||
#define S5P_OTHER_SYSC_INTOFF (1 << 0)
|
||||
#define STA_TYPE_EXPON 0
|
||||
#define STA_TYPE_SFR 1
|
||||
|
||||
#define S5P_PWR_STA_EXP_SCALE 0
|
||||
#define S5P_PWR_STA_CNT 4
|
||||
|
||||
#define S5P_PWR_STABLE_COUNT 85500
|
||||
|
||||
#define S5P_SLEEP_CFG_OSC_EN (1 << 0)
|
||||
#define S5P_SLEEP_CFG_USBOSC_EN (1 << 1)
|
||||
|
||||
/* OTHERS Resgister */
|
||||
#define S5P_OTHERS_RET_IO (1 << 31)
|
||||
#define S5P_OTHERS_RET_CF (1 << 30)
|
||||
#define S5P_OTHERS_RET_MMC (1 << 29)
|
||||
#define S5P_OTHERS_RET_UART (1 << 28)
|
||||
#define S5P_OTHERS_USB_SIG_MASK (1 << 16)
|
||||
|
||||
/* S5P_DAC_CONTROL */
|
||||
#define S5P_DAC_ENABLE (1)
|
||||
#define S5P_DAC_DISABLE (0)
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_CLOCK_H */
|
||||
77
arch/arm/mach-s5pv210/s5pv210.c
Normal file
77
arch/arm/mach-s5pv210/s5pv210.c
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* Samsung's S5PC110/S5PV210 flattened device tree enabled machine.
|
||||
*
|
||||
* Copyright (c) 2013-2014 Samsung Electronics Co., Ltd.
|
||||
* Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
|
||||
* Tomasz Figa <t.figa@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/system_misc.h>
|
||||
|
||||
#include <plat/map-base.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "regs-clock.h"
|
||||
|
||||
static int __init s5pv210_fdt_map_sys(unsigned long node, const char *uname,
|
||||
int depth, void *data)
|
||||
{
|
||||
struct map_desc iodesc;
|
||||
const __be32 *reg;
|
||||
int len;
|
||||
|
||||
if (!of_flat_dt_is_compatible(node, "samsung,s5pv210-clock"))
|
||||
return 0;
|
||||
|
||||
reg = of_get_flat_dt_prop(node, "reg", &len);
|
||||
if (reg == NULL || len != (sizeof(unsigned long) * 2))
|
||||
return 0;
|
||||
|
||||
iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
|
||||
iodesc.length = be32_to_cpu(reg[1]) - 1;
|
||||
iodesc.virtual = (unsigned long)S3C_VA_SYS;
|
||||
iodesc.type = MT_DEVICE;
|
||||
iotable_init(&iodesc, 1);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void __init s5pv210_dt_map_io(void)
|
||||
{
|
||||
debug_ll_io_init();
|
||||
|
||||
of_scan_flat_dt(s5pv210_fdt_map_sys, NULL);
|
||||
}
|
||||
|
||||
static void s5pv210_dt_restart(enum reboot_mode mode, const char *cmd)
|
||||
{
|
||||
__raw_writel(0x1, S5P_SWRESET);
|
||||
}
|
||||
|
||||
static void __init s5pv210_dt_init_late(void)
|
||||
{
|
||||
platform_device_register_simple("s5pv210-cpufreq", -1, NULL, 0);
|
||||
s5pv210_pm_init();
|
||||
}
|
||||
|
||||
static char const *s5pv210_dt_compat[] __initconst = {
|
||||
"samsung,s5pc110",
|
||||
"samsung,s5pv210",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(S5PV210_DT, "Samsung S5PC110/S5PV210-based board")
|
||||
.dt_compat = s5pv210_dt_compat,
|
||||
.map_io = s5pv210_dt_map_io,
|
||||
.restart = s5pv210_dt_restart,
|
||||
.init_late = s5pv210_dt_init_late,
|
||||
MACHINE_END
|
||||
36
arch/arm/mach-s5pv210/sleep.S
Normal file
36
arch/arm/mach-s5pv210/sleep.S
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV210 Sleep Code
|
||||
* Based on S3C64XX sleep code by:
|
||||
* Ben Dooks, (c) 2008 Simtec Electronics
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
|
||||
.data
|
||||
.align
|
||||
|
||||
/*
|
||||
* sleep magic, to allow the bootloader to check for an valid
|
||||
* image to resume to. Must be the first word before the
|
||||
* s3c_cpu_resume entry.
|
||||
*/
|
||||
|
||||
.word 0x2bedf00d
|
||||
|
||||
/*
|
||||
* s3c_cpu_resume
|
||||
*
|
||||
* resume code entry for bootloader to call
|
||||
*/
|
||||
|
||||
ENTRY(s5pv210_cpu_resume)
|
||||
b cpu_resume
|
||||
ENDPROC(s5pv210_cpu_resume)
|
||||
Loading…
Add table
Add a link
Reference in a new issue