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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
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Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
368
arch/arm/mach-versatile/pci.c
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368
arch/arm/mach-versatile/pci.c
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/*
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* linux/arch/arm/mach-versatile/pci.c
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*
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* (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
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* You can redistribute and/or modify this software under the terms of version 2
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* of the GNU General Public License as published by the Free Software Foundation.
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* THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
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* WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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* Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
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*
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* ARM Versatile PCI driver.
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*
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* 14/04/2005 Initial version, colin.king@philips.com
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*
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#include <asm/irq.h>
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#include <asm/mach/pci.h>
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/*
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* these spaces are mapped using the following base registers:
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*
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* Usage Local Bus Memory Base/Map registers used
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*
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* Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0, non prefetch
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* Mem 60000000 - 6FFFFFFF LB_BASE1/LB_MAP1, prefetch
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* IO 44000000 - 4FFFFFFF LB_BASE2/LB_MAP2, IO
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* Cfg 42000000 - 42FFFFFF PCI config
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*
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*/
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#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
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#define SYS_PCICTL __IO_ADDRESS(VERSATILE_SYS_PCICTL)
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#define PCI_IMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
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#define PCI_IMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
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#define PCI_IMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
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#define PCI_SMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
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#define PCI_SMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
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#define PCI_SMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x1c)
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#define PCI_SELFID __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
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#define DEVICE_ID_OFFSET 0x00
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#define CSR_OFFSET 0x04
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#define CLASS_ID_OFFSET 0x08
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#define VP_PCI_DEVICE_ID 0x030010ee
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#define VP_PCI_CLASS_ID 0x0b400000
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static unsigned long pci_slot_ignore = 0;
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static int __init versatile_pci_slot_ignore(char *str)
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{
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int retval;
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int slot;
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while ((retval = get_option(&str,&slot))) {
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if ((slot < 0) || (slot > 31)) {
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printk("Illegal slot value: %d\n",slot);
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} else {
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pci_slot_ignore |= (1 << slot);
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}
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}
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return 1;
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}
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__setup("pci_slot_ignore=", versatile_pci_slot_ignore);
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static void __iomem *__pci_addr(struct pci_bus *bus,
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unsigned int devfn, int offset)
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{
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unsigned int busnr = bus->number;
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/*
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* Trap out illegal values
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*/
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if (offset > 255)
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BUG();
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if (busnr > 255)
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BUG();
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if (devfn > 255)
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BUG();
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return VERSATILE_PCI_CFG_VIRT_BASE + ((busnr << 16) |
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(PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset);
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}
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static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *val)
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{
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void __iomem *addr = __pci_addr(bus, devfn, where & ~3);
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u32 v;
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int slot = PCI_SLOT(devfn);
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if (pci_slot_ignore & (1 << slot)) {
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/* Ignore this slot */
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switch (size) {
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case 1:
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v = 0xff;
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break;
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case 2:
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v = 0xffff;
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break;
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default:
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v = 0xffffffff;
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}
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} else {
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switch (size) {
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case 1:
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v = __raw_readl(addr);
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if (where & 2) v >>= 16;
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if (where & 1) v >>= 8;
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v &= 0xff;
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break;
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case 2:
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v = __raw_readl(addr);
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if (where & 2) v >>= 16;
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v &= 0xffff;
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break;
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default:
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v = __raw_readl(addr);
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break;
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}
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}
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*val = v;
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return PCIBIOS_SUCCESSFUL;
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}
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static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 val)
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{
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void __iomem *addr = __pci_addr(bus, devfn, where);
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int slot = PCI_SLOT(devfn);
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if (pci_slot_ignore & (1 << slot)) {
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return PCIBIOS_SUCCESSFUL;
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}
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switch (size) {
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case 1:
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__raw_writeb((u8)val, addr);
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break;
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case 2:
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__raw_writew((u16)val, addr);
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break;
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case 4:
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__raw_writel(val, addr);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops pci_versatile_ops = {
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.read = versatile_read_config,
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.write = versatile_write_config,
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};
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static struct resource unused_mem = {
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.name = "PCI unused",
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.start = VERSATILE_PCI_MEM_BASE0,
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.end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
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.flags = IORESOURCE_MEM,
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};
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static struct resource non_mem = {
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.name = "PCI non-prefetchable",
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.start = VERSATILE_PCI_MEM_BASE1,
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.end = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
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.flags = IORESOURCE_MEM,
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};
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static struct resource pre_mem = {
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.name = "PCI prefetchable",
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.start = VERSATILE_PCI_MEM_BASE2,
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.end = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
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.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
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};
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static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
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{
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int ret = 0;
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ret = request_resource(&iomem_resource, &unused_mem);
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if (ret) {
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printk(KERN_ERR "PCI: unable to allocate unused "
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"memory region (%d)\n", ret);
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goto out;
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}
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ret = request_resource(&iomem_resource, &non_mem);
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if (ret) {
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printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
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"memory region (%d)\n", ret);
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goto release_unused_mem;
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}
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ret = request_resource(&iomem_resource, &pre_mem);
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if (ret) {
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printk(KERN_ERR "PCI: unable to allocate prefetchable "
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"memory region (%d)\n", ret);
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goto release_non_mem;
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}
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/*
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* the mem resource for this bus
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* the prefetch mem resource for this bus
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*/
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pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
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pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
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goto out;
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release_non_mem:
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release_resource(&non_mem);
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release_unused_mem:
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release_resource(&unused_mem);
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out:
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return ret;
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}
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int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
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{
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int ret = 0;
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int i;
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int myslot = -1;
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unsigned long val;
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void __iomem *local_pci_cfg_base;
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val = __raw_readl(SYS_PCICTL);
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if (!(val & 1)) {
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printk("Not plugged into PCI backplane!\n");
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ret = -EIO;
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goto out;
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}
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ret = pci_ioremap_io(0, VERSATILE_PCI_IO_BASE);
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if (ret)
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goto out;
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if (nr == 0) {
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ret = pci_versatile_setup_resources(sys);
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if (ret < 0) {
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printk("pci_versatile_setup: resources... oops?\n");
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goto out;
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}
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} else {
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printk("pci_versatile_setup: resources... nr == 0??\n");
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goto out;
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}
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/*
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* We need to discover the PCI core first to configure itself
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* before the main PCI probing is performed
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*/
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for (i=0; i<32; i++)
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if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
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(__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
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myslot = i;
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break;
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}
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if (myslot == -1) {
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printk("Cannot find PCI core!\n");
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ret = -EIO;
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goto out;
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}
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printk("PCI core found (slot %d)\n",myslot);
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__raw_writel(myslot, PCI_SELFID);
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local_pci_cfg_base = VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11);
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val = __raw_readl(local_pci_cfg_base + CSR_OFFSET);
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val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
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__raw_writel(val, local_pci_cfg_base + CSR_OFFSET);
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/*
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* Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
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*/
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__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
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__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
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__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);
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/*
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* For many years the kernel and QEMU were symbiotically buggy
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* in that they both assumed the same broken IRQ mapping.
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* QEMU therefore attempts to auto-detect old broken kernels
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* so that they still work on newer QEMU as they did on old
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* QEMU. Since we now use the correct (ie matching-hardware)
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* IRQ mapping we write a definitely different value to a
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* PCI_INTERRUPT_LINE register to tell QEMU that we expect
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* real hardware behaviour and it need not be backwards
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* compatible for us. This write is harmless on real hardware.
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*/
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__raw_writel(0, VERSATILE_PCI_VIRT_BASE+PCI_INTERRUPT_LINE);
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/*
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* Do not to map Versatile FPGA PCI device into memory space
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*/
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pci_slot_ignore |= (1 << myslot);
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ret = 1;
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out:
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return ret;
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}
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void __init pci_versatile_preinit(void)
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{
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pcibios_min_mem = 0x50000000;
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__raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
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__raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
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__raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);
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__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0);
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__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1);
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__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP2);
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__raw_writel(1, SYS_PCICTL);
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}
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/*
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* map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
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*/
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static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq;
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/*
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* Slot INTA INTB INTC INTD
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* 31 PCI1 PCI2 PCI3 PCI0
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* 30 PCI0 PCI1 PCI2 PCI3
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* 29 PCI3 PCI0 PCI1 PCI2
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*/
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irq = IRQ_SIC_PCI0 + ((slot + 2 + pin - 1) & 3);
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return irq;
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}
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static struct hw_pci versatile_pci __initdata = {
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.map_irq = versatile_map_irq,
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.nr_controllers = 1,
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.ops = &pci_versatile_ops,
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.setup = pci_versatile_setup,
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.preinit = pci_versatile_preinit,
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};
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static int __init versatile_pci_init(void)
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{
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pci_common_init(&versatile_pci);
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return 0;
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}
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subsys_initcall(versatile_pci_init);
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