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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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26
arch/arm/mach-w90x900/include/mach/entry-macro.S Normal file
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/*
* arch/arm/mach-w90x900/include/mach/entry-macro.S
*
* Low-level IRQ helper macros for W90P910-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
*/
#include <mach/hardware.h>
#include <mach/regs-irq.h>
.macro get_irqnr_preamble, base, tmp
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \base, #AIC_BA
ldr \irqnr, [\base, #AIC_IPER]
ldr \irqnr, [\base, #AIC_ISNR]
cmp \irqnr, #0
.endm

24
arch/arm/mach-w90x900/include/mach/hardware.h Normal file
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/*
* arch/arm/mach-w90x900/include/mach/hardware.h
*
* Copyright (c) 2008 Nuvoton technology corporation
* All rights reserved.
*
* Wan ZongShun <mcuos.com@gmail.com>
*
* Based on arch/arm/mach-s3c2410/include/mach/hardware.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/sizes.h>
#include <mach/map.h>
#endif /* __ASM_ARCH_HARDWARE_H */

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arch/arm/mach-w90x900/include/mach/irqs.h Normal file
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/*
* arch/arm/mach-w90x900/include/mach/irqs.h
*
* Copyright (c) 2008 Nuvoton technology corporation.
*
* Wan ZongShun <mcuos.com@gmail.com>
*
* Based on arch/arm/mach-s3c2410/include/mach/irqs.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation;version 2 of the License.
*
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
/*
* we keep the first set of CPU IRQs out of the range of
* the ISA space, so that the PC104 has them to itself
* and we don't end up having to do horrible things to the
* standard ISA drivers....
*
*/
#define W90X900_IRQ(x) (x)
/* Main cpu interrupts */
#define IRQ_WDT W90X900_IRQ(1)
#define IRQ_GROUP0 W90X900_IRQ(2)
#define IRQ_GROUP1 W90X900_IRQ(3)
#define IRQ_ACTL W90X900_IRQ(4)
#define IRQ_LCD W90X900_IRQ(5)
#define IRQ_RTC W90X900_IRQ(6)
#define IRQ_UART0 W90X900_IRQ(7)
#define IRQ_UART1 W90X900_IRQ(8)
#define IRQ_UART2 W90X900_IRQ(9)
#define IRQ_UART3 W90X900_IRQ(10)
#define IRQ_UART4 W90X900_IRQ(11)
#define IRQ_TIMER0 W90X900_IRQ(12)
#define IRQ_TIMER1 W90X900_IRQ(13)
#define IRQ_T_INT_GROUP W90X900_IRQ(14)
#define IRQ_USBH W90X900_IRQ(15)
#define IRQ_EMCTX W90X900_IRQ(16)
#define IRQ_EMCRX W90X900_IRQ(17)
#define IRQ_GDMAGROUP W90X900_IRQ(18)
#define IRQ_DMAC W90X900_IRQ(19)
#define IRQ_FMI W90X900_IRQ(20)
#define IRQ_USBD W90X900_IRQ(21)
#define IRQ_ATAPI W90X900_IRQ(22)
#define IRQ_G2D W90X900_IRQ(23)
#define IRQ_PCI W90X900_IRQ(24)
#define IRQ_SCGROUP W90X900_IRQ(25)
#define IRQ_I2CGROUP W90X900_IRQ(26)
#define IRQ_SSP W90X900_IRQ(27)
#define IRQ_PWM W90X900_IRQ(28)
#define IRQ_KPI W90X900_IRQ(29)
#define IRQ_P2SGROUP W90X900_IRQ(30)
#define IRQ_ADC W90X900_IRQ(31)
#define NR_IRQS (IRQ_ADC+1)
/*for irq group*/
#define IRQ_PS2_PORT0 0x10000000
#define IRQ_PS2_PORT1 0x20000000
#define IRQ_I2C_LINE0 0x04000000
#define IRQ_I2C_LINE1 0x08000000
#define IRQ_SC_CARD0 0x01000000
#define IRQ_SC_CARD1 0x02000000
#define IRQ_GDMA_CH0 0x00100000
#define IRQ_GDMA_CH1 0x00200000
#define IRQ_TIMER2 0x00010000
#define IRQ_TIMER3 0x00020000
#define IRQ_TIMER4 0x00040000
#define IRQ_GROUP0_IRQ0 0x00000001
#define IRQ_GROUP0_IRQ1 0x00000002
#define IRQ_GROUP0_IRQ2 0x00000004
#define IRQ_GROUP0_IRQ3 0x00000008
#define IRQ_GROUP1_IRQ4 0x00000010
#define IRQ_GROUP1_IRQ5 0x00000020
#define IRQ_GROUP1_IRQ6 0x00000040
#define IRQ_GROUP1_IRQ7 0x00000080
#endif /* __ASM_ARCH_IRQ_H */

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arch/arm/mach-w90x900/include/mach/map.h Normal file
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/*
* arch/arm/mach-w90x900/include/mach/map.h
*
* Copyright (c) 2008 Nuvoton technology corporation.
*
* Wan ZongShun <mcuos.com@gmail.com>
*
* Based on arch/arm/mach-s3c2410/include/mach/map.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation;version 2 of the License.
*
*/
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H
#ifndef __ASSEMBLY__
#define W90X900_ADDR(x) ((void __iomem *)(0xF0000000 + (x)))
#else
#define W90X900_ADDR(x) (0xF0000000 + (x))
#endif
#define AHB_IO_BASE 0xB0000000
#define APB_IO_BASE 0xB8000000
#define CLOCKPW_BASE (APB_IO_BASE+0x200)
#define AIC_IO_BASE (APB_IO_BASE+0x2000)
#define TIMER_IO_BASE (APB_IO_BASE+0x1000)
/*
* interrupt controller is the first thing we put in, to make
* the assembly code for the irq detection easier
*/
#define W90X900_VA_IRQ W90X900_ADDR(0x00000000)
#define W90X900_PA_IRQ (0xB8002000)
#define W90X900_SZ_IRQ SZ_4K
#define W90X900_VA_GCR W90X900_ADDR(0x08002000)
#define W90X900_PA_GCR (0xB0000000)
#define W90X900_SZ_GCR SZ_4K
/* Clock and Power management */
#define W90X900_VA_CLKPWR (W90X900_VA_GCR+0x200)
#define W90X900_PA_CLKPWR (0xB0000200)
#define W90X900_SZ_CLKPWR SZ_4K
/* EBI management */
#define W90X900_VA_EBI W90X900_ADDR(0x00001000)
#define W90X900_PA_EBI (0xB0001000)
#define W90X900_SZ_EBI SZ_4K
/* UARTs */
#define W90X900_VA_UART W90X900_ADDR(0x08000000)
#define W90X900_PA_UART (0xB8000000)
#define W90X900_SZ_UART SZ_4K
/* Timers */
#define W90X900_VA_TIMER W90X900_ADDR(0x08001000)
#define W90X900_PA_TIMER (0xB8001000)
#define W90X900_SZ_TIMER SZ_4K
/* GPIO ports */
#define W90X900_VA_GPIO W90X900_ADDR(0x08003000)
#define W90X900_PA_GPIO (0xB8003000)
#define W90X900_SZ_GPIO SZ_4K
/* GDMA control */
#define W90X900_VA_GDMA W90X900_ADDR(0x00004000)
#define W90X900_PA_GDMA (0xB0004000)
#define W90X900_SZ_GDMA SZ_4K
/* USB host controller*/
#define W90X900_VA_USBEHCIHOST W90X900_ADDR(0x00005000)
#define W90X900_PA_USBEHCIHOST (0xB0005000)
#define W90X900_SZ_USBEHCIHOST SZ_4K
#define W90X900_VA_USBOHCIHOST W90X900_ADDR(0x00007000)
#define W90X900_PA_USBOHCIHOST (0xB0007000)
#define W90X900_SZ_USBOHCIHOST SZ_4K
/* I2C hardware controller */
#define W90X900_VA_I2C W90X900_ADDR(0x08006000)
#define W90X900_PA_I2C (0xB8006000)
#define W90X900_SZ_I2C SZ_4K
/* Keypad Interface*/
#define W90X900_VA_KPI W90X900_ADDR(0x08008000)
#define W90X900_PA_KPI (0xB8008000)
#define W90X900_SZ_KPI SZ_4K
/* Smart card host*/
#define W90X900_VA_SC W90X900_ADDR(0x08005000)
#define W90X900_PA_SC (0xB8005000)
#define W90X900_SZ_SC SZ_4K
/* LCD controller*/
#define W90X900_VA_LCD W90X900_ADDR(0x00008000)
#define W90X900_PA_LCD (0xB0008000)
#define W90X900_SZ_LCD SZ_4K
/* 2D controller*/
#define W90X900_VA_GE W90X900_ADDR(0x0000B000)
#define W90X900_PA_GE (0xB000B000)
#define W90X900_SZ_GE SZ_4K
/* ATAPI */
#define W90X900_VA_ATAPI W90X900_ADDR(0x0000A000)
#define W90X900_PA_ATAPI (0xB000A000)
#define W90X900_SZ_ATAPI SZ_4K
/* ADC */
#define W90X900_VA_ADC W90X900_ADDR(0x0800A000)
#define W90X900_PA_ADC (0xB800A000)
#define W90X900_SZ_ADC SZ_4K
/* PS2 Interface*/
#define W90X900_VA_PS2 W90X900_ADDR(0x08009000)
#define W90X900_PA_PS2 (0xB8009000)
#define W90X900_SZ_PS2 SZ_4K
/* RTC */
#define W90X900_VA_RTC W90X900_ADDR(0x08004000)
#define W90X900_PA_RTC (0xB8004000)
#define W90X900_SZ_RTC SZ_4K
/* Pulse Width Modulation(PWM) Registers */
#define W90X900_VA_PWM W90X900_ADDR(0x08007000)
#define W90X900_PA_PWM (0xB8007000)
#define W90X900_SZ_PWM SZ_4K
/* Audio Controller controller */
#define W90X900_VA_ACTL W90X900_ADDR(0x00009000)
#define W90X900_PA_ACTL (0xB0009000)
#define W90X900_SZ_ACTL SZ_4K
/* DMA controller */
#define W90X900_VA_DMA W90X900_ADDR(0x0000c000)
#define W90X900_PA_DMA (0xB000c000)
#define W90X900_SZ_DMA SZ_4K
/* FMI controller */
#define W90X900_VA_FMI W90X900_ADDR(0x0000d000)
#define W90X900_PA_FMI (0xB000d000)
#define W90X900_SZ_FMI SZ_4K
/* USB Device port */
#define W90X900_VA_USBDEV W90X900_ADDR(0x00006000)
#define W90X900_PA_USBDEV (0xB0006000)
#define W90X900_SZ_USBDEV SZ_4K
/* External MAC control*/
#define W90X900_VA_EMC W90X900_ADDR(0x00003000)
#define W90X900_PA_EMC (0xB0003000)
#define W90X900_SZ_EMC SZ_4K
#endif /* __ASM_ARCH_MAP_H */

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arch/arm/mach-w90x900/include/mach/mfp.h Normal file
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/*
* arch/arm/mach-w90x900/include/mach/mfp.h
*
* Copyright (c) 2010 Nuvoton technology corporation.
*
* Wan ZongShun <mcuos.com@gmail.com>
*
* Based on arch/arm/mach-s3c2410/include/mach/map.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation;version 2 of the License.
*
*/
#ifndef __ASM_ARCH_MFP_H
#define __ASM_ARCH_MFP_H
extern void mfp_set_groupf(struct device *dev);
extern void mfp_set_groupc(struct device *dev);
extern void mfp_set_groupi(struct device *dev);
extern void mfp_set_groupg(struct device *dev, const char *subname);
extern void mfp_set_groupd(struct device *dev, const char *subname);
#endif /* __ASM_ARCH_MFP_H */

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arch/arm/mach-w90x900/include/mach/regs-clock.h Normal file
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/*
* arch/arm/mach-w90x900/include/mach/regs-clock.h
*
* Copyright (c) 2008 Nuvoton technology corporation.
*
* Wan ZongShun <mcuos.com@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation;version 2 of the License.
*
*/
#ifndef __ASM_ARCH_REGS_CLOCK_H
#define __ASM_ARCH_REGS_CLOCK_H
/* Clock Control Registers */
#define CLK_BA W90X900_VA_CLKPWR
#define REG_CLKEN (CLK_BA + 0x00)
#define REG_CLKSEL (CLK_BA + 0x04)
#define REG_CLKDIV (CLK_BA + 0x08)
#define REG_PLLCON0 (CLK_BA + 0x0C)
#define REG_PLLCON1 (CLK_BA + 0x10)
#define REG_PMCON (CLK_BA + 0x14)
#define REG_IRQWAKECON (CLK_BA + 0x18)
#define REG_IRQWAKEFLAG (CLK_BA + 0x1C)
#define REG_IPSRST (CLK_BA + 0x20)
#define REG_CLKEN1 (CLK_BA + 0x24)
#define REG_CLKDIV1 (CLK_BA + 0x28)
/* Define PLL freq setting */
#define PLL_DISABLE 0x12B63
#define PLL_66MHZ 0x2B63
#define PLL_100MHZ 0x4F64
#define PLL_120MHZ 0x4F63
#define PLL_166MHZ 0x4124
#define PLL_200MHZ 0x4F24
/* Define AHB:CPUFREQ ratio */
#define AHB_CPUCLK_1_1 0x00
#define AHB_CPUCLK_1_2 0x01
#define AHB_CPUCLK_1_4 0x02
#define AHB_CPUCLK_1_8 0x03
/* Define APB:AHB ratio */
#define APB_AHB_1_2 0x01
#define APB_AHB_1_4 0x02
#define APB_AHB_1_8 0x03
/* Define clock skew */
#define DEFAULTSKEW 0x48
#endif /* __ASM_ARCH_REGS_CLOCK_H */

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arch/arm/mach-w90x900/include/mach/regs-ebi.h Normal file
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/*
* arch/arm/mach-w90x900/include/mach/regs-ebi.h
*
* Copyright (c) 2009 Nuvoton technology corporation.
*
* Wan ZongShun <mcuos.com@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation;version 2 of the License.
*
*/
#ifndef __ASM_ARCH_REGS_EBI_H
#define __ASM_ARCH_REGS_EBI_H
/* EBI Control Registers */
#define EBI_BA W90X900_VA_EBI
#define REG_EBICON (EBI_BA + 0x00)
#define REG_ROMCON (EBI_BA + 0x04)
#define REG_SDCONF0 (EBI_BA + 0x08)
#define REG_SDCONF1 (EBI_BA + 0x0C)
#define REG_SDTIME0 (EBI_BA + 0x10)
#define REG_SDTIME1 (EBI_BA + 0x14)
#define REG_EXT0CON (EBI_BA + 0x18)
#define REG_EXT1CON (EBI_BA + 0x1C)
#define REG_EXT2CON (EBI_BA + 0x20)
#define REG_EXT3CON (EBI_BA + 0x24)
#define REG_EXT4CON (EBI_BA + 0x28)
#define REG_CKSKEW (EBI_BA + 0x2C)
#endif /* __ASM_ARCH_REGS_EBI_H */

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arch/arm/mach-w90x900/include/mach/regs-gcr.h Normal file
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/*
* arch/arm/mach-w90x900/include/mach/regs-gcr.h
*
* Copyright (c) 2010 Nuvoton technology corporation
* All rights reserved.
*
* Wan ZongShun <mcuos.com@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_REGS_GCR_H
#define __ASM_ARCH_REGS_GCR_H
/* Global control registers */
#define GCR_BA W90X900_VA_GCR
#define REG_PDID (GCR_BA+0x000)
#define REG_PWRON (GCR_BA+0x004)
#define REG_ARBCON (GCR_BA+0x008)
#define REG_MFSEL (GCR_BA+0x00C)
#define REG_EBIDPE (GCR_BA+0x010)
#define REG_LCDDPE (GCR_BA+0x014)
#define REG_GPIOCPE (GCR_BA+0x018)
#define REG_GPIODPE (GCR_BA+0x01C)
#define REG_GPIOEPE (GCR_BA+0x020)
#define REG_GPIOFPE (GCR_BA+0x024)
#define REG_GPIOGPE (GCR_BA+0x028)
#define REG_GPIOHPE (GCR_BA+0x02C)
#define REG_GPIOIPE (GCR_BA+0x030)
#define REG_GTMP1 (GCR_BA+0x034)
#define REG_GTMP2 (GCR_BA+0x038)
#define REG_GTMP3 (GCR_BA+0x03C)
#endif /* __ASM_ARCH_REGS_GCR_H */

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arch/arm/mach-w90x900/include/mach/regs-irq.h Normal file
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/*
* arch/arm/mach-w90x900/include/mach/regs-irq.h
*
* Copyright (c) 2008 Nuvoton technology corporation
* All rights reserved.
*
* Wan ZongShun <mcuos.com@gmail.com>
*
* Based on arch/arm/mach-s3c2410/include/mach/regs-irq.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef ___ASM_ARCH_REGS_IRQ_H
#define ___ASM_ARCH_REGS_IRQ_H
/* Advance Interrupt Controller (AIC) Registers */
#define AIC_BA W90X900_VA_IRQ
#define REG_AIC_IRQSC (AIC_BA+0x80)
#define REG_AIC_GEN (AIC_BA+0x84)
#define REG_AIC_GASR (AIC_BA+0x88)
#define REG_AIC_GSCR (AIC_BA+0x8C)
#define REG_AIC_IRSR (AIC_BA+0x100)
#define REG_AIC_IASR (AIC_BA+0x104)
#define REG_AIC_ISR (AIC_BA+0x108)
#define REG_AIC_IPER (AIC_BA+0x10C)
#define REG_AIC_ISNR (AIC_BA+0x110)
#define REG_AIC_IMR (AIC_BA+0x114)
#define REG_AIC_OISR (AIC_BA+0x118)
#define REG_AIC_MECR (AIC_BA+0x120)
#define REG_AIC_MDCR (AIC_BA+0x124)
#define REG_AIC_SSCR (AIC_BA+0x128)
#define REG_AIC_SCCR (AIC_BA+0x12C)
#define REG_AIC_EOSCR (AIC_BA+0x130)
#define AIC_IPER (0x10C)
#define AIC_ISNR (0x110)
/*16-18 bits of REG_AIC_GEN define irq(2-4) group*/
#define TIMER2_IRQ (1 << 16)
#define TIMER3_IRQ (1 << 17)
#define TIMER4_IRQ (1 << 18)
#define TIME_GROUP_IRQ (TIMER2_IRQ|TIMER3_IRQ|TIMER4_IRQ)
#endif /* ___ASM_ARCH_REGS_IRQ_H */

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arch/arm/mach-w90x900/include/mach/regs-ldm.h Normal file
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/*
* arch/arm/mach-w90x900/include/mach/regs-serial.h
*
* Copyright (c) 2009 Nuvoton technology corporation
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* Description:
* Nuvoton Display, LCM Register list
* Author: Wang Qiang (rurality.linux@gmail.com) 2009/12/11
*
*/
#ifndef __ASM_ARM_W90X900_REGS_LDM_H
#define __ASM_ARM_W90X900_REGS_LDM_H
#include <mach/map.h>
/* Display Controller Control/Status Register */
#define REG_LCM_DCCS (0x00)
#define LCM_DCCS_ENG_RST (1 << 0)
#define LCM_DCCS_VA_EN (1 << 1)
#define LCM_DCCS_OSD_EN (1 << 2)
#define LCM_DCCS_DISP_OUT_EN (1 << 3)
#define LCM_DCCS_DISP_INT_EN (1 << 4)
#define LCM_DCCS_CMD_ON (1 << 5)
#define LCM_DCCS_FIELD_INTR (1 << 6)
#define LCM_DCCS_SINGLE (1 << 7)
enum LCM_DCCS_VA_SRC {
LCM_DCCS_VA_SRC_YUV422 = (0 << 8),
LCM_DCCS_VA_SRC_YCBCR422 = (1 << 8),
LCM_DCCS_VA_SRC_RGB888 = (2 << 8),
LCM_DCCS_VA_SRC_RGB666 = (3 << 8),
LCM_DCCS_VA_SRC_RGB565 = (4 << 8),
LCM_DCCS_VA_SRC_RGB444LOW = (5 << 8),
LCM_DCCS_VA_SRC_RGB444HIGH = (7 << 8)
};
/* Display Device Control Register */
#define REG_LCM_DEV_CTRL (0x04)
enum LCM_DEV_CTRL_SWAP_YCbCr {
LCM_DEV_CTRL_SWAP_UYVY = (0 << 1),
LCM_DEV_CTRL_SWAP_YUYV = (1 << 1),
LCM_DEV_CTRL_SWAP_VYUY = (2 << 1),
LCM_DEV_CTRL_SWAP_YVYU = (3 << 1)
};
enum LCM_DEV_CTRL_RGB_SHIFT {
LCM_DEV_CTRL_RGB_SHIFT_NOT = (0 << 3),
LCM_DEV_CTRL_RGB_SHIFT_ONECYCLE = (1 << 3),
LCM_DEV_CTRL_RGB_SHIFT_TWOCYCLE = (2 << 3),
LCM_DEV_CTRL_RGB_SHIFT_NOT_DEF = (3 << 3)
};
enum LCM_DEV_CTRL_DEVICE {
LCM_DEV_CTRL_DEVICE_YUV422 = (0 << 5),
LCM_DEV_CTRL_DEVICE_YUV444 = (1 << 5),
LCM_DEV_CTRL_DEVICE_UNIPAC = (4 << 5),
LCM_DEV_CTRL_DEVICE_SEIKO_EPSON = (5 << 5),
LCM_DEV_CTRL_DEVICE_HIGH_COLOR = (6 << 5),
LCM_DEV_CTRL_DEVICE_MPU = (7 << 5)
};
#define LCM_DEV_CTRL_LCD_DDA (8)
#define LCM_DEV_CTRL_YUV2CCIR (16)
enum LCM_DEV_CTRL_LCD_SEL {
LCM_DEV_CTRL_LCD_SEL_RGB_GBR = (0 << 17),
LCM_DEV_CTRL_LCD_SEL_BGR_RBG = (1 << 17),
LCM_DEV_CTRL_LCD_SEL_GBR_RGB = (2 << 17),
LCM_DEV_CTRL_LCD_SEL_RBG_BGR = (3 << 17)
};
enum LCM_DEV_CTRL_FAL_D {
LCM_DEV_CTRL_FAL_D_FALLING = (0 << 19),
LCM_DEV_CTRL_FAL_D_RISING = (1 << 19),
};
enum LCM_DEV_CTRL_H_POL {
LCM_DEV_CTRL_H_POL_LOW = (0 << 20),
LCM_DEV_CTRL_H_POL_HIGH = (1 << 20),
};
enum LCM_DEV_CTRL_V_POL {
LCM_DEV_CTRL_V_POL_LOW = (0 << 21),
LCM_DEV_CTRL_V_POL_HIGH = (1 << 21),
};
enum LCM_DEV_CTRL_VR_LACE {
LCM_DEV_CTRL_VR_LACE_NINTERLACE = (0 << 22),
LCM_DEV_CTRL_VR_LACE_INTERLACE = (1 << 22),
};
enum LCM_DEV_CTRL_LACE {
LCM_DEV_CTRL_LACE_NINTERLACE = (0 << 23),
LCM_DEV_CTRL_LACE_INTERLACE = (1 << 23),
};
enum LCM_DEV_CTRL_RGB_SCALE {
LCM_DEV_CTRL_RGB_SCALE_4096 = (0 << 24),
LCM_DEV_CTRL_RGB_SCALE_65536 = (1 << 24),
LCM_DEV_CTRL_RGB_SCALE_262144 = (2 << 24),
LCM_DEV_CTRL_RGB_SCALE_16777216 = (3 << 24),
};
enum LCM_DEV_CTRL_DBWORD {
LCM_DEV_CTRL_DBWORD_HALFWORD = (0 << 26),
LCM_DEV_CTRL_DBWORD_FULLWORD = (1 << 26),
};
enum LCM_DEV_CTRL_MPU68 {
LCM_DEV_CTRL_MPU68_80_SERIES = (0 << 27),
LCM_DEV_CTRL_MPU68_68_SERIES = (1 << 27),
};
enum LCM_DEV_CTRL_DE_POL {
LCM_DEV_CTRL_DE_POL_HIGH = (0 << 28),
LCM_DEV_CTRL_DE_POL_LOW = (1 << 28),
};
#define LCM_DEV_CTRL_CMD16 (29)
#define LCM_DEV_CTRL_CM16t18 (30)
#define LCM_DEV_CTRL_CMD_LOW (31)
/* MPU-Interface LCD Write Command */
#define REG_LCM_MPU_CMD (0x08)
/* Interrupt Control/Status Register */
#define REG_LCM_INT_CS (0x0c)
#define LCM_INT_CS_DISP_F_EN (1 << 0)
#define LCM_INT_CS_UNDERRUN_EN (1 << 1)
#define LCM_INT_CS_BUS_ERROR_INT (1 << 28)
#define LCM_INT_CS_UNDERRUN_INT (1 << 29)
#define LCM_INT_CS_DISP_F_STATUS (1 << 30)
#define LCM_INT_CS_DISP_F_INT (1 << 31)
/* CRTC Display Size Control Register */
#define REG_LCM_CRTC_SIZE (0x10)
#define LCM_CRTC_SIZE_VTTVAL(x) ((x) << 16)
#define LCM_CRTC_SIZE_HTTVAL(x) ((x) << 0)
/* CRTC Display Enable End */
#define REG_LCM_CRTC_DEND (0x14)
#define LCM_CRTC_DEND_VDENDVAL(x) ((x) << 16)
#define LCM_CRTC_DEND_HDENDVAL(x) ((x) << 0)
/* CRTC Internal Horizontal Retrace Control Register */
#define REG_LCM_CRTC_HR (0x18)
#define LCM_CRTC_HR_EVAL(x) ((x) << 16)
#define LCM_CRTC_HR_SVAL(x) ((x) << 0)
/* CRTC Horizontal Sync Control Register */
#define REG_LCM_CRTC_HSYNC (0x1C)
#define LCM_CRTC_HSYNC_SHIFTVAL(x) ((x) << 30)
#define LCM_CRTC_HSYNC_EVAL(x) ((x) << 16)
#define LCM_CRTC_HSYNC_SVAL(x) ((x) << 0)
/* CRTC Internal Vertical Retrace Control Register */
#define REG_LCM_CRTC_VR (0x20)
#define LCM_CRTC_VR_EVAL(x) ((x) << 16)
#define LCM_CRTC_VR_SVAL(x) ((x) << 0)
/* Video Stream Frame Buffer-0 Starting Address */
#define REG_LCM_VA_BADDR0 (0x24)
/* Video Stream Frame Buffer-1 Starting Address */
#define REG_LCM_VA_BADDR1 (0x28)
/* Video Stream Frame Buffer Control Register */
#define REG_LCM_VA_FBCTRL (0x2C)
#define LCM_VA_FBCTRL_IO_REGION_HALF (1 << 28)
#define LCM_VA_FBCTRL_FIELD_DUAL (1 << 29)
#define LCM_VA_FBCTRL_START_BUF (1 << 30)
#define LCM_VA_FBCTRL_DB_EN (1 << 31)
/* Video Stream Scaling Control Register */
#define REG_LCM_VA_SCALE (0x30)
#define LCM_VA_SCALE_XCOPY_INTERPOLATION (0 << 15)
#define LCM_VA_SCALE_XCOPY_DUPLICATION (1 << 15)
/* Image Stream Active Window Coordinates */
#define REG_LCM_VA_WIN (0x38)
/* Image Stream Stuff Pixel */
#define REG_LCM_VA_STUFF (0x3C)
/* OSD Window Starting Coordinates */
#define REG_LCM_OSD_WINS (0x40)
/* OSD Window Ending Coordinates */
#define REG_LCM_OSD_WINE (0x44)
/* OSD Stream Frame Buffer Starting Address */
#define REG_LCM_OSD_BADDR (0x48)
/* OSD Stream Frame Buffer Control Register */
#define REG_LCM_OSD_FBCTRL (0x4c)
/* OSD Overlay Control Register */
#define REG_LCM_OSD_OVERLAY (0x50)
/* OSD Overlay Color-Key Pattern Register */
#define REG_LCM_OSD_CKEY (0x54)
/* OSD Overlay Color-Key Mask Register */
#define REG_LCM_OSD_CMASK (0x58)
/* OSD Window Skip1 Register */
#define REG_LCM_OSD_SKIP1 (0x5C)
/* OSD Window Skip2 Register */
#define REG_LCM_OSD_SKIP2 (0x60)
/* OSD horizontal up scaling control register */
#define REG_LCM_OSD_SCALE (0x64)
/* MPU Vsync control register */
#define REG_LCM_MPU_VSYNC (0x68)
/* Hardware cursor control Register */
#define REG_LCM_HC_CTRL (0x6C)
/* Hardware cursot tip point potison on va picture */
#define REG_LCM_HC_POS (0x70)
/* Hardware Cursor Window Buffer Control Register */
#define REG_LCM_HC_WBCTRL (0x74)
/* Hardware cursor memory base address register */
#define REG_LCM_HC_BADDR (0x78)
/* Hardware cursor color ram register mapped to bpp = 0 */
#define REG_LCM_HC_COLOR0 (0x7C)
/* Hardware cursor color ram register mapped to bpp = 1 */
#define REG_LCM_HC_COLOR1 (0x80)
/* Hardware cursor color ram register mapped to bpp = 2 */
#define REG_LCM_HC_COLOR2 (0x84)
/* Hardware cursor color ram register mapped to bpp = 3 */
#define REG_LCM_HC_COLOR3 (0x88)
#endif /* __ASM_ARM_W90X900_REGS_LDM_H */

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/*
* arch/arm/mach-w90x900/include/mach/regs-serial.h
*
* Copyright (c) 2008 Nuvoton technology corporation
* All rights reserved.
*
* Wan ZongShun <mcuos.com@gmail.com>
*
* Based on arch/arm/mach-s3c2410/include/mach/regs-serial.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARM_REGS_SERIAL_H
#define __ASM_ARM_REGS_SERIAL_H
#define UART0_BA W90X900_VA_UART
#define UART1_BA (W90X900_VA_UART+0x100)
#define UART2_BA (W90X900_VA_UART+0x200)
#define UART3_BA (W90X900_VA_UART+0x300)
#define UART4_BA (W90X900_VA_UART+0x400)
#define UART0_PA W90X900_PA_UART
#define UART1_PA (W90X900_PA_UART+0x100)
#define UART2_PA (W90X900_PA_UART+0x200)
#define UART3_PA (W90X900_PA_UART+0x300)
#define UART4_PA (W90X900_PA_UART+0x400)
#ifndef __ASSEMBLY__
struct w90x900_uart_clksrc {
const char *name;
unsigned int divisor;
unsigned int min_baud;
unsigned int max_baud;
};
struct w90x900_uartcfg {
unsigned char hwport;
unsigned char unused;
unsigned short flags;
unsigned long uart_flags;
unsigned long ucon;
unsigned long ulcon;
unsigned long ufcon;
struct w90x900_uart_clksrc *clocks;
unsigned int clocks_size;
};
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARM_REGS_SERIAL_H */

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/*
* arch/arm/mach-w90x900/include/mach/regs-timer.h
*
* Copyright (c) 2008 Nuvoton technology corporation
* All rights reserved.
*
* Wan ZongShun <mcuos.com@gmail.com>
*
* Based on arch/arm/mach-s3c2410/include/mach/regs-timer.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_REGS_TIMER_H
#define __ASM_ARCH_REGS_TIMER_H
/* Timer Registers */
#define TMR_BA W90X900_VA_TIMER
#define REG_TCSR0 (TMR_BA+0x00)
#define REG_TCSR1 (TMR_BA+0x04)
#define REG_TICR0 (TMR_BA+0x08)
#define REG_TICR1 (TMR_BA+0x0C)
#define REG_TDR0 (TMR_BA+0x10)
#define REG_TDR1 (TMR_BA+0x14)
#define REG_TISR (TMR_BA+0x18)
#define REG_WTCR (TMR_BA+0x1C)
#define REG_TCSR2 (TMR_BA+0x20)
#define REG_TCSR3 (TMR_BA+0x24)
#define REG_TICR2 (TMR_BA+0x28)
#define REG_TICR3 (TMR_BA+0x2C)
#define REG_TDR2 (TMR_BA+0x30)
#define REG_TDR3 (TMR_BA+0x34)
#define REG_TCSR4 (TMR_BA+0x40)
#define REG_TICR4 (TMR_BA+0x48)
#define REG_TDR4 (TMR_BA+0x50)
#endif /* __ASM_ARCH_REGS_TIMER_H */

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arch/arm/mach-w90x900/include/mach/regs-usb.h Normal file
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/*
* arch/arm/mach-w90x900/include/mach/regs-usb.h
*
* Copyright (c) 2008 Nuvoton technology corporation.
*
* Wan ZongShun <mcuos.com@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation;version 2 of the License.
*
*/
#ifndef __ASM_ARCH_REGS_USB_H
#define __ASM_ARCH_REGS_USB_H
/* usb Control Registers */
#define USBH_BA W90X900_VA_USBEHCIHOST
#define USBD_BA W90X900_VA_USBDEV
#define USBO_BA W90X900_VA_USBOHCIHOST
/* USB Host Control Registers */
#define REG_UPSCR0 (USBH_BA+0x064)
#define REG_UPSCR1 (USBH_BA+0x068)
#define REG_USBPCR0 (USBH_BA+0x0C4)
#define REG_USBPCR1 (USBH_BA+0x0C8)
/* USBH OHCI Control Registers */
#define REG_OpModEn (USBO_BA+0x204)
/*This bit controls the polarity of over
*current flag from external power IC.
*/
#define OCALow 0x08
#endif /* __ASM_ARCH_REGS_USB_H */

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/*
* arch/arm/mach-w90x900/include/mach/uncompress.h
*
* Copyright (c) 2008 Nuvoton technology corporation
* All rights reserved.
*
* Wan ZongShun <mcuos.com@gmail.com>
*
* Based on arch/arm/mach-s3c2410/include/mach/uncompress.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
/* Defines for UART registers */
#include <mach/regs-serial.h>
#include <mach/map.h>
#include <linux/serial_reg.h>
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
static volatile u32 * const uart_base = (u32 *)UART0_PA;
static void putc(int ch)
{
/* Check THRE and TEMT bits before we transmit the character.
*/
while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
barrier();
*uart_base = ch;
}
static inline void flush(void)
{
}
static void arch_decomp_setup(void)
{
}
#endif/* __ASM_W90X900_UNCOMPRESS_H */