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synced 2025-09-11 01:42:44 -04:00
Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
157
arch/arm/mach-w90x900/include/mach/map.h
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157
arch/arm/mach-w90x900/include/mach/map.h
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/*
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* arch/arm/mach-w90x900/include/mach/map.h
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*
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* Copyright (c) 2008 Nuvoton technology corporation.
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*
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* Wan ZongShun <mcuos.com@gmail.com>
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*
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* Based on arch/arm/mach-s3c2410/include/mach/map.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation;version 2 of the License.
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*
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*/
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#ifndef __ASM_ARCH_MAP_H
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#define __ASM_ARCH_MAP_H
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#ifndef __ASSEMBLY__
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#define W90X900_ADDR(x) ((void __iomem *)(0xF0000000 + (x)))
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#else
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#define W90X900_ADDR(x) (0xF0000000 + (x))
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#endif
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#define AHB_IO_BASE 0xB0000000
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#define APB_IO_BASE 0xB8000000
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#define CLOCKPW_BASE (APB_IO_BASE+0x200)
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#define AIC_IO_BASE (APB_IO_BASE+0x2000)
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#define TIMER_IO_BASE (APB_IO_BASE+0x1000)
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/*
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* interrupt controller is the first thing we put in, to make
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* the assembly code for the irq detection easier
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*/
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#define W90X900_VA_IRQ W90X900_ADDR(0x00000000)
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#define W90X900_PA_IRQ (0xB8002000)
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#define W90X900_SZ_IRQ SZ_4K
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#define W90X900_VA_GCR W90X900_ADDR(0x08002000)
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#define W90X900_PA_GCR (0xB0000000)
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#define W90X900_SZ_GCR SZ_4K
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/* Clock and Power management */
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#define W90X900_VA_CLKPWR (W90X900_VA_GCR+0x200)
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#define W90X900_PA_CLKPWR (0xB0000200)
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#define W90X900_SZ_CLKPWR SZ_4K
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/* EBI management */
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#define W90X900_VA_EBI W90X900_ADDR(0x00001000)
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#define W90X900_PA_EBI (0xB0001000)
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#define W90X900_SZ_EBI SZ_4K
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/* UARTs */
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#define W90X900_VA_UART W90X900_ADDR(0x08000000)
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#define W90X900_PA_UART (0xB8000000)
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#define W90X900_SZ_UART SZ_4K
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/* Timers */
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#define W90X900_VA_TIMER W90X900_ADDR(0x08001000)
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#define W90X900_PA_TIMER (0xB8001000)
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#define W90X900_SZ_TIMER SZ_4K
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/* GPIO ports */
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#define W90X900_VA_GPIO W90X900_ADDR(0x08003000)
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#define W90X900_PA_GPIO (0xB8003000)
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#define W90X900_SZ_GPIO SZ_4K
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/* GDMA control */
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#define W90X900_VA_GDMA W90X900_ADDR(0x00004000)
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#define W90X900_PA_GDMA (0xB0004000)
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#define W90X900_SZ_GDMA SZ_4K
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/* USB host controller*/
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#define W90X900_VA_USBEHCIHOST W90X900_ADDR(0x00005000)
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#define W90X900_PA_USBEHCIHOST (0xB0005000)
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#define W90X900_SZ_USBEHCIHOST SZ_4K
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#define W90X900_VA_USBOHCIHOST W90X900_ADDR(0x00007000)
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#define W90X900_PA_USBOHCIHOST (0xB0007000)
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#define W90X900_SZ_USBOHCIHOST SZ_4K
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/* I2C hardware controller */
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#define W90X900_VA_I2C W90X900_ADDR(0x08006000)
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#define W90X900_PA_I2C (0xB8006000)
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#define W90X900_SZ_I2C SZ_4K
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/* Keypad Interface*/
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#define W90X900_VA_KPI W90X900_ADDR(0x08008000)
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#define W90X900_PA_KPI (0xB8008000)
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#define W90X900_SZ_KPI SZ_4K
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/* Smart card host*/
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#define W90X900_VA_SC W90X900_ADDR(0x08005000)
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#define W90X900_PA_SC (0xB8005000)
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#define W90X900_SZ_SC SZ_4K
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/* LCD controller*/
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#define W90X900_VA_LCD W90X900_ADDR(0x00008000)
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#define W90X900_PA_LCD (0xB0008000)
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#define W90X900_SZ_LCD SZ_4K
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/* 2D controller*/
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#define W90X900_VA_GE W90X900_ADDR(0x0000B000)
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#define W90X900_PA_GE (0xB000B000)
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#define W90X900_SZ_GE SZ_4K
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/* ATAPI */
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#define W90X900_VA_ATAPI W90X900_ADDR(0x0000A000)
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#define W90X900_PA_ATAPI (0xB000A000)
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#define W90X900_SZ_ATAPI SZ_4K
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/* ADC */
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#define W90X900_VA_ADC W90X900_ADDR(0x0800A000)
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#define W90X900_PA_ADC (0xB800A000)
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#define W90X900_SZ_ADC SZ_4K
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/* PS2 Interface*/
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#define W90X900_VA_PS2 W90X900_ADDR(0x08009000)
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#define W90X900_PA_PS2 (0xB8009000)
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#define W90X900_SZ_PS2 SZ_4K
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/* RTC */
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#define W90X900_VA_RTC W90X900_ADDR(0x08004000)
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#define W90X900_PA_RTC (0xB8004000)
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#define W90X900_SZ_RTC SZ_4K
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/* Pulse Width Modulation(PWM) Registers */
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#define W90X900_VA_PWM W90X900_ADDR(0x08007000)
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#define W90X900_PA_PWM (0xB8007000)
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#define W90X900_SZ_PWM SZ_4K
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/* Audio Controller controller */
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#define W90X900_VA_ACTL W90X900_ADDR(0x00009000)
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#define W90X900_PA_ACTL (0xB0009000)
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#define W90X900_SZ_ACTL SZ_4K
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/* DMA controller */
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#define W90X900_VA_DMA W90X900_ADDR(0x0000c000)
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#define W90X900_PA_DMA (0xB000c000)
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#define W90X900_SZ_DMA SZ_4K
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/* FMI controller */
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#define W90X900_VA_FMI W90X900_ADDR(0x0000d000)
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#define W90X900_PA_FMI (0xB000d000)
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#define W90X900_SZ_FMI SZ_4K
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/* USB Device port */
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#define W90X900_VA_USBDEV W90X900_ADDR(0x00006000)
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#define W90X900_PA_USBDEV (0xB0006000)
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#define W90X900_SZ_USBDEV SZ_4K
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/* External MAC control*/
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#define W90X900_VA_EMC W90X900_ADDR(0x00003000)
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#define W90X900_PA_EMC (0xB0003000)
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#define W90X900_SZ_EMC SZ_4K
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#endif /* __ASM_ARCH_MAP_H */
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