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Fixed MTP to work with TWRP

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This commit is contained in:
awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
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44
arch/arm64/boot/Makefile Normal file
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#
# arch/arm64/boot/Makefile
#
# This file is included by the global makefile so that you can add your own
# architecture-specific flags and dependencies.
#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
# Copyright (C) 2012, ARM Ltd.
# Author: Will Deacon <will.deacon@arm.com>
#
# Based on the ia64 boot/Makefile.
#
include $(srctree)/arch/arm64/boot/dts/Makefile
targets := Image Image.gz
DTB_NAMES := $(subst $\",,$(CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES))
ifneq ($(DTB_NAMES),)
DTB_LIST := $(addsuffix .dtb,$(DTB_NAMES))
else
DTB_LIST := $(dtb-y)
endif
DTB_OBJS := $(addprefix $(obj)/dts/,$(DTB_LIST))
$(obj)/Image: vmlinux FORCE
$(call if_changed,objcopy)
$(obj)/Image.gz: $(obj)/Image FORCE
$(call if_changed,gzip)
$(obj)/Image.gz-dtb: $(obj)/Image.gz $(DTB_OBJS) FORCE
$(call if_changed,cat)
install: $(obj)/Image
$(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
$(obj)/Image System.map "$(INSTALL_PATH)"
zinstall: $(obj)/Image.gz
$(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
$(obj)/Image.gz System.map "$(INSTALL_PATH)"

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arch/arm64/boot/dts/Makefile Normal file
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dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
dtb-$(CONFIG_SOC_EXYNOS8890) += exynos8890-espresso8890.dtb exynos8890-espresso8890_rev01.dtb exynos8890-universal8890.dtb exynos8890-smdk8890.dtb
dtb-$(CONFIG_SOC_EXYNOS8890) += exynos8890-evt1-smdk8890.dtb
dtb-$(CONFIG_SOC_EXYNOS7870) += exynos7870-smdk7870.dtb exynos7870-universal7870.dtb exynos7870-universal7870_rev01.dtb
dtb-$(CONFIG_SOC_EXYNOS7570) += exynos7570-smdk7570.dtb exynos7570-universal7570-IOT-rev02.dtb
targets += dtbs
DTB_NAMES := $(subst $\",,$(CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES))
ifneq ($(DTB_NAMES),)
DTB_LIST := $(addsuffix .dtb,$(DTB_NAMES))
else
DTB_LIST := $(dtb-y)
endif
targets += $(DTB_LIST)
dtbs: $(addprefix $(obj)/, $(DTB_LIST))
clean-files := dts/*.dtb *.dtb

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arch/arm64/boot/dts/apm-mustang.dts Normal file
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/*
* dts file for AppliedMicro (APM) Mustang Board
*
* Copyright (C) 2013, Applied Micro Circuits Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
/dts-v1/;
/include/ "apm-storm.dtsi"
/ {
model = "APM X-Gene Mustang board";
compatible = "apm,mustang", "apm,xgene-storm";
chosen { };
memory {
device_type = "memory";
reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */
};
};
&pcie0clk {
status = "ok";
};
&pcie0 {
status = "ok";
};
&serial0 {
status = "ok";
};
&menet {
status = "ok";
};
&sgenet0 {
status = "ok";
};
&xgenet {
status = "ok";
};

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arch/arm64/boot/dts/apm-storm.dtsi Normal file
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/*
* dts file for AppliedMicro (APM) X-Gene Storm SOC
*
* Copyright (C) 2013, Applied Micro Circuits Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
/ {
compatible = "apm,xgene-storm";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@000 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
reg = <0x0 0x000>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
};
cpu@001 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
reg = <0x0 0x001>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
};
cpu@100 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
};
cpu@101 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
};
cpu@200 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
reg = <0x0 0x200>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
};
cpu@201 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
reg = <0x0 0x201>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
};
cpu@300 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
reg = <0x0 0x300>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
};
cpu@301 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
reg = <0x0 0x301>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
};
};
gic: interrupt-controller@78010000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
<0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
<0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
<0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 0 0xff01>, /* Secure Phys IRQ */
<1 13 0xff01>, /* Non-secure Phys IRQ */
<1 14 0xff01>, /* Virt IRQ */
<1 15 0xff01>; /* Hyp IRQ */
clock-frequency = <50000000>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks {
#address-cells = <2>;
#size-cells = <2>;
ranges;
refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <1>;
clock-frequency = <100000000>;
clock-output-names = "refclk";
};
pcppll: pcppll@17000100 {
compatible = "apm,xgene-pcppll-clock";
#clock-cells = <1>;
clocks = <&refclk 0>;
clock-names = "pcppll";
reg = <0x0 0x17000100 0x0 0x1000>;
clock-output-names = "pcppll";
type = <0>;
};
socpll: socpll@17000120 {
compatible = "apm,xgene-socpll-clock";
#clock-cells = <1>;
clocks = <&refclk 0>;
clock-names = "socpll";
reg = <0x0 0x17000120 0x0 0x1000>;
clock-output-names = "socpll";
type = <1>;
};
socplldiv2: socplldiv2 {
compatible = "fixed-factor-clock";
#clock-cells = <1>;
clocks = <&socpll 0>;
clock-names = "socplldiv2";
clock-mult = <1>;
clock-div = <2>;
clock-output-names = "socplldiv2";
};
qmlclk: qmlclk {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
clock-names = "qmlclk";
reg = <0x0 0x1703C000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "qmlclk";
};
ethclk: ethclk {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
clock-names = "ethclk";
reg = <0x0 0x17000000 0x0 0x1000>;
reg-names = "div-reg";
divider-offset = <0x238>;
divider-width = <0x9>;
divider-shift = <0x0>;
clock-output-names = "ethclk";
};
menetclk: menetclk {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&ethclk 0>;
reg = <0x0 0x1702C000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "menetclk";
};
sge0clk: sge0clk@1f21c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f21c000 0x0 0x1000>;
reg-names = "csr-reg";
csr-mask = <0x3>;
clock-output-names = "sge0clk";
};
xge0clk: xge0clk@1f61c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f61c000 0x0 0x1000>;
reg-names = "csr-reg";
csr-mask = <0x3>;
clock-output-names = "xge0clk";
};
sataphy1clk: sataphy1clk@1f21c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f21c000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "sataphy1clk";
status = "disabled";
csr-offset = <0x4>;
csr-mask = <0x00>;
enable-offset = <0x0>;
enable-mask = <0x06>;
};
sataphy2clk: sataphy1clk@1f22c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f22c000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "sataphy2clk";
status = "ok";
csr-offset = <0x4>;
csr-mask = <0x3a>;
enable-offset = <0x0>;
enable-mask = <0x06>;
};
sataphy3clk: sataphy1clk@1f23c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f23c000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "sataphy3clk";
status = "ok";
csr-offset = <0x4>;
csr-mask = <0x3a>;
enable-offset = <0x0>;
enable-mask = <0x06>;
};
sata01clk: sata01clk@1f21c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f21c000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "sata01clk";
csr-offset = <0x4>;
csr-mask = <0x05>;
enable-offset = <0x0>;
enable-mask = <0x39>;
};
sata23clk: sata23clk@1f22c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f22c000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "sata23clk";
csr-offset = <0x4>;
csr-mask = <0x05>;
enable-offset = <0x0>;
enable-mask = <0x39>;
};
sata45clk: sata45clk@1f23c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f23c000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "sata45clk";
csr-offset = <0x4>;
csr-mask = <0x05>;
enable-offset = <0x0>;
enable-mask = <0x39>;
};
rtcclk: rtcclk@17000000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x17000000 0x0 0x2000>;
reg-names = "csr-reg";
csr-offset = <0xc>;
csr-mask = <0x2>;
enable-offset = <0x10>;
enable-mask = <0x2>;
clock-output-names = "rtcclk";
};
rngpkaclk: rngpkaclk@17000000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x17000000 0x0 0x2000>;
reg-names = "csr-reg";
csr-offset = <0xc>;
csr-mask = <0x10>;
enable-offset = <0x10>;
enable-mask = <0x10>;
clock-output-names = "rngpkaclk";
};
pcie0clk: pcie0clk@1f2bc000 {
status = "disabled";
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f2bc000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "pcie0clk";
};
pcie1clk: pcie1clk@1f2cc000 {
status = "disabled";
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f2cc000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "pcie1clk";
};
pcie2clk: pcie2clk@1f2dc000 {
status = "disabled";
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f2dc000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "pcie2clk";
};
pcie3clk: pcie3clk@1f50c000 {
status = "disabled";
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f50c000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "pcie3clk";
};
pcie4clk: pcie4clk@1f51c000 {
status = "disabled";
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f51c000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "pcie4clk";
};
};
pcie0: pcie@1f2b0000 {
status = "disabled";
device_type = "pci";
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
reg-names = "csr", "cfg";
ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
dma-coherent;
clocks = <&pcie0clk 0>;
};
pcie1: pcie@1f2c0000 {
status = "disabled";
device_type = "pci";
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
reg-names = "csr", "cfg";
ranges = <0x01000000 0x0 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
0x02000000 0x0 0x80000000 0xd1 0x80000000 0x00 0x80000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
dma-coherent;
clocks = <&pcie1clk 0>;
};
pcie2: pcie@1f2d0000 {
status = "disabled";
device_type = "pci";
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
reg-names = "csr", "cfg";
ranges = <0x01000000 0x0 0x00000000 0x90 0x10000000 0x0 0x00010000 /* io */
0x02000000 0x0 0x80000000 0x91 0x80000000 0x0 0x80000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
dma-coherent;
clocks = <&pcie2clk 0>;
};
pcie3: pcie@1f500000 {
status = "disabled";
device_type = "pci";
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
reg-names = "csr", "cfg";
ranges = <0x01000000 0x0 0x00000000 0xa0 0x10000000 0x0 0x00010000 /* io */
0x02000000 0x0 0x80000000 0xa1 0x80000000 0x0 0x80000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
dma-coherent;
clocks = <&pcie3clk 0>;
};
pcie4: pcie@1f510000 {
status = "disabled";
device_type = "pci";
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
reg-names = "csr", "cfg";
ranges = <0x01000000 0x0 0x00000000 0xc0 0x10000000 0x0 0x00010000 /* io */
0x02000000 0x0 0x80000000 0xc1 0x80000000 0x0 0x80000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
dma-coherent;
clocks = <&pcie4clk 0>;
};
serial0: serial@1c020000 {
status = "disabled";
device_type = "serial";
compatible = "ns16550a";
reg = <0 0x1c020000 0x0 0x1000>;
reg-shift = <2>;
clock-frequency = <10000000>; /* Updated by bootloader */
interrupt-parent = <&gic>;
interrupts = <0x0 0x4c 0x4>;
};
serial1: serial@1c021000 {
status = "disabled";
device_type = "serial";
compatible = "ns16550a";
reg = <0 0x1c021000 0x0 0x1000>;
reg-shift = <2>;
clock-frequency = <10000000>; /* Updated by bootloader */
interrupt-parent = <&gic>;
interrupts = <0x0 0x4d 0x4>;
};
serial2: serial@1c022000 {
status = "disabled";
device_type = "serial";
compatible = "ns16550a";
reg = <0 0x1c022000 0x0 0x1000>;
reg-shift = <2>;
clock-frequency = <10000000>; /* Updated by bootloader */
interrupt-parent = <&gic>;
interrupts = <0x0 0x4e 0x4>;
};
serial3: serial@1c023000 {
status = "disabled";
device_type = "serial";
compatible = "ns16550a";
reg = <0 0x1c023000 0x0 0x1000>;
reg-shift = <2>;
clock-frequency = <10000000>; /* Updated by bootloader */
interrupt-parent = <&gic>;
interrupts = <0x0 0x4f 0x4>;
};
phy1: phy@1f21a000 {
compatible = "apm,xgene-phy";
reg = <0x0 0x1f21a000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&sataphy1clk 0>;
status = "disabled";
apm,tx-boost-gain = <30 30 30 30 30 30>;
apm,tx-eye-tuning = <2 10 10 2 10 10>;
};
phy2: phy@1f22a000 {
compatible = "apm,xgene-phy";
reg = <0x0 0x1f22a000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&sataphy2clk 0>;
status = "ok";
apm,tx-boost-gain = <30 30 30 30 30 30>;
apm,tx-eye-tuning = <1 10 10 2 10 10>;
};
phy3: phy@1f23a000 {
compatible = "apm,xgene-phy";
reg = <0x0 0x1f23a000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&sataphy3clk 0>;
status = "ok";
apm,tx-boost-gain = <31 31 31 31 31 31>;
apm,tx-eye-tuning = <2 10 10 2 10 10>;
};
sata1: sata@1a000000 {
compatible = "apm,xgene-ahci";
reg = <0x0 0x1a000000 0x0 0x1000>,
<0x0 0x1f210000 0x0 0x1000>,
<0x0 0x1f21d000 0x0 0x1000>,
<0x0 0x1f21e000 0x0 0x1000>,
<0x0 0x1f217000 0x0 0x1000>;
interrupts = <0x0 0x86 0x4>;
dma-coherent;
status = "disabled";
clocks = <&sata01clk 0>;
phys = <&phy1 0>;
phy-names = "sata-phy";
};
sata2: sata@1a400000 {
compatible = "apm,xgene-ahci";
reg = <0x0 0x1a400000 0x0 0x1000>,
<0x0 0x1f220000 0x0 0x1000>,
<0x0 0x1f22d000 0x0 0x1000>,
<0x0 0x1f22e000 0x0 0x1000>,
<0x0 0x1f227000 0x0 0x1000>;
interrupts = <0x0 0x87 0x4>;
dma-coherent;
status = "ok";
clocks = <&sata23clk 0>;
phys = <&phy2 0>;
phy-names = "sata-phy";
};
sata3: sata@1a800000 {
compatible = "apm,xgene-ahci";
reg = <0x0 0x1a800000 0x0 0x1000>,
<0x0 0x1f230000 0x0 0x1000>,
<0x0 0x1f23d000 0x0 0x1000>,
<0x0 0x1f23e000 0x0 0x1000>;
interrupts = <0x0 0x88 0x4>;
dma-coherent;
status = "ok";
clocks = <&sata45clk 0>;
phys = <&phy3 0>;
phy-names = "sata-phy";
};
rtc: rtc@10510000 {
compatible = "apm,xgene-rtc";
reg = <0x0 0x10510000 0x0 0x400>;
interrupts = <0x0 0x46 0x4>;
#clock-cells = <1>;
clocks = <&rtcclk 0>;
};
menet: ethernet@17020000 {
compatible = "apm,xgene-enet";
status = "disabled";
reg = <0x0 0x17020000 0x0 0xd100>,
<0x0 0X17030000 0x0 0Xc300>,
<0x0 0X10000000 0x0 0X200>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0x3c 0x4>;
dma-coherent;
clocks = <&menetclk 0>;
/* mac address will be overwritten by the bootloader */
local-mac-address = [00 00 00 00 00 00];
phy-connection-type = "rgmii";
phy-handle = <&menetphy>;
mdio {
compatible = "apm,xgene-mdio";
#address-cells = <1>;
#size-cells = <0>;
menetphy: menetphy@3 {
compatible = "ethernet-phy-id001c.c915";
reg = <0x3>;
};
};
};
sgenet0: ethernet@1f210000 {
compatible = "apm,xgene-enet";
status = "disabled";
reg = <0x0 0x1f210000 0x0 0xd100>,
<0x0 0x1f200000 0x0 0Xc300>,
<0x0 0x1B000000 0x0 0X200>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0xA0 0x4>;
dma-coherent;
clocks = <&sge0clk 0>;
local-mac-address = [00 00 00 00 00 00];
phy-connection-type = "sgmii";
};
xgenet: ethernet@1f610000 {
compatible = "apm,xgene-enet";
status = "disabled";
reg = <0x0 0x1f610000 0x0 0xd100>,
<0x0 0x1f600000 0x0 0Xc300>,
<0x0 0x18000000 0x0 0X200>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0x60 0x4>;
dma-coherent;
clocks = <&xge0clk 0>;
/* mac address will be overwritten by the bootloader */
local-mac-address = [00 00 00 00 00 00];
phy-connection-type = "xgmii";
};
rng: rng@10520000 {
compatible = "apm,xgene-rng";
reg = <0x0 0x10520000 0x0 0x100>;
interrupts = <0x0 0x41 0x4>;
clocks = <&rngpkaclk 0>;
};
};
};

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arch/arm64/boot/dts/exynos7570-itm.dtsi Normal file
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/*
* SAMSUNG EXYNOS7570 SoC device tree source
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SAMSUNG EXYNOS7570 SoC device nodes are listed in this file.
* EXYNOS7570 based board files can include this file and provide
* values for board specfic bindings.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
ITM@0 {
compatible = "samsung,exynos-itm";
};
};

1846
arch/arm64/boot/dts/exynos7570-on5xe_common.dtsi Executable file
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170
arch/arm64/boot/dts/exynos7570-on5xelte_battery.dtsi Executable file
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/*
* SAMSUNG UNIVERSAL7570 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
s2mpu06-fuelgauge {
status = "disable";
compatible = "samsung,s2mpu06-fuelgauge";
fuelgauge,fuel_alert_soc = <1>;
fuelgauge,capacity_max = <1000>;
fuelgauge,capacity_max_margin = <70>;
fuelgauge,capacity_min = <0>;
fuelgauge,capacity_calculation_type = <28>;
fuelgauge,type_str = "SDI";
fuelgauge,model_type = <1>;
};
battery {
status = "okay";
pinctrl-names = "default";
compatible = "samsung,sec-battery";
battery,vendor = "SDI SDI";
battery,charger_name = "s2mpu06-charger";
battery,fuelgauge_name = "s2mpu06-fuelgauge";
battery,technology = <2>; /* POWER_SUPPLY_TECHNOLOGY_LION */
battery,chip_vendor = "LSI";
battery,battery_type = <&gpd1 5 0x1>;
battery,temp_adc_type = <1>; /* SEC_BATTERY_ADC_TYPE_AP */
battery,polling_time = <10 30 30 30 3600>;
battery,temp_table_adc = <300 354 412 490 565 661 795 908 1059 1214 1288 1407 1605 1820 2050
2280 2505 2726 2925 3126 3242 3324 3469 3591 3689>;
battery,temp_table_data = <900 850 800 750 700 650 600 550 500 450 430 400 350 300 250
200 150 100 50 0 (-30) (-50) (-100) (-150) (-200)>;
battery,input_current_limit = <1000 460 460 1000 460 900 1000 460 1000 0 820 820 820 1000 1000 0 0 400 700 1000 300 1000 1000 0 1667 1667 1000 1667 80 1800 1667 1400 1000 1000 820 820>;
battery,fast_charging_current = <1200 0 0 1200 460 1200 1000 460 1200 0 1200 1200 1200 1200 1200 0 0 400 700 1200 300 1000 1200 0 2550 2550 1000 2550 80 1800 1000 1400 0 1000 1200 1200>;
battery,full_check_current_1st = <200 0 0 200 200 200 200 200 200 0 200 200 200 200 200 0 0 200 200 200 200 200 200 0 200 200 200 200 0 200 200 200 0 200 200 200>;
battery,full_check_current_2nd = <100 0 0 100 100 100 100 100 100 0 100 100 100 100 100 0 0 100 100 100 100 100 100 0 100 100 100 100 0 100 100 100 0 100 100 100>;
battery,wireless_cc_cv = <86>;
battery,inbat_voltage = <1>;
battery,inbat_voltage_table_adc = <3120 3101 3061 3038 3001 2956 2920 2887 2856 2814
2793 2754 2720 2677 2641 2613 2572 2531 2502 2467 2436>;
battery,inbat_voltage_table_data = <438 435 430 425 420 415 410 405 400 395
390 385 380 375 370 365 360 355 350 345 340>;
battery,adc_check_count = <5>;
battery,cable_check_type = <4>; /* SEC_BATTERY_CABLE_CHECK_PSY */
battery,cable_source_type = <1>; /* SEC_BATTERY_CABLE_SOURCE_EXTERNAL */
battery,polling_type = <1>; /* SEC_BATTERY_MONITOR_ALARM */
battery,monitor_initial_count = <0>;
battery,battery_check_type = <5>; /* SEC_BATTERY_CHECK_CHARGER */
battery,check_count = <0>;
battery,ovp_uvlo_check_type = <3>; /* SEC_BATTERY_OVP_UVLO_CHGPOLLING */
battery,check_adc_max = <1440>;
battery,check_adc_min = <0>;
battery,thermal_source = <2>; /* SEC_BATTERY_THERMAL_SOURCE_ADC */
battery,temp_check_type = <2>; /* SEC_BATTERY_TEMP_CHECK_TEMP */
battery,temp_check_count = <1>;
battery,temp_highlimit_threshold_normal = <800>;
battery,temp_highlimit_recovery_normal = <750>;
battery,temp_high_threshold_normal = <550>;
battery,temp_high_recovery_normal = <500>;
battery,temp_low_threshold_normal = <(-50)>;
battery,temp_low_recovery_normal = <0>;
battery,temp_highlimit_threshold_lpm = <800>;
battery,temp_highlimit_recovery_lpm = <750>;
battery,temp_high_threshold_lpm = <550>;
battery,temp_high_recovery_lpm = <500>;
battery,temp_low_threshold_lpm = <(-50)>;
battery,temp_low_recovery_lpm = <0>;
battery,full_check_type = <7>; /* SEC_BATTERY_FULLCHARGED_CHGPSY */
battery,full_check_type_2nd = <7>; /* SEC_BATTERY_FULLCHARGED_CHGPSY */
battery,full_check_count = <1>;
battery,chg_gpio_full_check = <0>;
battery,chg_polarity_full_check = <1>;
battery,chg_high_temp_1st = <530>;
battery,chg_high_temp_2nd = <530>;
battery,chg_high_temp_recovery = <525>;
battery,chg_charging_limit_current = <1300>;
battery,chg_charging_limit_current_2nd = <1300>;
battery,chg_skip_check_capacity = <10>;
battery,chg_skip_check_time = <600>;
battery,wpc_high_temp = <420>;
battery,wpc_high_temp_recovery = <410>;
battery,wpc_charging_limit_current = <450>;
/* SEC_BATTERY_FULL_CONDITION_SOC |
SEC_BATTERY_FULL_CONDITION_NOTIMEFULL |
SEC_BATTERY_FULL_CONDITION_VCELL */
battery,full_condition_type = <15>;
battery,full_condition_soc = <93>;
battery,full_condition_vcell = <4230>;
battery,full_condition_vcell2 = <4280>;
battery,recharge_check_count = <2>;
battery,recharge_condition_type = <4>; /* SEC_BATTERY_RECHARGE_CONDITION_VCELL */
battery,recharge_condition_soc = <98>;
battery,recharge_condition_vcell = <4290>;
battery,recharge_condition_vcell2 = <4340>;
battery,charging_total_time = <21600>;
battery,recharging_total_time = <5400>;
battery,charging_reset_time = <0>;
battery,chg_float_voltage = <4330>;
battery,chg_float_voltage2 = <4380>;
battery,self_discharging_temp_block = <600>;
battery,self_discharging_volt_block = <4250>;
battery,self_discharging_temp_recov = <550>;
battery,self_discharging_temp_pollingtime = <400>;
battery,swelling_high_temp_block = <450>;
battery,swelling_high_temp_recov = <400>;
battery,swelling_low_temp_block = <100>;
battery,swelling_low_temp_recov = <150>;
battery,swelling_high_temp_current = <1200>;
battery,swelling_low_temp_current = <1200>;
battery,swelling_low_temp_additional = <50>;
battery,swelling_low_temp_additional_current = <480>;
battery,swelling_low_temp_topoff = <150>;
battery,swelling_high_temp_topoff = <150>;
battery,swelling_drop_float_voltage = <4210>;
battery,swelling_high_rechg_voltage = <4150>;
battery,swelling_low_rechg_voltage = <4050>;
battery,swelling_block_time = <600>;
io-channels = <&exynos_adc 1>;
io-channel-names = "adc-temp";
#io-channel-cells = <1>;
io-channel-ranges;
};
s2mpu06-charger {
status = "disable";
compatible = "samsung,s2mpu06-charger";
battery,is_1MHz_switching = <1>;
battery,chg_gpio_en = <0>;
battery,chg_polarity_en = <0>;
battery,chg_gpio_status = <0>;
battery,chg_polarity_status = <0>;
};
};

12
arch/arm64/boot/dts/exynos7570-on5xelte_battery_swa_00.dtsi Executable file
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/*
* SAMSUNG UNIVERSAL7570 board device tree source
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "exynos7570-on5xelte_battery.dtsi"

12
arch/arm64/boot/dts/exynos7570-on5xelte_battery_swa_02.dtsi Normal file
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/*
* SAMSUNG UNIVERSAL7570 board device tree source
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "exynos7570-on5xelte_battery.dtsi"

27
arch/arm64/boot/dts/exynos7570-on5xelte_battery_swa_03.dtsi Executable file
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/*
* SAMSUNG UNIVERSAL7570 board device tree source
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "exynos7570-on5xelte_battery.dtsi"
/ {
battery {
battery,inbat_voltage = <1>;
battery,inbat_voltage_table_adc = <2767 2750 2742 2697 2631 2609 2601 2585 2575 2565 2553 2545 2534 2526 2521 2514 2510 2495 2490 2485 2462 2453 2443 2433 2418 2406 2380 2374 2367>;
battery,inbat_voltage_table_data = <430 427 425 418 405 401 400 398 395 393 391 390 388 387 386 385 384 381 380 378 375 373 372 368 365 364 360 359 358>;
io-channels = <&exynos_adc 1>, <&exynos_adc 5>;
io-channel-names = "adc-temp", "adc-in-bat";
#io-channel-cells = <2>;
io-channel-ranges;
};
};

75
arch/arm64/boot/dts/exynos7570-on5xelte_fingerprint-sensor_00.dtsi Normal file
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/*
* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/ {
pinctrl@139F0000 {
btp_irq: btp-irq {
samsung,pins = "gpa1-3";
samsung,pin-function = <0>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
btp_check: btp-check {
samsung,pins = "gpa2-5";
samsung,pin-function = <0>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
};
pinctrl@139B0000 {
btp_reset: btp-reset {
samsung,pins = "gpf3-3";
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-drv = <1>;
};
};
pinctrl@139C0000 {
btp_ldo: btp-ldo {
samsung,pins = "gpc2-3";
samsung,pin-function = <1>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
};
spi_0: spi@100C0000 {
status = "okay";
secure-mode;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "idle";
pinctrl-0 = <&spi0_bus>;
pinctrl-1 = <&spi0_bus_inactive>;
etspi-spi@0 {
compatible = "etspi,et510";
reg = <0>;
spi-max-frequency = <16000000>;
pinctrl-names = "default";
pinctrl-0 = <&btp_irq &btp_reset &btp_ldo &btp_check>;
gpio-controller;
#gpio-cells = <2>;
etspi-sleepPin = <&gpf3 3 0x00>;
etspi-drdyPin = <&gpa1 3 0x00>;
etspi-ldoPin = <&gpc2 3 0x00>;
controller-data {
samsung,spi-feedback-delay = <0>;
samsung,spi-chip-select-mode = <0>;
};
};
};
};

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arch/arm64/boot/dts/exynos7570-on5xelte_ltn_open_05.dts Normal file
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/*
* SAMSUNG UNIVERSAL7570 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "exynos7570-on5xe_common.dtsi"
#include "modem-ss305ap-pdata.dtsi"
#include "exynos7570-rmem.dtsi"
#include "exynos7570-on5xelte_battery_ltn_05.dtsi"
#include "exynos7570-on5xelte_ltn_open_gpio_05.dtsi"
#include "exynos7570-on5xelte_fingerprint-sensor_00.dtsi"
/ {
model = "Samsung ON5XELTE LTN rev05 board based on Exynos7570";
model_info-chip = <7570>;
model_info-platform = "android";
model_info-subtype = "samsung";
model_info-hw_rev = <5>;
model_info-hw_rev_end = <255>;
compatible = "samsung,exynos7570", "samsung,exynos4210";
pinctrl@139B0000 {
fm_lna_en: fm-lna-en {
samsung,pins = "gpd1-0";
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-val = <0>;
};
};
fm_gpio: fm@14840000 {
elna_gpio = <&gpd1 0 0x1>; /* FM_LNA_EN */
pinctrl-names = "default";
pinctrl-0 = <&fm_lna_en>;
status = "okay";
};
i2c@138D0000 {
stk3013@48 {
stk,psctrl-reg = <0x71>;
stk,ledctrl-reg = <0xBF>;
stk,ps-thd-h = <20>;
stk,ps-thd-l = <13>;
stk,ps-default-offset = <3>;
stk,ps-cal-skip-adc = <10>;
stk,ps-cal-fail-adc = <23>;
};
};
pinctrl@139C0000 {
fimc_is_flash_host: fimc-is-flash-host {
samsung,pins = "gpc2-2";
samsung,pin-function = <1>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
fimc_is_flash_is: fimc-is-flash-is {
samsung,pins = "gpc2-2";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
};
leds_ktd2692 {
compatible = "ktd2692";
flash_control = <&gpc2 2 0x1>;
status = "okay";
pinctrl-names ="default","host","is";
pinctrl-0 = <&fimc_is_flash_is>;
pinctrl-1 = <&fimc_is_flash_host>;
pinctrl-2 = <&fimc_is_flash_is>;
};
};

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arch/arm64/boot/dts/exynos7570-on5xelte_swa_open_00.dts Executable file
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/*
* SAMSUNG UNIVERSAL7570 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "exynos7570-on5xe_common.dtsi"
#include "modem-ss305ap-pdata.dtsi"
#include "exynos7570-rmem.dtsi"
#include "exynos7570-on5xelte_battery_swa_00.dtsi"
#include "exynos7570-on5xelte_swa_open_gpio_00.dtsi"
#include "exynos7570-on5xelte_fingerprint-sensor_00.dtsi"
/ {
model = "Samsung ON5XELTE SWA rev00 board based on Exynos7570";
model_info-chip = <7570>;
model_info-platform = "android";
model_info-subtype = "samsung";
model_info-hw_rev = <0>;
model_info-hw_rev_end = <0>;
compatible = "samsung,exynos7570", "samsung,exynos4210";
pinctrl@139B0000 {
fm_lna_en: fm-lna-en {
samsung,pins = "gpd1-0";
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-val = <0>;
};
};
fm_gpio: fm@14840000 {
elna_gpio = <&gpd1 0 0x1>; /* FM_LNA_EN */
pinctrl-names = "default";
pinctrl-0 = <&fm_lna_en>;
status = "okay";
};
sec_vib {
compatible = "sec_vib";
sec_vib_pdata {
status = "okay";
sec_vib,max_timeout = <10000>;
sec_vib,ldo_type = <0>; /* 0: pmic ldo, 1: external ldo */
sec_vib,regulator = "VDD21_MOTOR_3P0";
};
};
};

38
arch/arm64/boot/dts/exynos7570-on5xelte_swa_open_01.dts Executable file
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/*
* SAMSUNG UNIVERSAL7570 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "exynos7570-on5xe_common.dtsi"
#include "modem-ss305ap-pdata.dtsi"
#include "exynos7570-rmem.dtsi"
#include "exynos7570-on5xelte_battery_swa_00.dtsi"
#include "exynos7570-on5xelte_swa_open_gpio_01.dtsi"
#include "exynos7570-on5xelte_fingerprint-sensor_00.dtsi"
/ {
model = "Samsung ON5XELTE SWA rev01 board based on Exynos7570";
model_info-chip = <7570>;
model_info-platform = "android";
model_info-subtype = "samsung";
model_info-hw_rev = <1>;
model_info-hw_rev_end = <1>;
compatible = "samsung,exynos7570", "samsung,exynos4210";
sec_vib {
compatible = "sec_vib";
sec_vib_pdata {
status = "okay";
sec_vib,max_timeout = <10000>;
sec_vib,ldo_type = <0>; /* 0: pmic ldo, 1: external ldo */
sec_vib,regulator = "VDD21_MOTOR_3P0";
};
};
};

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/*
* SAMSUNG UNIVERSAL7570 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "exynos7570-on5xe_common.dtsi"
#include "modem-ss305ap-pdata.dtsi"
#include "exynos7570-rmem.dtsi"
#include "exynos7570-on5xelte_battery_swa_02.dtsi"
#include "exynos7570-on5xelte_swa_open_gpio_02.dtsi"
#include "exynos7570-on5xelte_fingerprint-sensor_00.dtsi"
/ {
model = "Samsung ON5XELTE SWA rev02 board based on Exynos7570";
model_info-chip = <7570>;
model_info-platform = "android";
model_info-subtype = "samsung";
model_info-hw_rev = <2>;
model_info-hw_rev_end = <2>;
compatible = "samsung,exynos7570", "samsung,exynos4210";
i2c@138D0000 {
stk3013@48 {
stk,psctrl-reg = <0x71>;
stk,ledctrl-reg = <0xBF>;
stk,ps-thd-h = <20>;
stk,ps-thd-l = <13>;
stk,ps-default-offset = <3>;
stk,ps-cal-skip-adc = <10>;
stk,ps-cal-fail-adc = <23>;
};
};
sec_vib {
compatible = "sec_vib";
sec_vib_pdata {
status = "okay";
sec_vib,max_timeout = <10000>;
sec_vib,ldo_type = <0>; /* 0: pmic ldo, 1: external ldo */
sec_vib,regulator = "VDD21_MOTOR_3P0";
};
};
};

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/*
* SAMSUNG UNIVERSAL7570 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "exynos7570-on5xe_common.dtsi"
#include "modem-ss305ap-pdata.dtsi"
#include "exynos7570-rmem.dtsi"
#include "exynos7570-on5xelte_battery_swa_03.dtsi"
#include "exynos7570-on5xelte_swa_open_gpio_03.dtsi"
#include "exynos7570-on5xelte_fingerprint-sensor_00.dtsi"
/ {
model = "Samsung ON5XELTE SWA rev03 board based on Exynos7570";
model_info-chip = <7570>;
model_info-platform = "android";
model_info-subtype = "samsung";
model_info-hw_rev = <3>;
model_info-hw_rev_end = <3>;
compatible = "samsung,exynos7570", "samsung,exynos4210";
i2c@138D0000 {
stk3013@48 {
stk,psctrl-reg = <0x71>;
stk,ledctrl-reg = <0xBF>;
stk,ps-thd-h = <20>;
stk,ps-thd-l = <13>;
stk,ps-default-offset = <3>;
stk,ps-cal-skip-adc = <10>;
stk,ps-cal-fail-adc = <23>;
};
};
};

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arch/arm64/boot/dts/exynos7570-on5xelte_swa_open_04.dts Normal file
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/*
* SAMSUNG UNIVERSAL7570 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "exynos7570-on5xe_common.dtsi"
#include "modem-ss305ap-pdata.dtsi"
#include "exynos7570-rmem.dtsi"
#include "exynos7570-on5xelte_battery_swa_03.dtsi"
#include "exynos7570-on5xelte_swa_open_gpio_04.dtsi"
#include "exynos7570-on5xelte_fingerprint-sensor_00.dtsi"
/ {
model = "Samsung ON5XELTE SWA rev04 board based on Exynos7570";
model_info-chip = <7570>;
model_info-platform = "android";
model_info-subtype = "samsung";
model_info-hw_rev = <4>;
model_info-hw_rev_end = <4>;
compatible = "samsung,exynos7570", "samsung,exynos4210";
pinctrl@139B0000 {
fm_lna_en: fm-lna-en {
samsung,pins = "gpd1-0";
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-val = <0>;
};
};
fm_gpio: fm@14840000 {
elna_gpio = <&gpd1 0 0x1>; /* FM_LNA_EN */
pinctrl-names = "default";
pinctrl-0 = <&fm_lna_en>;
status = "okay";
};
i2c@138D0000 {
stk3013@48 {
stk,psctrl-reg = <0x71>;
stk,ledctrl-reg = <0xBF>;
stk,ps-thd-h = <20>;
stk,ps-thd-l = <13>;
stk,ps-default-offset = <3>;
stk,ps-cal-skip-adc = <10>;
stk,ps-cal-fail-adc = <23>;
};
};
};

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arch/arm64/boot/dts/exynos7570-on5xelte_swa_open_gpio_00.dtsi Executable file
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/*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "exynos_gpio_config_macros.dtsi"
/* 0x139F_0000(ALIVE): etc0~1, gpa0~2,gpq0 */
&pinctrl_0 {
pinctrl-names = "default";
pinctrl-0 = <&initial0>;
initial0: initial-state {
PIN_IN(etc0-0, DOWN, LV1); /* NC */
PIN_IN(etc0-1, DOWN, LV1); /* NC */
PIN_IN(etc0-3, DOWN, LV1); /* NC */
PIN_IN(etc0-4, DOWN, LV1); /* NC */
PIN_IN(etc0-5, DOWN, LV1); /* NC */
PIN_IN(gpq0-0, DOWN, LV1); /* NC */
PIN_IN(gpa0-6, NONE, LV1); /* IF_CON_SENSE_INT_AP */
};
/*
* Note:
* Please do not make "sleep-state" node for GPA group GPIOs.
* GPA group doesn't have power-down status.
*/
};
/* 0x148C_0000(DISPAUD): gpz1 */
&pinctrl_1 {
pinctrl-names = "default","sleep";
pinctrl-0 = <&initial1>;
pinctrl-1 = <&sleep1>;
initial1: initial-state {
PIN_IN(gpz1-1, DOWN, LV1); /* NC */
PIN_IN(gpz1-5, DOWN, LV1); /* NC */
};
sleep1: sleep-state {
PIN_SLP(gpz1-0, INPUT, DOWN); /* CODEC_I2S_SYNC */
PIN_SLP(gpz1-1, INPUT, DOWN); /* NC */
PIN_SLP(gpz1-2, INPUT, DOWN); /* CODEC_I2S_SDI */
PIN_SLP(gpz1-3, INPUT, DOWN); /* CODEC_I2S_SDO */
PIN_SLP(gpz1-5, INPUT, DOWN); /* NC */
PIN_SLP(gpz1-6, INPUT, NONE); /* FM_SPDY_TO_S610 */
};
};
/* 0x139E_0000(FP): gpc7 */
&pinctrl_2 {
pinctrl-names = "sleep";
pinctrl-0 = <&sleep2>;
sleep2: sleep-state {
PIN_SLP(gpc7-0, OUT0, NONE); /* FPS_SPI_CLK */
PIN_SLP(gpc7-1, OUT0, NONE); /* FPS_SPI_CS_N */
PIN_SLP(gpc7-2, INPUT, DOWN); /* FPS_SPI_MISO */
PIN_SLP(gpc7-3, OUT0, NONE); /* FPS_SPI_MOSI */
PIN_SLP(gpc7-4, INPUT, DOWN); /* NC */
};
};
/* 0x1375_0000(FSYS): gpr0~4 */
&pinctrl_3 {
pinctrl-names = "sleep";
pinctrl-0 = <&sleep3>;
sleep3: sleep-state {
PIN_SLP(gpr0-1, INPUT, NONE); /* EMMC_CMD */
};
};
/* 0x1053_0000(MIF): gpm0 */
/* &pinctrl_4 */
/* 0x139C_0000(NFC): gpc2 */
&pinctrl_5 {
pinctrl-names = "sleep";
pinctrl-0 = <&sleep5>;
sleep5: sleep-state {
PIN_SLP(gpc2-0, INPUT, NONE); /* LCD_BL_SDA_1P8 */
PIN_SLP(gpc2-1, INPUT, NONE); /* LCD_BL_SCL_1P8 */
PIN_SLP(gpc2-2, PREV, DOWN); /* SVDLEC_EN */
PIN_SLP(gpc2-3, PREV, NONE); /* FPS_LDO_EN */
};
};
/* 0x139B_0000(TOP): gpc0~1,4, gpd1, gpe0, gpf0~1,3 */
&pinctrl_6 {
pinctrl-names = "default","sleep";
pinctrl-0 = <&initial6>;
pinctrl-1 = <&sleep6>;
initial6: initial-state {
PIN_IN(gpc0-1, DOWN, LV1); /* NC */
PIN_IN(gpc0-2, DOWN, LV1); /* NC */
PIN_IN(gpd1-2, NONE, LV1); /* HW_REV0 */
PIN_IN(gpd1-3, NONE, LV1); /* HW_REV1 */
PIN_IN(gpd1-4, NONE, LV1); /* HW_REV2 */
PIN_IN(gpd1-5, NONE, LV1); /* HW_REV3 */
PIN_IN(gpe0-2, DOWN, LV1); /* NC */
PIN_IN(gpf3-1, DOWN, LV1); /* NC */
PIN_IN(gpf1-0, DOWN, LV1); /* NC */
PIN_IN(gpf1-1, DOWN, LV1); /* NC */
};
sleep6: sleep-state {
PIN_SLP(gpc0-1, INPUT, DOWN); /* NC */
PIN_SLP(gpc0-2, INPUT, DOWN); /* NC */
PIN_SLP(gpc1-2, PREV, UP); /* MUIC_I2C_SDA */
PIN_SLP(gpc1-3, PREV, UP); /* MUIC_I2C_SCL */
PIN_SLP(gpc4-0, INPUT, DOWN); /* TOUCHKEY_SDA_1P8 */
PIN_SLP(gpc4-1, INPUT, DOWN); /* TOUCHKEY_SCL_1P8 */
PIN_SLP(gpc4-2, INPUT, NONE); /* SENSOR_I2C_SDA */
PIN_SLP(gpc4-3, INPUT, NONE); /* SENSOR_I2C_SCL */
PIN_SLP(gpd1-0, PREV, NONE); /* FM_LNA_EN */
PIN_SLP(gpd1-1, INPUT, DOWN); /* CAM_RST_N */
PIN_SLP(gpd1-2, INPUT, NONE); /* HW_REV0 */
PIN_SLP(gpd1-3, INPUT, NONE); /* HW_REV1 */
PIN_SLP(gpd1-4, INPUT, NONE); /* HW_REV2 */
PIN_SLP(gpd1-5, INPUT, NONE); /* HW_REV3 */
PIN_SLP(gpd1-6, INPUT, DOWN); /* VTCAM_RST_N */
PIN_SLP(gpe0-0, INPUT, DOWN); /* CAM_MCLK */
PIN_SLP(gpe0-1, INPUT, DOWN); /* VTCAM_MCLK */
PIN_SLP(gpe0-2, INPUT, DOWN); /* NC */
PIN_SLP(gpf0-0, INPUT, DOWN); /* CAM_SDA_1P8 */
PIN_SLP(gpf0-1, INPUT, DOWN); /* CAM_SCL_1P8 */
PIN_SLP(gpf0-2, INPUT, DOWN); /* CAM_AF_EEP_SDA_1P8 */
PIN_SLP(gpf0-3, INPUT, DOWN); /* CAM_AF_EEP_SCL_1P8 */
PIN_SLP(gpf1-0, INPUT, DOWN); /* NC */
PIN_SLP(gpf1-1, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-0, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-1, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-2, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-3, PREV, NONE); /* FPS_RST_N */
};
};
/* 0x139D_0000(TOUCH): gpc3, gpd2 */
&pinctrl_7 {
pinctrl-names = "sleep";
pinctrl-0= <&sleep7>;
sleep7: sleep-state {
PIN_SLP(gpc3-0, INPUT, DOWN); /* TSP_SDA_1P8 */
PIN_SLP(gpc3-1, INPUT, DOWN); /* TSP_SCL_1P8 */
PIN_SLP(gpc3-2, INPUT, DOWN); /* TSP_INT */
};
};

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arch/arm64/boot/dts/exynos7570-on5xelte_swa_open_gpio_01.dtsi Executable file
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/*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "exynos_gpio_config_macros.dtsi"
/* 0x139F_0000(ALIVE): etc0~1, gpa0~2,gpq0 */
&pinctrl_0 {
pinctrl-names = "default";
pinctrl-0 = <&initial0>;
initial0: initial-state {
PIN_IN(etc0-0, DOWN, LV1); /* NC */
PIN_IN(etc0-1, DOWN, LV1); /* NC */
PIN_IN(etc0-3, DOWN, LV1); /* NC */
PIN_IN(etc0-4, DOWN, LV1); /* NC */
PIN_IN(etc0-5, DOWN, LV1); /* NC */
PIN_IN(gpq0-0, DOWN, LV1); /* NC */
PIN_IN(gpa0-3, DOWN, LV1); /* LCD_ESD_DET */
PIN_IN(gpa0-6, NONE, LV1); /* IF_CON_SENSE_INT_AP */
};
/*
* Note:
* Please do not make "sleep-state" node for GPA group GPIOs.
* GPA group doesn't have power-down status.
*/
};
/* 0x148C_0000(DISPAUD): gpz1 */
&pinctrl_1 {
pinctrl-names = "default","sleep";
pinctrl-0 = <&initial1>;
pinctrl-1 = <&sleep1>;
initial1: initial-state {
PIN_IN(gpz1-1, DOWN, LV1); /* NC */
PIN_IN(gpz1-5, DOWN, LV1); /* NC */
};
sleep1: sleep-state {
PIN_SLP(gpz1-0, INPUT, DOWN); /* CODEC_I2S_SYNC */
PIN_SLP(gpz1-1, INPUT, DOWN); /* NC */
PIN_SLP(gpz1-2, INPUT, DOWN); /* CODEC_I2S_SDI */
PIN_SLP(gpz1-3, INPUT, DOWN); /* CODEC_I2S_SDO */
PIN_SLP(gpz1-5, INPUT, DOWN); /* NC */
PIN_SLP(gpz1-6, INPUT, NONE); /* FM_SPDY_TO_S610 */
};
};
/* 0x139E_0000(FP): gpc7 */
&pinctrl_2 {
pinctrl-names = "sleep";
pinctrl-0 = <&sleep2>;
sleep2: sleep-state {
PIN_SLP(gpc7-0, OUT0, NONE); /* FPS_SPI_CLK */
PIN_SLP(gpc7-1, OUT0, NONE); /* FPS_SPI_CS_N */
PIN_SLP(gpc7-2, INPUT, DOWN); /* FPS_SPI_MISO */
PIN_SLP(gpc7-3, OUT0, NONE); /* FPS_SPI_MOSI */
PIN_SLP(gpc7-4, INPUT, DOWN); /* NC */
};
};
/* 0x1375_0000(FSYS): gpr0~4 */
&pinctrl_3 {
pinctrl-names = "sleep";
pinctrl-0 = <&sleep3>;
sleep3: sleep-state {
PIN_SLP(gpr0-1, INPUT, NONE); /* EMMC_CMD */
};
};
/* 0x1053_0000(MIF): gpm0 */
/* &pinctrl_4 */
/* 0x139C_0000(NFC): gpc2 */
&pinctrl_5 {
pinctrl-names = "sleep";
pinctrl-0 = <&sleep5>;
sleep5: sleep-state {
PIN_SLP(gpc2-0, INPUT, NONE); /* LCD_BL_SDA_1P8 */
PIN_SLP(gpc2-1, INPUT, NONE); /* LCD_BL_SCL_1P8 */
PIN_SLP(gpc2-2, PREV, DOWN); /* SVDLEC_EN */
PIN_SLP(gpc2-3, PREV, NONE); /* FPS_LDO_EN */
};
};
/* 0x139B_0000(TOP): gpc0~1,4, gpd1, gpe0, gpf0~1,3 */
&pinctrl_6 {
pinctrl-names = "default","sleep";
pinctrl-0 = <&initial6>;
pinctrl-1 = <&sleep6>;
initial6: initial-state {
PIN_IN(gpc0-1, DOWN, LV1); /* NC */
PIN_IN(gpc0-2, DOWN, LV1); /* NC */
PIN_IN(gpd1-2, NONE, LV1); /* HW_REV0 */
PIN_IN(gpd1-3, NONE, LV1); /* HW_REV1 */
PIN_IN(gpd1-4, NONE, LV1); /* HW_REV2 */
PIN_IN(gpd1-5, NONE, LV1); /* HW_REV3 */
PIN_IN(gpe0-2, DOWN, LV1); /* NC */
PIN_IN(gpf3-1, DOWN, LV1); /* NC */
PIN_IN(gpf1-0, DOWN, LV1); /* NC */
PIN_IN(gpf1-1, DOWN, LV1); /* NC */
};
sleep6: sleep-state {
PIN_SLP(gpc0-1, INPUT, DOWN); /* NC */
PIN_SLP(gpc0-2, INPUT, DOWN); /* NC */
PIN_SLP(gpc1-2, PREV, UP); /* MUIC_I2C_SDA */
PIN_SLP(gpc1-3, PREV, UP); /* MUIC_I2C_SCL */
PIN_SLP(gpc4-0, INPUT, DOWN); /* TOUCHKEY_SDA_1P8 */
PIN_SLP(gpc4-1, INPUT, DOWN); /* TOUCHKEY_SCL_1P8 */
PIN_SLP(gpc4-2, INPUT, NONE); /* SENSOR_I2C_SDA */
PIN_SLP(gpc4-3, INPUT, NONE); /* SENSOR_I2C_SCL */
PIN_SLP(gpd1-0, INPUT, DOWN); /* NC */
PIN_SLP(gpd1-1, INPUT, DOWN); /* CAM_RST_N */
PIN_SLP(gpd1-2, INPUT, NONE); /* HW_REV0 */
PIN_SLP(gpd1-3, INPUT, NONE); /* HW_REV1 */
PIN_SLP(gpd1-4, INPUT, NONE); /* HW_REV2 */
PIN_SLP(gpd1-5, INPUT, NONE); /* HW_REV3 */
PIN_SLP(gpd1-6, INPUT, DOWN); /* VTCAM_RST_N */
PIN_SLP(gpe0-0, INPUT, DOWN); /* CAM_MCLK */
PIN_SLP(gpe0-1, INPUT, DOWN); /* VTCAM_MCLK */
PIN_SLP(gpe0-2, INPUT, DOWN); /* NC */
PIN_SLP(gpf0-0, INPUT, DOWN); /* CAM_SDA_1P8 */
PIN_SLP(gpf0-1, INPUT, DOWN); /* CAM_SCL_1P8 */
PIN_SLP(gpf0-2, INPUT, DOWN); /* CAM_AF_EEP_SDA_1P8 */
PIN_SLP(gpf0-3, INPUT, DOWN); /* CAM_AF_EEP_SCL_1P8 */
PIN_SLP(gpf1-0, INPUT, DOWN); /* NC */
PIN_SLP(gpf1-1, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-0, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-1, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-2, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-3, PREV, NONE); /* FPS_RST_N */
};
};
/* 0x139D_0000(TOUCH): gpc3, gpd2 */
&pinctrl_7 {
pinctrl-names = "sleep";
pinctrl-0= <&sleep7>;
sleep7: sleep-state {
PIN_SLP(gpc3-0, INPUT, DOWN); /* TSP_SDA_1P8 */
PIN_SLP(gpc3-1, INPUT, DOWN); /* TSP_SCL_1P8 */
PIN_SLP(gpc3-2, INPUT, DOWN); /* TSP_INT */
};
};

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arch/arm64/boot/dts/exynos7570-on5xelte_swa_open_gpio_02.dtsi Executable file
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/*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "exynos_gpio_config_macros.dtsi"
/* 0x139F_0000(ALIVE): etc0~1, gpa0~2,gpq0 */
&pinctrl_0 {
pinctrl-names = "default";
pinctrl-0 = <&initial0>;
initial0: initial-state {
PIN_IN(etc0-0, DOWN, LV1); /* NC */
PIN_IN(etc0-1, DOWN, LV1); /* NC */
PIN_IN(etc0-3, DOWN, LV1); /* NC */
PIN_IN(etc0-4, DOWN, LV1); /* NC */
PIN_IN(etc0-5, DOWN, LV1); /* NC */
PIN_IN(gpq0-0, DOWN, LV1); /* NC */
PIN_IN(gpa0-3, DOWN, LV1); /* LCD_ESD_DET */
PIN_IN(gpa0-6, NONE, LV1); /* IF_CON_SENSE_INT_AP */
};
/*
* Note:
* Please do not make "sleep-state" node for GPA group GPIOs.
* GPA group doesn't have power-down status.
*/
};
/* 0x148C_0000(DISPAUD): gpz1 */
&pinctrl_1 {
pinctrl-names = "default","sleep";
pinctrl-0 = <&initial1>;
pinctrl-1 = <&sleep1>;
initial1: initial-state {
PIN_IN(gpz1-1, DOWN, LV1); /* NC */
PIN_IN(gpz1-5, DOWN, LV1); /* NC */
};
sleep1: sleep-state {
PIN_SLP(gpz1-0, INPUT, DOWN); /* CODEC_I2S_SYNC */
PIN_SLP(gpz1-1, INPUT, DOWN); /* NC */
PIN_SLP(gpz1-2, INPUT, DOWN); /* CODEC_I2S_SDI */
PIN_SLP(gpz1-3, INPUT, DOWN); /* CODEC_I2S_SDO */
PIN_SLP(gpz1-5, INPUT, DOWN); /* NC */
PIN_SLP(gpz1-6, INPUT, NONE); /* FM_SPDY_TO_S610 */
};
};
/* 0x139E_0000(FP): gpc7 */
&pinctrl_2 {
pinctrl-names = "sleep";
pinctrl-0 = <&sleep2>;
sleep2: sleep-state {
PIN_SLP(gpc7-0, OUT0, NONE); /* FPS_SPI_CLK */
PIN_SLP(gpc7-1, OUT0, NONE); /* FPS_SPI_CS_N */
PIN_SLP(gpc7-2, INPUT, DOWN); /* FPS_SPI_MISO */
PIN_SLP(gpc7-3, OUT0, NONE); /* FPS_SPI_MOSI */
PIN_SLP(gpc7-4, INPUT, DOWN); /* NC */
};
};
/* 0x1375_0000(FSYS): gpr0~4 */
&pinctrl_3 {
pinctrl-names = "sleep";
pinctrl-0 = <&sleep3>;
sleep3: sleep-state {
PIN_SLP(gpr0-1, INPUT, NONE); /* EMMC_CMD */
};
};
/* 0x1053_0000(MIF): gpm0 */
/* &pinctrl_4 */
/* 0x139C_0000(NFC): gpc2 */
&pinctrl_5 {
pinctrl-names = "sleep";
pinctrl-0 = <&sleep5>;
sleep5: sleep-state {
PIN_SLP(gpc2-0, INPUT, NONE); /* LCD_BL_SDA_1P8 */
PIN_SLP(gpc2-1, INPUT, NONE); /* LCD_BL_SCL_1P8 */
PIN_SLP(gpc2-2, PREV, DOWN); /* SVDLEC_EN */
PIN_SLP(gpc2-3, PREV, NONE); /* FPS_LDO_EN */
};
};
/* 0x139B_0000(TOP): gpc0~1,4, gpd1, gpe0, gpf0~1,3 */
&pinctrl_6 {
pinctrl-names = "default","sleep";
pinctrl-0 = <&initial6>;
pinctrl-1 = <&sleep6>;
initial6: initial-state {
PIN_IN(gpc0-1, DOWN, LV1); /* NC */
PIN_IN(gpc0-2, DOWN, LV1); /* NC */
PIN_IN(gpd1-2, NONE, LV1); /* HW_REV0 */
PIN_IN(gpd1-3, NONE, LV1); /* HW_REV1 */
PIN_IN(gpd1-4, NONE, LV1); /* HW_REV2 */
PIN_IN(gpd1-5, NONE, LV1); /* HW_REV3 */
PIN_IN(gpe0-2, DOWN, LV1); /* NC */
PIN_IN(gpf3-1, DOWN, LV1); /* NC */
};
sleep6: sleep-state {
PIN_SLP(gpc0-1, INPUT, DOWN); /* NC */
PIN_SLP(gpc0-2, INPUT, DOWN); /* NC */
PIN_SLP(gpc1-2, PREV, UP); /* MUIC_I2C_SDA */
PIN_SLP(gpc1-3, PREV, UP); /* MUIC_I2C_SCL */
PIN_SLP(gpc4-0, INPUT, DOWN); /* TOUCHKEY_SDA_1P8 */
PIN_SLP(gpc4-1, INPUT, DOWN); /* TOUCHKEY_SCL_1P8 */
PIN_SLP(gpc4-2, INPUT, NONE); /* SENSOR_I2C_SDA */
PIN_SLP(gpc4-3, INPUT, NONE); /* SENSOR_I2C_SCL */
PIN_SLP(gpd1-0, INPUT, DOWN); /* NC */
PIN_SLP(gpd1-1, INPUT, DOWN); /* CAM_RST_N */
PIN_SLP(gpd1-2, INPUT, NONE); /* HW_REV0 */
PIN_SLP(gpd1-3, INPUT, NONE); /* HW_REV1 */
PIN_SLP(gpd1-4, INPUT, NONE); /* HW_REV2 */
PIN_SLP(gpd1-5, INPUT, NONE); /* HW_REV3 */
PIN_SLP(gpd1-6, INPUT, DOWN); /* VTCAM_RST_N */
PIN_SLP(gpe0-0, INPUT, DOWN); /* CAM_MCLK */
PIN_SLP(gpe0-1, INPUT, DOWN); /* VTCAM_MCLK */
PIN_SLP(gpe0-2, INPUT, DOWN); /* NC */
PIN_SLP(gpf0-0, INPUT, DOWN); /* CAM_SDA_1P8 */
PIN_SLP(gpf0-1, INPUT, DOWN); /* CAM_SCL_1P8 */
PIN_SLP(gpf0-2, INPUT, DOWN); /* CAM_AF_EEP_SDA_1P8 */
PIN_SLP(gpf0-3, INPUT, DOWN); /* CAM_AF_EEP_SCL_1P8 */
PIN_SLP(gpf1-0, INPUT, DOWN); /* NC */
PIN_SLP(gpf1-1, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-0, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-1, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-2, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-3, PREV, NONE); /* FPS_RST_N */
};
};
/* 0x139D_0000(TOUCH): gpc3, gpd2 */
&pinctrl_7 {
pinctrl-names = "sleep";
pinctrl-0= <&sleep7>;
sleep7: sleep-state {
PIN_SLP(gpc3-0, INPUT, DOWN); /* TSP_SDA_1P8 */
PIN_SLP(gpc3-1, INPUT, DOWN); /* TSP_SCL_1P8 */
PIN_SLP(gpc3-2, INPUT, DOWN); /* TSP_INT */
};
};

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arch/arm64/boot/dts/exynos7570-on5xelte_swa_open_gpio_03.dtsi Executable file
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/*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "exynos_gpio_config_macros.dtsi"
/* 0x139F_0000(ALIVE): etc0~1, gpa0~2,gpq0 */
&pinctrl_0 {
pinctrl-names = "default";
pinctrl-0 = <&initial0>;
initial0: initial-state {
PIN_IN(etc0-0, DOWN, LV1); /* NC */
PIN_IN(etc0-1, DOWN, LV1); /* NC */
PIN_IN(etc0-3, DOWN, LV1); /* NC */
PIN_IN(etc0-4, DOWN, LV1); /* NC */
PIN_IN(etc0-5, DOWN, LV1); /* NC */
PIN_IN(gpq0-0, DOWN, LV1); /* NC */
PIN_IN(gpa0-6, NONE, LV1); /* IF_CON_SENSE_INT_AP */
};
/*
* Note:
* Please do not make "sleep-state" node for GPA group GPIOs.
* GPA group doesn't have power-down status.
*/
};
/* 0x148C_0000(DISPAUD): gpz1 */
&pinctrl_1 {
pinctrl-names = "default","sleep";
pinctrl-0 = <&initial1>;
pinctrl-1 = <&sleep1>;
initial1: initial-state {
PIN_IN(gpz1-1, DOWN, LV1); /* NC */
PIN_IN(gpz1-5, DOWN, LV1); /* NC */
};
sleep1: sleep-state {
PIN_SLP(gpz1-0, INPUT, DOWN); /* CODEC_I2S_SYNC */
PIN_SLP(gpz1-1, INPUT, DOWN); /* NC */
PIN_SLP(gpz1-2, INPUT, DOWN); /* CODEC_I2S_SDI */
PIN_SLP(gpz1-3, INPUT, DOWN); /* CODEC_I2S_SDO */
PIN_SLP(gpz1-5, INPUT, DOWN); /* NC */
PIN_SLP(gpz1-6, INPUT, NONE); /* FM_SPDY_TO_S610 */
};
};
/* 0x139E_0000(FP): gpc7 */
&pinctrl_2 {
pinctrl-names = "sleep";
pinctrl-0 = <&sleep2>;
sleep2: sleep-state {
PIN_SLP(gpc7-0, OUT0, NONE); /* FPS_SPI_CLK */
PIN_SLP(gpc7-1, OUT0, NONE); /* FPS_SPI_CS_N */
PIN_SLP(gpc7-2, INPUT, DOWN); /* FPS_SPI_MISO */
PIN_SLP(gpc7-3, OUT0, NONE); /* FPS_SPI_MOSI */
PIN_SLP(gpc7-4, INPUT, DOWN); /* NC */
};
};
/* 0x1375_0000(FSYS): gpr0~4 */
&pinctrl_3 {
pinctrl-names = "sleep";
pinctrl-0 = <&sleep3>;
sleep3: sleep-state {
PIN_SLP(gpr0-1, INPUT, NONE); /* EMMC_CMD */
};
};
/* 0x1053_0000(MIF): gpm0 */
/* &pinctrl_4 */
/* 0x139C_0000(NFC): gpc2 */
&pinctrl_5 {
pinctrl-names = "sleep";
pinctrl-0 = <&sleep5>;
sleep5: sleep-state {
PIN_SLP(gpc2-0, INPUT, NONE); /* LCD_BL_SDA_1P8 */
PIN_SLP(gpc2-1, INPUT, NONE); /* LCD_BL_SCL_1P8 */
PIN_SLP(gpc2-2, PREV, DOWN); /* SVDLEC_EN */
PIN_SLP(gpc2-3, PREV, NONE); /* FPS_LDO_EN */
};
};
/* 0x139B_0000(TOP): gpc0~1,4, gpd1, gpe0, gpf0~1,3 */
&pinctrl_6 {
pinctrl-names = "default","sleep";
pinctrl-0 = <&initial6>;
pinctrl-1 = <&sleep6>;
initial6: initial-state {
PIN_IN(gpc0-1, DOWN, LV1); /* NC */
PIN_IN(gpc0-2, DOWN, LV1); /* NC */
PIN_IN(gpd1-2, NONE, LV1); /* HW_REV0 */
PIN_IN(gpd1-3, NONE, LV1); /* HW_REV1 */
PIN_IN(gpd1-4, NONE, LV1); /* HW_REV2 */
PIN_IN(gpd1-5, NONE, LV1); /* HW_REV3 */
PIN_IN(gpe0-2, DOWN, LV1); /* NC */
PIN_IN(gpf3-1, DOWN, LV1); /* NC */
};
sleep6: sleep-state {
PIN_SLP(gpc0-1, INPUT, DOWN); /* NC */
PIN_SLP(gpc0-2, INPUT, DOWN); /* NC */
PIN_SLP(gpc1-2, PREV, UP); /* MUIC_I2C_SDA */
PIN_SLP(gpc1-3, PREV, UP); /* MUIC_I2C_SCL */
PIN_SLP(gpc4-0, INPUT, DOWN); /* TOUCHKEY_SDA_1P8 */
PIN_SLP(gpc4-1, INPUT, DOWN); /* TOUCHKEY_SCL_1P8 */
PIN_SLP(gpc4-2, INPUT, NONE); /* SENSOR_I2C_SDA */
PIN_SLP(gpc4-3, INPUT, NONE); /* SENSOR_I2C_SCL */
PIN_SLP(gpd1-0, INPUT, DOWN); /* NC */
PIN_SLP(gpd1-1, INPUT, DOWN); /* CAM_RST_N */
PIN_SLP(gpd1-2, INPUT, NONE); /* HW_REV0 */
PIN_SLP(gpd1-3, INPUT, NONE); /* HW_REV1 */
PIN_SLP(gpd1-4, INPUT, NONE); /* HW_REV2 */
PIN_SLP(gpd1-5, INPUT, NONE); /* HW_REV3 */
PIN_SLP(gpd1-6, INPUT, DOWN); /* VTCAM_RST_N */
PIN_SLP(gpe0-0, INPUT, DOWN); /* CAM_MCLK */
PIN_SLP(gpe0-1, INPUT, DOWN); /* VTCAM_MCLK */
PIN_SLP(gpe0-2, INPUT, DOWN); /* NC */
PIN_SLP(gpf0-0, INPUT, DOWN); /* CAM_SDA_1P8 */
PIN_SLP(gpf0-1, INPUT, DOWN); /* CAM_SCL_1P8 */
PIN_SLP(gpf0-2, INPUT, DOWN); /* CAM_AF_EEP_SDA_1P8 */
PIN_SLP(gpf0-3, INPUT, DOWN); /* CAM_AF_EEP_SCL_1P8 */
PIN_SLP(gpf1-0, INPUT, DOWN); /* NC */
PIN_SLP(gpf1-1, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-0, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-1, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-2, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-3, PREV, NONE); /* FPS_RST_N */
};
};
/* 0x139D_0000(TOUCH): gpc3, gpd2 */
&pinctrl_7 {
pinctrl-names = "sleep";
pinctrl-0= <&sleep7>;
sleep7: sleep-state {
PIN_SLP(gpc3-0, INPUT, DOWN); /* TSP_SDA_1P8 */
PIN_SLP(gpc3-1, INPUT, DOWN); /* TSP_SCL_1P8 */
PIN_SLP(gpc3-2, INPUT, DOWN); /* TSP_INT */
};
};

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arch/arm64/boot/dts/exynos7570-on5xelte_swa_open_gpio_04.dtsi Executable file
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/*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "exynos_gpio_config_macros.dtsi"
/* 0x139F_0000(ALIVE): etc0~1, gpa0~2,gpq0 */
&pinctrl_0 {
pinctrl-names = "default";
pinctrl-0 = <&initial0>;
initial0: initial-state {
PIN_IN(etc0-0, DOWN, LV1); /* NC */
PIN_IN(etc0-1, DOWN, LV1); /* NC */
PIN_IN(etc0-3, DOWN, LV1); /* NC */
PIN_IN(etc0-4, DOWN, LV1); /* NC */
PIN_IN(etc0-5, DOWN, LV1); /* NC */
PIN_IN(gpq0-0, DOWN, LV1); /* NC */
PIN_IN(gpa0-6, NONE, LV1); /* IF_CON_SENSE_INT_AP */
};
/*
* Note:
* Please do not make "sleep-state" node for GPA group GPIOs.
* GPA group doesn't have power-down status.
*/
};
/* 0x148C_0000(DISPAUD): gpz1 */
&pinctrl_1 {
pinctrl-names = "default","sleep";
pinctrl-0 = <&initial1>;
pinctrl-1 = <&sleep1>;
initial1: initial-state {
PIN_IN(gpz1-1, DOWN, LV1); /* NC */
PIN_IN(gpz1-5, DOWN, LV1); /* NC */
};
sleep1: sleep-state {
PIN_SLP(gpz1-0, INPUT, DOWN); /* CODEC_I2S_SYNC */
PIN_SLP(gpz1-1, INPUT, DOWN); /* NC */
PIN_SLP(gpz1-2, INPUT, DOWN); /* CODEC_I2S_SDI */
PIN_SLP(gpz1-3, INPUT, DOWN); /* CODEC_I2S_SDO */
PIN_SLP(gpz1-5, INPUT, DOWN); /* NC */
PIN_SLP(gpz1-6, INPUT, NONE); /* FM_SPDY_TO_S610 */
};
};
/* 0x139E_0000(FP): gpc7 */
&pinctrl_2 {
pinctrl-names = "sleep";
pinctrl-0 = <&sleep2>;
sleep2: sleep-state {
PIN_SLP(gpc7-0, OUT0, NONE); /* FPS_SPI_CLK */
PIN_SLP(gpc7-1, OUT0, NONE); /* FPS_SPI_CS_N */
PIN_SLP(gpc7-2, INPUT, DOWN); /* FPS_SPI_MISO */
PIN_SLP(gpc7-3, OUT0, NONE); /* FPS_SPI_MOSI */
PIN_SLP(gpc7-4, INPUT, DOWN); /* NC */
};
};
/* 0x1375_0000(FSYS): gpr0~4 */
&pinctrl_3 {
pinctrl-names = "sleep";
pinctrl-0 = <&sleep3>;
sleep3: sleep-state {
PIN_SLP(gpr0-1, INPUT, NONE); /* EMMC_CMD */
};
};
/* 0x1053_0000(MIF): gpm0 */
/* &pinctrl_4 */
/* 0x139C_0000(NFC): gpc2 */
&pinctrl_5 {
pinctrl-names = "sleep";
pinctrl-0 = <&sleep5>;
sleep5: sleep-state {
PIN_SLP(gpc2-0, INPUT, NONE); /* LCD_BL_SDA_1P8 */
PIN_SLP(gpc2-1, INPUT, NONE); /* LCD_BL_SCL_1P8 */
PIN_SLP(gpc2-2, PREV, DOWN); /* SVDLEC_EN */
PIN_SLP(gpc2-3, PREV, NONE); /* FPS_LDO_EN */
};
};
/* 0x139B_0000(TOP): gpc0~1,4, gpd1, gpe0, gpf0~1,3 */
&pinctrl_6 {
pinctrl-names = "default","sleep";
pinctrl-0 = <&initial6>;
pinctrl-1 = <&sleep6>;
initial6: initial-state {
PIN_IN(gpc0-1, DOWN, LV1); /* NC */
PIN_IN(gpc0-2, DOWN, LV1); /* NC */
PIN_IN(gpd1-2, NONE, LV1); /* HW_REV0 */
PIN_IN(gpd1-3, NONE, LV1); /* HW_REV1 */
PIN_IN(gpd1-4, NONE, LV1); /* HW_REV2 */
PIN_IN(gpd1-5, NONE, LV1); /* HW_REV3 */
PIN_IN(gpe0-2, DOWN, LV1); /* NC */
PIN_IN(gpf3-1, DOWN, LV1); /* NC */
};
sleep6: sleep-state {
PIN_SLP(gpc0-1, INPUT, DOWN); /* NC */
PIN_SLP(gpc0-2, INPUT, DOWN); /* NC */
PIN_SLP(gpc1-2, PREV, UP); /* MUIC_I2C_SDA */
PIN_SLP(gpc1-3, PREV, UP); /* MUIC_I2C_SCL */
PIN_SLP(gpc4-0, INPUT, DOWN); /* TOUCHKEY_SDA_1P8 */
PIN_SLP(gpc4-1, INPUT, DOWN); /* TOUCHKEY_SCL_1P8 */
PIN_SLP(gpc4-2, INPUT, NONE); /* SENSOR_I2C_SDA */
PIN_SLP(gpc4-3, INPUT, NONE); /* SENSOR_I2C_SCL */
PIN_SLP(gpd1-0, PREV, NONE); /* FM_LNA_EN */
PIN_SLP(gpd1-1, INPUT, DOWN); /* CAM_RST_N */
PIN_SLP(gpd1-2, INPUT, NONE); /* HW_REV0 */
PIN_SLP(gpd1-3, INPUT, NONE); /* HW_REV1 */
PIN_SLP(gpd1-4, INPUT, NONE); /* HW_REV2 */
PIN_SLP(gpd1-5, INPUT, NONE); /* HW_REV3 */
PIN_SLP(gpd1-6, INPUT, DOWN); /* VTCAM_RST_N */
PIN_SLP(gpe0-0, INPUT, DOWN); /* CAM_MCLK */
PIN_SLP(gpe0-1, INPUT, DOWN); /* VTCAM_MCLK */
PIN_SLP(gpe0-2, INPUT, DOWN); /* NC */
PIN_SLP(gpf0-0, INPUT, DOWN); /* CAM_SDA_1P8 */
PIN_SLP(gpf0-1, INPUT, DOWN); /* CAM_SCL_1P8 */
PIN_SLP(gpf0-2, INPUT, DOWN); /* CAM_AF_EEP_SDA_1P8 */
PIN_SLP(gpf0-3, INPUT, DOWN); /* CAM_AF_EEP_SCL_1P8 */
PIN_SLP(gpf1-0, INPUT, DOWN); /* NC */
PIN_SLP(gpf1-1, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-0, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-1, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-2, INPUT, DOWN); /* NC */
PIN_SLP(gpf3-3, PREV, NONE); /* FPS_RST_N */
};
};
/* 0x139D_0000(TOUCH): gpc3, gpd2 */
&pinctrl_7 {
pinctrl-names = "sleep";
pinctrl-0= <&sleep7>;
sleep7: sleep-state {
PIN_SLP(gpc3-0, INPUT, DOWN); /* TSP_SDA_1P8 */
PIN_SLP(gpc3-1, INPUT, DOWN); /* TSP_SCL_1P8 */
PIN_SLP(gpc3-2, INPUT, DOWN); /* TSP_INT */
};
};

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arch/arm64/boot/dts/exynos7570-pinctrl.dtsi Normal file
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/*
* Samsung's Exynos7570 SoC pin-mux and pin-config device tree source
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Samsung's Exynos7570 SoC pin-mux and pin-config options are listed as device
* tree nodes are listed in this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
/* ALIVE */
pinctrl@139F0000 {
etc0: etc0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
etc1: etc1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpa0: gpa0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>;
};
dwmmc2_cd_ext_irq: dwmmc2_cd_ext_irq {
samsung,pins = "gpa0-1";
samsung,pin-function = <0xf>;
samsung,pin-pud = <0>;
samsung,pin-drv = <4>;
};
gpa1: gpa1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
};
gpa2: gpa2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpq0: gpq0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/* UART_DEBUG */
uart2_bus: uart2-bus {
samsung,pins = "gpa1-6", "gpa1-5";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
};
uart2_sleep: uart2-sleep {
samsung,pins = "gpa1-6";
samsung,pin-function = <0>;
samsung,pin-pud = <1>;
};
/* I2C_SENSOR2 */
i2c6_bus: i2c6-bus {
samsung,pins = "gpa1-6", "gpa1-5";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
cp_gpio: cp_gpio {
samsung,pins = "gpa1-7", "gpa2-1";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
};
cp_gpio_on5: cp_gpio_on5 {
samsung,pins = "gpa1-7";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
};
cp_gpio_w: cp_gpio_w {
samsung,pins = "gpa2-5", "gpa2-6";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
};
cp_gpio_iot: cp_gpio_iot {
samsung,pins = "gpa1-3", "gpa2-0", "gpa2-2", "gpa2-7";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
};
sim0_gpio_on5: sim0_gpio_on5 {
samsung,pins = "gpa2-4";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
};
sim1_gpio_on5: sim1_gpio_on5 {
samsung,pins = "gpa1-4";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
};
fimc_is_flash: fimc-is-flash {
samsung,pins = "gpa0-0";
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
/* UART_USI_0 (Single mode)*/
uart3_bus_single: uart3-bus-single {
samsung,pins = "gpa2-0", "gpa1-7", "gpa2-1", "gpa2-2";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
};
/* UART_USI_0 (Dual mode)*/
uart3_bus_dual: uart3-bus-dual {
samsung,pins = "gpa2-0", "gpa1-7";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
};
/* UART_USI_1 (Single mode)*/
uart4_bus_single: uart4-bus-single {
samsung,pins = "gpa2-5", "gpa2-4", "gpa2-6", "gpa2-7";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
};
/* UART_USI_1 (Dual mode)*/
uart4_bus_dual: uart4-bus-dual {
samsung,pins = "gpa2-5", "gpa2-4";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
};
/* USI_0_CH0_HSI2C */
hs_i2c5_bus: hs-i2c5-bus {
samsung,pins = "gpa2-0", "gpa1-7";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
/* USI_0_CH1_HSI2C */
hs_i2c6_bus: hs-i2c6-bus {
samsung,pins = "gpa2-2", "gpa2-1";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
/* USI_1_CH0_HSI2C */
hs_i2c7_bus: hs-i2c7-bus {
samsung,pins = "gpa2-5", "gpa2-4";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
/* USI_1_CH1_HSI2C */
hs_i2c8_bus: hs-i2c8-bus {
samsung,pins = "gpa2-7", "gpa2-6";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
/* SPI USI0 */
spi2_bus: spi2-bus {
samsung,pins = "gpa2-0", "gpa1-7", "gpa2-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
spi2_cs_0: spi2-cs-0 {
samsung,pins = "gpa2-1";
samsung,pin-function = <1>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
/* SPI USI1 */
spi3_bus: spi3-bus {
samsung,pins = "gpa2-5", "gpa2-4", "gpa2-7";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
spi3_cs_0: spi3-cs-0 {
samsung,pins = "gpa2-6";
samsung,pin-function = <1>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
};
/* ESE */
pinctrl@139E0000 {
gpc7: gpc7 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/* SPI_ESE */
spi0_bus: spi0-bus {
samsung,pins = "gpc7-3", "gpc7-2", "gpc7-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
spi0_cs_0: spi0-cs-0 {
samsung,pins = "gpc7-1";
samsung,pin-function = <1>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
spi0_cs_1: spi0-cs-1 {
samsung,pins = "gpc7-4";
samsung,pin-function = <1>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
};
/* DISPAUD */
pinctrl@148C0000 {
gpz1: gpz1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
i2s_pmic_bus: i2s-pmic-bus {
samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
i2s_pmic_bus_idle: i2s-pmic-bus-idle {
samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3";
samsung,pin-function = <0>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
i2s_codec_clk: i2s-codec-clk {
samsung,pins = "gpz1-4";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
i2s_amp_bus: i2s-amp-bus {
samsung,pins = "gpz1-5";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <2>;
};
i2s_amp_bus_idle: i2s-amp-bus-idle {
samsung,pins = "gpz1-5";
samsung,pin-function = <0>;
samsung,pin-pud = <3>;
samsung,pin-drv = <2>;
};
fm_speedy_bus: fm-speedy-bus {
samsung,pins = "gpz1-6";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <2>;
};
fm_speedy_bus_idle: fm-speedy-bus-idle {
samsung,pins = "gpz1-6";
samsung,pin-function = <0>;
samsung,pin-pud = <3>;
samsung,pin-drv = <2>;
};
};
/* FSYS */
pinctrl@13750000 {
gpr0: gpr0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpr1: gpr1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpr4: gpr4 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sd0_clk: sd0-clk {
samsung,pins = "gpr0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <2>;
};
sd0_cmd: sd0-cmd {
samsung,pins = "gpr0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <2>;
};
sd0_rdqs: sd0-rdqs {
samsung,pins = "gpr0-2";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <2>;
};
sd0_clk_fast_slew_rate_1x: sd0-clk_fast_slew_rate_1x {
samsung,pins = "gpr0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
sd0_clk_fast_slew_rate_2x: sd0-clk_fast_slew_rate_2x {
samsung,pins = "gpr0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <1>;
};
sd0_clk_fast_slew_rate_3x: sd0-clk_fast_slew_rate_3x {
samsung,pins = "gpr0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <2>;
};
sd0_clk_fast_slew_rate_4x: sd0-clk_fast_slew_rate_4x {
samsung,pins = "gpr0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd0_bus1: sd0-bus-width1 {
samsung,pins = "gpr1-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <2>;
};
sd0_bus4: sd0-bus-width4 {
samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <2>;
};
sd0_bus8: sd0-bus-width8 {
samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <2>;
};
sd2_clk: sd2-clk {
samsung,pins = "gpr4-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <2>;
};
sd2_cmd: sd2-cmd {
samsung,pins = "gpr4-1";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <2>;
};
sd2_bus1: sd2-bus-width1 {
samsung,pins = "gpr4-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <2>;
};
sd2_bus4: sd2-bus-width4 {
samsung,pins = "gpr4-3", "gpr4-4", "gpr4-5";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <2>;
};
sd2_clk_fast_slew_rate_1x: sd2-clk_fast_slew_rate_1x {
samsung,pins = "gpr4-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
sd2_clk_fast_slew_rate_2x: sd2-clk_fast_slew_rate_2x {
samsung,pins = "gpr4-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <1>;
};
sd2_clk_fast_slew_rate_3x: sd2-clk_fast_slew_rate_3x {
samsung,pins = "gpr4-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <2>;
};
sd2_clk_fast_slew_rate_4x: sd2-clk_fast_slew_rate_4x {
samsung,pins = "gpr4-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
};
/* MIF */
pinctrl@10530000 {
gpm0: gpm0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
speedy_bus: speedy-bus {
samsung,pins = "gpm0-0";
samsung,pin-function = <2>;
samsung,pin-drv = <0>;
samsung,pin-con-pdn = <3>;
};
};
/* NFC */
pinctrl@139C0000 {
gpc2: gpc2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/* I2C_NFC */
i2c2_bus: i2c2-bus {
samsung,pins = "gpc2-1", "gpc2-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
gpio_nfc: gpio-nfc {
samsung,pins = "gpc2-2";
samsung,pin-function = <0x1>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
samsung,pin-con-pdn = <3>;
samsung,pin-val = <1>;
};
nfc_pd: nfc_pd {
samsung,pins = "gpc2-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
nfc_clk_req: nfc_clk_req {
samsung,pins = "gpc2-3";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
};
/* TOP */
pinctrl@139B0000 {
gpc0: gpc0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc1: gpc1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc4: gpc4 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd1: gpd1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpe0: gpe0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf0: gpf0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf1: gpf1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf3: gpf3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/* TE SIGNAL */
decon_te_on: decon_te_on {
samsung,pins = "gpe0-2";
samsung,pin-function = <2>;
};
decon_te_off: decon_te_off {
samsung,pins = "gpe0-2";
samsung,pin-function = <0>;
};
/* UART_SENSOR */
uart1_bus: uart1-bus {
samsung,pins = "gpc4-3", "gpc4-2";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
};
/* I2C_MUIC */
i2c1_bus: i2c1-bus {
samsung,pins = "gpc1-3", "gpc1-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
/* I2C_FUELGAUGE */
i2c4_bus: i2c4-bus {
samsung,pins = "gpc4-1", "gpc4-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
/* I2C_SENSOR1 */
i2c5_bus: i2c5-bus {
samsung,pins = "gpc4-3", "gpc4-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
/* HSI2C_MAINCAM */
hs_i2c0_bus: hs-i2c0-bus {
samsung,pins = "gpf3-0", "gpf3-1";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
samsung,pin-con-pdn = <3>;
};
/* HSI2C_FRONTCAM */
hs_i2c1_bus: hs-i2c1-bus {
samsung,pins = "gpf3-2", "gpf3-3";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
samsung,pin-con-pdn = <3>;
};
/* HSI2C_REARSENSOR */
hs_i2c2_bus: hs-i2c2-bus {
samsung,pins = "gpf0-1", "gpf0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
samsung,pin-con-pdn = <3>;
};
/* HSI2C_FRONTSENSOR */
hs_i2c3_bus: hs-i2c3-bus {
samsung,pins = "gpf0-3", "gpf0-2";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
samsung,pin-con-pdn = <3>;
};
/* HSI2C_REARAF */
hs_i2c4_bus: hs-i2c4-bus {
samsung,pins = "gpf1-1", "gpf1-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
samsung,pin-con-pdn = <3>;
};
/* SPI_REARFROM */
spi1_bus: spi1-bus {
samsung,pins = "gpf3-3", "gpf3-2", "gpf3-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
spi1_cs_0: spi1-cs-0 {
samsung,pins = "gpf3-1";
samsung,pin-function = <1>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
spi1_cs_1: spi1-cs-1 {
samsung,pins = "gpd1-0";
samsung,pin-function = <1>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
/* PWM */
pwm_tout0: pwm-tout0 {
samsung,pins = "gpc0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
pwm_tout1: pwm-tout1 {
samsung,pins = "gpc0-2";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
fimc_is_mclk0_in: fimc_is_mclk0_in {
samsung,pins = "gpe0-0";
samsung,pin-function = <0>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
fimc_is_mclk0_out: fimc_is_mclk0_out {
samsung,pins = "gpe0-0";
samsung,pin-function = <1>;
samsung,pin-pud = <1>;
samsung,pin-drv = <2>;
};
fimc_is_mclk0_fn: fimc_is_mclk0_fn {
samsung,pins = "gpe0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <1>;
};
nfc_firm: nfc_firm {
samsung,pins = "gpd1-0";
samsung,pin-function = <1>;
samsung,pin-pud = <1>;
samsung,pin-val = <0>;
};
nfc_pvdd_en: nfc_pvdd_en {
samsung,pins = "gpf1-0";
samsung,pin-function = <1>;
samsung,pin-pud = <3>;
samsung,pin-val = <0>;
};
ese_pvdd_en: ese_pvdd_en {
samsung,pins = "gpf1-1";
samsung,pin-function = <1>;
samsung,pin-pud = <1>;
samsung,pin-val = <0>;
};
};
/* TOUCH */
pinctrl@139D0000 {
gpc3: gpc3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd2: gpd2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/* I2C_TSP */
i2c3_bus: i2c3-bus {
samsung,pins = "gpc3-1", "gpc3-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
};
};

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/*
* SAMSUNG EXYNOS7570 SoC PM Domains device tree source
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SAMSUNG EXYNOS7570 SoC PM domains device nodes are listed in this file.
* EXYNOS7570 based board files can include this file and provide
* values for board specfic bindings.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
pd_dispaud: pd-dispaud@11C84020 {
compatible = "samsung,exynos-pd";
reg = <0x0 0x11C84020 0x20>;
cal_id = <0xB138000D>;
status = "okay";
check-cp-status = "true";
spd_aud: spd-aud@11C84020 {
compatible = "samsung,exynos-spd";
};
spd_disp: spd-disp@11C84020 {
compatible = "samsung,exynos-spd";
};
spd_fm: spd-fm@11C84020 {
compatible = "samsung,exynos-spd";
};
};
pd_isp: pd-isp@11C84040 {
compatible = "samsung,exynos-pd";
reg = <0x0 0x11C84040 0x20>;
parent = <&pd_mfcmscl>;
cal_id = <0xB1380003>;
devfreq-sync-voltage = <3>;
status = "okay";
};
pd_mfcmscl: pd-mfcmscl@11C84060 {
compatible = "samsung,exynos-pd";
reg = <0x0 0x11C84060 0x20>;
cal_id = <0xB1380008>;
status = "okay";
};
pd_g3d: pd-g3d@11C84000 {
compatible = "samsung,exynos-pd";
reg = <0x0 0x11C84000 0x20>;
cal_id = <0xB1380000>;
status = "okay";
};
dbgdev-pd-dispaud {
compatible = "samsung,exynos-pd-dbg";
samsung,power-domain = <&pd_dispaud>;
};
dbgdev-pd-isp {
compatible = "samsung,exynos-pd-dbg";
samsung,power-domain = <&pd_isp>;
};
dbgdev-pd-mfcmscl {
compatible = "samsung,exynos-pd-dbg";
samsung,power-domain = <&pd_mfcmscl>;
};
dbgdev-pd-g3d {
compatible = "samsung,exynos-pd-dbg";
samsung,power-domain = <&pd_g3d>;
};
};

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arch/arm64/boot/dts/exynos7570-rmem.dtsi Normal file
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/*
* SAMSUNG EXYNOS device tree source for reserved-memory
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <1>;
ranges;
camera {
compatible = "exynos8890-ion,camera";
reg = <0x0 0x710EF000 0x1000>;
id = <10>;
};
video_nfw {
compatible = "exynos7570-mfc,vnfw";
reg = <0x0 0x710F0000 0x110000>;
fixed_upper_base = <0xffffff80>;
fixed_lower_base = <0x40000000>;
};
video_stream {
compatible = "exynos8890-ion,vstream";
secure;
reg = <0x0 0x72200000 0x1200000>;
id = <3>;
compat-id = <25 31>;
};
modem_if {
compatible = "exynos,modem_if";
reg = <0 0x73400000 0x5C00000>;
};
wifibt_if {
compatible = "exynos,wifibt_if";
reg = <0 0x79000000 0x400000>;
};
crypto {
compatible = "exynos8890-ion,crypto";
reusable;
reg = <0x0 0x79400000 0x800000>;
id = <1>;
};
video_frame {
compatible = "exynos8890-ion,vframe";
secure;
reusable;
reg = <0x0 0x79C00000 0x3800000>;
id = <5>;
compat-id = <26 29>;
};
video_scaler {
compatible = "exynos8890-ion,vscaler";
secure;
reusable;
reg = <0x0 0x71200000 0x1000000>;
id = <6>;
compat-id = <28>;
};
gnss_if {
compatible = "exynos,gnss_if";
reg = <0 0x7E100000 0x200000>;
};
};
};

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arch/arm64/boot/dts/exynos7570-universal7570-IOT-rev02.dts Normal file
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arch/arm64/boot/dts/exynos_gpio_config_macros.dtsi Normal file
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/*
* SAMSUNG UNIVERSAL5430 board device tree source
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define PIN_PULL_NONE 0
#define PIN_PULL_DOWN 1
#define PIN_PULL_UP 3
#define PIN_DRV_LV1 0x0
#define PIN_DRV_LV2 0x1
#define PIN_DRV_LV3 0x2
#define PIN_DRV_LV4 0x3
#define PIN_DRV_LV5 0x4
#define PIN_DRV_LV6 0x5
#define PIN_DRV_SLOW_LV1 0x8
#define PIN_DRV_SLOW_LV2 0x9
#define PIN_DRV_SLOW_LV3 0xA
#define PIN_DRV_SLOW_LV4 0xB
#define PIN_DRV_SLOW_LV5 0xC
#define PIN_DRV_SLOW_LV6 0xF
#define PIN_PDN_OUT0 0
#define PIN_PDN_OUT1 1
#define PIN_PDN_INPUT 2
#define PIN_PDN_PREV 3
#define PIN_IN(_pin, _pull, _drv) \
_pin { \
samsung,pins = #_pin; \
samsung,pin-function = <0>; \
samsung,pin-pud = <PIN_PULL_ ##_pull>; \
samsung,pin-drv = <PIN_DRV_ ##_drv>; \
}
#define PIN_OUT(_pin, _drv) \
_pin { \
samsung,pins = #_pin; \
samsung,pin-function = <1>; \
samsung,pin-pud = <0>; \
samsung,pin-drv = <PIN_DRV_ ##_drv>; \
}
#define PIN_OUT_SET(_pin, _val, _drv) \
_pin { \
samsung,pins = #_pin; \
samsung,pin-function = <1>; \
samsung,pin-pud = <0>; \
samsung,pin-drv = <PIN_DRV_ ##_drv>; \
samsung,pin-val = <_val>; \
}
#define PIN_SLP(_pin, _mode, _pull) \
_pin { \
samsung,pins = #_pin; \
samsung,pin-con-pdn = <PIN_PDN_ ##_mode>; \
samsung,pin-pud-pdn = <PIN_PULL_ ##_pull>; \
}

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/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS
*/
/dts-v1/;
/memreserve/ 0x80000000 0x00010000;
/ {
model = "Foundation-v8A";
compatible = "arm,foundation-aarch64", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
aliases {
serial0 = &v2m_serial0;
serial1 = &v2m_serial1;
serial2 = &v2m_serial2;
serial3 = &v2m_serial3;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>,
<0x00000008 0x80000000 0 0x80000000>;
};
gic: interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0x2c001000 0 0x1000>,
<0x0 0x2c002000 0 0x1000>,
<0x0 0x2c004000 0 0x2000>,
<0x0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xff01>,
<1 14 0xff01>,
<1 11 0xff01>,
<1 10 0xff01>;
clock-frequency = <100000000>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 60 4>,
<0 61 4>,
<0 62 4>,
<0 63 4>;
};
smb {
compatible = "arm,vexpress,v2m-p1", "simple-bus";
arm,v2m-memory-map = "rs1";
#address-cells = <2>; /* SMB chipselect number and offset */
#size-cells = <1>;
ranges = <0 0 0 0x08000000 0x04000000>,
<1 0 0 0x14000000 0x04000000>,
<2 0 0 0x18000000 0x04000000>,
<3 0 0 0x1c000000 0x04000000>,
<4 0 0 0x0c000000 0x04000000>,
<5 0 0 0x10000000 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic 0 0 4>,
<0 0 1 &gic 0 1 4>,
<0 0 2 &gic 0 2 4>,
<0 0 3 &gic 0 3 4>,
<0 0 4 &gic 0 4 4>,
<0 0 5 &gic 0 5 4>,
<0 0 6 &gic 0 6 4>,
<0 0 7 &gic 0 7 4>,
<0 0 8 &gic 0 8 4>,
<0 0 9 &gic 0 9 4>,
<0 0 10 &gic 0 10 4>,
<0 0 11 &gic 0 11 4>,
<0 0 12 &gic 0 12 4>,
<0 0 13 &gic 0 13 4>,
<0 0 14 &gic 0 14 4>,
<0 0 15 &gic 0 15 4>,
<0 0 16 &gic 0 16 4>,
<0 0 17 &gic 0 17 4>,
<0 0 18 &gic 0 18 4>,
<0 0 19 &gic 0 19 4>,
<0 0 20 &gic 0 20 4>,
<0 0 21 &gic 0 21 4>,
<0 0 22 &gic 0 22 4>,
<0 0 23 &gic 0 23 4>,
<0 0 24 &gic 0 24 4>,
<0 0 25 &gic 0 25 4>,
<0 0 26 &gic 0 26 4>,
<0 0 27 &gic 0 27 4>,
<0 0 28 &gic 0 28 4>,
<0 0 29 &gic 0 29 4>,
<0 0 30 &gic 0 30 4>,
<0 0 31 &gic 0 31 4>,
<0 0 32 &gic 0 32 4>,
<0 0 33 &gic 0 33 4>,
<0 0 34 &gic 0 34 4>,
<0 0 35 &gic 0 35 4>,
<0 0 36 &gic 0 36 4>,
<0 0 37 &gic 0 37 4>,
<0 0 38 &gic 0 38 4>,
<0 0 39 &gic 0 39 4>,
<0 0 40 &gic 0 40 4>,
<0 0 41 &gic 0 41 4>,
<0 0 42 &gic 0 42 4>;
ethernet@2,02000000 {
compatible = "smsc,lan91c111";
reg = <2 0x02000000 0x10000>;
interrupts = <15>;
};
v2m_clk24mhz: clk24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
v2m_refclk1mhz: refclk1mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
v2m_refclk32khz: refclk32khz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "v2m:refclk32khz";
};
iofpga@3,00000000 {
compatible = "arm,amba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 3 0 0x200000>;
v2m_sysreg: sysreg@010000 {
compatible = "arm,vexpress-sysreg";
reg = <0x010000 0x1000>;
};
v2m_serial0: uart@090000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x090000 0x1000>;
interrupts = <5>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial1: uart@0a0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0a0000 0x1000>;
interrupts = <6>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial2: uart@0b0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0b0000 0x1000>;
interrupts = <7>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial3: uart@0c0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0c0000 0x1000>;
interrupts = <8>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
virtio_block@0130000 {
compatible = "virtio,mmio";
reg = <0x130000 0x200>;
interrupts = <42>;
};
};
};
};

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/*
* SAMSUNG UNIVERSAL7570 board device tree source
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
/* modem_interface_driver: Samsung Electronics Java */
mif_pdata {
compatible = "sec_modem,modem_pdata";
status = "okay";
interrupts = <0 18 0>, <0 479 0>;
/* common pdata */
mif,name = "ss305ap";
mif,modem_net = <0>; /* UMTS_NETWORK */
mif,modem_type = <10>; /* SEC_SS310AP */
mif,use_handover = <0>; /* not used */
mif,ipc_version = <50>; /* SIPC 5.0 */
mif,link_types = <0x200>; /* LINKDEV_SHMEM */
mif,link_name = "shmem";
mif,link_attrs = <0x7C8>; /* XMIT_BTDLR(0x400) | DUMP_ALIGNED (0x200) | BOOT_ALIGNED (0x100) | MEM_DUMP (0x80) | MEM_BOOT (0x40) | DPRAM_MAGIC (0x08) */
mif,num_iodevs = <18>;
/* mbox pdata */
mbx_ap2cp_msg = <0>;
mbx_cp2ap_msg = <1>;
mbx_ap2cp_united_status = <2>;
mbx_cp2ap_united_status = <3>;
mif,int_ap2cp_msg = <0>;
mif,int_ap2cp_status = <2>;
mif,int_ap2cp_active = <3>;
mif,irq_cp2ap_msg = <0>;
mif,irq_cp2ap_status = <2>;
mif,irq_cp2ap_active = <3>;
mif,irq_cp2ap_wake_lock = <8>;
/* mbox pdata for performance request */
mbx_cp2ap_dvfsreq = <4>;
mbx_cp2ap_dvfsreq_cpu = <5>;
mbx_cp2ap_dvfsreq_mif = <6>;
mbx_cp2ap_dvfsreq_int = <7>;
mif,irq_cp2ap_perf_req_cpu = <5>; /* CP2AP_DVFSREQ_CPU */
mif,irq_cp2ap_perf_req_mif = <6>; /* CP2AP_DVFSREQ_MIF */
mif,irq_cp2ap_perf_req_int = <7>; /* CP2AP_DVFSREQ_INT */
/* mbox pdata for sbi(status bit info) */
sbi_evs_mode_mask = <0x1>;
sbi_evs_mode_pos = <7>;
sbi_lte_active_mask = <0x1>;
sbi_lte_active_pos = <5>;
sbi_cp_status_mask = <0xf>;
sbi_cp_status_pos = <1>;
sbi_pda_active_mask = <0x1>;
sbi_pda_active_pos = <5>;
sbi_ap_status_mask = <0xf>;
sbi_ap_status_pos = <1>;
sbi_ds_det_mask = <0x3>;
sbi_ds_det_pos = <14>;
sbi_sys_rev_mask = <0xff>;
sbi_sys_rev_pos = <6>;
iodevs {
io_device_0 {
iod,name = "umts_ipc0";
iod,id = <235>;
iod,format = <0>; /* IPC_FMT */
iod,io_type = <0>; /* IODEV_MISC */
iod,links = <0x200>; /* LINKDEV_SHMEM */
iod,attrs = <0x2>; /* ATTR_SIPC5 */
iod,app = "RIL";
};
io_device_1 {
iod,name = "umts_ipc1";
iod,id = <236>;
iod,format = <0>; /* IPC_FMT */
iod,io_type = <0>; /* IODEV_MISC */
iod,links = <0x200>; /* LINKDEV_SHMEM */
iod,attrs = <0x2>; /* ATTR_SBD_IPC | ATTR_SIPC5 */
iod,app = "RIL";
};
io_device_2 {
iod,name = "umts_rfs0";
iod,id = <245>;
iod,format = <1>; /* IPC_RFS */
iod,io_type = <0>;
iod,links = <0x200>;
iod,attrs = <0x2>;
iod,app = "RFS";
};
io_device_3 {
iod,name = "umts_csd";
iod,id = <1>;
iod,format = <1>;
iod,io_type = <0>;
iod,links = <0x200>;
iod,attrs = <0x2>;
iod,app = "CSVT";
};
io_device_4 {
iod,name = "umts_router";
iod,id = <25>;
iod,format = <1>;
iod,io_type = <0>;
iod,links = <0x200>;
iod,attrs = <0x2>;
iod,app = "Data Router";
iod,max_tx_size = <2048>;
};
io_device_5 {
iod,name = "umts_dm0";
iod,id = <28>;
iod,format = <1>;
iod,io_type = <0>;
iod,links = <0x200>;
iod,attrs = <0x2>;
iod,app = "DIAG";
};
io_device_6 {
iod,name = "ipc_loopback0";
iod,id = <244>;
iod,format = <0>;
iod,io_type = <0>;
iod,links = <0x200>;
iod,attrs = <0x2>;
iod,app = "CLD";
};
io_device_7 {
iod,name = "rmnet0";
iod,id = <10>;
iod,format = <1>;
iod,io_type = <1>; /* IODEV_NET */
iod,links = <0x200>;
iod,attrs = <0x2>;
iod,app = "NET";
};
io_device_8 {
iod,name = "rmnet1";
iod,id = <11>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x200>;
iod,attrs = <0x2>;
iod,app = "NET";
};
io_device_9 {
iod,name = "rmnet2";
iod,id = <12>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x200>;
iod,attrs = <0x2>;
iod,app = "NET";
};
io_device_10 {
iod,name = "rmnet3";
iod,id = <13>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x200>;
iod,attrs = <0x2>;
iod,app = "NET";
};
io_device_11 {
iod,name = "rmnet4";
iod,id = <14>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x200>;
iod,attrs = <0x2>;
};
io_device_12 {
iod,name = "rmnet5";
iod,id = <15>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x200>;
iod,attrs = <0x2>;
};
io_device_13 {
iod,name = "rmnet6";
iod,id = <16>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x200>;
iod,attrs = <0x2>;
};
io_device_14 {
iod,name = "rmnet7";
iod,id = <17>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x200>;
iod,attrs = <0x2>;
};
io_device_15 {
iod,name = "multipdp";
iod,id = <0>;
iod,format = <3>; /* IPC_MULTI_RAW */
iod,io_type = <2>; /* IODEV_DUMMY */
iod,links = <0x200>;
iod,attrs = <0x2>;
iod,app = "RIL";
};
io_device_16 {
iod,name = "umts_boot0";
iod,id = <215>;
iod,format = <4>; /* IPC_BOOT */
iod,io_type = <0>;
iod,links = <0x200>;
iod,attrs = <0x2>;
iod,app = "CBD";
};
io_device_17 {
iod,name = "umts_ramdump0";
iod,id = <225>;
iod,format = <5>; /* IPC_DUMP */
iod,io_type = <0>;
iod,links = <0x200>;
iod,attrs = <0x202>; /* ATTR_NO_CHECK_MAXQ | ATTR_SIPC5 */
iod,app = "CBD";
};
}; /* end of iodevs */
}; /* end of mif_pdata */
shmem: shmem@90000000 {
compatible = "samsung,exynos-shm_ipc";
shmem,ipc_offset = <0x5800000>;
shmem,ipc_size = <0x400000>;
};
};

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/*
* SAMSUNG UNIVERSAL7870 board device tree source
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
/* modem_interface_driver: Samsung Electronics Jungfrau */
mif_pdata {
compatible = "sec_modem,modem_pdata";
status = "okay";
interrupts = <0 18 0>, <0 479 0>;
mif,int_ap2cp_msg = <0>;
mif,int_ap2cp_status = <2>;
mif,int_ap2cp_active = <3>;
mif,int_ap2cp_uart_noti = <15>;
mif,irq_cp2ap_msg = <0>;
mif,irq_cp2ap_status = <2>;
mif,irq_cp2ap_active = <3>;
mif,irq_cp2ap_perf_req_cpu = <5>;
mif,irq_cp2ap_perf_req_mif = <6>;
mif,irq_cp2ap_perf_req_int = <7>;
mif,irq_cp2ap_wakelock = <8>;
mbx_ap2cp_msg = <0>;
mbx_cp2ap_msg = <1>;
mbx_ap2cp_status = <2>;
mbx_cp2ap_status = <3>;
mbx_ap2cp_mif_freq = <4>;
mbx_cp2ap_dvfsreq_cpu = <5>;
mbx_cp2ap_dvfsreq_mif = <6>;
mbx_cp2ap_dvfsreq_int = <7>;
shmem,dump_offset = <0x1000>;
mif,name = "ss315ap";
mif,modem_net = <0>; /* UMTS_NETWORK */
mif,modem_type = <10>; /* SEC_SS310AP */
mif,use_handover = <0>; /* not used */
mif,ipc_version = <50>; /* SIPC 5.0 */
mif,link_types = <0x80>; /* LINKDEV_SHMEM */
mif,link_name = "shmem";
mif,link_attrs = <0x7C8>; /* XMIT_BTDLR(0x400) | DUMP_ALIGNED (0x200) | BOOT_ALIGNED (0x100) | MEM_DUMP (0x80) | MEM_BOOT (0x40) | DPRAM_MAGIC (0x08) */
mif,num_iodevs = <16>;
iodevs {
io_device_0 {
iod,name = "umts_ipc0";
iod,id = <245>;
iod,format = <0>;
iod,io_type = <0>;
iod,links = <0x80>;
iod,attrs = <0x82>;
iod,app = "RIL";
};
io_device_1 {
iod,name = "umts_ipc1";
iod,id = <246>;
iod,format = <0>;
iod,io_type = <0>;
iod,links = <0x80>;
iod,attrs = <0x82>;
iod,app = "RIL";
};
io_device_2 {
iod,name = "umts_rfs0";
iod,id = <41>;
iod,format = <1>;
iod,io_type = <0>;
iod,links = <0x80>;
iod,attrs = <0x82>;
iod,app = "RFS";
};
io_device_3 {
iod,name = "umts_router";
iod,id = <21>;
iod,format = <1>;
iod,io_type = <0>;
iod,links = <0x80>;
iod,attrs = <0x82>;
iod,app = "Data Router";
};
io_device_4 {
iod,name = "umts_dm0";
iod,id = <81>;
iod,format = <1>;
iod,io_type = <0>;
iod,links = <0x80>;
iod,attrs = <0x82>;
iod,app = "DIAG";
};
io_device_5 {
iod,name = "umts_loopback";
iod,id = <82>;
iod,format = <1>;
iod,io_type = <0>;
iod,links = <0x80>;
iod,attrs = <0x82>;
iod,app = "LOOPBACK";
};
io_device_6 {
iod,name = "rmnet0";
iod,id = <1>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x80>;
iod,attrs = <0x82>;
iod,app = "NET";
};
io_device_7 {
iod,name = "rmnet1";
iod,id = <2>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x80>;
iod,attrs = <0x82>;
iod,app = "NET";
};
io_device_8 {
iod,name = "rmnet2";
iod,id = <3>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x80>;
iod,attrs = <0x82>;
iod,app = "NET";
};
io_device_9 {
iod,name = "rmnet3";
iod,id = <4>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x80>;
iod,attrs = <0x82>;
iod,app = "NET";
};
io_device_10 {
iod,name = "rmnet4";
iod,id = <5>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x80>;
iod,attrs = <0x82>;
iod,app = "NET";
};
io_device_11 {
iod,name = "rmnet5";
iod,id = <6>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x80>;
iod,attrs = <0x82>;
iod,app = "NET";
};
io_device_12 {
iod,name = "rmnet6";
iod,id = <7>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x80>;
iod,attrs = <0x82>;
iod,app = "NET";
};
io_device_13 {
iod,name = "rmnet7";
iod,id = <8>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x80>;
iod,attrs = <0x82>;
iod,app = "NET";
};
io_device_14 {
iod,name = "multipdp";
iod,id = <0>;
iod,format = <3>;
iod,io_type = <2>;
iod,links = <0x80>;
iod,attrs = <0x02>;
iod,app = "RIL";
};
io_device_15 {
iod,name = "umts_boot0";
iod,id = <241>;
iod,format = <4>;
iod,io_type = <0>;
iod,links = <0x80>;
iod,attrs = <0x02>;
iod,app = "CBD";
};
}; /* end of iodevs */
}; /* end of mif_pdata */
shmem: shmem@90000000 {
compatible = "samsung,exynos-shm_ipc";
shmem,ipc_offset = <0x5800000>;
shmem,ipc_size = <0x400000>;
};
};

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/*
* SAMSUNG UNIVERSAL8890 board device tree source
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
/* modem_interface_driver: Samsung Electronics Jungfrau */
mif_pdata {
compatible = "sec_modem,modem_pdata";
status = "okay";
interrupts = <0 21 0>, <0 96 0>;
reg = <0x0 0x20C5800 0x800>;
samsung,syscon-phandle = <&pmu_system_controller>;
mif,int_ap2cp_msg = <0>;
mif,int_ap2cp_wakeup = <1>;
mif,int_ap2cp_status = <2>;
mif,int_ap2cp_active = <3>;
mif,irq_cp2ap_msg = <0>;
mif,irq_cp2ap_wakeup = <1>;
mif,irq_cp2ap_status = <2>;
mif,irq_cp2ap_perf_req = <3>;
mif,irq_cp2ap_active = <4>;
mbx_ap2cp_msg = <0>;
mbx_cp2ap_msg = <1>;
mbx_ap2cp_wakeup = <2>;
mbx_cp2ap_wakeup = <3>;
mbx_ap2cp_status = <4>;
mbx_cp2ap_status = <5>;
mbx_ap2cp_active = <6>;
mbx_cp2ap_dvfsreq = <7>;
mbx_cp2ap_active = <9>;
mbx_ap2cp_info_value = <33>;
mbx_ap2cp_lock_value = <39>;
mif,name = "ss335ap";
mif,modem_net = <0>; /* UMTS_NETWORK */
mif,modem_type = <10>; /* SEC_SS310AP */
mif,use_handover = <0>; /* not used */
mif,ipc_version = <50>; /* SIPC 5.0 */
mif,link_types = <0x200>; /* LINKDEV_SHMEM */
mif,link_name = "shmem";
mif,link_attrs = <0x7C9>; /* XMIT_BTDLR(0x400) | DUMP_ALIGNED (0x200) | BOOT_ALIGNED (0x100) | MEM_DUMP (0x80) | MEM_BOOT (0x40) | DPRAM_MAGIC (0x08) | SBD_IPC (0x01) */
mif,num_iodevs = <18>;
iodevs {
io_device_0 {
iod,name = "umts_ipc0";
iod,id = <235>;
iod,format = <0>; /* IPC_FMT */
iod,io_type = <0>; /* IODEV_MISC */
iod,links = <0x200>; /* LINKDEV_SHMEM */
iod,attrs = <0x82>; /* ATTR_SBD_IPC | ATTR_SIPC5 */
iod,app = "RIL";
iod,ul_num_buffers = <16>;
iod,ul_buffer_size = <4096>;
iod,dl_num_buffers = <32>;
iod,dl_buffer_size = <4096>;
};
io_device_1 {
iod,name = "umts_ipc1";
iod,id = <236>;
iod,format = <0>; /* IPC_FMT */
iod,io_type = <0>; /* IODEV_MISC */
iod,links = <0x200>; /* LINKDEV_SHMEM */
iod,attrs = <0x82>; /* ATTR_SBD_IPC | ATTR_SIPC5 */
iod,app = "RIL";
iod,ul_num_buffers = <16>;
iod,ul_buffer_size = <4096>;
iod,dl_num_buffers = <32>;
iod,dl_buffer_size = <4096>;
};
io_device_2 {
iod,name = "umts_rfs0";
iod,id = <245>;
iod,format = <1>; /* IPC_RFS */
iod,io_type = <0>;
iod,links = <0x200>;
iod,attrs = <0x82>;
iod,app = "RFS";
iod,ul_num_buffers = <16>;
iod,ul_buffer_size = <2048>;
iod,dl_num_buffers = <512>;
iod,dl_buffer_size = <2048>;
};
io_device_3 {
iod,name = "umts_csd";
iod,id = <1>;
iod,format = <1>;
iod,io_type = <0>;
iod,links = <0x200>;
iod,attrs = <0x82>;
iod,app = "CSVT";
iod,ul_num_buffers = <32>;
iod,ul_buffer_size = <2048>;
iod,dl_num_buffers = <64>;
iod,dl_buffer_size = <2048>;
};
io_device_4 {
iod,name = "umts_router";
iod,id = <25>;
iod,format = <1>;
iod,io_type = <0>;
iod,links = <0x200>;
iod,attrs = <0x82>;
iod,app = "Data Router";
iod,ul_num_buffers = <16>;
iod,ul_buffer_size = <2048>;
iod,dl_num_buffers = <16>;
iod,dl_buffer_size = <2048>;
};
io_device_5 {
iod,name = "umts_dm0";
iod,id = <28>;
iod,format = <1>;
iod,io_type = <0>;
iod,links = <0x200>;
iod,attrs = <0x82>;
iod,app = "DIAG";
iod,ul_num_buffers = <16>;
iod,ul_buffer_size = <2048>;
iod,dl_num_buffers = <128>;
iod,dl_buffer_size = <2048>;
};
io_device_6 {
iod,name = "ipc_loopback0";
iod,id = <244>;
iod,format = <0>;
iod,io_type = <0>;
iod,links = <0x200>;
iod,attrs = <0x82>;
iod,app = "CLD";
iod,ul_num_buffers = <16>;
iod,ul_buffer_size = <2048>;
iod,dl_num_buffers = <32>;
iod,dl_buffer_size = <2048>;
};
io_device_7 {
iod,name = "rmnet0";
iod,id = <10>;
iod,format = <1>;
iod,io_type = <1>; /* IODEV_NET */
iod,links = <0x200>;
iod,attrs = <0x180>; /* ATTR_SBD_IPC (0x80) | ATTR_NO_LINK_HDR(0x100) */
iod,app = "NET";
iod,ul_num_buffers = <0>;
iod,ul_buffer_size = <2048>;
iod,dl_num_buffers = <0>;
iod,dl_buffer_size = <2048>;
};
io_device_8 {
iod,name = "rmnet1";
iod,id = <11>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x200>;
iod,attrs = <0x180>;
iod,app = "NET";
iod,ul_num_buffers = <0>;
iod,ul_buffer_size = <2048>;
iod,dl_num_buffers = <0>;
iod,dl_buffer_size = <2048>;
};
io_device_9 {
iod,name = "rmnet2";
iod,id = <12>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x200>;
iod,attrs = <0x180>;
iod,app = "NET";
iod,ul_num_buffers = <0>;
iod,ul_buffer_size = <2048>;
iod,dl_num_buffers = <0>;
iod,dl_buffer_size = <2048>;
};
io_device_10 {
iod,name = "rmnet3";
iod,id = <13>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x200>;
iod,attrs = <0x180>;
iod,app = "NET";
iod,ul_num_buffers = <0>;
iod,ul_buffer_size = <2048>;
iod,dl_num_buffers = <0>;
iod,dl_buffer_size = <2048>;
};
io_device_11 {
iod,name = "rmnet4";
iod,id = <14>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x200>;
iod,attrs = <0x580>; /* ATTR_DUALSIM (0x400) | ATTR_NO_LINK_HDR(0x100) | ATTR_SBD_IPC (0x80) */
iod,ul_num_buffers = <0>;
iod,ul_buffer_size = <2048>;
iod,dl_num_buffers = <0>;
iod,dl_buffer_size = <2048>;
};
io_device_12 {
iod,name = "rmnet5";
iod,id = <15>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x200>;
iod,attrs = <0x580>;
iod,ul_num_buffers = <0>;
iod,ul_buffer_size = <2048>;
iod,dl_num_buffers = <0>;
iod,dl_buffer_size = <2048>;
};
io_device_13 {
iod,name = "rmnet6";
iod,id = <16>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x200>;
iod,attrs = <0x580>;
iod,ul_num_buffers = <0>;
iod,ul_buffer_size = <2048>;
iod,dl_num_buffers = <0>;
iod,dl_buffer_size = <2048>;
};
io_device_14 {
iod,name = "rmnet7";
iod,id = <17>;
iod,format = <1>;
iod,io_type = <1>;
iod,links = <0x200>;
iod,attrs = <0x580>;
iod,ul_num_buffers = <0>;
iod,ul_buffer_size = <2048>;
iod,dl_num_buffers = <0>;
iod,dl_buffer_size = <2048>;
};
io_device_15 {
iod,name = "multipdp";
iod,id = <0>;
iod,format = <3>; /* IPC_MULTI_RAW */
iod,io_type = <2>; /* IODEV_DUMMY */
iod,links = <0x200>;
iod,attrs = <0x180>;
iod,app = "RIL";
iod,ul_num_buffers = <512>;
iod,ul_buffer_size = <2048>;
iod,dl_num_buffers = <1024>;
iod,dl_buffer_size = <2048>;
};
io_device_16 {
iod,name = "umts_boot0";
iod,id = <215>;
iod,format = <4>; /* IPC_BOOT */
iod,io_type = <0>;
iod,links = <0x200>;
iod,attrs = <0x02>;
iod,app = "CBD";
};
io_device_17 {
iod,name = "umts_ramdump0";
iod,id = <225>;
iod,format = <5>; /* IPC_DUMP */
iod,io_type = <0>;
iod,links = <0x200>;
iod,attrs = <0x202>; /* ATTR_NO_CHECK_MAXQ | ATTR_SIPC5 */
iod,app = "CBD";
};
}; /* end of iodevs */
}; /* end of mif_pdata */
shmem: shmem@F0000000 {
compatible = "samsung,exynos8890-shm_ipc";
reg = <0x0 0xF0000000 0x8800000>;
shmem,ipc_offset = <0x8000000>;
shmem,ipc_size = <0x800000>;
};
};

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arch/arm64/boot/dts/rtsm_ve-aemv8a.dts Normal file
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/*
* ARM Ltd. Fast Models
*
* Architecture Envelope Model (AEM) ARMv8-A
* ARMAEMv8AMPCT
*
* RTSM_VE_AEMv8A.lisa
*/
/dts-v1/;
/memreserve/ 0x80000000 0x00010000;
/ {
model = "RTSM_VE_AEMv8A";
compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
aliases {
serial0 = &v2m_serial0;
serial1 = &v2m_serial1;
serial2 = &v2m_serial2;
serial3 = &v2m_serial3;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>,
<0x00000008 0x80000000 0 0x80000000>;
};
gic: interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0x2c001000 0 0x1000>,
<0x0 0x2c002000 0 0x1000>,
<0x0 0x2c004000 0 0x2000>,
<0x0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xff01>,
<1 14 0xff01>,
<1 11 0xff01>,
<1 10 0xff01>;
clock-frequency = <100000000>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 60 4>,
<0 61 4>,
<0 62 4>,
<0 63 4>;
};
smb {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0 0x08000000 0x04000000>,
<1 0 0 0x14000000 0x04000000>,
<2 0 0 0x18000000 0x04000000>,
<3 0 0 0x1c000000 0x04000000>,
<4 0 0 0x0c000000 0x04000000>,
<5 0 0 0x10000000 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic 0 0 4>,
<0 0 1 &gic 0 1 4>,
<0 0 2 &gic 0 2 4>,
<0 0 3 &gic 0 3 4>,
<0 0 4 &gic 0 4 4>,
<0 0 5 &gic 0 5 4>,
<0 0 6 &gic 0 6 4>,
<0 0 7 &gic 0 7 4>,
<0 0 8 &gic 0 8 4>,
<0 0 9 &gic 0 9 4>,
<0 0 10 &gic 0 10 4>,
<0 0 11 &gic 0 11 4>,
<0 0 12 &gic 0 12 4>,
<0 0 13 &gic 0 13 4>,
<0 0 14 &gic 0 14 4>,
<0 0 15 &gic 0 15 4>,
<0 0 16 &gic 0 16 4>,
<0 0 17 &gic 0 17 4>,
<0 0 18 &gic 0 18 4>,
<0 0 19 &gic 0 19 4>,
<0 0 20 &gic 0 20 4>,
<0 0 21 &gic 0 21 4>,
<0 0 22 &gic 0 22 4>,
<0 0 23 &gic 0 23 4>,
<0 0 24 &gic 0 24 4>,
<0 0 25 &gic 0 25 4>,
<0 0 26 &gic 0 26 4>,
<0 0 27 &gic 0 27 4>,
<0 0 28 &gic 0 28 4>,
<0 0 29 &gic 0 29 4>,
<0 0 30 &gic 0 30 4>,
<0 0 31 &gic 0 31 4>,
<0 0 32 &gic 0 32 4>,
<0 0 33 &gic 0 33 4>,
<0 0 34 &gic 0 34 4>,
<0 0 35 &gic 0 35 4>,
<0 0 36 &gic 0 36 4>,
<0 0 37 &gic 0 37 4>,
<0 0 38 &gic 0 38 4>,
<0 0 39 &gic 0 39 4>,
<0 0 40 &gic 0 40 4>,
<0 0 41 &gic 0 41 4>,
<0 0 42 &gic 0 42 4>;
/include/ "rtsm_ve-motherboard.dtsi"
};
};

273
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/*
* ARM Ltd. Fast Models
*
* Versatile Express (VE) system model
* Motherboard component
*
* VEMotherBoard.lisa
*/
motherboard {
arm,v2m-memory-map = "rs1";
compatible = "arm,vexpress,v2m-p1", "simple-bus";
#address-cells = <2>; /* SMB chipselect number and offset */
#size-cells = <1>;
#interrupt-cells = <1>;
ranges;
flash@0,00000000 {
compatible = "arm,vexpress-flash", "cfi-flash";
reg = <0 0x00000000 0x04000000>,
<4 0x00000000 0x04000000>;
bank-width = <4>;
};
v2m_video_ram: vram@2,00000000 {
compatible = "arm,vexpress-vram";
reg = <2 0x00000000 0x00800000>;
};
ethernet@2,02000000 {
compatible = "smsc,lan91c111";
reg = <2 0x02000000 0x10000>;
interrupts = <15>;
};
v2m_clk24mhz: clk24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
v2m_refclk1mhz: refclk1mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
v2m_refclk32khz: refclk32khz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "v2m:refclk32khz";
};
iofpga@3,00000000 {
compatible = "arm,amba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 3 0 0x200000>;
v2m_sysreg: sysreg@010000 {
compatible = "arm,vexpress-sysreg";
reg = <0x010000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
};
v2m_sysctl: sysctl@020000 {
compatible = "arm,sp810", "arm,primecell";
reg = <0x020000 0x1000>;
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
clock-names = "refclk", "timclk", "apb_pclk";
#clock-cells = <1>;
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
};
aaci@040000 {
compatible = "arm,pl041", "arm,primecell";
reg = <0x040000 0x1000>;
interrupts = <11>;
clocks = <&v2m_clk24mhz>;
clock-names = "apb_pclk";
};
mmci@050000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x050000 0x1000>;
interrupts = <9 10>;
cd-gpios = <&v2m_sysreg 0 0>;
wp-gpios = <&v2m_sysreg 1 0>;
max-frequency = <12000000>;
vmmc-supply = <&v2m_fixed_3v3>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "mclk", "apb_pclk";
};
kmi@060000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x060000 0x1000>;
interrupts = <12>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@070000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x070000 0x1000>;
interrupts = <13>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
v2m_serial0: uart@090000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x090000 0x1000>;
interrupts = <5>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial1: uart@0a0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0a0000 0x1000>;
interrupts = <6>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial2: uart@0b0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0b0000 0x1000>;
interrupts = <7>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial3: uart@0c0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0c0000 0x1000>;
interrupts = <8>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
wdt@0f0000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0f0000 0x1000>;
interrupts = <0>;
clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
clock-names = "wdogclk", "apb_pclk";
};
v2m_timer01: timer@110000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x110000 0x1000>;
interrupts = <2>;
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
clock-names = "timclken1", "timclken2", "apb_pclk";
};
v2m_timer23: timer@120000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x120000 0x1000>;
interrupts = <3>;
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
clock-names = "timclken1", "timclken2", "apb_pclk";
};
rtc@170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x170000 0x1000>;
interrupts = <4>;
clocks = <&v2m_clk24mhz>;
clock-names = "apb_pclk";
};
clcd@1f0000 {
compatible = "arm,pl111", "arm,primecell";
reg = <0x1f0000 0x1000>;
interrupt-names = "combined";
interrupts = <14>;
clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
clock-names = "clcdclk", "apb_pclk";
arm,pl11x,framebuffer = <0x18000000 0x00180000>;
memory-region = <&v2m_video_ram>;
max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
port {
v2m_clcd_pads: endpoint {
remote-endpoint = <&v2m_clcd_panel>;
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
};
};
panel {
compatible = "panel-dpi";
port {
v2m_clcd_panel: endpoint {
remote-endpoint = <&v2m_clcd_pads>;
};
};
panel-timing {
clock-frequency = <63500127>;
hactive = <1024>;
hback-porch = <152>;
hfront-porch = <48>;
hsync-len = <104>;
vactive = <768>;
vback-porch = <23>;
vfront-porch = <3>;
vsync-len = <4>;
};
};
};
virtio_block@0130000 {
compatible = "virtio,mmio";
reg = <0x130000 0x200>;
interrupts = <42>;
};
};
v2m_fixed_3v3: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
mcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
v2m_oscclk1: osc@1 {
/* CLCD clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
freq-range = <23750000 63500000>;
#clock-cells = <0>;
clock-output-names = "v2m:oscclk1";
};
reset@0 {
compatible = "arm,vexpress-reset";
arm,vexpress-sysreg,func = <5 0>;
};
muxfpga@0 {
compatible = "arm,vexpress-muxfpga";
arm,vexpress-sysreg,func = <7 0>;
};
shutdown@0 {
compatible = "arm,vexpress-shutdown";
arm,vexpress-sysreg,func = <8 0>;
};
reboot@0 {
compatible = "arm,vexpress-reboot";
arm,vexpress-sysreg,func = <9 0>;
};
dvimode@0 {
compatible = "arm,vexpress-dvimode";
arm,vexpress-sysreg,func = <11 0>;
};
};
};

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arch/arm64/boot/dts/skeleton.dtsi Normal file
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/*
* Skeleton device tree; the bare minimum needed to boot; just include and
* add a compatible value. The bootloader will typically populate the memory
* node.
*/
/ {
#address-cells = <2>;
#size-cells = <1>;
chosen { };
aliases { };
memory { device_type = "memory"; reg = <0 0 0>; };
};

46
arch/arm64/boot/install.sh Normal file
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#!/bin/sh
#
# arch/arm64/boot/install.sh
#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
# Copyright (C) 1995 by Linus Torvalds
#
# Adapted from code in arch/i386/boot/Makefile by H. Peter Anvin
# Adapted from code in arch/i386/boot/install.sh by Russell King
#
# "make install" script for the AArch64 Linux port
#
# Arguments:
# $1 - kernel version
# $2 - kernel image file
# $3 - kernel map file
# $4 - default install path (blank if root directory)
#
# User may have a custom install script
if [ -x ~/bin/${INSTALLKERNEL} ]; then exec ~/bin/${INSTALLKERNEL} "$@"; fi
if [ -x /sbin/${INSTALLKERNEL} ]; then exec /sbin/${INSTALLKERNEL} "$@"; fi
if [ "$(basename $2)" = "Image.gz" ]; then
# Compressed install
echo "Installing compressed kernel"
base=vmlinuz
else
# Normal install
echo "Installing normal kernel"
base=vmlinux
fi
if [ -f $4/$base-$1 ]; then
mv $4/$base-$1 $4/$base-$1.old
fi
cat $2 > $4/$base-$1
# Install system map file
if [ -f $4/System.map-$1 ]; then
mv $4/System.map-$1 $4/System.map-$1.old
fi
cp $3 $4/System.map-$1