mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
282
arch/avr32/mach-at32ap/hsmc.c
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282
arch/avr32/mach-at32ap/hsmc.c
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/*
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* Static Memory Controller for AT32 chips
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*
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* Copyright (C) 2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <asm/io.h>
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#include <mach/smc.h>
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#include "hsmc.h"
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#define NR_CHIP_SELECTS 6
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struct hsmc {
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void __iomem *regs;
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struct clk *pclk;
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struct clk *mck;
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};
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static struct hsmc *hsmc;
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void smc_set_timing(struct smc_config *config,
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const struct smc_timing *timing)
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{
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int recover;
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int cycle;
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unsigned long mul;
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/* Reset all SMC timings */
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config->ncs_read_setup = 0;
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config->nrd_setup = 0;
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config->ncs_write_setup = 0;
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config->nwe_setup = 0;
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config->ncs_read_pulse = 0;
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config->nrd_pulse = 0;
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config->ncs_write_pulse = 0;
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config->nwe_pulse = 0;
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config->read_cycle = 0;
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config->write_cycle = 0;
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/*
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* cycles = x / T = x * f
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* = ((x * 1000000000) * ((f * 65536) / 1000000000)) / 65536
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* = ((x * 1000000000) * (((f / 10000) * 65536) / 100000)) / 65536
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*/
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mul = (clk_get_rate(hsmc->mck) / 10000) << 16;
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mul /= 100000;
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#define ns2cyc(x) ((((x) * mul) + 65535) >> 16)
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if (timing->ncs_read_setup > 0)
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config->ncs_read_setup = ns2cyc(timing->ncs_read_setup);
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if (timing->nrd_setup > 0)
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config->nrd_setup = ns2cyc(timing->nrd_setup);
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if (timing->ncs_write_setup > 0)
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config->ncs_write_setup = ns2cyc(timing->ncs_write_setup);
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if (timing->nwe_setup > 0)
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config->nwe_setup = ns2cyc(timing->nwe_setup);
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if (timing->ncs_read_pulse > 0)
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config->ncs_read_pulse = ns2cyc(timing->ncs_read_pulse);
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if (timing->nrd_pulse > 0)
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config->nrd_pulse = ns2cyc(timing->nrd_pulse);
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if (timing->ncs_write_pulse > 0)
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config->ncs_write_pulse = ns2cyc(timing->ncs_write_pulse);
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if (timing->nwe_pulse > 0)
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config->nwe_pulse = ns2cyc(timing->nwe_pulse);
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if (timing->read_cycle > 0)
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config->read_cycle = ns2cyc(timing->read_cycle);
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if (timing->write_cycle > 0)
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config->write_cycle = ns2cyc(timing->write_cycle);
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/* Extend read cycle in needed */
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if (timing->ncs_read_recover > 0)
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recover = ns2cyc(timing->ncs_read_recover);
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else
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recover = 1;
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cycle = config->ncs_read_setup + config->ncs_read_pulse + recover;
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if (config->read_cycle < cycle)
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config->read_cycle = cycle;
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/* Extend read cycle in needed */
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if (timing->nrd_recover > 0)
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recover = ns2cyc(timing->nrd_recover);
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else
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recover = 1;
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cycle = config->nrd_setup + config->nrd_pulse + recover;
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if (config->read_cycle < cycle)
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config->read_cycle = cycle;
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/* Extend write cycle in needed */
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if (timing->ncs_write_recover > 0)
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recover = ns2cyc(timing->ncs_write_recover);
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else
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recover = 1;
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cycle = config->ncs_write_setup + config->ncs_write_pulse + recover;
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if (config->write_cycle < cycle)
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config->write_cycle = cycle;
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/* Extend write cycle in needed */
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if (timing->nwe_recover > 0)
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recover = ns2cyc(timing->nwe_recover);
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else
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recover = 1;
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cycle = config->nwe_setup + config->nwe_pulse + recover;
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if (config->write_cycle < cycle)
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config->write_cycle = cycle;
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}
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EXPORT_SYMBOL(smc_set_timing);
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int smc_set_configuration(int cs, const struct smc_config *config)
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{
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unsigned long offset;
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u32 setup, pulse, cycle, mode;
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if (!hsmc)
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return -ENODEV;
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if (cs >= NR_CHIP_SELECTS)
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return -EINVAL;
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setup = (HSMC_BF(NWE_SETUP, config->nwe_setup)
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| HSMC_BF(NCS_WR_SETUP, config->ncs_write_setup)
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| HSMC_BF(NRD_SETUP, config->nrd_setup)
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| HSMC_BF(NCS_RD_SETUP, config->ncs_read_setup));
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pulse = (HSMC_BF(NWE_PULSE, config->nwe_pulse)
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| HSMC_BF(NCS_WR_PULSE, config->ncs_write_pulse)
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| HSMC_BF(NRD_PULSE, config->nrd_pulse)
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| HSMC_BF(NCS_RD_PULSE, config->ncs_read_pulse));
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cycle = (HSMC_BF(NWE_CYCLE, config->write_cycle)
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| HSMC_BF(NRD_CYCLE, config->read_cycle));
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switch (config->bus_width) {
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case 1:
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mode = HSMC_BF(DBW, HSMC_DBW_8_BITS);
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break;
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case 2:
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mode = HSMC_BF(DBW, HSMC_DBW_16_BITS);
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break;
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case 4:
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mode = HSMC_BF(DBW, HSMC_DBW_32_BITS);
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break;
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default:
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return -EINVAL;
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}
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switch (config->nwait_mode) {
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case 0:
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mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_DISABLED);
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break;
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case 1:
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mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_RESERVED);
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break;
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case 2:
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mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_FROZEN);
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break;
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case 3:
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mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_READY);
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break;
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default:
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return -EINVAL;
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}
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if (config->tdf_cycles) {
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mode |= HSMC_BF(TDF_CYCLES, config->tdf_cycles);
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}
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if (config->nrd_controlled)
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mode |= HSMC_BIT(READ_MODE);
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if (config->nwe_controlled)
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mode |= HSMC_BIT(WRITE_MODE);
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if (config->byte_write)
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mode |= HSMC_BIT(BAT);
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if (config->tdf_mode)
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mode |= HSMC_BIT(TDF_MODE);
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pr_debug("smc cs%d: setup/%08x pulse/%08x cycle/%08x mode/%08x\n",
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cs, setup, pulse, cycle, mode);
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offset = cs * 0x10;
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hsmc_writel(hsmc, SETUP0 + offset, setup);
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hsmc_writel(hsmc, PULSE0 + offset, pulse);
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hsmc_writel(hsmc, CYCLE0 + offset, cycle);
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hsmc_writel(hsmc, MODE0 + offset, mode);
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hsmc_readl(hsmc, MODE0); /* I/O barrier */
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return 0;
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}
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EXPORT_SYMBOL(smc_set_configuration);
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static int hsmc_probe(struct platform_device *pdev)
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{
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struct resource *regs;
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struct clk *pclk, *mck;
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int ret;
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if (hsmc)
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return -EBUSY;
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!regs)
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return -ENXIO;
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pclk = clk_get(&pdev->dev, "pclk");
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if (IS_ERR(pclk))
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return PTR_ERR(pclk);
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mck = clk_get(&pdev->dev, "mck");
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if (IS_ERR(mck)) {
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ret = PTR_ERR(mck);
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goto out_put_pclk;
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}
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ret = -ENOMEM;
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hsmc = kzalloc(sizeof(struct hsmc), GFP_KERNEL);
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if (!hsmc)
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goto out_put_clocks;
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clk_enable(pclk);
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clk_enable(mck);
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hsmc->pclk = pclk;
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hsmc->mck = mck;
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hsmc->regs = ioremap(regs->start, resource_size(regs));
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if (!hsmc->regs)
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goto out_disable_clocks;
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dev_info(&pdev->dev, "Atmel Static Memory Controller at 0x%08lx\n",
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(unsigned long)regs->start);
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platform_set_drvdata(pdev, hsmc);
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return 0;
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out_disable_clocks:
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clk_disable(mck);
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clk_disable(pclk);
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kfree(hsmc);
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out_put_clocks:
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clk_put(mck);
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out_put_pclk:
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clk_put(pclk);
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hsmc = NULL;
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return ret;
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}
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static struct platform_driver hsmc_driver = {
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.probe = hsmc_probe,
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.driver = {
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.name = "smc",
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},
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};
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static int __init hsmc_init(void)
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{
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return platform_driver_register(&hsmc_driver);
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}
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core_initcall(hsmc_init);
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