mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-09 01:28:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
10
arch/blackfin/kernel/cplb-nompu/Makefile
Normal file
10
arch/blackfin/kernel/cplb-nompu/Makefile
Normal file
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@ -0,0 +1,10 @@
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#
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# arch/blackfin/kernel/cplb-nompu/Makefile
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#
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obj-y := cplbinit.o cplbmgr.o
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CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \
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-ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
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-ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \
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-ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3
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212
arch/blackfin/kernel/cplb-nompu/cplbinit.c
Normal file
212
arch/blackfin/kernel/cplb-nompu/cplbinit.c
Normal file
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@ -0,0 +1,212 @@
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/*
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* Blackfin CPLB initialization
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*
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* Copyright 2007-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/module.h>
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#include <asm/blackfin.h>
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#include <asm/cacheflush.h>
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#include <asm/cplb.h>
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#include <asm/cplbinit.h>
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#include <asm/mem_map.h>
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struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
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struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
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int first_switched_icplb PDT_ATTR;
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int first_switched_dcplb PDT_ATTR;
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struct cplb_boundary dcplb_bounds[9] PDT_ATTR;
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struct cplb_boundary icplb_bounds[9] PDT_ATTR;
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int icplb_nr_bounds PDT_ATTR;
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int dcplb_nr_bounds PDT_ATTR;
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void __init generate_cplb_tables_cpu(unsigned int cpu)
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{
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int i_d, i_i;
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unsigned long addr;
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unsigned long cplb_pageflags, cplb_pagesize;
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struct cplb_entry *d_tbl = dcplb_tbl[cpu];
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struct cplb_entry *i_tbl = icplb_tbl[cpu];
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printk(KERN_INFO "NOMPU: setting up cplb tables\n");
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i_d = i_i = 0;
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#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
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/* Set up the zero page. */
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d_tbl[i_d].addr = 0;
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d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
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i_tbl[i_i].addr = 0;
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i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
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#endif
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/* Cover kernel memory with 4M pages. */
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addr = 0;
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#ifdef PAGE_SIZE_16MB
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cplb_pageflags = PAGE_SIZE_16MB;
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cplb_pagesize = SIZE_16M;
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#else
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cplb_pageflags = PAGE_SIZE_4MB;
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cplb_pagesize = SIZE_4M;
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#endif
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for (; addr < memory_start; addr += cplb_pagesize) {
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d_tbl[i_d].addr = addr;
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d_tbl[i_d++].data = SDRAM_DGENERIC | cplb_pageflags;
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i_tbl[i_i].addr = addr;
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i_tbl[i_i++].data = SDRAM_IGENERIC | cplb_pageflags;
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}
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#ifdef CONFIG_ROMKERNEL
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/* Cover kernel XIP flash area */
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#ifdef CONFIG_BF60x
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addr = CONFIG_ROM_BASE & ~(16 * 1024 * 1024 - 1);
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d_tbl[i_d].addr = addr;
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d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_16MB;
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i_tbl[i_i].addr = addr;
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i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_16MB;
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#else
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addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1);
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d_tbl[i_d].addr = addr;
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d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;
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i_tbl[i_i].addr = addr;
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i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;
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#endif
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#endif
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/* Cover L1 memory. One 4M area for code and data each is enough. */
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if (cpu == 0) {
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if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
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d_tbl[i_d].addr = L1_DATA_A_START;
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d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
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}
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i_tbl[i_i].addr = L1_CODE_START;
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i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
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}
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#ifdef CONFIG_SMP
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else {
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if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
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d_tbl[i_d].addr = COREB_L1_DATA_A_START;
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d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
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}
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i_tbl[i_i].addr = COREB_L1_CODE_START;
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i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
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}
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#endif
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first_switched_dcplb = i_d;
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first_switched_icplb = i_i;
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BUG_ON(first_switched_dcplb > MAX_CPLBS);
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BUG_ON(first_switched_icplb > MAX_CPLBS);
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while (i_d < MAX_CPLBS)
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d_tbl[i_d++].data = 0;
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while (i_i < MAX_CPLBS)
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i_tbl[i_i++].data = 0;
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}
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void __init generate_cplb_tables_all(void)
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{
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unsigned long uncached_end;
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int i_d, i_i;
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i_d = 0;
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/* Normal RAM, including MTD FS. */
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#ifdef CONFIG_MTD_UCLINUX
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uncached_end = memory_mtd_start + mtd_size;
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#else
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uncached_end = memory_end;
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#endif
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/*
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* if DMA uncached is less than 1MB, mark the 1MB chunk as uncached
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* so that we don't have to use 4kB pages and cause CPLB thrashing
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*/
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if ((DMA_UNCACHED_REGION >= 1 * 1024 * 1024) || !DMA_UNCACHED_REGION ||
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((_ramend - uncached_end) >= 1 * 1024 * 1024))
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dcplb_bounds[i_d].eaddr = uncached_end;
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else
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dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024 - 1);
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dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
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/* DMA uncached region. */
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if (DMA_UNCACHED_REGION) {
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dcplb_bounds[i_d].eaddr = _ramend;
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dcplb_bounds[i_d++].data = SDRAM_DNON_CHBL;
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}
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if (_ramend != physical_mem_end) {
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/* Reserved memory. */
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dcplb_bounds[i_d].eaddr = physical_mem_end;
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dcplb_bounds[i_d++].data = (reserved_mem_dcache_on ?
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SDRAM_DGENERIC : SDRAM_DNON_CHBL);
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}
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/* Addressing hole up to the async bank. */
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dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE;
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dcplb_bounds[i_d++].data = 0;
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/* ASYNC banks. */
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dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
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dcplb_bounds[i_d++].data = SDRAM_EBIU;
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/* Addressing hole up to BootROM. */
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dcplb_bounds[i_d].eaddr = BOOT_ROM_START;
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dcplb_bounds[i_d++].data = 0;
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/* BootROM -- largest one should be less than 1 meg. */
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dcplb_bounds[i_d].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
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dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
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if (L2_LENGTH) {
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/* Addressing hole up to L2 SRAM. */
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dcplb_bounds[i_d].eaddr = L2_START;
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dcplb_bounds[i_d++].data = 0;
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/* L2 SRAM. */
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dcplb_bounds[i_d].eaddr = L2_START + L2_LENGTH;
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dcplb_bounds[i_d++].data = L2_DMEMORY;
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}
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dcplb_nr_bounds = i_d;
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BUG_ON(dcplb_nr_bounds > ARRAY_SIZE(dcplb_bounds));
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i_i = 0;
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/* Normal RAM, including MTD FS. */
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icplb_bounds[i_i].eaddr = uncached_end;
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icplb_bounds[i_i++].data = SDRAM_IGENERIC;
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if (_ramend != physical_mem_end) {
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/* DMA uncached region. */
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if (DMA_UNCACHED_REGION) {
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/* Normally this hole is caught by the async below. */
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icplb_bounds[i_i].eaddr = _ramend;
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icplb_bounds[i_i++].data = 0;
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}
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/* Reserved memory. */
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icplb_bounds[i_i].eaddr = physical_mem_end;
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icplb_bounds[i_i++].data = (reserved_mem_icache_on ?
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SDRAM_IGENERIC : SDRAM_INON_CHBL);
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}
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/* Addressing hole up to the async bank. */
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icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE;
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icplb_bounds[i_i++].data = 0;
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/* ASYNC banks. */
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icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
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icplb_bounds[i_i++].data = SDRAM_EBIU;
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/* Addressing hole up to BootROM. */
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icplb_bounds[i_i].eaddr = BOOT_ROM_START;
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icplb_bounds[i_i++].data = 0;
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/* BootROM -- largest one should be less than 1 meg. */
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icplb_bounds[i_i].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
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icplb_bounds[i_i++].data = SDRAM_IGENERIC;
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if (L2_LENGTH) {
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/* Addressing hole up to L2 SRAM. */
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icplb_bounds[i_i].eaddr = L2_START;
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icplb_bounds[i_i++].data = 0;
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/* L2 SRAM. */
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icplb_bounds[i_i].eaddr = L2_START + L2_LENGTH;
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icplb_bounds[i_i++].data = L2_IMEMORY;
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}
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icplb_nr_bounds = i_i;
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BUG_ON(icplb_nr_bounds > ARRAY_SIZE(icplb_bounds));
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}
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227
arch/blackfin/kernel/cplb-nompu/cplbmgr.c
Normal file
227
arch/blackfin/kernel/cplb-nompu/cplbmgr.c
Normal file
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@ -0,0 +1,227 @@
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/*
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* Based on: arch/blackfin/kernel/cplb-mpu/cplbmgr.c
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* Author: Michael McTernan <mmcternan@airvana.com>
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*
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* Description: CPLB miss handler.
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*
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* Modified:
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* Copyright 2008 Airvana Inc.
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* Copyright 2008-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later
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*/
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#include <linux/kernel.h>
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#include <asm/blackfin.h>
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#include <asm/cplbinit.h>
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#include <asm/cplb.h>
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#include <asm/mmu_context.h>
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#include <asm/traps.h>
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|
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/*
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* WARNING
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*
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* This file is compiled with certain -ffixed-reg options. We have to
|
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* make sure not to call any functions here that could clobber these
|
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* registers.
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*/
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int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
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int nr_dcplb_supv_miss[NR_CPUS], nr_icplb_supv_miss[NR_CPUS];
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int nr_cplb_flush[NR_CPUS], nr_dcplb_prot[NR_CPUS];
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#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
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#define MGR_ATTR __attribute__((l1_text))
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#else
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#define MGR_ATTR
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#endif
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static inline void write_dcplb_data(int cpu, int idx, unsigned long data,
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unsigned long addr)
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{
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_disable_dcplb();
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bfin_write32(DCPLB_DATA0 + idx * 4, data);
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bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
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_enable_dcplb();
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|
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#ifdef CONFIG_CPLB_INFO
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dcplb_tbl[cpu][idx].addr = addr;
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dcplb_tbl[cpu][idx].data = data;
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#endif
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}
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|
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static inline void write_icplb_data(int cpu, int idx, unsigned long data,
|
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unsigned long addr)
|
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{
|
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_disable_icplb();
|
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bfin_write32(ICPLB_DATA0 + idx * 4, data);
|
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bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
|
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_enable_icplb();
|
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|
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#ifdef CONFIG_CPLB_INFO
|
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icplb_tbl[cpu][idx].addr = addr;
|
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icplb_tbl[cpu][idx].data = data;
|
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#endif
|
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}
|
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|
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/* Counters to implement round-robin replacement. */
|
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static int icplb_rr_index[NR_CPUS] PDT_ATTR;
|
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static int dcplb_rr_index[NR_CPUS] PDT_ATTR;
|
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|
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/*
|
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* Find an ICPLB entry to be evicted and return its index.
|
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*/
|
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static int evict_one_icplb(int cpu)
|
||||
{
|
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int i = first_switched_icplb + icplb_rr_index[cpu];
|
||||
if (i >= MAX_CPLBS) {
|
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i -= MAX_CPLBS - first_switched_icplb;
|
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icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
|
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}
|
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icplb_rr_index[cpu]++;
|
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return i;
|
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}
|
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|
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static int evict_one_dcplb(int cpu)
|
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{
|
||||
int i = first_switched_dcplb + dcplb_rr_index[cpu];
|
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if (i >= MAX_CPLBS) {
|
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i -= MAX_CPLBS - first_switched_dcplb;
|
||||
dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
|
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}
|
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dcplb_rr_index[cpu]++;
|
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return i;
|
||||
}
|
||||
|
||||
MGR_ATTR static int icplb_miss(int cpu)
|
||||
{
|
||||
unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
|
||||
int status = bfin_read_ICPLB_STATUS();
|
||||
int idx;
|
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unsigned long i_data, base, addr1, eaddr;
|
||||
|
||||
nr_icplb_miss[cpu]++;
|
||||
if (unlikely(status & FAULT_USERSUPV))
|
||||
nr_icplb_supv_miss[cpu]++;
|
||||
|
||||
base = 0;
|
||||
idx = 0;
|
||||
do {
|
||||
eaddr = icplb_bounds[idx].eaddr;
|
||||
if (addr < eaddr)
|
||||
break;
|
||||
base = eaddr;
|
||||
} while (++idx < icplb_nr_bounds);
|
||||
|
||||
if (unlikely(idx == icplb_nr_bounds))
|
||||
return CPLB_NO_ADDR_MATCH;
|
||||
|
||||
i_data = icplb_bounds[idx].data;
|
||||
if (unlikely(i_data == 0))
|
||||
return CPLB_NO_ADDR_MATCH;
|
||||
|
||||
addr1 = addr & ~(SIZE_4M - 1);
|
||||
addr &= ~(SIZE_1M - 1);
|
||||
i_data |= PAGE_SIZE_1MB;
|
||||
if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) {
|
||||
/*
|
||||
* This works because
|
||||
* (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
|
||||
*/
|
||||
i_data |= PAGE_SIZE_4MB;
|
||||
addr = addr1;
|
||||
}
|
||||
|
||||
/* Pick entry to evict */
|
||||
idx = evict_one_icplb(cpu);
|
||||
|
||||
write_icplb_data(cpu, idx, i_data, addr);
|
||||
|
||||
return CPLB_RELOADED;
|
||||
}
|
||||
|
||||
MGR_ATTR static int dcplb_miss(int cpu)
|
||||
{
|
||||
unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
|
||||
int status = bfin_read_DCPLB_STATUS();
|
||||
int idx;
|
||||
unsigned long d_data, base, addr1, eaddr, cplb_pagesize, cplb_pageflags;
|
||||
|
||||
nr_dcplb_miss[cpu]++;
|
||||
if (unlikely(status & FAULT_USERSUPV))
|
||||
nr_dcplb_supv_miss[cpu]++;
|
||||
|
||||
base = 0;
|
||||
idx = 0;
|
||||
do {
|
||||
eaddr = dcplb_bounds[idx].eaddr;
|
||||
if (addr < eaddr)
|
||||
break;
|
||||
base = eaddr;
|
||||
} while (++idx < dcplb_nr_bounds);
|
||||
|
||||
if (unlikely(idx == dcplb_nr_bounds))
|
||||
return CPLB_NO_ADDR_MATCH;
|
||||
|
||||
d_data = dcplb_bounds[idx].data;
|
||||
if (unlikely(d_data == 0))
|
||||
return CPLB_NO_ADDR_MATCH;
|
||||
|
||||
addr &= ~(SIZE_1M - 1);
|
||||
d_data |= PAGE_SIZE_1MB;
|
||||
|
||||
/* BF60x support large than 4M CPLB page size */
|
||||
#ifdef PAGE_SIZE_16MB
|
||||
cplb_pageflags = PAGE_SIZE_16MB;
|
||||
cplb_pagesize = SIZE_16M;
|
||||
#else
|
||||
cplb_pageflags = PAGE_SIZE_4MB;
|
||||
cplb_pagesize = SIZE_4M;
|
||||
#endif
|
||||
|
||||
find_pagesize:
|
||||
addr1 = addr & ~(cplb_pagesize - 1);
|
||||
if (addr1 >= base && (addr1 + cplb_pagesize) <= eaddr) {
|
||||
/*
|
||||
* This works because
|
||||
* (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
|
||||
*/
|
||||
d_data |= cplb_pageflags;
|
||||
addr = addr1;
|
||||
goto found_pagesize;
|
||||
} else {
|
||||
if (cplb_pagesize > SIZE_4M) {
|
||||
cplb_pageflags = PAGE_SIZE_4MB;
|
||||
cplb_pagesize = SIZE_4M;
|
||||
goto find_pagesize;
|
||||
}
|
||||
}
|
||||
|
||||
found_pagesize:
|
||||
#ifdef CONFIG_BF60x
|
||||
if ((addr >= ASYNC_BANK0_BASE)
|
||||
&& (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
|
||||
d_data |= PAGE_SIZE_64MB;
|
||||
#endif
|
||||
|
||||
/* Pick entry to evict */
|
||||
idx = evict_one_dcplb(cpu);
|
||||
|
||||
write_dcplb_data(cpu, idx, d_data, addr);
|
||||
|
||||
return CPLB_RELOADED;
|
||||
}
|
||||
|
||||
MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs)
|
||||
{
|
||||
int cause = seqstat & 0x3f;
|
||||
unsigned int cpu = raw_smp_processor_id();
|
||||
switch (cause) {
|
||||
case VEC_CPLB_I_M:
|
||||
return icplb_miss(cpu);
|
||||
case VEC_CPLB_M:
|
||||
return dcplb_miss(cpu);
|
||||
default:
|
||||
return CPLB_UNKNOWN_ERR;
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue