mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 08:08:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
290
arch/blackfin/mach-bf527/include/mach/anomaly.h
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290
arch/blackfin/mach-bf527/include/mach/anomaly.h
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@ -0,0 +1,290 @@
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/*
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* DO NOT EDIT THIS FILE
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* This file is under version control at
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* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
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* and can be replaced with that version at any time
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* DO NOT EDIT THIS FILE
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*
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* Copyright 2004-2011 Analog Devices Inc.
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* Licensed under the Clear BSD license.
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*/
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/* This file should be up to date with:
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* - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
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* - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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/* We do not support old silicon - sorry */
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#if __SILICON_REVISION__ < 0
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# error will not work on BF526/BF527 silicon version
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#endif
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#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
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# define ANOMALY_BF526 1
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#else
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# define ANOMALY_BF526 0
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#endif
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#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
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# define ANOMALY_BF527 1
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#else
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# define ANOMALY_BF527 0
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#endif
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#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526)
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#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
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#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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#define ANOMALY_05000119 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
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#define ANOMALY_05000254 (1)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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#define ANOMALY_05000265 (1)
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_05000310 (1)
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/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
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#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Incorrect Access of OTP_STATUS During otp_write() Function */
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#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
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/* Host DMA Boot Modes Are Not Functional */
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#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
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/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
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#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
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/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
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#define ANOMALY_05000341 (_ANOMALY_BF527(< 2))
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/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
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#define ANOMALY_05000342 (_ANOMALY_BF527(< 2))
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/* USB Calibration Value Is Not Initialized */
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#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* USB Calibration Value to use */
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#define ANOMALY_05000346_value 0xE510
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/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
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#define ANOMALY_05000347 (_ANOMALY_BF527(< 2))
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/* Security Features Are Not Functional */
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#define ANOMALY_05000348 (_ANOMALY_BF527(< 1))
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/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
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#define ANOMALY_05000353 (_ANOMALY_BF526(< 1))
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/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
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#define ANOMALY_05000355 (_ANOMALY_BF527(< 2))
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (_ANOMALY_BF527(< 2))
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/* Incorrect Revision Number in DSPID Register */
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#define ANOMALY_05000364 (_ANOMALY_BF527(== 1))
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* Incorrect Default CSEL Value in PLL_DIV */
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#define ANOMALY_05000368 (_ANOMALY_BF527(< 2))
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (_ANOMALY_BF527(< 2))
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/* Authentication Fails To Initiate */
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#define ANOMALY_05000376 (_ANOMALY_BF527(< 2))
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/* Data Read From L3 Memory by USB DMA May be Corrupted */
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#define ANOMALY_05000380 (_ANOMALY_BF527(< 2))
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/* 8-Bit NAND Flash Boot Mode Not Functional */
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#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Boot from OTP Memory Not Functional */
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#define ANOMALY_05000385 (_ANOMALY_BF527(< 2))
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/* bfrom_SysControl() Firmware Routine Not Functional */
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#define ANOMALY_05000386 (_ANOMALY_BF527(< 2))
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/* Programmable Preboot Settings Not Functional */
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#define ANOMALY_05000387 (_ANOMALY_BF527(< 2))
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/* CRC32 Checksum Support Not Functional */
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#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Reset Vector Must Not Be in SDRAM Memory Space */
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#define ANOMALY_05000389 (_ANOMALY_BF527(< 2))
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/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
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#define ANOMALY_05000392 (_ANOMALY_BF527(< 2))
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/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
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#define ANOMALY_05000393 (_ANOMALY_BF527(< 2))
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/* Log Buffer Not Functional */
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#define ANOMALY_05000394 (_ANOMALY_BF527(< 2))
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/* Hook Routine Not Functional */
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#define ANOMALY_05000395 (_ANOMALY_BF527(< 2))
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/* Header Indirect Bit Not Functional */
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#define ANOMALY_05000396 (_ANOMALY_BF527(< 2))
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/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
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#define ANOMALY_05000397 (_ANOMALY_BF527(< 2))
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/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
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#define ANOMALY_05000398 (_ANOMALY_BF527(< 2))
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/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
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#define ANOMALY_05000399 (_ANOMALY_BF527(< 2))
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/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
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#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
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#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Lockbox SESR Disallows Certain User Interrupts */
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#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
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#define ANOMALY_05000405 (1)
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/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
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#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
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#define ANOMALY_05000408 (1)
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/* Lockbox firmware leaves MDMA0 channel enabled */
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#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Incorrect Default Internal Voltage Regulator Setting */
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#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
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/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
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#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
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/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
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#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* DEB2_URGENT Bit Not Functional */
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#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Speculative Fetches Can Cause Undesired External FIFO Operations */
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#define ANOMALY_05000416 (1)
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/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
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#define ANOMALY_05000417 (_ANOMALY_BF527(< 2))
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/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
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#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
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#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
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#define ANOMALY_05000421 (1)
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/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
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#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1))
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/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
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#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Internal Voltage Regulator Not Trimmed */
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#define ANOMALY_05000424 (_ANOMALY_BF527(< 2))
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/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
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#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
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#define ANOMALY_05000426 (1)
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/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
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#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Software System Reset Corrupts PLL_LOCKCNT Register */
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#define ANOMALY_05000430 (_ANOMALY_BF527(> 1))
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/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
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#define ANOMALY_05000431 (1)
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/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
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#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
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/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
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#define ANOMALY_05000434 (1)
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/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
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#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
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/* Preboot Cannot be Used to Alter the PLL_DIV Register */
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#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0))
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/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
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#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0))
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/* OTP Write Accesses Not Supported */
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#define ANOMALY_05000442 (_ANOMALY_BF527(< 1))
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/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
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#define ANOMALY_05000443 (1)
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/* The WURESET Bit in the SYSCR Register is not Functional */
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#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
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/* USB DMA Short Packet Data Corruption */
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#define ANOMALY_05000450 (1)
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/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
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#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
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/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
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#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
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/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
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#define ANOMALY_05000456 (1)
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/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
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#define ANOMALY_05000457 (1)
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/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
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#define ANOMALY_05000460 (1)
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/* False Hardware Error when RETI Points to Invalid Memory */
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#define ANOMALY_05000461 (1)
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/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
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#define ANOMALY_05000462 (1)
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/* USB Rx DMA Hang */
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#define ANOMALY_05000465 (1)
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/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
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#define ANOMALY_05000466 (1)
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/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
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#define ANOMALY_05000467 (1)
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/* PLL Latches Incorrect Settings During Reset */
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#define ANOMALY_05000469 (1)
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/* Incorrect Default MSEL Value in PLL_CTL */
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#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
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/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
|
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#define ANOMALY_05000473 (1)
|
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/* Possible Lockup Condition when Modifying PLL from External Memory */
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#define ANOMALY_05000475 (1)
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/* TESTSET Instruction Cannot Be Interrupted */
|
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#define ANOMALY_05000477 (1)
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
|
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#define ANOMALY_05000481 (1)
|
||||
/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
|
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#define ANOMALY_05000483 (1)
|
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/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
|
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#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
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/* The CODEC Zero-Cross Detect Feature is not Functional */
|
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#define ANOMALY_05000487 (1)
|
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/* SPI Master Boot Can Fail Under Certain Conditions */
|
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#define ANOMALY_05000490 (1)
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/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
|
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#define ANOMALY_05000491 (1)
|
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/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
|
||||
#define ANOMALY_05000494 (1)
|
||||
/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
|
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#define ANOMALY_05000498 (1)
|
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/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
|
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#define ANOMALY_05000501 (1)
|
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|
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000099 (0)
|
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#define ANOMALY_05000120 (0)
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#define ANOMALY_05000125 (0)
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#define ANOMALY_05000149 (0)
|
||||
#define ANOMALY_05000158 (0)
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||||
#define ANOMALY_05000171 (0)
|
||||
#define ANOMALY_05000179 (0)
|
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#define ANOMALY_05000182 (0)
|
||||
#define ANOMALY_05000183 (0)
|
||||
#define ANOMALY_05000189 (0)
|
||||
#define ANOMALY_05000198 (0)
|
||||
#define ANOMALY_05000202 (0)
|
||||
#define ANOMALY_05000215 (0)
|
||||
#define ANOMALY_05000219 (0)
|
||||
#define ANOMALY_05000220 (0)
|
||||
#define ANOMALY_05000227 (0)
|
||||
#define ANOMALY_05000230 (0)
|
||||
#define ANOMALY_05000231 (0)
|
||||
#define ANOMALY_05000233 (0)
|
||||
#define ANOMALY_05000234 (0)
|
||||
#define ANOMALY_05000242 (0)
|
||||
#define ANOMALY_05000244 (0)
|
||||
#define ANOMALY_05000248 (0)
|
||||
#define ANOMALY_05000250 (0)
|
||||
#define ANOMALY_05000257 (0)
|
||||
#define ANOMALY_05000261 (0)
|
||||
#define ANOMALY_05000263 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000274 (0)
|
||||
#define ANOMALY_05000278 (0)
|
||||
#define ANOMALY_05000281 (0)
|
||||
#define ANOMALY_05000283 (0)
|
||||
#define ANOMALY_05000285 (0)
|
||||
#define ANOMALY_05000287 (0)
|
||||
#define ANOMALY_05000301 (0)
|
||||
#define ANOMALY_05000305 (0)
|
||||
#define ANOMALY_05000307 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000312 (0)
|
||||
#define ANOMALY_05000315 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000362 (1)
|
||||
#define ANOMALY_05000363 (0)
|
||||
#define ANOMALY_05000383 (0)
|
||||
#define ANOMALY_05000400 (0)
|
||||
#define ANOMALY_05000402 (0)
|
||||
#define ANOMALY_05000412 (0)
|
||||
#define ANOMALY_05000447 (0)
|
||||
#define ANOMALY_05000448 (0)
|
||||
#define ANOMALY_05000474 (0)
|
||||
#define ANOMALY_05000480 (0)
|
||||
#define ANOMALY_16000030 (0)
|
||||
|
||||
#endif
|
||||
237
arch/blackfin/mach-bf527/include/mach/bf527.h
Normal file
237
arch/blackfin/mach-bf527/include/mach/bf527.h
Normal file
|
|
@ -0,0 +1,237 @@
|
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/*
|
||||
* Copyright 2007-2009 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_BF527_H__
|
||||
#define __MACH_BF527_H__
|
||||
|
||||
#define OFFSET_(x) ((x) & 0x0000FFFF)
|
||||
|
||||
/*some misc defines*/
|
||||
#define IMASK_IVG15 0x8000
|
||||
#define IMASK_IVG14 0x4000
|
||||
#define IMASK_IVG13 0x2000
|
||||
#define IMASK_IVG12 0x1000
|
||||
|
||||
#define IMASK_IVG11 0x0800
|
||||
#define IMASK_IVG10 0x0400
|
||||
#define IMASK_IVG9 0x0200
|
||||
#define IMASK_IVG8 0x0100
|
||||
|
||||
#define IMASK_IVG7 0x0080
|
||||
#define IMASK_IVGTMR 0x0040
|
||||
#define IMASK_IVGHW 0x0020
|
||||
|
||||
/***************************/
|
||||
|
||||
#define BFIN_DSUBBANKS 4
|
||||
#define BFIN_DWAYS 2
|
||||
#define BFIN_DLINES 64
|
||||
#define BFIN_ISUBBANKS 4
|
||||
#define BFIN_IWAYS 4
|
||||
#define BFIN_ILINES 32
|
||||
|
||||
#define WAY0_L 0x1
|
||||
#define WAY1_L 0x2
|
||||
#define WAY01_L 0x3
|
||||
#define WAY2_L 0x4
|
||||
#define WAY02_L 0x5
|
||||
#define WAY12_L 0x6
|
||||
#define WAY012_L 0x7
|
||||
|
||||
#define WAY3_L 0x8
|
||||
#define WAY03_L 0x9
|
||||
#define WAY13_L 0xA
|
||||
#define WAY013_L 0xB
|
||||
|
||||
#define WAY32_L 0xC
|
||||
#define WAY320_L 0xD
|
||||
#define WAY321_L 0xE
|
||||
#define WAYALL_L 0xF
|
||||
|
||||
#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
|
||||
|
||||
/********************************* EBIU Settings ************************************/
|
||||
#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
|
||||
#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
|
||||
|
||||
#ifdef CONFIG_C_AMBEN_ALL
|
||||
#define V_AMBEN AMBEN_ALL
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMBEN
|
||||
#define V_AMBEN 0x0
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMBEN_B0
|
||||
#define V_AMBEN AMBEN_B0
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMBEN_B0_B1
|
||||
#define V_AMBEN AMBEN_B0_B1
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMBEN_B0_B1_B2
|
||||
#define V_AMBEN AMBEN_B0_B1_B2
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMCKEN
|
||||
#define V_AMCKEN AMCKEN
|
||||
#else
|
||||
#define V_AMCKEN 0x0
|
||||
#endif
|
||||
#ifdef CONFIG_C_CDPRIO
|
||||
#define V_CDPRIO 0x100
|
||||
#else
|
||||
#define V_CDPRIO 0x0
|
||||
#endif
|
||||
|
||||
#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
|
||||
|
||||
/**************************** Hysteresis Settings ****************************/
|
||||
|
||||
#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
|
||||
#ifdef CONFIG_GPIO_HYST_PORTF_0_7
|
||||
#define HYST_PORTF_0_7 (1 << 0)
|
||||
#else
|
||||
#define HYST_PORTF_0_7 (0 << 0)
|
||||
#endif
|
||||
#ifdef CONFIG_GPIO_HYST_PORTF_8_9
|
||||
#define HYST_PORTF_8_9 (1 << 2)
|
||||
#else
|
||||
#define HYST_PORTF_8_9 (0 << 2)
|
||||
#endif
|
||||
#ifdef CONFIG_GPIO_HYST_PORTF_10
|
||||
#define HYST_PORTF_10 (1 << 4)
|
||||
#else
|
||||
#define HYST_PORTF_10 (0 << 4)
|
||||
#endif
|
||||
#ifdef CONFIG_GPIO_HYST_PORTF_11
|
||||
#define HYST_PORTF_11 (1 << 6)
|
||||
#else
|
||||
#define HYST_PORTF_11 (0 << 6)
|
||||
#endif
|
||||
#ifdef CONFIG_GPIO_HYST_PORTF_12_13
|
||||
#define HYST_PORTF_12_13 (1 << 8)
|
||||
#else
|
||||
#define HYST_PORTF_12_13 (0 << 8)
|
||||
#endif
|
||||
#ifdef CONFIG_GPIO_HYST_PORTF_14_15
|
||||
#define HYST_PORTF_14_15 (1 << 10)
|
||||
#else
|
||||
#define HYST_PORTF_14_15 (0 << 10)
|
||||
#endif
|
||||
|
||||
#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
|
||||
HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
|
||||
|
||||
#ifdef CONFIG_GPIO_HYST_PORTG_0
|
||||
#define HYST_PORTG_0 (1 << 0)
|
||||
#else
|
||||
#define HYST_PORTG_0 (0 << 0)
|
||||
#endif
|
||||
#ifdef CONFIG_GPIO_HYST_PORTG_1_4
|
||||
#define HYST_PORTG_1_4 (1 << 2)
|
||||
#else
|
||||
#define HYST_PORTG_1_4 (0 << 2)
|
||||
#endif
|
||||
#ifdef CONFIG_GPIO_HYST_PORTG_5_6
|
||||
#define HYST_PORTG_5_6 (1 << 4)
|
||||
#else
|
||||
#define HYST_PORTG_5_6 (0 << 4)
|
||||
#endif
|
||||
#ifdef CONFIG_GPIO_HYST_PORTG_7_8
|
||||
#define HYST_PORTG_7_8 (1 << 6)
|
||||
#else
|
||||
#define HYST_PORTG_7_8 (0 << 6)
|
||||
#endif
|
||||
#ifdef CONFIG_GPIO_HYST_PORTG_9
|
||||
#define HYST_PORTG_9 (1 << 8)
|
||||
#else
|
||||
#define HYST_PORTG_9 (0 << 8)
|
||||
#endif
|
||||
#ifdef CONFIG_GPIO_HYST_PORTG_10
|
||||
#define HYST_PORTG_10 (1 << 10)
|
||||
#else
|
||||
#define HYST_PORTG_10 (0 << 10)
|
||||
#endif
|
||||
#ifdef CONFIG_GPIO_HYST_PORTG_11_13
|
||||
#define HYST_PORTG_11_13 (1 << 12)
|
||||
#else
|
||||
#define HYST_PORTG_11_13 (0 << 12)
|
||||
#endif
|
||||
#ifdef CONFIG_GPIO_HYST_PORTG_14_15
|
||||
#define HYST_PORTG_14_15 (1 << 14)
|
||||
#else
|
||||
#define HYST_PORTG_14_15 (0 << 14)
|
||||
#endif
|
||||
|
||||
#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
|
||||
HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
|
||||
HYST_PORTG_11_13 | HYST_PORTG_14_15)
|
||||
|
||||
#ifdef CONFIG_GPIO_HYST_PORTH_0_7
|
||||
#define HYST_PORTH_0_7 (1 << 0)
|
||||
#else
|
||||
#define HYST_PORTH_0_7 (0 << 0)
|
||||
#endif
|
||||
#ifdef CONFIG_GPIO_HYST_PORTH_8
|
||||
#define HYST_PORTH_8 (1 << 2)
|
||||
#else
|
||||
#define HYST_PORTH_8 (0 << 2)
|
||||
#endif
|
||||
#ifdef CONFIG_GPIO_HYST_PORTH_9_15
|
||||
#define HYST_PORTH_9_15 (1 << 4)
|
||||
#else
|
||||
#define HYST_PORTH_9_15 (0 << 4)
|
||||
#endif
|
||||
|
||||
#define HYST_PORTH_0_15 (HYST_PORTH_0_7 | HYST_PORTH_8 | HYST_PORTH_9_15)
|
||||
|
||||
#ifdef CONFIG_NONEGPIO_HYST_TMR0_FS1_PPICLK
|
||||
#define HYST_TMR0_FS1_PPICLK (1 << 0)
|
||||
#else
|
||||
#define HYST_TMR0_FS1_PPICLK (0 << 0)
|
||||
#endif
|
||||
#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
|
||||
#define HYST_NMI_RST_BMODE (1 << 2)
|
||||
#else
|
||||
#define HYST_NMI_RST_BMODE (0 << 2)
|
||||
#endif
|
||||
#ifdef CONFIG_NONEGPIO_HYST_JTAG
|
||||
#define HYST_JTAG (1 << 4)
|
||||
#else
|
||||
#define HYST_JTAG (0 << 4)
|
||||
#endif
|
||||
|
||||
#define HYST_NONEGPIO (HYST_TMR0_FS1_PPICLK | HYST_NMI_RST_BMODE | HYST_JTAG)
|
||||
#define HYST_NONEGPIO_MASK (0x3F)
|
||||
#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
|
||||
|
||||
#ifdef CONFIG_BF527
|
||||
#define CPU "BF527"
|
||||
#define CPUID 0x27e0
|
||||
#endif
|
||||
#ifdef CONFIG_BF526
|
||||
#define CPU "BF526"
|
||||
#define CPUID 0x27e4
|
||||
#endif
|
||||
#ifdef CONFIG_BF525
|
||||
#define CPU "BF525"
|
||||
#define CPUID 0x27e0
|
||||
#endif
|
||||
#ifdef CONFIG_BF524
|
||||
#define CPU "BF524"
|
||||
#define CPUID 0x27e4
|
||||
#endif
|
||||
#ifdef CONFIG_BF523
|
||||
#define CPU "BF523"
|
||||
#define CPUID 0x27e0
|
||||
#endif
|
||||
#ifdef CONFIG_BF522
|
||||
#define CPU "BF522"
|
||||
#define CPUID 0x27e4
|
||||
#endif
|
||||
|
||||
#ifndef CPU
|
||||
#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
|
||||
#endif
|
||||
|
||||
#endif /* __MACH_BF527_H__ */
|
||||
14
arch/blackfin/mach-bf527/include/mach/bfin_serial.h
Normal file
14
arch/blackfin/mach-bf527/include/mach/bfin_serial.h
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* mach/bfin_serial.h - Blackfin UART/Serial definitions
|
||||
*
|
||||
* Copyright 2006-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_MACH_SERIAL_H__
|
||||
#define __BFIN_MACH_SERIAL_H__
|
||||
|
||||
#define BFIN_UART_NR_PORTS 2
|
||||
|
||||
#endif
|
||||
37
arch/blackfin/mach-bf527/include/mach/blackfin.h
Normal file
37
arch/blackfin/mach-bf527/include/mach/blackfin.h
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* Copyright 2007-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_BLACKFIN_H_
|
||||
#define _MACH_BLACKFIN_H_
|
||||
|
||||
#include "bf527.h"
|
||||
#include "anomaly.h"
|
||||
|
||||
#include <asm/def_LPBlackfin.h>
|
||||
#if defined(CONFIG_BF523) || defined(CONFIG_BF522)
|
||||
# include "defBF522.h"
|
||||
#endif
|
||||
#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
|
||||
# include "defBF525.h"
|
||||
#endif
|
||||
#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
|
||||
# include "defBF527.h"
|
||||
#endif
|
||||
|
||||
#if !defined(__ASSEMBLY__)
|
||||
# include <asm/cdef_LPBlackfin.h>
|
||||
# if defined(CONFIG_BF523) || defined(CONFIG_BF522)
|
||||
# include "cdefBF522.h"
|
||||
# endif
|
||||
# if defined(CONFIG_BF525) || defined(CONFIG_BF524)
|
||||
# include "cdefBF525.h"
|
||||
# endif
|
||||
# if defined(CONFIG_BF527) || defined(CONFIG_BF526)
|
||||
# include "cdefBF527.h"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
1095
arch/blackfin/mach-bf527/include/mach/cdefBF522.h
Normal file
1095
arch/blackfin/mach-bf527/include/mach/cdefBF522.h
Normal file
File diff suppressed because it is too large
Load diff
426
arch/blackfin/mach-bf527/include/mach/cdefBF525.h
Normal file
426
arch/blackfin/mach-bf527/include/mach/cdefBF525.h
Normal file
|
|
@ -0,0 +1,426 @@
|
|||
/*
|
||||
* Copyright 2007-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _CDEF_BF525_H
|
||||
#define _CDEF_BF525_H
|
||||
|
||||
/* BF525 is BF522 + USB */
|
||||
#include "cdefBF522.h"
|
||||
|
||||
/* USB Control Registers */
|
||||
|
||||
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
|
||||
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
|
||||
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
|
||||
#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
|
||||
#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
|
||||
#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
|
||||
#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
|
||||
#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
|
||||
#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
|
||||
#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
|
||||
#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
|
||||
#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
|
||||
#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
|
||||
#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
|
||||
#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
|
||||
#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
|
||||
#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
|
||||
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
|
||||
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
|
||||
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
|
||||
#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
|
||||
#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
|
||||
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
|
||||
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
|
||||
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
|
||||
#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
|
||||
|
||||
/* USB Packet Control Registers */
|
||||
|
||||
#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
|
||||
#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
|
||||
#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
|
||||
#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
|
||||
#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
|
||||
#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
|
||||
#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
|
||||
#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
|
||||
#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
|
||||
#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
|
||||
#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
|
||||
#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
|
||||
#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
|
||||
#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
|
||||
#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
|
||||
#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
|
||||
#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
|
||||
#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
|
||||
#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
|
||||
#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
|
||||
#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
|
||||
#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
|
||||
#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
|
||||
#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
|
||||
#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
|
||||
#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint FIFO Registers */
|
||||
|
||||
#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
|
||||
#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
|
||||
#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
|
||||
#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
|
||||
#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
|
||||
#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
|
||||
#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
|
||||
#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
|
||||
#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
|
||||
#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
|
||||
#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
|
||||
#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
|
||||
#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
|
||||
#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
|
||||
#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
|
||||
#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
|
||||
|
||||
/* USB OTG Control Registers */
|
||||
|
||||
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
|
||||
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
|
||||
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
|
||||
#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
|
||||
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
|
||||
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
|
||||
|
||||
/* USB Phy Control Registers */
|
||||
|
||||
#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
|
||||
#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
|
||||
#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
|
||||
#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
|
||||
#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
|
||||
#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
|
||||
#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
|
||||
#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
|
||||
#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
|
||||
#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
|
||||
|
||||
/* (APHY_CNTRL is for ADI usage only) */
|
||||
|
||||
#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
|
||||
#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
|
||||
|
||||
/* (APHY_CALIB is for ADI usage only) */
|
||||
|
||||
#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
|
||||
#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
|
||||
|
||||
#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
|
||||
#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
|
||||
|
||||
/* (PHY_TEST is for ADI usage only) */
|
||||
|
||||
#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
|
||||
#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
|
||||
|
||||
#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
|
||||
#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
|
||||
#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
|
||||
#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
|
||||
|
||||
/* USB Endpoint 0 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
|
||||
#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
|
||||
#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 1 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
|
||||
#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
|
||||
#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 2 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
|
||||
#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
|
||||
#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 3 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
|
||||
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
|
||||
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 4 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
|
||||
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
|
||||
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 5 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
|
||||
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
|
||||
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 6 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
|
||||
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
|
||||
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
|
||||
|
||||
/* USB Endpoint 7 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
|
||||
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
|
||||
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
|
||||
|
||||
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
|
||||
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
|
||||
|
||||
/* USB Channel 0 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
|
||||
#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
|
||||
#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
|
||||
#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
|
||||
#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
|
||||
#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
|
||||
#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 1 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
|
||||
#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
|
||||
#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
|
||||
#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
|
||||
#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
|
||||
#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
|
||||
#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 2 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
|
||||
#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
|
||||
#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
|
||||
#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
|
||||
#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
|
||||
#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
|
||||
#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 3 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
|
||||
#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
|
||||
#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
|
||||
#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
|
||||
#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
|
||||
#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
|
||||
#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 4 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
|
||||
#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
|
||||
#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
|
||||
#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
|
||||
#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
|
||||
#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
|
||||
#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 5 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
|
||||
#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
|
||||
#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
|
||||
#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
|
||||
#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
|
||||
#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
|
||||
#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 6 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
|
||||
#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
|
||||
#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
|
||||
#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
|
||||
#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
|
||||
#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
|
||||
#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 7 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
|
||||
#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
|
||||
#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
|
||||
#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
|
||||
#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
|
||||
#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
|
||||
#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
|
||||
|
||||
#endif /* _CDEF_BF525_H */
|
||||
178
arch/blackfin/mach-bf527/include/mach/cdefBF527.h
Normal file
178
arch/blackfin/mach-bf527/include/mach/cdefBF527.h
Normal file
|
|
@ -0,0 +1,178 @@
|
|||
/*
|
||||
* Copyright 2007-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _CDEF_BF527_H
|
||||
#define _CDEF_BF527_H
|
||||
|
||||
/* BF527 is BF525 + EMAC */
|
||||
#include "cdefBF525.h"
|
||||
|
||||
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
|
||||
|
||||
#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
|
||||
#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
|
||||
#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
|
||||
#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
|
||||
#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
|
||||
#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
|
||||
#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
|
||||
#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
|
||||
#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
|
||||
#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
|
||||
#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
|
||||
#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
|
||||
#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
|
||||
#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
|
||||
#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
|
||||
#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
|
||||
#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
|
||||
#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
|
||||
#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
|
||||
#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
|
||||
#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
|
||||
#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
|
||||
#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
|
||||
#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
|
||||
#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
|
||||
#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
|
||||
#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
|
||||
#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
|
||||
#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
|
||||
#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
|
||||
#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
|
||||
#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
|
||||
#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
|
||||
#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
|
||||
#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
|
||||
#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
|
||||
#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
|
||||
#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
|
||||
|
||||
#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
|
||||
#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
|
||||
#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
|
||||
#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
|
||||
#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
|
||||
#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
|
||||
#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
|
||||
#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
|
||||
#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
|
||||
#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
|
||||
#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
|
||||
#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
|
||||
#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
|
||||
#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
|
||||
#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
|
||||
#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
|
||||
|
||||
#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
|
||||
#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
|
||||
#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
|
||||
#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
|
||||
#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
|
||||
#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
|
||||
#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
|
||||
#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
|
||||
#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
|
||||
#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
|
||||
|
||||
#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
|
||||
#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
|
||||
#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
|
||||
#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
|
||||
#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
|
||||
#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
|
||||
#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
|
||||
#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
|
||||
#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
|
||||
#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
|
||||
#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
|
||||
#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
|
||||
#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
|
||||
#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
|
||||
#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
|
||||
#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
|
||||
#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
|
||||
#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
|
||||
#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
|
||||
#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
|
||||
#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
|
||||
#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
|
||||
#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
|
||||
#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
|
||||
#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
|
||||
#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
|
||||
#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
|
||||
#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
|
||||
#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
|
||||
#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
|
||||
#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
|
||||
#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
|
||||
#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
|
||||
#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
|
||||
#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
|
||||
#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
|
||||
#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
|
||||
#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
|
||||
#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
|
||||
#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
|
||||
#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
|
||||
#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
|
||||
#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
|
||||
#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
|
||||
#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
|
||||
#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
|
||||
#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
|
||||
#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
|
||||
|
||||
#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
|
||||
#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
|
||||
#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
|
||||
#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
|
||||
#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
|
||||
#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
|
||||
#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
|
||||
#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
|
||||
#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
|
||||
#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
|
||||
#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
|
||||
#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
|
||||
#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
|
||||
#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
|
||||
#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
|
||||
#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
|
||||
#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
|
||||
#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
|
||||
#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
|
||||
#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
|
||||
#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
|
||||
#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
|
||||
#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
|
||||
#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
|
||||
#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
|
||||
#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
|
||||
#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
|
||||
#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
|
||||
#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
|
||||
#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
|
||||
#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
|
||||
#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
|
||||
#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
|
||||
#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
|
||||
#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
|
||||
#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
|
||||
#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
|
||||
#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
|
||||
#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
|
||||
#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
|
||||
#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
|
||||
#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
|
||||
#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
|
||||
#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
|
||||
#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
|
||||
#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
|
||||
|
||||
#endif /* _CDEF_BF527_H */
|
||||
1309
arch/blackfin/mach-bf527/include/mach/defBF522.h
Normal file
1309
arch/blackfin/mach-bf527/include/mach/defBF522.h
Normal file
File diff suppressed because it is too large
Load diff
682
arch/blackfin/mach-bf527/include/mach/defBF525.h
Normal file
682
arch/blackfin/mach-bf527/include/mach/defBF525.h
Normal file
|
|
@ -0,0 +1,682 @@
|
|||
/*
|
||||
* Copyright 2007-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the Clear BSD license or the GPL-2 (or later)
|
||||
*/
|
||||
|
||||
#ifndef _DEF_BF525_H
|
||||
#define _DEF_BF525_H
|
||||
|
||||
/* BF525 is BF522 + USB */
|
||||
#include "defBF522.h"
|
||||
|
||||
/* USB Control Registers */
|
||||
|
||||
#define USB_FADDR 0xffc03800 /* Function address register */
|
||||
#define USB_POWER 0xffc03804 /* Power management register */
|
||||
#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
|
||||
#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
|
||||
#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
|
||||
#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
|
||||
#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
|
||||
#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
|
||||
#define USB_FRAME 0xffc03820 /* USB frame number */
|
||||
#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
|
||||
#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
|
||||
#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
|
||||
#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
|
||||
|
||||
/* USB Packet Control Registers */
|
||||
|
||||
#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
|
||||
#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
|
||||
#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
|
||||
#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
|
||||
#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
|
||||
#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
|
||||
#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
|
||||
#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
|
||||
#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
|
||||
#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
|
||||
#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
|
||||
#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
|
||||
#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
|
||||
|
||||
/* USB Endpoint FIFO Registers */
|
||||
|
||||
#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
|
||||
#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
|
||||
#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
|
||||
#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
|
||||
#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
|
||||
#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
|
||||
#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
|
||||
#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
|
||||
|
||||
/* USB OTG Control Registers */
|
||||
|
||||
#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
|
||||
#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
|
||||
#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
|
||||
|
||||
/* USB Phy Control Registers */
|
||||
|
||||
#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
|
||||
#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
|
||||
#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
|
||||
#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
|
||||
#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
|
||||
|
||||
/* (APHY_CNTRL is for ADI usage only) */
|
||||
|
||||
#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
|
||||
|
||||
/* (APHY_CALIB is for ADI usage only) */
|
||||
|
||||
#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
|
||||
|
||||
#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
|
||||
|
||||
/* (PHY_TEST is for ADI usage only) */
|
||||
|
||||
#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
|
||||
|
||||
#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
|
||||
#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
|
||||
|
||||
/* USB Endpoint 0 Control Registers */
|
||||
|
||||
#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
|
||||
#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
|
||||
#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
|
||||
#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
|
||||
#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
|
||||
#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
|
||||
#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
|
||||
#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
|
||||
#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
|
||||
#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
|
||||
|
||||
/* USB Endpoint 1 Control Registers */
|
||||
|
||||
#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
|
||||
#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
|
||||
#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
|
||||
#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
|
||||
#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
|
||||
#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
|
||||
#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
|
||||
#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
|
||||
#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
|
||||
#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
|
||||
|
||||
/* USB Endpoint 2 Control Registers */
|
||||
|
||||
#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
|
||||
#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
|
||||
#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
|
||||
#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
|
||||
#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
|
||||
#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
|
||||
#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
|
||||
#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
|
||||
#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
|
||||
#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
|
||||
|
||||
/* USB Endpoint 3 Control Registers */
|
||||
|
||||
#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
|
||||
#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
|
||||
#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
|
||||
#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
|
||||
#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
|
||||
#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
|
||||
#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
|
||||
#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
|
||||
#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
|
||||
#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
|
||||
|
||||
/* USB Endpoint 4 Control Registers */
|
||||
|
||||
#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
|
||||
#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
|
||||
#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
|
||||
#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
|
||||
#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
|
||||
#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
|
||||
#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
|
||||
#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
|
||||
#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
|
||||
#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
|
||||
|
||||
/* USB Endpoint 5 Control Registers */
|
||||
|
||||
#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
|
||||
#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
|
||||
#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
|
||||
#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
|
||||
#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
|
||||
#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
|
||||
#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
|
||||
#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
|
||||
#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
|
||||
#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
|
||||
|
||||
/* USB Endpoint 6 Control Registers */
|
||||
|
||||
#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
|
||||
#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
|
||||
#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
|
||||
#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
|
||||
#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
|
||||
#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
|
||||
#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
|
||||
#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
|
||||
#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
|
||||
#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
|
||||
|
||||
/* USB Endpoint 7 Control Registers */
|
||||
|
||||
#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
|
||||
#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
|
||||
#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
|
||||
#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
|
||||
#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
|
||||
#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
|
||||
#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
|
||||
#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
|
||||
#define USB_EP_NI7_RXINTERVAL 0xffc03be0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
|
||||
#define USB_EP_NI7_TXCOUNT 0xffc03be8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
|
||||
|
||||
#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
|
||||
|
||||
/* USB Channel 0 Config Registers */
|
||||
|
||||
#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
|
||||
#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
|
||||
#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
|
||||
#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
|
||||
#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
|
||||
|
||||
/* USB Channel 1 Config Registers */
|
||||
|
||||
#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
|
||||
#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
|
||||
#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
|
||||
#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
|
||||
#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
|
||||
|
||||
/* USB Channel 2 Config Registers */
|
||||
|
||||
#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
|
||||
#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
|
||||
#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
|
||||
#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
|
||||
#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
|
||||
|
||||
/* USB Channel 3 Config Registers */
|
||||
|
||||
#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
|
||||
#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
|
||||
#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
|
||||
#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
|
||||
#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
|
||||
|
||||
/* USB Channel 4 Config Registers */
|
||||
|
||||
#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
|
||||
#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
|
||||
#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
|
||||
#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
|
||||
#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
|
||||
|
||||
/* USB Channel 5 Config Registers */
|
||||
|
||||
#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
|
||||
#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
|
||||
#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
|
||||
#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
|
||||
#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
|
||||
|
||||
/* USB Channel 6 Config Registers */
|
||||
|
||||
#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
|
||||
#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
|
||||
#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
|
||||
#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
|
||||
#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
|
||||
|
||||
/* USB Channel 7 Config Registers */
|
||||
|
||||
#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
|
||||
#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
|
||||
#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
|
||||
#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
|
||||
#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
|
||||
|
||||
/* Bit masks for USB_FADDR */
|
||||
|
||||
#define FUNCTION_ADDRESS 0x7f /* Function address */
|
||||
|
||||
/* Bit masks for USB_POWER */
|
||||
|
||||
#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
|
||||
#define nENABLE_SUSPENDM 0x0
|
||||
#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
|
||||
#define nSUSPEND_MODE 0x0
|
||||
#define RESUME_MODE 0x4 /* DMA Mode */
|
||||
#define nRESUME_MODE 0x0
|
||||
#define RESET 0x8 /* Reset indicator */
|
||||
#define nRESET 0x0
|
||||
#define HS_MODE 0x10 /* High Speed mode indicator */
|
||||
#define nHS_MODE 0x0
|
||||
#define HS_ENABLE 0x20 /* high Speed Enable */
|
||||
#define nHS_ENABLE 0x0
|
||||
#define SOFT_CONN 0x40 /* Soft connect */
|
||||
#define nSOFT_CONN 0x0
|
||||
#define ISO_UPDATE 0x80 /* Isochronous update */
|
||||
#define nISO_UPDATE 0x0
|
||||
|
||||
/* Bit masks for USB_INTRTX */
|
||||
|
||||
#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
|
||||
#define nEP0_TX 0x0
|
||||
#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
|
||||
#define nEP1_TX 0x0
|
||||
#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
|
||||
#define nEP2_TX 0x0
|
||||
#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
|
||||
#define nEP3_TX 0x0
|
||||
#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
|
||||
#define nEP4_TX 0x0
|
||||
#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
|
||||
#define nEP5_TX 0x0
|
||||
#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
|
||||
#define nEP6_TX 0x0
|
||||
#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
|
||||
#define nEP7_TX 0x0
|
||||
|
||||
/* Bit masks for USB_INTRRX */
|
||||
|
||||
#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
|
||||
#define nEP1_RX 0x0
|
||||
#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
|
||||
#define nEP2_RX 0x0
|
||||
#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
|
||||
#define nEP3_RX 0x0
|
||||
#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
|
||||
#define nEP4_RX 0x0
|
||||
#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
|
||||
#define nEP5_RX 0x0
|
||||
#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
|
||||
#define nEP6_RX 0x0
|
||||
#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
|
||||
#define nEP7_RX 0x0
|
||||
|
||||
/* Bit masks for USB_INTRTXE */
|
||||
|
||||
#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
|
||||
#define nEP0_TX_E 0x0
|
||||
#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
|
||||
#define nEP1_TX_E 0x0
|
||||
#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
|
||||
#define nEP2_TX_E 0x0
|
||||
#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
|
||||
#define nEP3_TX_E 0x0
|
||||
#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
|
||||
#define nEP4_TX_E 0x0
|
||||
#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
|
||||
#define nEP5_TX_E 0x0
|
||||
#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
|
||||
#define nEP6_TX_E 0x0
|
||||
#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
|
||||
#define nEP7_TX_E 0x0
|
||||
|
||||
/* Bit masks for USB_INTRRXE */
|
||||
|
||||
#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
|
||||
#define nEP1_RX_E 0x0
|
||||
#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
|
||||
#define nEP2_RX_E 0x0
|
||||
#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
|
||||
#define nEP3_RX_E 0x0
|
||||
#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
|
||||
#define nEP4_RX_E 0x0
|
||||
#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
|
||||
#define nEP5_RX_E 0x0
|
||||
#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
|
||||
#define nEP6_RX_E 0x0
|
||||
#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
|
||||
#define nEP7_RX_E 0x0
|
||||
|
||||
/* Bit masks for USB_INTRUSB */
|
||||
|
||||
#define SUSPEND_B 0x1 /* Suspend indicator */
|
||||
#define nSUSPEND_B 0x0
|
||||
#define RESUME_B 0x2 /* Resume indicator */
|
||||
#define nRESUME_B 0x0
|
||||
#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
|
||||
#define nRESET_OR_BABLE_B 0x0
|
||||
#define SOF_B 0x8 /* Start of frame */
|
||||
#define nSOF_B 0x0
|
||||
#define CONN_B 0x10 /* Connection indicator */
|
||||
#define nCONN_B 0x0
|
||||
#define DISCON_B 0x20 /* Disconnect indicator */
|
||||
#define nDISCON_B 0x0
|
||||
#define SESSION_REQ_B 0x40 /* Session Request */
|
||||
#define nSESSION_REQ_B 0x0
|
||||
#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
|
||||
#define nVBUS_ERROR_B 0x0
|
||||
|
||||
/* Bit masks for USB_INTRUSBE */
|
||||
|
||||
#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
|
||||
#define nSUSPEND_BE 0x0
|
||||
#define RESUME_BE 0x2 /* Resume indicator int enable */
|
||||
#define nRESUME_BE 0x0
|
||||
#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
|
||||
#define nRESET_OR_BABLE_BE 0x0
|
||||
#define SOF_BE 0x8 /* Start of frame int enable */
|
||||
#define nSOF_BE 0x0
|
||||
#define CONN_BE 0x10 /* Connection indicator int enable */
|
||||
#define nCONN_BE 0x0
|
||||
#define DISCON_BE 0x20 /* Disconnect indicator int enable */
|
||||
#define nDISCON_BE 0x0
|
||||
#define SESSION_REQ_BE 0x40 /* Session Request int enable */
|
||||
#define nSESSION_REQ_BE 0x0
|
||||
#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
|
||||
#define nVBUS_ERROR_BE 0x0
|
||||
|
||||
/* Bit masks for USB_FRAME */
|
||||
|
||||
#define FRAME_NUMBER 0x7ff /* Frame number */
|
||||
|
||||
/* Bit masks for USB_INDEX */
|
||||
|
||||
#define SELECTED_ENDPOINT 0xf /* selected endpoint */
|
||||
|
||||
/* Bit masks for USB_GLOBAL_CTL */
|
||||
|
||||
#define GLOBAL_ENA 0x1 /* enables USB module */
|
||||
#define nGLOBAL_ENA 0x0
|
||||
#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
|
||||
#define nEP1_TX_ENA 0x0
|
||||
#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
|
||||
#define nEP2_TX_ENA 0x0
|
||||
#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
|
||||
#define nEP3_TX_ENA 0x0
|
||||
#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
|
||||
#define nEP4_TX_ENA 0x0
|
||||
#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
|
||||
#define nEP5_TX_ENA 0x0
|
||||
#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
|
||||
#define nEP6_TX_ENA 0x0
|
||||
#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
|
||||
#define nEP7_TX_ENA 0x0
|
||||
#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
|
||||
#define nEP1_RX_ENA 0x0
|
||||
#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
|
||||
#define nEP2_RX_ENA 0x0
|
||||
#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
|
||||
#define nEP3_RX_ENA 0x0
|
||||
#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
|
||||
#define nEP4_RX_ENA 0x0
|
||||
#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
|
||||
#define nEP5_RX_ENA 0x0
|
||||
#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
|
||||
#define nEP6_RX_ENA 0x0
|
||||
#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
|
||||
#define nEP7_RX_ENA 0x0
|
||||
|
||||
/* Bit masks for USB_OTG_DEV_CTL */
|
||||
|
||||
#define SESSION 0x1 /* session indicator */
|
||||
#define nSESSION 0x0
|
||||
#define HOST_REQ 0x2 /* Host negotiation request */
|
||||
#define nHOST_REQ 0x0
|
||||
#define HOST_MODE 0x4 /* indicates USBDRC is a host */
|
||||
#define nHOST_MODE 0x0
|
||||
#define VBUS0 0x8 /* Vbus level indicator[0] */
|
||||
#define nVBUS0 0x0
|
||||
#define VBUS1 0x10 /* Vbus level indicator[1] */
|
||||
#define nVBUS1 0x0
|
||||
#define LSDEV 0x20 /* Low-speed indicator */
|
||||
#define nLSDEV 0x0
|
||||
#define FSDEV 0x40 /* Full or High-speed indicator */
|
||||
#define nFSDEV 0x0
|
||||
#define B_DEVICE 0x80 /* A' or 'B' device indicator */
|
||||
#define nB_DEVICE 0x0
|
||||
|
||||
/* Bit masks for USB_OTG_VBUS_IRQ */
|
||||
|
||||
#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
|
||||
#define nDRIVE_VBUS_ON 0x0
|
||||
#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
|
||||
#define nDRIVE_VBUS_OFF 0x0
|
||||
#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
|
||||
#define nCHRG_VBUS_START 0x0
|
||||
#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
|
||||
#define nCHRG_VBUS_END 0x0
|
||||
#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
|
||||
#define nDISCHRG_VBUS_START 0x0
|
||||
#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
|
||||
#define nDISCHRG_VBUS_END 0x0
|
||||
|
||||
/* Bit masks for USB_OTG_VBUS_MASK */
|
||||
|
||||
#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
|
||||
#define nDRIVE_VBUS_ON_ENA 0x0
|
||||
#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
|
||||
#define nDRIVE_VBUS_OFF_ENA 0x0
|
||||
#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
|
||||
#define nCHRG_VBUS_START_ENA 0x0
|
||||
#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
|
||||
#define nCHRG_VBUS_END_ENA 0x0
|
||||
#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
|
||||
#define nDISCHRG_VBUS_START_ENA 0x0
|
||||
#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
|
||||
#define nDISCHRG_VBUS_END_ENA 0x0
|
||||
|
||||
/* Bit masks for USB_CSR0 */
|
||||
|
||||
#define RXPKTRDY 0x1 /* data packet receive indicator */
|
||||
#define nRXPKTRDY 0x0
|
||||
#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
|
||||
#define nTXPKTRDY 0x0
|
||||
#define STALL_SENT 0x4 /* STALL handshake sent */
|
||||
#define nSTALL_SENT 0x0
|
||||
#define DATAEND 0x8 /* Data end indicator */
|
||||
#define nDATAEND 0x0
|
||||
#define SETUPEND 0x10 /* Setup end */
|
||||
#define nSETUPEND 0x0
|
||||
#define SENDSTALL 0x20 /* Send STALL handshake */
|
||||
#define nSENDSTALL 0x0
|
||||
#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
|
||||
#define nSERVICED_RXPKTRDY 0x0
|
||||
#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
|
||||
#define nSERVICED_SETUPEND 0x0
|
||||
#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
|
||||
#define nFLUSHFIFO 0x0
|
||||
#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
|
||||
#define nSTALL_RECEIVED_H 0x0
|
||||
#define SETUPPKT_H 0x8 /* send Setup token host mode */
|
||||
#define nSETUPPKT_H 0x0
|
||||
#define ERROR_H 0x10 /* timeout error indicator host mode */
|
||||
#define nERROR_H 0x0
|
||||
#define REQPKT_H 0x20 /* Request an IN transaction host mode */
|
||||
#define nREQPKT_H 0x0
|
||||
#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
|
||||
#define nSTATUSPKT_H 0x0
|
||||
#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
|
||||
#define nNAK_TIMEOUT_H 0x0
|
||||
|
||||
/* Bit masks for USB_COUNT0 */
|
||||
|
||||
#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
|
||||
|
||||
/* Bit masks for USB_NAKLIMIT0 */
|
||||
|
||||
#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
|
||||
|
||||
/* Bit masks for USB_TX_MAX_PACKET */
|
||||
|
||||
#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
|
||||
|
||||
/* Bit masks for USB_RX_MAX_PACKET */
|
||||
|
||||
#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
|
||||
|
||||
/* Bit masks for USB_TXCSR */
|
||||
|
||||
#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
|
||||
#define nTXPKTRDY_T 0x0
|
||||
#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
|
||||
#define nFIFO_NOT_EMPTY_T 0x0
|
||||
#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
|
||||
#define nUNDERRUN_T 0x0
|
||||
#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
|
||||
#define nFLUSHFIFO_T 0x0
|
||||
#define STALL_SEND_T 0x10 /* issue a Stall handshake */
|
||||
#define nSTALL_SEND_T 0x0
|
||||
#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
|
||||
#define nSTALL_SENT_T 0x0
|
||||
#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
|
||||
#define nCLEAR_DATATOGGLE_T 0x0
|
||||
#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
|
||||
#define nINCOMPTX_T 0x0
|
||||
#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
|
||||
#define nDMAREQMODE_T 0x0
|
||||
#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
|
||||
#define nFORCE_DATATOGGLE_T 0x0
|
||||
#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
|
||||
#define nDMAREQ_ENA_T 0x0
|
||||
#define ISO_T 0x4000 /* enable Isochronous transfers */
|
||||
#define nISO_T 0x0
|
||||
#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
|
||||
#define nAUTOSET_T 0x0
|
||||
#define ERROR_TH 0x4 /* error condition host mode */
|
||||
#define nERROR_TH 0x0
|
||||
#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
|
||||
#define nSTALL_RECEIVED_TH 0x0
|
||||
#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
|
||||
#define nNAK_TIMEOUT_TH 0x0
|
||||
|
||||
/* Bit masks for USB_TXCOUNT */
|
||||
|
||||
#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
|
||||
|
||||
/* Bit masks for USB_RXCSR */
|
||||
|
||||
#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
|
||||
#define nRXPKTRDY_R 0x0
|
||||
#define FIFO_FULL_R 0x2 /* FIFO not empty */
|
||||
#define nFIFO_FULL_R 0x0
|
||||
#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
|
||||
#define nOVERRUN_R 0x0
|
||||
#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
|
||||
#define nDATAERROR_R 0x0
|
||||
#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
|
||||
#define nFLUSHFIFO_R 0x0
|
||||
#define STALL_SEND_R 0x20 /* issue a Stall handshake */
|
||||
#define nSTALL_SEND_R 0x0
|
||||
#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
|
||||
#define nSTALL_SENT_R 0x0
|
||||
#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
|
||||
#define nCLEAR_DATATOGGLE_R 0x0
|
||||
#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
|
||||
#define nINCOMPRX_R 0x0
|
||||
#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
|
||||
#define nDMAREQMODE_R 0x0
|
||||
#define DISNYET_R 0x1000 /* disable Nyet handshakes */
|
||||
#define nDISNYET_R 0x0
|
||||
#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
|
||||
#define nDMAREQ_ENA_R 0x0
|
||||
#define ISO_R 0x4000 /* enable Isochronous transfers */
|
||||
#define nISO_R 0x0
|
||||
#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
|
||||
#define nAUTOCLEAR_R 0x0
|
||||
#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
|
||||
#define nERROR_RH 0x0
|
||||
#define REQPKT_RH 0x20 /* request an IN transaction host mode */
|
||||
#define nREQPKT_RH 0x0
|
||||
#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
|
||||
#define nSTALL_RECEIVED_RH 0x0
|
||||
#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
|
||||
#define nINCOMPRX_RH 0x0
|
||||
#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
|
||||
#define nDMAREQMODE_RH 0x0
|
||||
#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
|
||||
#define nAUTOREQ_RH 0x0
|
||||
|
||||
/* Bit masks for USB_RXCOUNT */
|
||||
|
||||
#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
|
||||
|
||||
/* Bit masks for USB_TXTYPE */
|
||||
|
||||
#define TARGET_EP_NO_T 0xf /* EP number */
|
||||
#define PROTOCOL_T 0xc /* transfer type */
|
||||
|
||||
/* Bit masks for USB_TXINTERVAL */
|
||||
|
||||
#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
|
||||
|
||||
/* Bit masks for USB_RXTYPE */
|
||||
|
||||
#define TARGET_EP_NO_R 0xf /* EP number */
|
||||
#define PROTOCOL_R 0xc /* transfer type */
|
||||
|
||||
/* Bit masks for USB_RXINTERVAL */
|
||||
|
||||
#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
|
||||
|
||||
/* Bit masks for USB_DMA_INTERRUPT */
|
||||
|
||||
#define DMA0_INT 0x1 /* DMA0 pending interrupt */
|
||||
#define nDMA0_INT 0x0
|
||||
#define DMA1_INT 0x2 /* DMA1 pending interrupt */
|
||||
#define nDMA1_INT 0x0
|
||||
#define DMA2_INT 0x4 /* DMA2 pending interrupt */
|
||||
#define nDMA2_INT 0x0
|
||||
#define DMA3_INT 0x8 /* DMA3 pending interrupt */
|
||||
#define nDMA3_INT 0x0
|
||||
#define DMA4_INT 0x10 /* DMA4 pending interrupt */
|
||||
#define nDMA4_INT 0x0
|
||||
#define DMA5_INT 0x20 /* DMA5 pending interrupt */
|
||||
#define nDMA5_INT 0x0
|
||||
#define DMA6_INT 0x40 /* DMA6 pending interrupt */
|
||||
#define nDMA6_INT 0x0
|
||||
#define DMA7_INT 0x80 /* DMA7 pending interrupt */
|
||||
#define nDMA7_INT 0x0
|
||||
|
||||
/* Bit masks for USB_DMAxCONTROL */
|
||||
|
||||
#define DMA_ENA 0x1 /* DMA enable */
|
||||
#define nDMA_ENA 0x0
|
||||
#define DIRECTION 0x2 /* direction of DMA transfer */
|
||||
#define nDIRECTION 0x0
|
||||
#define MODE 0x4 /* DMA Bus error */
|
||||
#define nMODE 0x0
|
||||
#define INT_ENA 0x8 /* Interrupt enable */
|
||||
#define nINT_ENA 0x0
|
||||
#define EPNUM 0xf0 /* EP number */
|
||||
#define BUSERROR 0x100 /* DMA Bus error */
|
||||
#define nBUSERROR 0x0
|
||||
|
||||
/* Bit masks for USB_DMAxADDRHIGH */
|
||||
|
||||
#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
|
||||
|
||||
/* Bit masks for USB_DMAxADDRLOW */
|
||||
|
||||
#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
|
||||
|
||||
/* Bit masks for USB_DMAxCOUNTHIGH */
|
||||
|
||||
#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
|
||||
|
||||
/* Bit masks for USB_DMAxCOUNTLOW */
|
||||
|
||||
#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
|
||||
|
||||
#endif /* _DEF_BF525_H */
|
||||
391
arch/blackfin/mach-bf527/include/mach/defBF527.h
Normal file
391
arch/blackfin/mach-bf527/include/mach/defBF527.h
Normal file
|
|
@ -0,0 +1,391 @@
|
|||
/*
|
||||
* Copyright 2007-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the Clear BSD license or the GPL-2 (or later)
|
||||
*/
|
||||
|
||||
#ifndef _DEF_BF527_H
|
||||
#define _DEF_BF527_H
|
||||
|
||||
/* BF527 is BF525 + EMAC */
|
||||
#include "defBF525.h"
|
||||
|
||||
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
|
||||
|
||||
#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
|
||||
#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
|
||||
#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
|
||||
#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
|
||||
#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
|
||||
#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
|
||||
#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
|
||||
#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
|
||||
#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
|
||||
#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
|
||||
#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
|
||||
#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
|
||||
#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
|
||||
#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
|
||||
#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
|
||||
#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
|
||||
|
||||
#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
|
||||
#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
|
||||
#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
|
||||
#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
|
||||
#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
|
||||
#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
|
||||
#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
|
||||
#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
|
||||
|
||||
#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
|
||||
#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
|
||||
#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
|
||||
#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
|
||||
#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
|
||||
|
||||
#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
|
||||
#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
|
||||
#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
|
||||
#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
|
||||
#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
|
||||
#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
|
||||
#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
|
||||
#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
|
||||
#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
|
||||
#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
|
||||
#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
|
||||
#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
|
||||
#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
|
||||
#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
|
||||
#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
|
||||
#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
|
||||
#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
|
||||
#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
|
||||
#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
|
||||
#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
|
||||
#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
|
||||
|
||||
#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
|
||||
#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
|
||||
#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
|
||||
#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
|
||||
#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
|
||||
#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
|
||||
#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
|
||||
#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
|
||||
#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
|
||||
#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
|
||||
#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
|
||||
#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
|
||||
#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
|
||||
#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
|
||||
#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
|
||||
#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
|
||||
#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
|
||||
#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
|
||||
#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
|
||||
#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
|
||||
|
||||
/* Listing for IEEE-Supported Count Registers */
|
||||
|
||||
#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
|
||||
#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
|
||||
#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
|
||||
#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
|
||||
#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
|
||||
#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
|
||||
#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
|
||||
#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
|
||||
#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
|
||||
#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
|
||||
#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
|
||||
#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
|
||||
#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
|
||||
#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
|
||||
#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
|
||||
#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
|
||||
#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
|
||||
#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
|
||||
#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
|
||||
#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
|
||||
#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
|
||||
|
||||
#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
|
||||
#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
|
||||
#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
|
||||
#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
|
||||
#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
|
||||
#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
|
||||
#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
|
||||
#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
|
||||
#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
|
||||
#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
|
||||
#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
|
||||
#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
|
||||
#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
|
||||
#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
|
||||
#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
|
||||
#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
|
||||
#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
|
||||
#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
|
||||
#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
|
||||
#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
|
||||
#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
|
||||
#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
|
||||
#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
|
||||
|
||||
/***********************************************************************************
|
||||
** System MMR Register Bits And Macros
|
||||
**
|
||||
** Disclaimer: All macros are intended to make C and Assembly code more readable.
|
||||
** Use these macros carefully, as any that do left shifts for field
|
||||
** depositing will result in the lower order bits being destroyed. Any
|
||||
** macro that shifts left to properly position the bit-field should be
|
||||
** used as part of an OR to initialize a register and NOT as a dynamic
|
||||
** modifier UNLESS the lower order bits are saved and ORed back in when
|
||||
** the macro is used.
|
||||
*************************************************************************************/
|
||||
|
||||
/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
|
||||
|
||||
/* EMAC_OPMODE Masks */
|
||||
|
||||
#define RE 0x00000001 /* Receiver Enable */
|
||||
#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
|
||||
#define HU 0x00000010 /* Hash Filter Unicast Address */
|
||||
#define HM 0x00000020 /* Hash Filter Multicast Address */
|
||||
#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
|
||||
#define PR 0x00000080 /* Promiscuous Mode Enable */
|
||||
#define IFE 0x00000100 /* Inverse Filtering Enable */
|
||||
#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
|
||||
#define PBF 0x00000400 /* Pass Bad Frames Enable */
|
||||
#define PSF 0x00000800 /* Pass Short Frames Enable */
|
||||
#define RAF 0x00001000 /* Receive-All Mode */
|
||||
#define TE 0x00010000 /* Transmitter Enable */
|
||||
#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
|
||||
#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
|
||||
#define DC 0x00080000 /* Deferral Check */
|
||||
#define BOLMT 0x00300000 /* Back-Off Limit */
|
||||
#define BOLMT_10 0x00000000 /* 10-bit range */
|
||||
#define BOLMT_8 0x00100000 /* 8-bit range */
|
||||
#define BOLMT_4 0x00200000 /* 4-bit range */
|
||||
#define BOLMT_1 0x00300000 /* 1-bit range */
|
||||
#define DRTY 0x00400000 /* Disable TX Retry On Collision */
|
||||
#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
|
||||
#define RMII 0x01000000 /* RMII/MII* Mode */
|
||||
#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
|
||||
#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
|
||||
#define LB 0x08000000 /* Internal Loopback Enable */
|
||||
#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
|
||||
|
||||
/* EMAC_STAADD Masks */
|
||||
|
||||
#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
|
||||
#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
|
||||
#define STADISPRE 0x00000004 /* Disable Preamble Generation */
|
||||
#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
|
||||
#define REGAD 0x000007C0 /* STA Register Address */
|
||||
#define PHYAD 0x0000F800 /* PHY Device Address */
|
||||
|
||||
#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
|
||||
#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
|
||||
|
||||
/* EMAC_STADAT Mask */
|
||||
|
||||
#define STADATA 0x0000FFFF /* Station Management Data */
|
||||
|
||||
/* EMAC_FLC Masks */
|
||||
|
||||
#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
|
||||
#define FLCE 0x00000002 /* Flow Control Enable */
|
||||
#define PCF 0x00000004 /* Pass Control Frames */
|
||||
#define BKPRSEN 0x00000008 /* Enable Backpressure */
|
||||
#define FLCPAUSE 0xFFFF0000 /* Pause Time */
|
||||
|
||||
#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
|
||||
|
||||
/* EMAC_WKUP_CTL Masks */
|
||||
|
||||
#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
|
||||
#define MPKE 0x00000002 /* Magic Packet Enable */
|
||||
#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
|
||||
#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
|
||||
#define MPKS 0x00000020 /* Magic Packet Received Status */
|
||||
#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
|
||||
|
||||
/* EMAC_WKUP_FFCMD Masks */
|
||||
|
||||
#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
|
||||
#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
|
||||
#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
|
||||
#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
|
||||
#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
|
||||
#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
|
||||
#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
|
||||
#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
|
||||
|
||||
/* EMAC_WKUP_FFOFF Masks */
|
||||
|
||||
#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
|
||||
#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
|
||||
#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
|
||||
#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
|
||||
|
||||
#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
|
||||
#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
|
||||
#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
|
||||
#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
|
||||
/* Set ALL Offsets */
|
||||
#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
|
||||
|
||||
/* EMAC_WKUP_FFCRC0 Masks */
|
||||
|
||||
#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
|
||||
#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
|
||||
|
||||
#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
|
||||
#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
|
||||
|
||||
/* EMAC_WKUP_FFCRC1 Masks */
|
||||
|
||||
#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
|
||||
#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
|
||||
|
||||
#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
|
||||
#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
|
||||
|
||||
/* EMAC_SYSCTL Masks */
|
||||
|
||||
#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
|
||||
#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
|
||||
#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
|
||||
#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
|
||||
#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
|
||||
|
||||
#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
|
||||
|
||||
/* EMAC_SYSTAT Masks */
|
||||
|
||||
#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
|
||||
#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
|
||||
#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
|
||||
#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
|
||||
#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
|
||||
#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
|
||||
#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
|
||||
#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
|
||||
|
||||
/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
|
||||
|
||||
#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
|
||||
#define RX_COMP 0x00001000 /* RX Frame Complete */
|
||||
#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
|
||||
#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
|
||||
#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
|
||||
#define RX_CRC 0x00010000 /* RX Frame CRC Error */
|
||||
#define RX_LEN 0x00020000 /* RX Frame Length Error */
|
||||
#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
|
||||
#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
|
||||
#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
|
||||
#define RX_PHY 0x00200000 /* RX Frame PHY Error */
|
||||
#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
|
||||
#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
|
||||
#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
|
||||
#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
|
||||
#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
|
||||
#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
|
||||
#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
|
||||
#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
|
||||
#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
|
||||
#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
|
||||
|
||||
/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
|
||||
|
||||
#define TX_COMP 0x00000001 /* TX Frame Complete */
|
||||
#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
|
||||
#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
|
||||
#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
|
||||
#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
|
||||
#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
|
||||
#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
|
||||
#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
|
||||
#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
|
||||
#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
|
||||
#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
|
||||
#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
|
||||
#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
|
||||
#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
|
||||
#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
|
||||
|
||||
/* EMAC_MMC_CTL Masks */
|
||||
#define RSTC 0x00000001 /* Reset All Counters */
|
||||
#define CROLL 0x00000002 /* Counter Roll-Over Enable */
|
||||
#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
|
||||
#define MMCE 0x00000008 /* Enable MMC Counter Operation */
|
||||
|
||||
/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
|
||||
#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
|
||||
#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
|
||||
#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
|
||||
#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
|
||||
#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
|
||||
#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
|
||||
#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
|
||||
#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
|
||||
#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
|
||||
#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
|
||||
#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
|
||||
#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
|
||||
#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
|
||||
#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
|
||||
#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
|
||||
#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
|
||||
#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
|
||||
#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
|
||||
#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
|
||||
#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
|
||||
#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
|
||||
#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
|
||||
#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
|
||||
#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
|
||||
|
||||
/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
|
||||
|
||||
#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
|
||||
#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
|
||||
#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
|
||||
#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
|
||||
#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
|
||||
#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
|
||||
#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
|
||||
#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
|
||||
#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
|
||||
#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
|
||||
#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
|
||||
#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
|
||||
#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
|
||||
#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
|
||||
#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
|
||||
#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
|
||||
#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
|
||||
#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
|
||||
#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
|
||||
#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
|
||||
#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
|
||||
#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
|
||||
#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
|
||||
|
||||
#endif /* _DEF_BF527_H */
|
||||
38
arch/blackfin/mach-bf527/include/mach/dma.h
Normal file
38
arch/blackfin/mach-bf527/include/mach/dma.h
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
/* mach/dma.h - arch-specific DMA defines
|
||||
*
|
||||
* Copyright 2004-2008 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_DMA_H_
|
||||
#define _MACH_DMA_H_
|
||||
|
||||
#define MAX_DMA_CHANNELS 16
|
||||
|
||||
#define CH_PPI 0 /* PPI receive/transmit or NFC */
|
||||
#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */
|
||||
#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */
|
||||
#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */
|
||||
#define CH_SPORT0_RX 3 /* SPORT0 receive */
|
||||
#define CH_SPORT0_TX 4 /* SPORT0 transmit */
|
||||
#define CH_SPORT1_RX 5 /* SPORT1 receive */
|
||||
#define CH_SPORT1_TX 6 /* SPORT1 transmit */
|
||||
#define CH_SPI 7 /* SPI transmit/receive */
|
||||
#define CH_UART0_RX 8 /* UART0 receive */
|
||||
#define CH_UART0_TX 9 /* UART0 transmit */
|
||||
#define CH_UART1_RX 10 /* UART1 receive */
|
||||
#define CH_UART1_TX 11 /* UART1 transmit */
|
||||
|
||||
#define CH_MEM_STREAM0_DEST 12 /* TX */
|
||||
#define CH_MEM_STREAM0_SRC 13 /* RX */
|
||||
#define CH_MEM_STREAM1_DEST 14 /* TX */
|
||||
#define CH_MEM_STREAM1_SRC 15 /* RX */
|
||||
|
||||
#if defined(CONFIG_BF527_NAND_D_PORTF)
|
||||
#define CH_NFC CH_PPI /* PPI receive/transmit or NFC */
|
||||
#elif defined(CONFIG_BF527_NAND_D_PORTH)
|
||||
#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */
|
||||
#endif
|
||||
|
||||
#endif
|
||||
69
arch/blackfin/mach-bf527/include/mach/gpio.h
Normal file
69
arch/blackfin/mach-bf527/include/mach/gpio.h
Normal file
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* Copyright (C) 2008 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACH_GPIO_H_
|
||||
#define _MACH_GPIO_H_
|
||||
|
||||
#define MAX_BLACKFIN_GPIOS 48
|
||||
|
||||
#define GPIO_PF0 0
|
||||
#define GPIO_PF1 1
|
||||
#define GPIO_PF2 2
|
||||
#define GPIO_PF3 3
|
||||
#define GPIO_PF4 4
|
||||
#define GPIO_PF5 5
|
||||
#define GPIO_PF6 6
|
||||
#define GPIO_PF7 7
|
||||
#define GPIO_PF8 8
|
||||
#define GPIO_PF9 9
|
||||
#define GPIO_PF10 10
|
||||
#define GPIO_PF11 11
|
||||
#define GPIO_PF12 12
|
||||
#define GPIO_PF13 13
|
||||
#define GPIO_PF14 14
|
||||
#define GPIO_PF15 15
|
||||
#define GPIO_PG0 16
|
||||
#define GPIO_PG1 17
|
||||
#define GPIO_PG2 18
|
||||
#define GPIO_PG3 19
|
||||
#define GPIO_PG4 20
|
||||
#define GPIO_PG5 21
|
||||
#define GPIO_PG6 22
|
||||
#define GPIO_PG7 23
|
||||
#define GPIO_PG8 24
|
||||
#define GPIO_PG9 25
|
||||
#define GPIO_PG10 26
|
||||
#define GPIO_PG11 27
|
||||
#define GPIO_PG12 28
|
||||
#define GPIO_PG13 29
|
||||
#define GPIO_PG14 30
|
||||
#define GPIO_PG15 31
|
||||
#define GPIO_PH0 32
|
||||
#define GPIO_PH1 33
|
||||
#define GPIO_PH2 34
|
||||
#define GPIO_PH3 35
|
||||
#define GPIO_PH4 36
|
||||
#define GPIO_PH5 37
|
||||
#define GPIO_PH6 38
|
||||
#define GPIO_PH7 39
|
||||
#define GPIO_PH8 40
|
||||
#define GPIO_PH9 41
|
||||
#define GPIO_PH10 42
|
||||
#define GPIO_PH11 43
|
||||
#define GPIO_PH12 44
|
||||
#define GPIO_PH13 45
|
||||
#define GPIO_PH14 46
|
||||
#define GPIO_PH15 47
|
||||
|
||||
#define PORT_F GPIO_PF0
|
||||
#define PORT_G GPIO_PG0
|
||||
#define PORT_H GPIO_PH0
|
||||
|
||||
#include <mach-common/ports-f.h>
|
||||
#include <mach-common/ports-g.h>
|
||||
#include <mach-common/ports-h.h>
|
||||
|
||||
#endif /* _MACH_GPIO_H_ */
|
||||
204
arch/blackfin/mach-bf527/include/mach/irq.h
Normal file
204
arch/blackfin/mach-bf527/include/mach/irq.h
Normal file
|
|
@ -0,0 +1,204 @@
|
|||
/*
|
||||
* Copyright 2007-2008 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later
|
||||
*/
|
||||
|
||||
#ifndef _BF527_IRQ_H_
|
||||
#define _BF527_IRQ_H_
|
||||
|
||||
#include <mach-common/irq.h>
|
||||
|
||||
#define NR_PERI_INTS (2 * 32)
|
||||
|
||||
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
|
||||
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
|
||||
#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
|
||||
#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
|
||||
#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
|
||||
#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
|
||||
#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
|
||||
#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
|
||||
#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
|
||||
#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
|
||||
#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
|
||||
#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
|
||||
#define IRQ_RTC BFIN_IRQ(14) /* RTC */
|
||||
#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
|
||||
#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
|
||||
#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
|
||||
#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */
|
||||
#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
|
||||
#define IRQ_TWI BFIN_IRQ(20) /* TWI */
|
||||
#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
|
||||
#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
|
||||
#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
|
||||
#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
|
||||
#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
|
||||
#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
|
||||
#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
|
||||
#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
|
||||
#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
|
||||
#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
|
||||
#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
|
||||
#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
|
||||
#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
|
||||
#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */
|
||||
#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */
|
||||
#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */
|
||||
#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */
|
||||
#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */
|
||||
#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */
|
||||
#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */
|
||||
#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
|
||||
#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
|
||||
#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
|
||||
#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
|
||||
#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
|
||||
#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
|
||||
#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
|
||||
#define IRQ_SPI_ERROR BFIN_IRQ(47) /* SPI Status */
|
||||
#define IRQ_NFC_ERROR BFIN_IRQ(48) /* NAND Error */
|
||||
#define IRQ_HDMA_ERROR BFIN_IRQ(49) /* HDMA Error */
|
||||
#define IRQ_HDMA BFIN_IRQ(50) /* HDMA (TFI) */
|
||||
#define IRQ_USB_EINT BFIN_IRQ(51) /* USB_EINT Interrupt */
|
||||
#define IRQ_USB_INT0 BFIN_IRQ(52) /* USB_INT0 Interrupt */
|
||||
#define IRQ_USB_INT1 BFIN_IRQ(53) /* USB_INT1 Interrupt */
|
||||
#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */
|
||||
#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */
|
||||
|
||||
#define SYS_IRQS BFIN_IRQ(63) /* 70 */
|
||||
|
||||
#define IRQ_PF0 71
|
||||
#define IRQ_PF1 72
|
||||
#define IRQ_PF2 73
|
||||
#define IRQ_PF3 74
|
||||
#define IRQ_PF4 75
|
||||
#define IRQ_PF5 76
|
||||
#define IRQ_PF6 77
|
||||
#define IRQ_PF7 78
|
||||
#define IRQ_PF8 79
|
||||
#define IRQ_PF9 80
|
||||
#define IRQ_PF10 81
|
||||
#define IRQ_PF11 82
|
||||
#define IRQ_PF12 83
|
||||
#define IRQ_PF13 84
|
||||
#define IRQ_PF14 85
|
||||
#define IRQ_PF15 86
|
||||
|
||||
#define IRQ_PG0 87
|
||||
#define IRQ_PG1 88
|
||||
#define IRQ_PG2 89
|
||||
#define IRQ_PG3 90
|
||||
#define IRQ_PG4 91
|
||||
#define IRQ_PG5 92
|
||||
#define IRQ_PG6 93
|
||||
#define IRQ_PG7 94
|
||||
#define IRQ_PG8 95
|
||||
#define IRQ_PG9 96
|
||||
#define IRQ_PG10 97
|
||||
#define IRQ_PG11 98
|
||||
#define IRQ_PG12 99
|
||||
#define IRQ_PG13 100
|
||||
#define IRQ_PG14 101
|
||||
#define IRQ_PG15 102
|
||||
|
||||
#define IRQ_PH0 103
|
||||
#define IRQ_PH1 104
|
||||
#define IRQ_PH2 105
|
||||
#define IRQ_PH3 106
|
||||
#define IRQ_PH4 107
|
||||
#define IRQ_PH5 108
|
||||
#define IRQ_PH6 109
|
||||
#define IRQ_PH7 110
|
||||
#define IRQ_PH8 111
|
||||
#define IRQ_PH9 112
|
||||
#define IRQ_PH10 113
|
||||
#define IRQ_PH11 114
|
||||
#define IRQ_PH12 115
|
||||
#define IRQ_PH13 116
|
||||
#define IRQ_PH14 117
|
||||
#define IRQ_PH15 118
|
||||
|
||||
#define GPIO_IRQ_BASE IRQ_PF0
|
||||
|
||||
#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
|
||||
#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
|
||||
#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
|
||||
#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
|
||||
#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
|
||||
#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
|
||||
#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
|
||||
#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
|
||||
|
||||
#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
|
||||
|
||||
/* IAR0 BIT FIELDS */
|
||||
#define IRQ_PLL_WAKEUP_POS 0
|
||||
#define IRQ_DMA0_ERROR_POS 4
|
||||
#define IRQ_DMAR0_BLK_POS 8
|
||||
#define IRQ_DMAR1_BLK_POS 12
|
||||
#define IRQ_DMAR0_OVR_POS 16
|
||||
#define IRQ_DMAR1_OVR_POS 20
|
||||
#define IRQ_PPI_ERROR_POS 24
|
||||
#define IRQ_MAC_ERROR_POS 28
|
||||
|
||||
/* IAR1 BIT FIELDS */
|
||||
#define IRQ_SPORT0_ERROR_POS 0
|
||||
#define IRQ_SPORT1_ERROR_POS 4
|
||||
#define IRQ_UART0_ERROR_POS 16
|
||||
#define IRQ_UART1_ERROR_POS 20
|
||||
#define IRQ_RTC_POS 24
|
||||
#define IRQ_PPI_POS 28
|
||||
|
||||
/* IAR2 BIT FIELDS */
|
||||
#define IRQ_SPORT0_RX_POS 0
|
||||
#define IRQ_SPORT0_TX_POS 4
|
||||
#define IRQ_SPORT1_RX_POS 8
|
||||
#define IRQ_SPORT1_TX_POS 12
|
||||
#define IRQ_TWI_POS 16
|
||||
#define IRQ_SPI_POS 20
|
||||
#define IRQ_UART0_RX_POS 24
|
||||
#define IRQ_UART0_TX_POS 28
|
||||
|
||||
/* IAR3 BIT FIELDS */
|
||||
#define IRQ_UART1_RX_POS 0
|
||||
#define IRQ_UART1_TX_POS 4
|
||||
#define IRQ_OPTSEC_POS 8
|
||||
#define IRQ_CNT_POS 12
|
||||
#define IRQ_MAC_RX_POS 16
|
||||
#define IRQ_PORTH_INTA_POS 20
|
||||
#define IRQ_MAC_TX_POS 24
|
||||
#define IRQ_PORTH_INTB_POS 28
|
||||
|
||||
/* IAR4 BIT FIELDS */
|
||||
#define IRQ_TIMER0_POS 0
|
||||
#define IRQ_TIMER1_POS 4
|
||||
#define IRQ_TIMER2_POS 8
|
||||
#define IRQ_TIMER3_POS 12
|
||||
#define IRQ_TIMER4_POS 16
|
||||
#define IRQ_TIMER5_POS 20
|
||||
#define IRQ_TIMER6_POS 24
|
||||
#define IRQ_TIMER7_POS 28
|
||||
|
||||
/* IAR5 BIT FIELDS */
|
||||
#define IRQ_PORTG_INTA_POS 0
|
||||
#define IRQ_PORTG_INTB_POS 4
|
||||
#define IRQ_MEM_DMA0_POS 8
|
||||
#define IRQ_MEM_DMA1_POS 12
|
||||
#define IRQ_WATCH_POS 16
|
||||
#define IRQ_PORTF_INTA_POS 20
|
||||
#define IRQ_PORTF_INTB_POS 24
|
||||
#define IRQ_SPI_ERROR_POS 28
|
||||
|
||||
/* IAR6 BIT FIELDS */
|
||||
#define IRQ_NFC_ERROR_POS 0
|
||||
#define IRQ_HDMA_ERROR_POS 4
|
||||
#define IRQ_HDMA_POS 8
|
||||
#define IRQ_USB_EINT_POS 12
|
||||
#define IRQ_USB_INT0_POS 16
|
||||
#define IRQ_USB_INT1_POS 20
|
||||
#define IRQ_USB_INT2_POS 24
|
||||
#define IRQ_USB_DMA_POS 28
|
||||
|
||||
#endif
|
||||
70
arch/blackfin/mach-bf527/include/mach/mem_map.h
Normal file
70
arch/blackfin/mach-bf527/include/mach/mem_map.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* BF52x memory map
|
||||
*
|
||||
* Copyright 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_MACH_MEM_MAP_H__
|
||||
#define __BFIN_MACH_MEM_MAP_H__
|
||||
|
||||
#ifndef __BFIN_MEM_MAP_H__
|
||||
# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
|
||||
#endif
|
||||
|
||||
/* Async Memory Banks */
|
||||
#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
|
||||
#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
|
||||
#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
|
||||
#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
|
||||
#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
|
||||
#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
|
||||
#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
|
||||
#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
|
||||
|
||||
/* Boot ROM Memory */
|
||||
|
||||
#define BOOT_ROM_START 0xEF000000
|
||||
#define BOOT_ROM_LENGTH 0x8000
|
||||
|
||||
/* Level 1 Memory */
|
||||
|
||||
/* Memory Map for ADSP-BF527 ADSP-BF525 ADSP-BF522 processors */
|
||||
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
#define BFIN_ICACHESIZE (16*1024)
|
||||
#else
|
||||
#define BFIN_ICACHESIZE (0*1024)
|
||||
#endif
|
||||
|
||||
#define L1_CODE_START 0xFFA00000
|
||||
#define L1_DATA_A_START 0xFF800000
|
||||
#define L1_DATA_B_START 0xFF900000
|
||||
|
||||
#define L1_CODE_LENGTH 0xC000
|
||||
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
|
||||
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BFIN_DCACHESIZE (16*1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
#else
|
||||
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
|
||||
#define BFIN_DCACHESIZE (32*1024)
|
||||
#define BFIN_DSUPBANKS 2
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x8000
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BFIN_DCACHESIZE (0*1024)
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE */
|
||||
|
||||
#endif
|
||||
1
arch/blackfin/mach-bf527/include/mach/pll.h
Normal file
1
arch/blackfin/mach-bf527/include/mach/pll.h
Normal file
|
|
@ -0,0 +1 @@
|
|||
#include <mach-common/pll.h>
|
||||
220
arch/blackfin/mach-bf527/include/mach/portmux.h
Normal file
220
arch/blackfin/mach-bf527/include/mach/portmux.h
Normal file
|
|
@ -0,0 +1,220 @@
|
|||
/*
|
||||
* Copyright 2007-2009 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later
|
||||
*/
|
||||
|
||||
#ifndef _MACH_PORTMUX_H_
|
||||
#define _MACH_PORTMUX_H_
|
||||
|
||||
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
|
||||
|
||||
#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
|
||||
#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
|
||||
#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
|
||||
#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
|
||||
#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
|
||||
#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
|
||||
#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
|
||||
#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
|
||||
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
|
||||
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
|
||||
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
|
||||
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
|
||||
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
|
||||
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
|
||||
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
|
||||
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
|
||||
|
||||
#if defined(CONFIG_BF527_SPORT0_PORTF)
|
||||
#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
|
||||
#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
|
||||
#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
|
||||
#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
|
||||
#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
|
||||
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
|
||||
#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
|
||||
#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
|
||||
#elif defined(CONFIG_BF527_SPORT0_PORTG)
|
||||
#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
|
||||
#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
|
||||
#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
|
||||
#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
|
||||
#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
|
||||
#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
|
||||
#if defined(CONFIG_BF527_SPORT0_TSCLK_PG10)
|
||||
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
|
||||
#elif defined(CONFIG_BF527_SPORT0_TSCLK_PG14)
|
||||
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
|
||||
#endif
|
||||
#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
|
||||
#endif
|
||||
|
||||
#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
|
||||
#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
|
||||
#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
|
||||
#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
|
||||
#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
|
||||
#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
|
||||
#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
|
||||
#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
|
||||
|
||||
#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
|
||||
#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
|
||||
|
||||
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
|
||||
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
|
||||
|
||||
#if defined(CONFIG_BF527_UART1_PORTF)
|
||||
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
|
||||
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
|
||||
#elif defined(CONFIG_BF527_UART1_PORTG)
|
||||
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
|
||||
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
|
||||
#endif
|
||||
|
||||
#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(3))
|
||||
#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(3))
|
||||
#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(3))
|
||||
|
||||
#define P_HWAIT (P_DONTCARE)
|
||||
|
||||
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1
|
||||
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
|
||||
|
||||
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
|
||||
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
|
||||
#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
|
||||
#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
|
||||
#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
|
||||
#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
|
||||
#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
|
||||
#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
|
||||
#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
|
||||
#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
|
||||
#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
|
||||
/* #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */
|
||||
#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
|
||||
#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
|
||||
#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
|
||||
#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
|
||||
#define P_MDC (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
|
||||
#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
|
||||
#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
|
||||
|
||||
#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
|
||||
#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
|
||||
#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
|
||||
|
||||
#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
|
||||
#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
|
||||
#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
|
||||
#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
|
||||
#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
|
||||
|
||||
#if defined(CONFIG_BF527_NAND_D_PORTF)
|
||||
#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
|
||||
#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
|
||||
#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
|
||||
#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
|
||||
#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
|
||||
#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
|
||||
#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
|
||||
#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
|
||||
#elif defined(CONFIG_BF527_NAND_D_PORTH)
|
||||
#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
|
||||
#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
|
||||
#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
|
||||
#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
|
||||
#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
|
||||
#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
|
||||
#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
|
||||
#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
|
||||
#endif
|
||||
|
||||
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
|
||||
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
|
||||
#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
|
||||
#define P_NAND_WE (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
|
||||
#define P_NAND_RE (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
|
||||
#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
|
||||
#define P_NAND_CLE (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
|
||||
#define P_NAND_ALE (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
|
||||
|
||||
#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
|
||||
#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
|
||||
#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
|
||||
#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
|
||||
#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
|
||||
#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2))
|
||||
#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
|
||||
#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
|
||||
#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
|
||||
#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2))
|
||||
#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2))
|
||||
#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2))
|
||||
#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2))
|
||||
#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2))
|
||||
#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2))
|
||||
#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2))
|
||||
|
||||
#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
|
||||
#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
|
||||
#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1))
|
||||
#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1))
|
||||
#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
|
||||
#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
|
||||
#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
|
||||
#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
|
||||
#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1))
|
||||
#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1))
|
||||
#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1))
|
||||
#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1))
|
||||
#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1))
|
||||
#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
|
||||
#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
|
||||
#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
|
||||
#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
|
||||
#define P_MDIO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
|
||||
|
||||
#define P_TWI0_SCL (P_DONTCARE)
|
||||
#define P_TWI0_SDA (P_DONTCARE)
|
||||
#define P_PPI0_FS1 (P_DONTCARE)
|
||||
#define P_TMR0 (P_DONTCARE)
|
||||
#define P_TMRCLK (P_DONTCARE)
|
||||
#define P_PPI0_CLK (P_DONTCARE)
|
||||
|
||||
#define P_MII0 {\
|
||||
P_MII0_ETxD0, \
|
||||
P_MII0_ETxD1, \
|
||||
P_MII0_ETxD2, \
|
||||
P_MII0_ETxD3, \
|
||||
P_MII0_ETxEN, \
|
||||
P_MII0_TxCLK, \
|
||||
P_MII0_PHYINT, \
|
||||
P_MII0_COL, \
|
||||
P_MII0_ERxD0, \
|
||||
P_MII0_ERxD1, \
|
||||
P_MII0_ERxD2, \
|
||||
P_MII0_ERxD3, \
|
||||
P_MII0_ERxDV, \
|
||||
P_MII0_ERxCLK, \
|
||||
P_MII0_ERxER, \
|
||||
P_MII0_CRS, \
|
||||
P_MDC, \
|
||||
P_MDIO, 0}
|
||||
|
||||
#define P_RMII0 {\
|
||||
P_MII0_ETxD0, \
|
||||
P_MII0_ETxD1, \
|
||||
P_MII0_ETxEN, \
|
||||
P_MII0_ERxD0, \
|
||||
P_MII0_ERxD1, \
|
||||
P_MII0_ERxER, \
|
||||
P_RMII0_REF_CLK, \
|
||||
P_RMII0_MDINT, \
|
||||
P_RMII0_CRS_DV, \
|
||||
P_MDC, \
|
||||
P_MDIO, 0}
|
||||
|
||||
#endif /* _MACH_PORTMUX_H_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue