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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-02 00:55:37 +01:00
Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
237
arch/blackfin/mach-bf527/include/mach/bf527.h
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237
arch/blackfin/mach-bf527/include/mach/bf527.h
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/*
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* Copyright 2007-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef __MACH_BF527_H__
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#define __MACH_BF527_H__
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#define OFFSET_(x) ((x) & 0x0000FFFF)
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/*some misc defines*/
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#define IMASK_IVG15 0x8000
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#define IMASK_IVG14 0x4000
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#define IMASK_IVG13 0x2000
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#define IMASK_IVG12 0x1000
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#define IMASK_IVG11 0x0800
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#define IMASK_IVG10 0x0400
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#define IMASK_IVG9 0x0200
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#define IMASK_IVG8 0x0100
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#define IMASK_IVG7 0x0080
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#define IMASK_IVGTMR 0x0040
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#define IMASK_IVGHW 0x0020
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/***************************/
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#define BFIN_DSUBBANKS 4
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#define BFIN_DWAYS 2
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#define BFIN_DLINES 64
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#define BFIN_ISUBBANKS 4
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#define BFIN_IWAYS 4
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#define BFIN_ILINES 32
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#define WAY0_L 0x1
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#define WAY1_L 0x2
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#define WAY01_L 0x3
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#define WAY2_L 0x4
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#define WAY02_L 0x5
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#define WAY12_L 0x6
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#define WAY012_L 0x7
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#define WAY3_L 0x8
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#define WAY03_L 0x9
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#define WAY13_L 0xA
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#define WAY013_L 0xB
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#define WAY32_L 0xC
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#define WAY320_L 0xD
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#define WAY321_L 0xE
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#define WAYALL_L 0xF
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#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
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/********************************* EBIU Settings ************************************/
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#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
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#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
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#ifdef CONFIG_C_AMBEN_ALL
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#define V_AMBEN AMBEN_ALL
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#endif
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#ifdef CONFIG_C_AMBEN
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#define V_AMBEN 0x0
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#endif
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#ifdef CONFIG_C_AMBEN_B0
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#define V_AMBEN AMBEN_B0
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#endif
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#ifdef CONFIG_C_AMBEN_B0_B1
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#define V_AMBEN AMBEN_B0_B1
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#endif
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#ifdef CONFIG_C_AMBEN_B0_B1_B2
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#define V_AMBEN AMBEN_B0_B1_B2
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#endif
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#ifdef CONFIG_C_AMCKEN
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#define V_AMCKEN AMCKEN
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#else
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#define V_AMCKEN 0x0
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#endif
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#ifdef CONFIG_C_CDPRIO
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#define V_CDPRIO 0x100
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#else
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#define V_CDPRIO 0x0
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#endif
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#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
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/**************************** Hysteresis Settings ****************************/
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#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
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#ifdef CONFIG_GPIO_HYST_PORTF_0_7
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#define HYST_PORTF_0_7 (1 << 0)
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#else
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#define HYST_PORTF_0_7 (0 << 0)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTF_8_9
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#define HYST_PORTF_8_9 (1 << 2)
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#else
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#define HYST_PORTF_8_9 (0 << 2)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTF_10
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#define HYST_PORTF_10 (1 << 4)
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#else
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#define HYST_PORTF_10 (0 << 4)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTF_11
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#define HYST_PORTF_11 (1 << 6)
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#else
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#define HYST_PORTF_11 (0 << 6)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTF_12_13
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#define HYST_PORTF_12_13 (1 << 8)
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#else
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#define HYST_PORTF_12_13 (0 << 8)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTF_14_15
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#define HYST_PORTF_14_15 (1 << 10)
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#else
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#define HYST_PORTF_14_15 (0 << 10)
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#endif
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#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
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HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
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#ifdef CONFIG_GPIO_HYST_PORTG_0
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#define HYST_PORTG_0 (1 << 0)
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#else
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#define HYST_PORTG_0 (0 << 0)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_1_4
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#define HYST_PORTG_1_4 (1 << 2)
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#else
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#define HYST_PORTG_1_4 (0 << 2)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_5_6
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#define HYST_PORTG_5_6 (1 << 4)
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#else
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#define HYST_PORTG_5_6 (0 << 4)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_7_8
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#define HYST_PORTG_7_8 (1 << 6)
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#else
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#define HYST_PORTG_7_8 (0 << 6)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_9
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#define HYST_PORTG_9 (1 << 8)
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#else
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#define HYST_PORTG_9 (0 << 8)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_10
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#define HYST_PORTG_10 (1 << 10)
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#else
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#define HYST_PORTG_10 (0 << 10)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_11_13
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#define HYST_PORTG_11_13 (1 << 12)
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#else
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#define HYST_PORTG_11_13 (0 << 12)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_14_15
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#define HYST_PORTG_14_15 (1 << 14)
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#else
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#define HYST_PORTG_14_15 (0 << 14)
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#endif
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#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
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HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
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HYST_PORTG_11_13 | HYST_PORTG_14_15)
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#ifdef CONFIG_GPIO_HYST_PORTH_0_7
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#define HYST_PORTH_0_7 (1 << 0)
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#else
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#define HYST_PORTH_0_7 (0 << 0)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTH_8
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#define HYST_PORTH_8 (1 << 2)
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#else
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#define HYST_PORTH_8 (0 << 2)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTH_9_15
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#define HYST_PORTH_9_15 (1 << 4)
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#else
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#define HYST_PORTH_9_15 (0 << 4)
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#endif
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#define HYST_PORTH_0_15 (HYST_PORTH_0_7 | HYST_PORTH_8 | HYST_PORTH_9_15)
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#ifdef CONFIG_NONEGPIO_HYST_TMR0_FS1_PPICLK
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#define HYST_TMR0_FS1_PPICLK (1 << 0)
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#else
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#define HYST_TMR0_FS1_PPICLK (0 << 0)
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#endif
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#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
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#define HYST_NMI_RST_BMODE (1 << 2)
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#else
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#define HYST_NMI_RST_BMODE (0 << 2)
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#endif
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#ifdef CONFIG_NONEGPIO_HYST_JTAG
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#define HYST_JTAG (1 << 4)
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#else
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#define HYST_JTAG (0 << 4)
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#endif
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#define HYST_NONEGPIO (HYST_TMR0_FS1_PPICLK | HYST_NMI_RST_BMODE | HYST_JTAG)
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#define HYST_NONEGPIO_MASK (0x3F)
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#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
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#ifdef CONFIG_BF527
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#define CPU "BF527"
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#define CPUID 0x27e0
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#endif
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#ifdef CONFIG_BF526
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#define CPU "BF526"
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#define CPUID 0x27e4
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#endif
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#ifdef CONFIG_BF525
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#define CPU "BF525"
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#define CPUID 0x27e0
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#endif
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#ifdef CONFIG_BF524
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#define CPU "BF524"
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#define CPUID 0x27e4
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#endif
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#ifdef CONFIG_BF523
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#define CPU "BF523"
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#define CPUID 0x27e0
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#endif
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#ifdef CONFIG_BF522
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#define CPU "BF522"
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#define CPUID 0x27e4
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#endif
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#ifndef CPU
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#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
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#endif
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#endif /* __MACH_BF527_H__ */
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