mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 09:08:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
165
arch/blackfin/mach-bf538/Kconfig
Normal file
165
arch/blackfin/mach-bf538/Kconfig
Normal file
|
|
@ -0,0 +1,165 @@
|
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if (BF538 || BF539)
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|
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source "arch/blackfin/mach-bf538/boards/Kconfig"
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|
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menu "BF538 Specific Configuration"
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|
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comment "Interrupt Priority Assignment"
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menu "Priority"
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|
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config IRQ_PLL_WAKEUP
|
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int "IRQ_PLL_WAKEUP"
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default 7
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config IRQ_DMA0_ERROR
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int "IRQ_DMA0_ERROR"
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default 7
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config IRQ_PPI_ERROR
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int "IRQ_PPI_ERROR"
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default 7
|
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config IRQ_SPORT0_ERROR
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int "IRQ_SPORT0_ERROR"
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default 7
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config IRQ_SPORT1_ERROR
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int "IRQ_SPORT1_ERROR"
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default 7
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config IRQ_SPI0_ERROR
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int "IRQ_SPI0_ERROR"
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default 7
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config IRQ_UART0_ERROR
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int "IRQ_UART0_ERROR"
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default 7
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config IRQ_RTC
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int "IRQ_RTC"
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default 8
|
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config IRQ_PPI
|
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int "IRQ_PPI"
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default 8
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config IRQ_SPORT0_RX
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int "IRQ_SPORT0_RX"
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default 9
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config IRQ_SPORT0_TX
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int "IRQ_SPORT0_TX"
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default 9
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config IRQ_SPORT1_RX
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int "IRQ_SPORT1_RX"
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default 9
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config IRQ_SPORT1_TX
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int "IRQ_SPORT1_TX"
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default 9
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config IRQ_SPI0
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int "IRQ_SPI0"
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default 10
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config IRQ_UART0_RX
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int "IRQ_UART0_RX"
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default 10
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config IRQ_UART0_TX
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int "IRQ_UART0_TX"
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default 10
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config IRQ_TIMER0
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int "IRQ_TIMER0"
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default 7 if TICKSOURCE_GPTMR0
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default 8
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config IRQ_TIMER1
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int "IRQ_TIMER1"
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default 11
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config IRQ_TIMER2
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int "IRQ_TIMER2"
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default 11
|
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config IRQ_PORTF_INTA
|
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int "IRQ_PORTF_INTA"
|
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default 12
|
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config IRQ_PORTF_INTB
|
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int "IRQ_PORTF_INTB"
|
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default 12
|
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config IRQ_MEM0_DMA0
|
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int "IRQ_MEM0_DMA0"
|
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default 13
|
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config IRQ_MEM0_DMA1
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int "IRQ_MEM0_DMA1"
|
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default 13
|
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config IRQ_WATCH
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int "IRQ_WATCH"
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default 13
|
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config IRQ_DMA1_ERROR
|
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int "IRQ_DMA1_ERROR"
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default 7
|
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config IRQ_SPORT2_ERROR
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int "IRQ_SPORT2_ERROR"
|
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default 7
|
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config IRQ_SPORT3_ERROR
|
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int "IRQ_SPORT3_ERROR"
|
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default 7
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config IRQ_SPI1_ERROR
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int "IRQ_SPI1_ERROR"
|
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default 7
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config IRQ_SPI2_ERROR
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int "IRQ_SPI2_ERROR"
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default 7
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config IRQ_UART1_ERROR
|
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int "IRQ_UART1_ERROR"
|
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default 7
|
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config IRQ_UART2_ERROR
|
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int "IRQ_UART2_ERROR"
|
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default 7
|
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config IRQ_CAN_ERROR
|
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int "IRQ_CAN_ERROR"
|
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default 7
|
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config IRQ_SPORT2_RX
|
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int "IRQ_SPORT2_RX"
|
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default 9
|
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config IRQ_SPORT2_TX
|
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int "IRQ_SPORT2_TX"
|
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default 9
|
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config IRQ_SPORT3_RX
|
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int "IRQ_SPORT3_RX"
|
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default 9
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config IRQ_SPORT3_TX
|
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int "IRQ_SPORT3_TX"
|
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default 9
|
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config IRQ_SPI1
|
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int "IRQ_SPI1"
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default 10
|
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config IRQ_SPI2
|
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int "IRQ_SPI2"
|
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default 10
|
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config IRQ_UART1_RX
|
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int "IRQ_UART1_RX"
|
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default 10
|
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config IRQ_UART1_TX
|
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int "IRQ_UART1_TX"
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default 10
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config IRQ_UART2_RX
|
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int "IRQ_UART2_RX"
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default 10
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config IRQ_UART2_TX
|
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int "IRQ_UART2_TX"
|
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default 10
|
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config IRQ_TWI0
|
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int "IRQ_TWI0"
|
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default 11
|
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config IRQ_TWI1
|
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int "IRQ_TWI1"
|
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default 11
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config IRQ_CAN_RX
|
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int "IRQ_CAN_RX"
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default 11
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config IRQ_CAN_TX
|
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int "IRQ_CAN_TX"
|
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default 11
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config IRQ_MEM1_DMA0
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int "IRQ_MEM1_DMA0"
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default 13
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config IRQ_MEM1_DMA1
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int "IRQ_MEM1_DMA1"
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default 13
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help
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Enter the priority numbers between 7-13 ONLY. Others are Reserved.
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This applies to all the above. It is not recommended to assign the
|
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highest priority number 7 to UART or any other device.
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endmenu
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endmenu
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endif
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6
arch/blackfin/mach-bf538/Makefile
Normal file
6
arch/blackfin/mach-bf538/Makefile
Normal file
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@ -0,0 +1,6 @@
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#
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# arch/blackfin/mach-bf538/Makefile
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#
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obj-y := ints-priority.o dma.o
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obj-$(CONFIG_GPIOLIB) += ext-gpio.o
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12
arch/blackfin/mach-bf538/boards/Kconfig
Normal file
12
arch/blackfin/mach-bf538/boards/Kconfig
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
choice
|
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prompt "System type"
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default BFIN538_EZKIT
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help
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Select your board!
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config BFIN538_EZKIT
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bool "BF538-EZKIT"
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help
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BF538-EZKIT-LITE board support.
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endchoice
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5
arch/blackfin/mach-bf538/boards/Makefile
Normal file
5
arch/blackfin/mach-bf538/boards/Makefile
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
#
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||||
# arch/blackfin/mach-bf538/boards/Makefile
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#
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||||
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obj-$(CONFIG_BFIN538_EZKIT) += ezkit.o
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987
arch/blackfin/mach-bf538/boards/ezkit.c
Normal file
987
arch/blackfin/mach-bf538/boards/ezkit.c
Normal file
|
|
@ -0,0 +1,987 @@
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/*
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* Copyright 2004-2009 Analog Devices Inc.
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* 2005 National ICT Australia (NICTA)
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* Aidan Williams <aidan@nicta.com.au>
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*
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* Licensed under the GPL-2
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*/
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mtd/partitions.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/bfin5xx_spi.h>
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#include <asm/dma.h>
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#include <asm/gpio.h>
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#include <asm/nand.h>
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#include <asm/portmux.h>
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#include <asm/dpmc.h>
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#include <linux/input.h>
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/*
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* Name the Board for the /proc/cpuinfo
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*/
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const char bfin_board_name[] = "ADI BF538-EZKIT";
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/*
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* Driver needs to know address, irq and flag pin.
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*/
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#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
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static struct platform_device rtc_device = {
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.name = "rtc-bfin",
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.id = -1,
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};
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#endif /* CONFIG_RTC_DRV_BFIN */
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#if IS_ENABLED(CONFIG_SERIAL_BFIN)
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#ifdef CONFIG_SERIAL_BFIN_UART0
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static struct resource bfin_uart0_resources[] = {
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{
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.start = UART0_THR,
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.end = UART0_GCTL+2,
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.flags = IORESOURCE_MEM,
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},
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{
|
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.start = IRQ_UART0_TX,
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.end = IRQ_UART0_TX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = IRQ_UART0_RX,
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.end = IRQ_UART0_RX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = IRQ_UART0_ERROR,
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.end = IRQ_UART0_ERROR,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = CH_UART0_TX,
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.end = CH_UART0_TX,
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.flags = IORESOURCE_DMA,
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},
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{
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.start = CH_UART0_RX,
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.end = CH_UART0_RX,
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.flags = IORESOURCE_DMA,
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},
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#ifdef CONFIG_BFIN_UART0_CTSRTS
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{ /* CTS pin */
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.start = GPIO_PG7,
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.end = GPIO_PG7,
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.flags = IORESOURCE_IO,
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},
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{ /* RTS pin */
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.start = GPIO_PG6,
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.end = GPIO_PG6,
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.flags = IORESOURCE_IO,
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},
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#endif
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};
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static unsigned short bfin_uart0_peripherals[] = {
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P_UART0_TX, P_UART0_RX, 0
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};
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static struct platform_device bfin_uart0_device = {
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.name = "bfin-uart",
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.id = 0,
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.num_resources = ARRAY_SIZE(bfin_uart0_resources),
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.resource = bfin_uart0_resources,
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.dev = {
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.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
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},
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};
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#endif /* CONFIG_SERIAL_BFIN_UART0 */
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#ifdef CONFIG_SERIAL_BFIN_UART1
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static struct resource bfin_uart1_resources[] = {
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{
|
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.start = UART1_THR,
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.end = UART1_GCTL+2,
|
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.flags = IORESOURCE_MEM,
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},
|
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{
|
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.start = IRQ_UART1_TX,
|
||||
.end = IRQ_UART1_TX,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART1_RX,
|
||||
.end = IRQ_UART1_RX,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART1_ERROR,
|
||||
.end = IRQ_UART1_ERROR,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = CH_UART1_TX,
|
||||
.end = CH_UART1_TX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.start = CH_UART1_RX,
|
||||
.end = CH_UART1_RX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static unsigned short bfin_uart1_peripherals[] = {
|
||||
P_UART1_TX, P_UART1_RX, 0
|
||||
};
|
||||
|
||||
static struct platform_device bfin_uart1_device = {
|
||||
.name = "bfin-uart",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(bfin_uart1_resources),
|
||||
.resource = bfin_uart1_resources,
|
||||
.dev = {
|
||||
.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_SERIAL_BFIN_UART1 */
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART2
|
||||
static struct resource bfin_uart2_resources[] = {
|
||||
{
|
||||
.start = UART2_THR,
|
||||
.end = UART2_GCTL+2,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART2_TX,
|
||||
.end = IRQ_UART2_TX,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART2_RX,
|
||||
.end = IRQ_UART2_RX,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART2_ERROR,
|
||||
.end = IRQ_UART2_ERROR,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = CH_UART2_TX,
|
||||
.end = CH_UART2_TX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.start = CH_UART2_RX,
|
||||
.end = CH_UART2_RX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static unsigned short bfin_uart2_peripherals[] = {
|
||||
P_UART2_TX, P_UART2_RX, 0
|
||||
};
|
||||
|
||||
static struct platform_device bfin_uart2_device = {
|
||||
.name = "bfin-uart",
|
||||
.id = 2,
|
||||
.num_resources = ARRAY_SIZE(bfin_uart2_resources),
|
||||
.resource = bfin_uart2_resources,
|
||||
.dev = {
|
||||
.platform_data = &bfin_uart2_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_SERIAL_BFIN_UART2 */
|
||||
#endif /* CONFIG_SERIAL_BFIN */
|
||||
|
||||
#if IS_ENABLED(CONFIG_BFIN_SIR)
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
static struct resource bfin_sir0_resources[] = {
|
||||
{
|
||||
.start = 0xFFC00400,
|
||||
.end = 0xFFC004FF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART0_RX,
|
||||
.end = IRQ_UART0_RX+1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = CH_UART0_RX,
|
||||
.end = CH_UART0_RX+1,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
static struct platform_device bfin_sir0_device = {
|
||||
.name = "bfin_sir",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(bfin_sir0_resources),
|
||||
.resource = bfin_sir0_resources,
|
||||
};
|
||||
#endif /* CONFIG_BFIN_SIR0 */
|
||||
#ifdef CONFIG_BFIN_SIR1
|
||||
static struct resource bfin_sir1_resources[] = {
|
||||
{
|
||||
.start = 0xFFC02000,
|
||||
.end = 0xFFC020FF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART1_RX,
|
||||
.end = IRQ_UART1_RX+1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = CH_UART1_RX,
|
||||
.end = CH_UART1_RX+1,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
static struct platform_device bfin_sir1_device = {
|
||||
.name = "bfin_sir",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(bfin_sir1_resources),
|
||||
.resource = bfin_sir1_resources,
|
||||
};
|
||||
#endif /* CONFIG_BFIN_SIR1 */
|
||||
#ifdef CONFIG_BFIN_SIR2
|
||||
static struct resource bfin_sir2_resources[] = {
|
||||
{
|
||||
.start = 0xFFC02100,
|
||||
.end = 0xFFC021FF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART2_RX,
|
||||
.end = IRQ_UART2_RX+1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = CH_UART2_RX,
|
||||
.end = CH_UART2_RX+1,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
static struct platform_device bfin_sir2_device = {
|
||||
.name = "bfin_sir",
|
||||
.id = 2,
|
||||
.num_resources = ARRAY_SIZE(bfin_sir2_resources),
|
||||
.resource = bfin_sir2_resources,
|
||||
};
|
||||
#endif /* CONFIG_BFIN_SIR2 */
|
||||
#endif /* CONFIG_BFIN_SIR */
|
||||
|
||||
#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
|
||||
static struct resource bfin_sport0_uart_resources[] = {
|
||||
{
|
||||
.start = SPORT0_TCR1,
|
||||
.end = SPORT0_MRCS3+4,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_SPORT0_RX,
|
||||
.end = IRQ_SPORT0_RX+1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_SPORT0_ERROR,
|
||||
.end = IRQ_SPORT0_ERROR,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static unsigned short bfin_sport0_peripherals[] = {
|
||||
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
|
||||
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
|
||||
};
|
||||
|
||||
static struct platform_device bfin_sport0_uart_device = {
|
||||
.name = "bfin-sport-uart",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
|
||||
.resource = bfin_sport0_uart_resources,
|
||||
.dev = {
|
||||
.platform_data = &bfin_sport0_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT0_UART */
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
|
||||
static struct resource bfin_sport1_uart_resources[] = {
|
||||
{
|
||||
.start = SPORT1_TCR1,
|
||||
.end = SPORT1_MRCS3+4,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_SPORT1_RX,
|
||||
.end = IRQ_SPORT1_RX+1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_SPORT1_ERROR,
|
||||
.end = IRQ_SPORT1_ERROR,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static unsigned short bfin_sport1_peripherals[] = {
|
||||
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
|
||||
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
|
||||
};
|
||||
|
||||
static struct platform_device bfin_sport1_uart_device = {
|
||||
.name = "bfin-sport-uart",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
|
||||
.resource = bfin_sport1_uart_resources,
|
||||
.dev = {
|
||||
.platform_data = &bfin_sport1_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT1_UART */
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
|
||||
static struct resource bfin_sport2_uart_resources[] = {
|
||||
{
|
||||
.start = SPORT2_TCR1,
|
||||
.end = SPORT2_MRCS3+4,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_SPORT2_RX,
|
||||
.end = IRQ_SPORT2_RX+1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_SPORT2_ERROR,
|
||||
.end = IRQ_SPORT2_ERROR,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static unsigned short bfin_sport2_peripherals[] = {
|
||||
P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
|
||||
P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
|
||||
};
|
||||
|
||||
static struct platform_device bfin_sport2_uart_device = {
|
||||
.name = "bfin-sport-uart",
|
||||
.id = 2,
|
||||
.num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
|
||||
.resource = bfin_sport2_uart_resources,
|
||||
.dev = {
|
||||
.platform_data = &bfin_sport2_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT2_UART */
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
|
||||
static struct resource bfin_sport3_uart_resources[] = {
|
||||
{
|
||||
.start = SPORT3_TCR1,
|
||||
.end = SPORT3_MRCS3+4,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_SPORT3_RX,
|
||||
.end = IRQ_SPORT3_RX+1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_SPORT3_ERROR,
|
||||
.end = IRQ_SPORT3_ERROR,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static unsigned short bfin_sport3_peripherals[] = {
|
||||
P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
|
||||
P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
|
||||
};
|
||||
|
||||
static struct platform_device bfin_sport3_uart_device = {
|
||||
.name = "bfin-sport-uart",
|
||||
.id = 3,
|
||||
.num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
|
||||
.resource = bfin_sport3_uart_resources,
|
||||
.dev = {
|
||||
.platform_data = &bfin_sport3_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT3_UART */
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT */
|
||||
|
||||
#if IS_ENABLED(CONFIG_CAN_BFIN)
|
||||
static unsigned short bfin_can_peripherals[] = {
|
||||
P_CAN0_RX, P_CAN0_TX, 0
|
||||
};
|
||||
|
||||
static struct resource bfin_can_resources[] = {
|
||||
{
|
||||
.start = 0xFFC02A00,
|
||||
.end = 0xFFC02FFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_CAN_RX,
|
||||
.end = IRQ_CAN_RX,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_CAN_TX,
|
||||
.end = IRQ_CAN_TX,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_CAN_ERROR,
|
||||
.end = IRQ_CAN_ERROR,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device bfin_can_device = {
|
||||
.name = "bfin_can",
|
||||
.num_resources = ARRAY_SIZE(bfin_can_resources),
|
||||
.resource = bfin_can_resources,
|
||||
.dev = {
|
||||
.platform_data = &bfin_can_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_CAN_BFIN */
|
||||
|
||||
/*
|
||||
* USB-LAN EzExtender board
|
||||
* Driver needs to know address, irq and flag pin.
|
||||
*/
|
||||
#if IS_ENABLED(CONFIG_SMC91X)
|
||||
#include <linux/smc91x.h>
|
||||
|
||||
static struct smc91x_platdata smc91x_info = {
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
|
||||
.leda = RPC_LED_100_10,
|
||||
.ledb = RPC_LED_TX_RX,
|
||||
};
|
||||
|
||||
static struct resource smc91x_resources[] = {
|
||||
{
|
||||
.name = "smc91x-regs",
|
||||
.start = 0x20310300,
|
||||
.end = 0x20310300 + 16,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_PF0,
|
||||
.end = IRQ_PF0,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
|
||||
},
|
||||
};
|
||||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
.dev = {
|
||||
.platform_data = &smc91x_info,
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_SMC91X */
|
||||
|
||||
#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
|
||||
/* all SPI peripherals info goes here */
|
||||
#if IS_ENABLED(CONFIG_MTD_M25P80)
|
||||
/* SPI flash chip (m25p16) */
|
||||
static struct mtd_partition bfin_spi_flash_partitions[] = {
|
||||
{
|
||||
.name = "bootloader(spi)",
|
||||
.size = 0x00040000,
|
||||
.offset = 0,
|
||||
.mask_flags = MTD_CAP_ROM
|
||||
}, {
|
||||
.name = "linux kernel(spi)",
|
||||
.size = 0x1c0000,
|
||||
.offset = 0x40000
|
||||
}
|
||||
};
|
||||
|
||||
static struct flash_platform_data bfin_spi_flash_data = {
|
||||
.name = "m25p80",
|
||||
.parts = bfin_spi_flash_partitions,
|
||||
.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
|
||||
.type = "m25p16",
|
||||
};
|
||||
|
||||
static struct bfin5xx_spi_chip spi_flash_chip_info = {
|
||||
.enable_dma = 0, /* use dma transfer with this chip*/
|
||||
};
|
||||
#endif /* CONFIG_MTD_M25P80 */
|
||||
#endif /* CONFIG_SPI_BFIN5XX */
|
||||
|
||||
#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
|
||||
#include <linux/spi/ad7879.h>
|
||||
static const struct ad7879_platform_data bfin_ad7879_ts_info = {
|
||||
.model = 7879, /* Model = AD7879 */
|
||||
.x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
|
||||
.pressure_max = 10000,
|
||||
.pressure_min = 0,
|
||||
.first_conversion_delay = 3, /* wait 512us before do a first conversion */
|
||||
.acquisition_time = 1, /* 4us acquisition time per sample */
|
||||
.median = 2, /* do 8 measurements */
|
||||
.averaging = 1, /* take the average of 4 middle samples */
|
||||
.pen_down_acc_interval = 255, /* 9.4 ms */
|
||||
.gpio_export = 1, /* Export GPIO to gpiolib */
|
||||
.gpio_base = -1, /* Dynamic allocation */
|
||||
};
|
||||
#endif /* CONFIG_TOUCHSCREEN_AD7879 */
|
||||
|
||||
#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
|
||||
#include <asm/bfin-lq035q1.h>
|
||||
|
||||
static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
|
||||
.mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
|
||||
.ppi_mode = USE_RGB565_16_BIT_PPI,
|
||||
.use_bl = 0, /* let something else control the LCD Blacklight */
|
||||
.gpio_bl = GPIO_PF7,
|
||||
};
|
||||
|
||||
static struct resource bfin_lq035q1_resources[] = {
|
||||
{
|
||||
.start = IRQ_PPI_ERROR,
|
||||
.end = IRQ_PPI_ERROR,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device bfin_lq035q1_device = {
|
||||
.name = "bfin-lq035q1",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
|
||||
.resource = bfin_lq035q1_resources,
|
||||
.dev = {
|
||||
.platform_data = &bfin_lq035q1_data,
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_FB_BFIN_LQ035Q1 */
|
||||
|
||||
static struct spi_board_info bf538_spi_board_info[] __initdata = {
|
||||
#if IS_ENABLED(CONFIG_MTD_M25P80)
|
||||
{
|
||||
/* the modalias must be the same as spi device driver name */
|
||||
.modalias = "m25p80", /* Name of spi_driver for this device */
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0, /* Framework bus number */
|
||||
.chip_select = 1, /* SPI_SSEL1*/
|
||||
.platform_data = &bfin_spi_flash_data,
|
||||
.controller_data = &spi_flash_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif /* CONFIG_MTD_M25P80 */
|
||||
#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
|
||||
{
|
||||
.modalias = "ad7879",
|
||||
.platform_data = &bfin_ad7879_ts_info,
|
||||
.irq = IRQ_PF3,
|
||||
.max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 1,
|
||||
.mode = SPI_CPHA | SPI_CPOL,
|
||||
},
|
||||
#endif /* CONFIG_TOUCHSCREEN_AD7879_SPI */
|
||||
#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
|
||||
{
|
||||
.modalias = "bfin-lq035q1-spi",
|
||||
.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 2,
|
||||
.mode = SPI_CPHA | SPI_CPOL,
|
||||
},
|
||||
#endif /* CONFIG_FB_BFIN_LQ035Q1 */
|
||||
#if IS_ENABLED(CONFIG_SPI_SPIDEV)
|
||||
{
|
||||
.modalias = "spidev",
|
||||
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 1,
|
||||
},
|
||||
#endif /* CONFIG_SPI_SPIDEV */
|
||||
};
|
||||
|
||||
/* SPI (0) */
|
||||
static struct resource bfin_spi0_resource[] = {
|
||||
[0] = {
|
||||
.start = SPI0_REGBASE,
|
||||
.end = SPI0_REGBASE + 0xFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = CH_SPI0,
|
||||
.end = CH_SPI0,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[2] = {
|
||||
.start = IRQ_SPI0,
|
||||
.end = IRQ_SPI0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
/* SPI (1) */
|
||||
static struct resource bfin_spi1_resource[] = {
|
||||
[0] = {
|
||||
.start = SPI1_REGBASE,
|
||||
.end = SPI1_REGBASE + 0xFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = CH_SPI1,
|
||||
.end = CH_SPI1,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[2] = {
|
||||
.start = IRQ_SPI1,
|
||||
.end = IRQ_SPI1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
/* SPI (2) */
|
||||
static struct resource bfin_spi2_resource[] = {
|
||||
[0] = {
|
||||
.start = SPI2_REGBASE,
|
||||
.end = SPI2_REGBASE + 0xFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = CH_SPI2,
|
||||
.end = CH_SPI2,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[2] = {
|
||||
.start = IRQ_SPI2,
|
||||
.end = IRQ_SPI2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
/* SPI controller data */
|
||||
static struct bfin5xx_spi_master bf538_spi_master_info0 = {
|
||||
.num_chipselect = 8,
|
||||
.enable_dma = 1, /* master has the ability to do dma transfer */
|
||||
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
|
||||
};
|
||||
|
||||
static struct platform_device bf538_spi_master0 = {
|
||||
.name = "bfin-spi",
|
||||
.id = 0, /* Bus number */
|
||||
.num_resources = ARRAY_SIZE(bfin_spi0_resource),
|
||||
.resource = bfin_spi0_resource,
|
||||
.dev = {
|
||||
.platform_data = &bf538_spi_master_info0, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
|
||||
static struct bfin5xx_spi_master bf538_spi_master_info1 = {
|
||||
.num_chipselect = 2,
|
||||
.enable_dma = 1, /* master has the ability to do dma transfer */
|
||||
.pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
|
||||
};
|
||||
|
||||
static struct platform_device bf538_spi_master1 = {
|
||||
.name = "bfin-spi",
|
||||
.id = 1, /* Bus number */
|
||||
.num_resources = ARRAY_SIZE(bfin_spi1_resource),
|
||||
.resource = bfin_spi1_resource,
|
||||
.dev = {
|
||||
.platform_data = &bf538_spi_master_info1, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
|
||||
static struct bfin5xx_spi_master bf538_spi_master_info2 = {
|
||||
.num_chipselect = 2,
|
||||
.enable_dma = 1, /* master has the ability to do dma transfer */
|
||||
.pin_req = {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0},
|
||||
};
|
||||
|
||||
static struct platform_device bf538_spi_master2 = {
|
||||
.name = "bfin-spi",
|
||||
.id = 2, /* Bus number */
|
||||
.num_resources = ARRAY_SIZE(bfin_spi2_resource),
|
||||
.resource = bfin_spi2_resource,
|
||||
.dev = {
|
||||
.platform_data = &bf538_spi_master_info2, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
|
||||
static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
|
||||
|
||||
static struct resource bfin_twi0_resource[] = {
|
||||
[0] = {
|
||||
.start = TWI0_REGBASE,
|
||||
.end = TWI0_REGBASE + 0xFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_TWI0,
|
||||
.end = IRQ_TWI0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c_bfin_twi0_device = {
|
||||
.name = "i2c-bfin-twi",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
|
||||
.resource = bfin_twi0_resource,
|
||||
.dev = {
|
||||
.platform_data = &bfin_twi0_pins,
|
||||
},
|
||||
};
|
||||
|
||||
static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
|
||||
|
||||
static struct resource bfin_twi1_resource[] = {
|
||||
[0] = {
|
||||
.start = TWI1_REGBASE,
|
||||
.end = TWI1_REGBASE + 0xFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_TWI1,
|
||||
.end = IRQ_TWI1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c_bfin_twi1_device = {
|
||||
.name = "i2c-bfin-twi",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(bfin_twi1_resource),
|
||||
.resource = bfin_twi1_resource,
|
||||
};
|
||||
#endif /* CONFIG_I2C_BLACKFIN_TWI */
|
||||
|
||||
#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
|
||||
#include <linux/gpio_keys.h>
|
||||
|
||||
static struct gpio_keys_button bfin_gpio_keys_table[] = {
|
||||
{BTN_0, GPIO_PC7, 1, "gpio-keys: BTN0"},
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data bfin_gpio_keys_data = {
|
||||
.buttons = bfin_gpio_keys_table,
|
||||
.nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
|
||||
};
|
||||
|
||||
static struct platform_device bfin_device_gpiokeys = {
|
||||
.name = "gpio-keys",
|
||||
.dev = {
|
||||
.platform_data = &bfin_gpio_keys_data,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
static const unsigned int cclk_vlev_datasheet[] =
|
||||
{
|
||||
/*
|
||||
* Internal VLEV BF538SBBC1533
|
||||
****temporarily using these values until data sheet is updated
|
||||
*/
|
||||
VRPAIR(VLEV_100, 150000000),
|
||||
VRPAIR(VLEV_100, 250000000),
|
||||
VRPAIR(VLEV_110, 276000000),
|
||||
VRPAIR(VLEV_115, 301000000),
|
||||
VRPAIR(VLEV_120, 525000000),
|
||||
VRPAIR(VLEV_125, 550000000),
|
||||
VRPAIR(VLEV_130, 600000000),
|
||||
};
|
||||
|
||||
static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
|
||||
.tuple_tab = cclk_vlev_datasheet,
|
||||
.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
|
||||
.vr_settling_time = 25 /* us */,
|
||||
};
|
||||
|
||||
static struct platform_device bfin_dpmc = {
|
||||
.name = "bfin dpmc",
|
||||
.dev = {
|
||||
.platform_data = &bfin_dmpc_vreg_data,
|
||||
},
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
|
||||
static struct mtd_partition ezkit_partitions[] = {
|
||||
{
|
||||
.name = "bootloader(nor)",
|
||||
.size = 0x40000,
|
||||
.offset = 0,
|
||||
}, {
|
||||
.name = "linux kernel(nor)",
|
||||
.size = 0x180000,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
}, {
|
||||
.name = "file system(nor)",
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
}
|
||||
};
|
||||
|
||||
static struct physmap_flash_data ezkit_flash_data = {
|
||||
.width = 2,
|
||||
.parts = ezkit_partitions,
|
||||
.nr_parts = ARRAY_SIZE(ezkit_partitions),
|
||||
};
|
||||
|
||||
static struct resource ezkit_flash_resource = {
|
||||
.start = 0x20000000,
|
||||
#if IS_ENABLED(CONFIG_SMC91X)
|
||||
.end = 0x202fffff,
|
||||
#else
|
||||
.end = 0x203fffff,
|
||||
#endif
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct platform_device ezkit_flash_device = {
|
||||
.name = "physmap-flash",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &ezkit_flash_data,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &ezkit_flash_resource,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct platform_device *cm_bf538_devices[] __initdata = {
|
||||
|
||||
&bfin_dpmc,
|
||||
|
||||
#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
|
||||
&rtc_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SERIAL_BFIN)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
&bfin_uart0_device,
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART1
|
||||
&bfin_uart1_device,
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART2
|
||||
&bfin_uart2_device,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
|
||||
&bf538_spi_master0,
|
||||
&bf538_spi_master1,
|
||||
&bf538_spi_master2,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
|
||||
&i2c_bfin_twi0_device,
|
||||
&i2c_bfin_twi1_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_BFIN_SIR)
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
&bfin_sir0_device,
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_SIR1
|
||||
&bfin_sir1_device,
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_SIR2
|
||||
&bfin_sir2_device,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
|
||||
&bfin_sport0_uart_device,
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
|
||||
&bfin_sport1_uart_device,
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
|
||||
&bfin_sport2_uart_device,
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
|
||||
&bfin_sport3_uart_device,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_CAN_BFIN)
|
||||
&bfin_can_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SMC91X)
|
||||
&smc91x_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
|
||||
&bfin_lq035q1_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
|
||||
&bfin_device_gpiokeys,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
|
||||
&ezkit_flash_device,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int __init ezkit_init(void)
|
||||
{
|
||||
printk(KERN_INFO "%s(): registering device resources\n", __func__);
|
||||
platform_add_devices(cm_bf538_devices, ARRAY_SIZE(cm_bf538_devices));
|
||||
|
||||
#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
|
||||
spi_register_board_info(bf538_spi_board_info,
|
||||
ARRAY_SIZE(bf538_spi_board_info));
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(ezkit_init);
|
||||
|
||||
static struct platform_device *ezkit_early_devices[] __initdata = {
|
||||
#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
&bfin_uart0_device,
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART1
|
||||
&bfin_uart1_device,
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART2
|
||||
&bfin_uart2_device,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
|
||||
&bfin_sport0_uart_device,
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
|
||||
&bfin_sport1_uart_device,
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
|
||||
&bfin_sport2_uart_device,
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
|
||||
&bfin_sport3_uart_device,
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
void __init native_machine_early_platform_add_devices(void)
|
||||
{
|
||||
printk(KERN_INFO "register early platform devices\n");
|
||||
early_platform_add_devices(ezkit_early_devices,
|
||||
ARRAY_SIZE(ezkit_early_devices));
|
||||
}
|
||||
141
arch/blackfin/mach-bf538/dma.c
Normal file
141
arch/blackfin/mach-bf538/dma.c
Normal file
|
|
@ -0,0 +1,141 @@
|
|||
/*
|
||||
* the simple DMA Implementation for Blackfin
|
||||
*
|
||||
* Copyright 2008 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/dma.h>
|
||||
|
||||
struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
|
||||
(struct dma_register *) DMA0_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA1_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA2_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA3_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA4_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA5_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA6_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA7_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA8_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA9_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA10_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA11_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA12_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA13_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA14_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA15_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA16_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA17_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA18_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA19_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
|
||||
};
|
||||
EXPORT_SYMBOL(dma_io_base_addr);
|
||||
|
||||
int channel2irq(unsigned int channel)
|
||||
{
|
||||
int ret_irq = -1;
|
||||
|
||||
switch (channel) {
|
||||
case CH_PPI:
|
||||
ret_irq = IRQ_PPI;
|
||||
break;
|
||||
|
||||
case CH_UART0_RX:
|
||||
ret_irq = IRQ_UART0_RX;
|
||||
break;
|
||||
|
||||
case CH_UART0_TX:
|
||||
ret_irq = IRQ_UART0_TX;
|
||||
break;
|
||||
|
||||
case CH_UART1_RX:
|
||||
ret_irq = IRQ_UART1_RX;
|
||||
break;
|
||||
|
||||
case CH_UART1_TX:
|
||||
ret_irq = IRQ_UART1_TX;
|
||||
break;
|
||||
|
||||
case CH_UART2_RX:
|
||||
ret_irq = IRQ_UART2_RX;
|
||||
break;
|
||||
|
||||
case CH_UART2_TX:
|
||||
ret_irq = IRQ_UART2_TX;
|
||||
break;
|
||||
|
||||
case CH_SPORT0_RX:
|
||||
ret_irq = IRQ_SPORT0_RX;
|
||||
break;
|
||||
|
||||
case CH_SPORT0_TX:
|
||||
ret_irq = IRQ_SPORT0_TX;
|
||||
break;
|
||||
|
||||
case CH_SPORT1_RX:
|
||||
ret_irq = IRQ_SPORT1_RX;
|
||||
break;
|
||||
|
||||
case CH_SPORT1_TX:
|
||||
ret_irq = IRQ_SPORT1_TX;
|
||||
break;
|
||||
|
||||
case CH_SPORT2_RX:
|
||||
ret_irq = IRQ_SPORT2_RX;
|
||||
break;
|
||||
|
||||
case CH_SPORT2_TX:
|
||||
ret_irq = IRQ_SPORT2_TX;
|
||||
break;
|
||||
|
||||
case CH_SPORT3_RX:
|
||||
ret_irq = IRQ_SPORT3_RX;
|
||||
break;
|
||||
|
||||
case CH_SPORT3_TX:
|
||||
ret_irq = IRQ_SPORT3_TX;
|
||||
break;
|
||||
|
||||
case CH_SPI0:
|
||||
ret_irq = IRQ_SPI0;
|
||||
break;
|
||||
|
||||
case CH_SPI1:
|
||||
ret_irq = IRQ_SPI1;
|
||||
break;
|
||||
|
||||
case CH_SPI2:
|
||||
ret_irq = IRQ_SPI2;
|
||||
break;
|
||||
|
||||
case CH_MEM_STREAM0_SRC:
|
||||
case CH_MEM_STREAM0_DEST:
|
||||
ret_irq = IRQ_MEM0_DMA0;
|
||||
break;
|
||||
case CH_MEM_STREAM1_SRC:
|
||||
case CH_MEM_STREAM1_DEST:
|
||||
ret_irq = IRQ_MEM0_DMA1;
|
||||
break;
|
||||
case CH_MEM_STREAM2_SRC:
|
||||
case CH_MEM_STREAM2_DEST:
|
||||
ret_irq = IRQ_MEM1_DMA0;
|
||||
break;
|
||||
case CH_MEM_STREAM3_SRC:
|
||||
case CH_MEM_STREAM3_DEST:
|
||||
ret_irq = IRQ_MEM1_DMA1;
|
||||
break;
|
||||
}
|
||||
return ret_irq;
|
||||
}
|
||||
158
arch/blackfin/mach-bf538/ext-gpio.c
Normal file
158
arch/blackfin/mach-bf538/ext-gpio.c
Normal file
|
|
@ -0,0 +1,158 @@
|
|||
/*
|
||||
* GPIOLIB interface for BF538/9 PORT C, D, and E GPIOs
|
||||
*
|
||||
* Copyright 2009-2011 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/err.h>
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/portmux.h>
|
||||
|
||||
#define DEFINE_REG(reg, off) \
|
||||
static inline u16 read_##reg(void __iomem *port) \
|
||||
{ return bfin_read16(port + off); } \
|
||||
static inline void write_##reg(void __iomem *port, u16 v) \
|
||||
{ bfin_write16(port + off, v); }
|
||||
|
||||
DEFINE_REG(PORTIO, 0x00)
|
||||
DEFINE_REG(PORTIO_CLEAR, 0x10)
|
||||
DEFINE_REG(PORTIO_SET, 0x20)
|
||||
DEFINE_REG(PORTIO_DIR, 0x40)
|
||||
DEFINE_REG(PORTIO_INEN, 0x50)
|
||||
|
||||
static void __iomem *gpio_chip_to_mmr(struct gpio_chip *chip)
|
||||
{
|
||||
switch (chip->base) {
|
||||
default: /* not really needed, but keeps gcc happy */
|
||||
case GPIO_PC0: return (void __iomem *)PORTCIO;
|
||||
case GPIO_PD0: return (void __iomem *)PORTDIO;
|
||||
case GPIO_PE0: return (void __iomem *)PORTEIO;
|
||||
}
|
||||
}
|
||||
|
||||
static int bf538_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
|
||||
{
|
||||
void __iomem *port = gpio_chip_to_mmr(chip);
|
||||
return !!(read_PORTIO(port) & (1u << gpio));
|
||||
}
|
||||
|
||||
static void bf538_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
|
||||
{
|
||||
void __iomem *port = gpio_chip_to_mmr(chip);
|
||||
if (value)
|
||||
write_PORTIO_SET(port, (1u << gpio));
|
||||
else
|
||||
write_PORTIO_CLEAR(port, (1u << gpio));
|
||||
}
|
||||
|
||||
static int bf538_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
|
||||
{
|
||||
void __iomem *port = gpio_chip_to_mmr(chip);
|
||||
write_PORTIO_DIR(port, read_PORTIO_DIR(port) & ~(1u << gpio));
|
||||
write_PORTIO_INEN(port, read_PORTIO_INEN(port) | (1u << gpio));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bf538_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
|
||||
{
|
||||
void __iomem *port = gpio_chip_to_mmr(chip);
|
||||
write_PORTIO_INEN(port, read_PORTIO_INEN(port) & ~(1u << gpio));
|
||||
bf538_gpio_set_value(port, gpio, value);
|
||||
write_PORTIO_DIR(port, read_PORTIO_DIR(port) | (1u << gpio));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bf538_gpio_request(struct gpio_chip *chip, unsigned gpio)
|
||||
{
|
||||
return bfin_special_gpio_request(chip->base + gpio, chip->label);
|
||||
}
|
||||
|
||||
static void bf538_gpio_free(struct gpio_chip *chip, unsigned gpio)
|
||||
{
|
||||
return bfin_special_gpio_free(chip->base + gpio);
|
||||
}
|
||||
|
||||
/* We don't set the irq fields as these banks cannot generate interrupts */
|
||||
|
||||
static struct gpio_chip bf538_portc_chip = {
|
||||
.label = "GPIO-PC",
|
||||
.direction_input = bf538_gpio_direction_input,
|
||||
.get = bf538_gpio_get_value,
|
||||
.direction_output = bf538_gpio_direction_output,
|
||||
.set = bf538_gpio_set_value,
|
||||
.request = bf538_gpio_request,
|
||||
.free = bf538_gpio_free,
|
||||
.base = GPIO_PC0,
|
||||
.ngpio = GPIO_PC9 - GPIO_PC0 + 1,
|
||||
};
|
||||
|
||||
static struct gpio_chip bf538_portd_chip = {
|
||||
.label = "GPIO-PD",
|
||||
.direction_input = bf538_gpio_direction_input,
|
||||
.get = bf538_gpio_get_value,
|
||||
.direction_output = bf538_gpio_direction_output,
|
||||
.set = bf538_gpio_set_value,
|
||||
.request = bf538_gpio_request,
|
||||
.free = bf538_gpio_free,
|
||||
.base = GPIO_PD0,
|
||||
.ngpio = GPIO_PD13 - GPIO_PD0 + 1,
|
||||
};
|
||||
|
||||
static struct gpio_chip bf538_porte_chip = {
|
||||
.label = "GPIO-PE",
|
||||
.direction_input = bf538_gpio_direction_input,
|
||||
.get = bf538_gpio_get_value,
|
||||
.direction_output = bf538_gpio_direction_output,
|
||||
.set = bf538_gpio_set_value,
|
||||
.request = bf538_gpio_request,
|
||||
.free = bf538_gpio_free,
|
||||
.base = GPIO_PE0,
|
||||
.ngpio = GPIO_PE15 - GPIO_PE0 + 1,
|
||||
};
|
||||
|
||||
static int __init bf538_extgpio_setup(void)
|
||||
{
|
||||
return gpiochip_add(&bf538_portc_chip) |
|
||||
gpiochip_add(&bf538_portd_chip) |
|
||||
gpiochip_add(&bf538_porte_chip);
|
||||
}
|
||||
arch_initcall(bf538_extgpio_setup);
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static struct {
|
||||
u16 data, dir, inen;
|
||||
} gpio_bank_saved[3];
|
||||
|
||||
static void __iomem * const port_bases[3] = {
|
||||
(void *)PORTCIO,
|
||||
(void *)PORTDIO,
|
||||
(void *)PORTEIO,
|
||||
};
|
||||
|
||||
void bfin_special_gpio_pm_hibernate_suspend(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(port_bases); ++i) {
|
||||
gpio_bank_saved[i].data = read_PORTIO(port_bases[i]);
|
||||
gpio_bank_saved[i].inen = read_PORTIO_INEN(port_bases[i]);
|
||||
gpio_bank_saved[i].dir = read_PORTIO_DIR(port_bases[i]);
|
||||
}
|
||||
}
|
||||
|
||||
void bfin_special_gpio_pm_hibernate_restore(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(port_bases); ++i) {
|
||||
write_PORTIO_INEN(port_bases[i], gpio_bank_saved[i].inen);
|
||||
write_PORTIO_SET(port_bases[i],
|
||||
gpio_bank_saved[i].data & gpio_bank_saved[i].dir);
|
||||
write_PORTIO_DIR(port_bases[i], gpio_bank_saved[i].dir);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
215
arch/blackfin/mach-bf538/include/mach/anomaly.h
Normal file
215
arch/blackfin/mach-bf538/include/mach/anomaly.h
Normal file
|
|
@ -0,0 +1,215 @@
|
|||
/*
|
||||
* DO NOT EDIT THIS FILE
|
||||
* This file is under version control at
|
||||
* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
|
||||
* and can be replaced with that version at any time
|
||||
* DO NOT EDIT THIS FILE
|
||||
*
|
||||
* Copyright 2004-2011 Analog Devices Inc.
|
||||
* Licensed under the Clear BSD license.
|
||||
*/
|
||||
|
||||
/* This file should be up to date with:
|
||||
* - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List
|
||||
* - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
#define _MACH_ANOMALY_H_
|
||||
|
||||
/* We do not support old silicon - sorry */
|
||||
#if __SILICON_REVISION__ < 4
|
||||
# error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3
|
||||
#endif
|
||||
|
||||
#if defined(__ADSPBF538__)
|
||||
# define ANOMALY_BF538 1
|
||||
#else
|
||||
# define ANOMALY_BF538 0
|
||||
#endif
|
||||
#if defined(__ADSPBF539__)
|
||||
# define ANOMALY_BF539 1
|
||||
#else
|
||||
# define ANOMALY_BF539 0
|
||||
#endif
|
||||
|
||||
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
|
||||
#define ANOMALY_05000074 (1)
|
||||
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
|
||||
#define ANOMALY_05000119 (1)
|
||||
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
|
||||
#define ANOMALY_05000122 (1)
|
||||
/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
|
||||
#define ANOMALY_05000166 (1)
|
||||
/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
|
||||
#define ANOMALY_05000179 (1)
|
||||
/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
|
||||
#define ANOMALY_05000180 (1)
|
||||
/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
|
||||
#define ANOMALY_05000193 (1)
|
||||
/* Current DMA Address Shows Wrong Value During Carry Fix */
|
||||
#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
|
||||
/* NMI Event at Boot Time Results in Unpredictable State */
|
||||
#define ANOMALY_05000219 (1)
|
||||
/* SPI Slave Boot Mode Modifies Registers from Reset Value */
|
||||
#define ANOMALY_05000229 (1)
|
||||
/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
|
||||
#define ANOMALY_05000233 (1)
|
||||
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
|
||||
#define ANOMALY_05000245 (1)
|
||||
/* Maximum External Clock Speed for Timers */
|
||||
#define ANOMALY_05000253 (1)
|
||||
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
|
||||
#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
|
||||
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
|
||||
#define ANOMALY_05000272 (ANOMALY_BF538)
|
||||
/* Writes to Synchronous SDRAM Memory May Be Lost */
|
||||
#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
|
||||
/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
|
||||
#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
|
||||
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
|
||||
#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
|
||||
/* False Hardware Error when ISR Context Is Not Restored */
|
||||
#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
|
||||
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
|
||||
#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
|
||||
/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
|
||||
#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
|
||||
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
|
||||
#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
|
||||
/* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */
|
||||
#define ANOMALY_05000291 (__SILICON_REVISION__ < 4)
|
||||
/* Hibernate Leakage Current Is Higher Than Specified */
|
||||
#define ANOMALY_05000293 (__SILICON_REVISION__ < 4)
|
||||
/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
|
||||
#define ANOMALY_05000294 (1)
|
||||
/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
|
||||
#define ANOMALY_05000301 (__SILICON_REVISION__ < 4)
|
||||
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
|
||||
#define ANOMALY_05000304 (__SILICON_REVISION__ < 4)
|
||||
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
|
||||
#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
|
||||
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
|
||||
#define ANOMALY_05000310 (1)
|
||||
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
|
||||
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
|
||||
#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
|
||||
/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
|
||||
#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
|
||||
/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */
|
||||
#define ANOMALY_05000317 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000318 */
|
||||
/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
|
||||
#define ANOMALY_05000318 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000317 */
|
||||
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
|
||||
#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
|
||||
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
|
||||
#define ANOMALY_05000357 (__SILICON_REVISION__ < 5)
|
||||
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
|
||||
#define ANOMALY_05000366 (1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
|
||||
/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
|
||||
#define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
|
||||
/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
|
||||
#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
|
||||
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
|
||||
#define ANOMALY_05000402 (__SILICON_REVISION__ == 3)
|
||||
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
|
||||
#define ANOMALY_05000403 (1)
|
||||
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
|
||||
#define ANOMALY_05000416 (1)
|
||||
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
|
||||
#define ANOMALY_05000425 (1)
|
||||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* Specific GPIO Pins May Change State when Entering Hibernate */
|
||||
#define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
/* False Hardware Error when RETI Points to Invalid Memory */
|
||||
#define ANOMALY_05000461 (1)
|
||||
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
|
||||
#define ANOMALY_05000462 (1)
|
||||
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
|
||||
#define ANOMALY_05000473 (1)
|
||||
/* Possible Lockup Condition when Modifying PLL from External Memory */
|
||||
#define ANOMALY_05000475 (1)
|
||||
/* TESTSET Instruction Cannot Be Interrupted */
|
||||
#define ANOMALY_05000477 (1)
|
||||
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
|
||||
#define ANOMALY_05000481 (1)
|
||||
/* PLL May Latch Incorrect Values Coming Out of Reset */
|
||||
#define ANOMALY_05000489 (1)
|
||||
/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
|
||||
#define ANOMALY_05000491 (1)
|
||||
/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
|
||||
#define ANOMALY_05000494 (1)
|
||||
/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
|
||||
#define ANOMALY_05000501 (1)
|
||||
|
||||
/*
|
||||
* These anomalies have been "phased" out of analog.com anomaly sheets and are
|
||||
* here to show running on older silicon just isn't feasible.
|
||||
*/
|
||||
|
||||
/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
|
||||
#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
|
||||
/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
|
||||
#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000099 (0)
|
||||
#define ANOMALY_05000120 (0)
|
||||
#define ANOMALY_05000125 (0)
|
||||
#define ANOMALY_05000149 (0)
|
||||
#define ANOMALY_05000158 (0)
|
||||
#define ANOMALY_05000171 (0)
|
||||
#define ANOMALY_05000182 (0)
|
||||
#define ANOMALY_05000189 (0)
|
||||
#define ANOMALY_05000198 (0)
|
||||
#define ANOMALY_05000202 (0)
|
||||
#define ANOMALY_05000215 (0)
|
||||
#define ANOMALY_05000220 (0)
|
||||
#define ANOMALY_05000227 (0)
|
||||
#define ANOMALY_05000230 (0)
|
||||
#define ANOMALY_05000231 (0)
|
||||
#define ANOMALY_05000234 (0)
|
||||
#define ANOMALY_05000242 (0)
|
||||
#define ANOMALY_05000248 (0)
|
||||
#define ANOMALY_05000250 (0)
|
||||
#define ANOMALY_05000254 (0)
|
||||
#define ANOMALY_05000257 (0)
|
||||
#define ANOMALY_05000263 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000274 (0)
|
||||
#define ANOMALY_05000287 (0)
|
||||
#define ANOMALY_05000305 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
#define ANOMALY_05000362 (1)
|
||||
#define ANOMALY_05000363 (0)
|
||||
#define ANOMALY_05000364 (0)
|
||||
#define ANOMALY_05000380 (0)
|
||||
#define ANOMALY_05000383 (0)
|
||||
#define ANOMALY_05000386 (1)
|
||||
#define ANOMALY_05000389 (0)
|
||||
#define ANOMALY_05000400 (0)
|
||||
#define ANOMALY_05000412 (0)
|
||||
#define ANOMALY_05000430 (0)
|
||||
#define ANOMALY_05000432 (0)
|
||||
#define ANOMALY_05000435 (0)
|
||||
#define ANOMALY_05000440 (0)
|
||||
#define ANOMALY_05000447 (0)
|
||||
#define ANOMALY_05000448 (0)
|
||||
#define ANOMALY_05000456 (0)
|
||||
#define ANOMALY_05000450 (0)
|
||||
#define ANOMALY_05000465 (0)
|
||||
#define ANOMALY_05000467 (0)
|
||||
#define ANOMALY_05000474 (0)
|
||||
#define ANOMALY_05000480 (0)
|
||||
#define ANOMALY_05000485 (0)
|
||||
#define ANOMALY_16000030 (0)
|
||||
|
||||
#endif
|
||||
103
arch/blackfin/mach-bf538/include/mach/bf538.h
Normal file
103
arch/blackfin/mach-bf538/include/mach/bf538.h
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF538
|
||||
*
|
||||
* Copyright 2008 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_BF538_H__
|
||||
#define __MACH_BF538_H__
|
||||
|
||||
#define OFFSET_(x) ((x) & 0x0000FFFF)
|
||||
|
||||
/*some misc defines*/
|
||||
#define IMASK_IVG15 0x8000
|
||||
#define IMASK_IVG14 0x4000
|
||||
#define IMASK_IVG13 0x2000
|
||||
#define IMASK_IVG12 0x1000
|
||||
|
||||
#define IMASK_IVG11 0x0800
|
||||
#define IMASK_IVG10 0x0400
|
||||
#define IMASK_IVG9 0x0200
|
||||
#define IMASK_IVG8 0x0100
|
||||
|
||||
#define IMASK_IVG7 0x0080
|
||||
#define IMASK_IVGTMR 0x0040
|
||||
#define IMASK_IVGHW 0x0020
|
||||
|
||||
/***************************/
|
||||
|
||||
#define BFIN_DSUBBANKS 4
|
||||
#define BFIN_DWAYS 2
|
||||
#define BFIN_DLINES 64
|
||||
#define BFIN_ISUBBANKS 4
|
||||
#define BFIN_IWAYS 4
|
||||
#define BFIN_ILINES 32
|
||||
|
||||
#define WAY0_L 0x1
|
||||
#define WAY1_L 0x2
|
||||
#define WAY01_L 0x3
|
||||
#define WAY2_L 0x4
|
||||
#define WAY02_L 0x5
|
||||
#define WAY12_L 0x6
|
||||
#define WAY012_L 0x7
|
||||
|
||||
#define WAY3_L 0x8
|
||||
#define WAY03_L 0x9
|
||||
#define WAY13_L 0xA
|
||||
#define WAY013_L 0xB
|
||||
|
||||
#define WAY32_L 0xC
|
||||
#define WAY320_L 0xD
|
||||
#define WAY321_L 0xE
|
||||
#define WAYALL_L 0xF
|
||||
|
||||
#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
|
||||
|
||||
/********************************* EBIU Settings ************************************/
|
||||
#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
|
||||
#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
|
||||
|
||||
#ifdef CONFIG_C_AMBEN_ALL
|
||||
#define V_AMBEN AMBEN_ALL
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMBEN
|
||||
#define V_AMBEN 0x0
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMBEN_B0
|
||||
#define V_AMBEN AMBEN_B0
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMBEN_B0_B1
|
||||
#define V_AMBEN AMBEN_B0_B1
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMBEN_B0_B1_B2
|
||||
#define V_AMBEN AMBEN_B0_B1_B2
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMCKEN
|
||||
#define V_AMCKEN AMCKEN
|
||||
#else
|
||||
#define V_AMCKEN 0x0
|
||||
#endif
|
||||
#ifdef CONFIG_C_CDPRIO
|
||||
#define V_CDPRIO 0x100
|
||||
#else
|
||||
#define V_CDPRIO 0x0
|
||||
#endif
|
||||
|
||||
#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
|
||||
|
||||
#ifdef CONFIG_BF538
|
||||
#define CPU "BF538"
|
||||
#define CPUID 0x27C4
|
||||
#endif
|
||||
#ifdef CONFIG_BF539
|
||||
#define CPU "BF539"
|
||||
#define CPUID 0x27C4 /* FXIME:? */
|
||||
#endif
|
||||
|
||||
#ifndef CPU
|
||||
#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
|
||||
#endif
|
||||
|
||||
#endif /* __MACH_BF538_H__ */
|
||||
14
arch/blackfin/mach-bf538/include/mach/bfin_serial.h
Normal file
14
arch/blackfin/mach-bf538/include/mach/bfin_serial.h
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* mach/bfin_serial.h - Blackfin UART/Serial definitions
|
||||
*
|
||||
* Copyright 2006-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_MACH_SERIAL_H__
|
||||
#define __BFIN_MACH_SERIAL_H__
|
||||
|
||||
#define BFIN_UART_NR_PORTS 3
|
||||
|
||||
#endif
|
||||
33
arch/blackfin/mach-bf538/include/mach/blackfin.h
Normal file
33
arch/blackfin/mach-bf538/include/mach/blackfin.h
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Copyright 2008-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_BLACKFIN_H_
|
||||
#define _MACH_BLACKFIN_H_
|
||||
|
||||
#define BF538_FAMILY
|
||||
|
||||
#include "bf538.h"
|
||||
#include "anomaly.h"
|
||||
|
||||
#include <asm/def_LPBlackfin.h>
|
||||
#ifdef CONFIG_BF538
|
||||
# include "defBF538.h"
|
||||
#endif
|
||||
#ifdef CONFIG_BF539
|
||||
# include "defBF539.h"
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <asm/cdef_LPBlackfin.h>
|
||||
# ifdef CONFIG_BF538
|
||||
# include "cdefBF538.h"
|
||||
# endif
|
||||
# ifdef CONFIG_BF539
|
||||
# include "cdefBF539.h"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
1960
arch/blackfin/mach-bf538/include/mach/cdefBF538.h
Normal file
1960
arch/blackfin/mach-bf538/include/mach/cdefBF538.h
Normal file
File diff suppressed because it is too large
Load diff
240
arch/blackfin/mach-bf538/include/mach/cdefBF539.h
Normal file
240
arch/blackfin/mach-bf538/include/mach/cdefBF539.h
Normal file
|
|
@ -0,0 +1,240 @@
|
|||
/*
|
||||
* Copyright 2008-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _CDEF_BF539_H
|
||||
#define _CDEF_BF539_H
|
||||
|
||||
/* Include MMRs Common to BF538 */
|
||||
#include "cdefBF538.h"
|
||||
|
||||
#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG)
|
||||
#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
|
||||
#define bfin_read_MXVR_PLL_CTL_0() bfin_read32(MXVR_PLL_CTL_0)
|
||||
#define bfin_write_MXVR_PLL_CTL_0(val) bfin_write32(MXVR_PLL_CTL_0, val)
|
||||
#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0)
|
||||
#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
|
||||
#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1)
|
||||
#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
|
||||
#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0)
|
||||
#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
|
||||
#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1)
|
||||
#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
|
||||
#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0)
|
||||
#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
|
||||
#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1)
|
||||
#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
|
||||
#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION)
|
||||
#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
|
||||
#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION)
|
||||
#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
|
||||
#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY)
|
||||
#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
|
||||
#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY)
|
||||
#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
|
||||
#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)
|
||||
#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
|
||||
#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR)
|
||||
#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
|
||||
#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)
|
||||
#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
|
||||
#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0)
|
||||
#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
|
||||
#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1)
|
||||
#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
|
||||
#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2)
|
||||
#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val)
|
||||
#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3)
|
||||
#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val)
|
||||
#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4)
|
||||
#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val)
|
||||
#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5)
|
||||
#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val)
|
||||
#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6)
|
||||
#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val)
|
||||
#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7)
|
||||
#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val)
|
||||
#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8)
|
||||
#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val)
|
||||
#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9)
|
||||
#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val)
|
||||
#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10)
|
||||
#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val)
|
||||
#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11)
|
||||
#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val)
|
||||
#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12)
|
||||
#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val)
|
||||
#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13)
|
||||
#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val)
|
||||
#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14)
|
||||
#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val)
|
||||
#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0)
|
||||
#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
|
||||
#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1)
|
||||
#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
|
||||
#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2)
|
||||
#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
|
||||
#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3)
|
||||
#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
|
||||
#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4)
|
||||
#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
|
||||
#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5)
|
||||
#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
|
||||
#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6)
|
||||
#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
|
||||
#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7)
|
||||
#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
|
||||
#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG)
|
||||
#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
|
||||
#define bfin_read_MXVR_DMA0_START_ADDR() bfin_readPTR(MXVR_DMA0_START_ADDR)
|
||||
#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val)
|
||||
#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT)
|
||||
#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_readPTR(MXVR_DMA0_CURR_ADDR)
|
||||
#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val)
|
||||
#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
|
||||
#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG)
|
||||
#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
|
||||
#define bfin_read_MXVR_DMA1_START_ADDR() bfin_readPTR(MXVR_DMA1_START_ADDR)
|
||||
#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val)
|
||||
#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT)
|
||||
#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_readPTR(MXVR_DMA1_CURR_ADDR)
|
||||
#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val)
|
||||
#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
|
||||
#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG)
|
||||
#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
|
||||
#define bfin_read_MXVR_DMA2_START_ADDR() bfin_readPTR(MXVR_DMA2_START_ADDR)
|
||||
#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val)
|
||||
#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT)
|
||||
#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_readPTR(MXVR_DMA2_CURR_ADDR)
|
||||
#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val)
|
||||
#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
|
||||
#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG)
|
||||
#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
|
||||
#define bfin_read_MXVR_DMA3_START_ADDR() bfin_readPTR(MXVR_DMA3_START_ADDR)
|
||||
#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val)
|
||||
#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT)
|
||||
#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_readPTR(MXVR_DMA3_CURR_ADDR)
|
||||
#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val)
|
||||
#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
|
||||
#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG)
|
||||
#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
|
||||
#define bfin_read_MXVR_DMA4_START_ADDR() bfin_readPTR(MXVR_DMA4_START_ADDR)
|
||||
#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val)
|
||||
#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT)
|
||||
#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_readPTR(MXVR_DMA4_CURR_ADDR)
|
||||
#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val)
|
||||
#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
|
||||
#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG)
|
||||
#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
|
||||
#define bfin_read_MXVR_DMA5_START_ADDR() bfin_readPTR(MXVR_DMA5_START_ADDR)
|
||||
#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val)
|
||||
#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT)
|
||||
#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_readPTR(MXVR_DMA5_CURR_ADDR)
|
||||
#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val)
|
||||
#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
|
||||
#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG)
|
||||
#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
|
||||
#define bfin_read_MXVR_DMA6_START_ADDR() bfin_readPTR(MXVR_DMA6_START_ADDR)
|
||||
#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val)
|
||||
#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT)
|
||||
#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_readPTR(MXVR_DMA6_CURR_ADDR)
|
||||
#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val)
|
||||
#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
|
||||
#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG)
|
||||
#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
|
||||
#define bfin_read_MXVR_DMA7_START_ADDR() bfin_readPTR(MXVR_DMA7_START_ADDR)
|
||||
#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val)
|
||||
#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT)
|
||||
#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_readPTR(MXVR_DMA7_CURR_ADDR)
|
||||
#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val)
|
||||
#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
|
||||
#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
|
||||
#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL)
|
||||
#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
|
||||
#define bfin_read_MXVR_APRB_START_ADDR() bfin_readPTR(MXVR_APRB_START_ADDR)
|
||||
#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val)
|
||||
#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_readPTR(MXVR_APRB_CURR_ADDR)
|
||||
#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val)
|
||||
#define bfin_read_MXVR_APTB_START_ADDR() bfin_readPTR(MXVR_APTB_START_ADDR)
|
||||
#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val)
|
||||
#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_readPTR(MXVR_APTB_CURR_ADDR)
|
||||
#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val)
|
||||
#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL)
|
||||
#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
|
||||
#define bfin_read_MXVR_CMRB_START_ADDR() bfin_readPTR(MXVR_CMRB_START_ADDR)
|
||||
#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val)
|
||||
#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_readPTR(MXVR_CMRB_CURR_ADDR)
|
||||
#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val)
|
||||
#define bfin_read_MXVR_CMTB_START_ADDR() bfin_readPTR(MXVR_CMTB_START_ADDR)
|
||||
#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val)
|
||||
#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_readPTR(MXVR_CMTB_CURR_ADDR)
|
||||
#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val)
|
||||
#define bfin_read_MXVR_RRDB_START_ADDR() bfin_readPTR(MXVR_RRDB_START_ADDR)
|
||||
#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val)
|
||||
#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_readPTR(MXVR_RRDB_CURR_ADDR)
|
||||
#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val)
|
||||
#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0)
|
||||
#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
|
||||
#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0)
|
||||
#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val)
|
||||
#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1)
|
||||
#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
|
||||
#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1)
|
||||
#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val)
|
||||
#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0)
|
||||
#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
|
||||
#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1)
|
||||
#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
|
||||
#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0)
|
||||
#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
|
||||
#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1)
|
||||
#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
|
||||
#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2)
|
||||
#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
|
||||
#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3)
|
||||
#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
|
||||
#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4)
|
||||
#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
|
||||
#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5)
|
||||
#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
|
||||
#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6)
|
||||
#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
|
||||
#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7)
|
||||
#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
|
||||
#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8)
|
||||
#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
|
||||
#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9)
|
||||
#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
|
||||
#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10)
|
||||
#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
|
||||
#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11)
|
||||
#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
|
||||
#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12)
|
||||
#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
|
||||
#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13)
|
||||
#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
|
||||
#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14)
|
||||
#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
|
||||
#define bfin_read_MXVR_PLL_CTL_1() bfin_read32(MXVR_PLL_CTL_1)
|
||||
#define bfin_write_MXVR_PLL_CTL_1(val) bfin_write32(MXVR_PLL_CTL_1, val)
|
||||
#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT)
|
||||
#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
|
||||
|
||||
#endif /* _CDEF_BF539_H */
|
||||
1749
arch/blackfin/mach-bf538/include/mach/defBF538.h
Normal file
1749
arch/blackfin/mach-bf538/include/mach/defBF538.h
Normal file
File diff suppressed because it is too large
Load diff
152
arch/blackfin/mach-bf538/include/mach/defBF539.h
Normal file
152
arch/blackfin/mach-bf538/include/mach/defBF539.h
Normal file
|
|
@ -0,0 +1,152 @@
|
|||
/*
|
||||
* Copyright 2008-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the Clear BSD license or the GPL-2 (or later)
|
||||
*/
|
||||
|
||||
#ifndef _DEF_BF539_H
|
||||
#define _DEF_BF539_H
|
||||
|
||||
#include "defBF538.h"
|
||||
|
||||
/* Media Transceiver (MXVR) (0xFFC02700 - 0xFFC028FF) */
|
||||
|
||||
#define MXVR_CONFIG 0xFFC02700 /* MXVR Configuration Register */
|
||||
#define MXVR_PLL_CTL_0 0xFFC02704 /* MXVR Phase Lock Loop Control Register 0 */
|
||||
|
||||
#define MXVR_STATE_0 0xFFC02708 /* MXVR State Register 0 */
|
||||
#define MXVR_STATE_1 0xFFC0270C /* MXVR State Register 1 */
|
||||
|
||||
#define MXVR_INT_STAT_0 0xFFC02710 /* MXVR Interrupt Status Register 0 */
|
||||
#define MXVR_INT_STAT_1 0xFFC02714 /* MXVR Interrupt Status Register 1 */
|
||||
|
||||
#define MXVR_INT_EN_0 0xFFC02718 /* MXVR Interrupt Enable Register 0 */
|
||||
#define MXVR_INT_EN_1 0xFFC0271C /* MXVR Interrupt Enable Register 1 */
|
||||
|
||||
#define MXVR_POSITION 0xFFC02720 /* MXVR Node Position Register */
|
||||
#define MXVR_MAX_POSITION 0xFFC02724 /* MXVR Maximum Node Position Register */
|
||||
|
||||
#define MXVR_DELAY 0xFFC02728 /* MXVR Node Frame Delay Register */
|
||||
#define MXVR_MAX_DELAY 0xFFC0272C /* MXVR Maximum Node Frame Delay Register */
|
||||
|
||||
#define MXVR_LADDR 0xFFC02730 /* MXVR Logical Address Register */
|
||||
#define MXVR_GADDR 0xFFC02734 /* MXVR Group Address Register */
|
||||
#define MXVR_AADDR 0xFFC02738 /* MXVR Alternate Address Register */
|
||||
|
||||
#define MXVR_ALLOC_0 0xFFC0273C /* MXVR Allocation Table Register 0 */
|
||||
#define MXVR_ALLOC_1 0xFFC02740 /* MXVR Allocation Table Register 1 */
|
||||
#define MXVR_ALLOC_2 0xFFC02744 /* MXVR Allocation Table Register 2 */
|
||||
#define MXVR_ALLOC_3 0xFFC02748 /* MXVR Allocation Table Register 3 */
|
||||
#define MXVR_ALLOC_4 0xFFC0274C /* MXVR Allocation Table Register 4 */
|
||||
#define MXVR_ALLOC_5 0xFFC02750 /* MXVR Allocation Table Register 5 */
|
||||
#define MXVR_ALLOC_6 0xFFC02754 /* MXVR Allocation Table Register 6 */
|
||||
#define MXVR_ALLOC_7 0xFFC02758 /* MXVR Allocation Table Register 7 */
|
||||
#define MXVR_ALLOC_8 0xFFC0275C /* MXVR Allocation Table Register 8 */
|
||||
#define MXVR_ALLOC_9 0xFFC02760 /* MXVR Allocation Table Register 9 */
|
||||
#define MXVR_ALLOC_10 0xFFC02764 /* MXVR Allocation Table Register 10 */
|
||||
#define MXVR_ALLOC_11 0xFFC02768 /* MXVR Allocation Table Register 11 */
|
||||
#define MXVR_ALLOC_12 0xFFC0276C /* MXVR Allocation Table Register 12 */
|
||||
#define MXVR_ALLOC_13 0xFFC02770 /* MXVR Allocation Table Register 13 */
|
||||
#define MXVR_ALLOC_14 0xFFC02774 /* MXVR Allocation Table Register 14 */
|
||||
|
||||
#define MXVR_SYNC_LCHAN_0 0xFFC02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
|
||||
#define MXVR_SYNC_LCHAN_1 0xFFC0277C /* MXVR Sync Data Logical Channel Assign Register 1 */
|
||||
#define MXVR_SYNC_LCHAN_2 0xFFC02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
|
||||
#define MXVR_SYNC_LCHAN_3 0xFFC02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
|
||||
#define MXVR_SYNC_LCHAN_4 0xFFC02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
|
||||
#define MXVR_SYNC_LCHAN_5 0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */
|
||||
#define MXVR_SYNC_LCHAN_6 0xFFC02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
|
||||
#define MXVR_SYNC_LCHAN_7 0xFFC02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
|
||||
|
||||
#define MXVR_DMA0_CONFIG 0xFFC02798 /* MXVR Sync Data DMA0 Config Register */
|
||||
#define MXVR_DMA0_START_ADDR 0xFFC0279C /* MXVR Sync Data DMA0 Start Address Register */
|
||||
#define MXVR_DMA0_COUNT 0xFFC027A0 /* MXVR Sync Data DMA0 Loop Count Register */
|
||||
#define MXVR_DMA0_CURR_ADDR 0xFFC027A4 /* MXVR Sync Data DMA0 Current Address Register */
|
||||
#define MXVR_DMA0_CURR_COUNT 0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count Register */
|
||||
|
||||
#define MXVR_DMA1_CONFIG 0xFFC027AC /* MXVR Sync Data DMA1 Config Register */
|
||||
#define MXVR_DMA1_START_ADDR 0xFFC027B0 /* MXVR Sync Data DMA1 Start Address Register */
|
||||
#define MXVR_DMA1_COUNT 0xFFC027B4 /* MXVR Sync Data DMA1 Loop Count Register */
|
||||
#define MXVR_DMA1_CURR_ADDR 0xFFC027B8 /* MXVR Sync Data DMA1 Current Address Register */
|
||||
#define MXVR_DMA1_CURR_COUNT 0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count Register */
|
||||
|
||||
#define MXVR_DMA2_CONFIG 0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */
|
||||
#define MXVR_DMA2_START_ADDR 0xFFC027C4 /* MXVR Sync Data DMA2 Start Address Register */
|
||||
#define MXVR_DMA2_COUNT 0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */
|
||||
#define MXVR_DMA2_CURR_ADDR 0xFFC027CC /* MXVR Sync Data DMA2 Current Address Register */
|
||||
#define MXVR_DMA2_CURR_COUNT 0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count Register */
|
||||
|
||||
#define MXVR_DMA3_CONFIG 0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */
|
||||
#define MXVR_DMA3_START_ADDR 0xFFC027D8 /* MXVR Sync Data DMA3 Start Address Register */
|
||||
#define MXVR_DMA3_COUNT 0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */
|
||||
#define MXVR_DMA3_CURR_ADDR 0xFFC027E0 /* MXVR Sync Data DMA3 Current Address Register */
|
||||
#define MXVR_DMA3_CURR_COUNT 0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count Register */
|
||||
|
||||
#define MXVR_DMA4_CONFIG 0xFFC027E8 /* MXVR Sync Data DMA4 Config Register */
|
||||
#define MXVR_DMA4_START_ADDR 0xFFC027EC /* MXVR Sync Data DMA4 Start Address Register */
|
||||
#define MXVR_DMA4_COUNT 0xFFC027F0 /* MXVR Sync Data DMA4 Loop Count Register */
|
||||
#define MXVR_DMA4_CURR_ADDR 0xFFC027F4 /* MXVR Sync Data DMA4 Current Address Register */
|
||||
#define MXVR_DMA4_CURR_COUNT 0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count Register */
|
||||
|
||||
#define MXVR_DMA5_CONFIG 0xFFC027FC /* MXVR Sync Data DMA5 Config Register */
|
||||
#define MXVR_DMA5_START_ADDR 0xFFC02800 /* MXVR Sync Data DMA5 Start Address Register */
|
||||
#define MXVR_DMA5_COUNT 0xFFC02804 /* MXVR Sync Data DMA5 Loop Count Register */
|
||||
#define MXVR_DMA5_CURR_ADDR 0xFFC02808 /* MXVR Sync Data DMA5 Current Address Register */
|
||||
#define MXVR_DMA5_CURR_COUNT 0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count Register */
|
||||
|
||||
#define MXVR_DMA6_CONFIG 0xFFC02810 /* MXVR Sync Data DMA6 Config Register */
|
||||
#define MXVR_DMA6_START_ADDR 0xFFC02814 /* MXVR Sync Data DMA6 Start Address Register */
|
||||
#define MXVR_DMA6_COUNT 0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */
|
||||
#define MXVR_DMA6_CURR_ADDR 0xFFC0281C /* MXVR Sync Data DMA6 Current Address Register */
|
||||
#define MXVR_DMA6_CURR_COUNT 0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count Register */
|
||||
|
||||
#define MXVR_DMA7_CONFIG 0xFFC02824 /* MXVR Sync Data DMA7 Config Register */
|
||||
#define MXVR_DMA7_START_ADDR 0xFFC02828 /* MXVR Sync Data DMA7 Start Address Register */
|
||||
#define MXVR_DMA7_COUNT 0xFFC0282C /* MXVR Sync Data DMA7 Loop Count Register */
|
||||
#define MXVR_DMA7_CURR_ADDR 0xFFC02830 /* MXVR Sync Data DMA7 Current Address Register */
|
||||
#define MXVR_DMA7_CURR_COUNT 0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count Register */
|
||||
|
||||
#define MXVR_AP_CTL 0xFFC02838 /* MXVR Async Packet Control Register */
|
||||
#define MXVR_APRB_START_ADDR 0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */
|
||||
#define MXVR_APRB_CURR_ADDR 0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */
|
||||
#define MXVR_APTB_START_ADDR 0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */
|
||||
#define MXVR_APTB_CURR_ADDR 0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */
|
||||
|
||||
#define MXVR_CM_CTL 0xFFC0284C /* MXVR Control Message Control Register */
|
||||
#define MXVR_CMRB_START_ADDR 0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */
|
||||
#define MXVR_CMRB_CURR_ADDR 0xFFC02854 /* MXVR Control Message RX Buffer Current Address */
|
||||
#define MXVR_CMTB_START_ADDR 0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */
|
||||
#define MXVR_CMTB_CURR_ADDR 0xFFC0285C /* MXVR Control Message TX Buffer Current Address */
|
||||
|
||||
#define MXVR_RRDB_START_ADDR 0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */
|
||||
#define MXVR_RRDB_CURR_ADDR 0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */
|
||||
|
||||
#define MXVR_PAT_DATA_0 0xFFC02868 /* MXVR Pattern Data Register 0 */
|
||||
#define MXVR_PAT_EN_0 0xFFC0286C /* MXVR Pattern Enable Register 0 */
|
||||
#define MXVR_PAT_DATA_1 0xFFC02870 /* MXVR Pattern Data Register 1 */
|
||||
#define MXVR_PAT_EN_1 0xFFC02874 /* MXVR Pattern Enable Register 1 */
|
||||
|
||||
#define MXVR_FRAME_CNT_0 0xFFC02878 /* MXVR Frame Counter 0 */
|
||||
#define MXVR_FRAME_CNT_1 0xFFC0287C /* MXVR Frame Counter 1 */
|
||||
|
||||
#define MXVR_ROUTING_0 0xFFC02880 /* MXVR Routing Table Register 0 */
|
||||
#define MXVR_ROUTING_1 0xFFC02884 /* MXVR Routing Table Register 1 */
|
||||
#define MXVR_ROUTING_2 0xFFC02888 /* MXVR Routing Table Register 2 */
|
||||
#define MXVR_ROUTING_3 0xFFC0288C /* MXVR Routing Table Register 3 */
|
||||
#define MXVR_ROUTING_4 0xFFC02890 /* MXVR Routing Table Register 4 */
|
||||
#define MXVR_ROUTING_5 0xFFC02894 /* MXVR Routing Table Register 5 */
|
||||
#define MXVR_ROUTING_6 0xFFC02898 /* MXVR Routing Table Register 6 */
|
||||
#define MXVR_ROUTING_7 0xFFC0289C /* MXVR Routing Table Register 7 */
|
||||
#define MXVR_ROUTING_8 0xFFC028A0 /* MXVR Routing Table Register 8 */
|
||||
#define MXVR_ROUTING_9 0xFFC028A4 /* MXVR Routing Table Register 9 */
|
||||
#define MXVR_ROUTING_10 0xFFC028A8 /* MXVR Routing Table Register 10 */
|
||||
#define MXVR_ROUTING_11 0xFFC028AC /* MXVR Routing Table Register 11 */
|
||||
#define MXVR_ROUTING_12 0xFFC028B0 /* MXVR Routing Table Register 12 */
|
||||
#define MXVR_ROUTING_13 0xFFC028B4 /* MXVR Routing Table Register 13 */
|
||||
#define MXVR_ROUTING_14 0xFFC028B8 /* MXVR Routing Table Register 14 */
|
||||
|
||||
#define MXVR_PLL_CTL_1 0xFFC028BC /* MXVR Phase Lock Loop Control Register 1 */
|
||||
#define MXVR_BLOCK_CNT 0xFFC028C0 /* MXVR Block Counter */
|
||||
#define MXVR_PLL_CTL_2 0xFFC028C4 /* MXVR Phase Lock Loop Control Register 2 */
|
||||
|
||||
#endif /* _DEF_BF539_H */
|
||||
41
arch/blackfin/mach-bf538/include/mach/dma.h
Normal file
41
arch/blackfin/mach-bf538/include/mach/dma.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/* mach/dma.h - arch-specific DMA defines
|
||||
*
|
||||
* Copyright 2004-2008 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_DMA_H_
|
||||
#define _MACH_DMA_H_
|
||||
|
||||
#define CH_PPI 0
|
||||
#define CH_SPORT0_RX 1
|
||||
#define CH_SPORT0_TX 2
|
||||
#define CH_SPORT1_RX 3
|
||||
#define CH_SPORT1_TX 4
|
||||
#define CH_SPI0 5
|
||||
#define CH_UART0_RX 6
|
||||
#define CH_UART0_TX 7
|
||||
#define CH_SPORT2_RX 8
|
||||
#define CH_SPORT2_TX 9
|
||||
#define CH_SPORT3_RX 10
|
||||
#define CH_SPORT3_TX 11
|
||||
#define CH_SPI1 14
|
||||
#define CH_SPI2 15
|
||||
#define CH_UART1_RX 16
|
||||
#define CH_UART1_TX 17
|
||||
#define CH_UART2_RX 18
|
||||
#define CH_UART2_TX 19
|
||||
|
||||
#define CH_MEM_STREAM0_DEST 20
|
||||
#define CH_MEM_STREAM0_SRC 21
|
||||
#define CH_MEM_STREAM1_DEST 22
|
||||
#define CH_MEM_STREAM1_SRC 23
|
||||
#define CH_MEM_STREAM2_DEST 24
|
||||
#define CH_MEM_STREAM2_SRC 25
|
||||
#define CH_MEM_STREAM3_DEST 26
|
||||
#define CH_MEM_STREAM3_SRC 27
|
||||
|
||||
#define MAX_DMA_CHANNELS 28
|
||||
|
||||
#endif
|
||||
81
arch/blackfin/mach-bf538/include/mach/gpio.h
Normal file
81
arch/blackfin/mach-bf538/include/mach/gpio.h
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACH_GPIO_H_
|
||||
#define _MACH_GPIO_H_
|
||||
|
||||
#define MAX_BLACKFIN_GPIOS 16
|
||||
#ifdef CONFIG_GPIOLIB
|
||||
/* We only use the special logic with GPIOLIB devices */
|
||||
#define BFIN_SPECIAL_GPIO_BANKS 3
|
||||
#endif
|
||||
|
||||
#define GPIO_PF0 0 /* PF */
|
||||
#define GPIO_PF1 1
|
||||
#define GPIO_PF2 2
|
||||
#define GPIO_PF3 3
|
||||
#define GPIO_PF4 4
|
||||
#define GPIO_PF5 5
|
||||
#define GPIO_PF6 6
|
||||
#define GPIO_PF7 7
|
||||
#define GPIO_PF8 8
|
||||
#define GPIO_PF9 9
|
||||
#define GPIO_PF10 10
|
||||
#define GPIO_PF11 11
|
||||
#define GPIO_PF12 12
|
||||
#define GPIO_PF13 13
|
||||
#define GPIO_PF14 14
|
||||
#define GPIO_PF15 15
|
||||
#define GPIO_PC0 16 /* PC */
|
||||
#define GPIO_PC1 17
|
||||
#define GPIO_PC4 20
|
||||
#define GPIO_PC5 21
|
||||
#define GPIO_PC6 22
|
||||
#define GPIO_PC7 23
|
||||
#define GPIO_PC8 24
|
||||
#define GPIO_PC9 25
|
||||
#define GPIO_PD0 32 /* PD */
|
||||
#define GPIO_PD1 33
|
||||
#define GPIO_PD2 34
|
||||
#define GPIO_PD3 35
|
||||
#define GPIO_PD4 36
|
||||
#define GPIO_PD5 37
|
||||
#define GPIO_PD6 38
|
||||
#define GPIO_PD7 39
|
||||
#define GPIO_PD8 40
|
||||
#define GPIO_PD9 41
|
||||
#define GPIO_PD10 42
|
||||
#define GPIO_PD11 43
|
||||
#define GPIO_PD12 44
|
||||
#define GPIO_PD13 45
|
||||
#define GPIO_PE0 48 /* PE */
|
||||
#define GPIO_PE1 49
|
||||
#define GPIO_PE2 50
|
||||
#define GPIO_PE3 51
|
||||
#define GPIO_PE4 52
|
||||
#define GPIO_PE5 53
|
||||
#define GPIO_PE6 54
|
||||
#define GPIO_PE7 55
|
||||
#define GPIO_PE8 56
|
||||
#define GPIO_PE9 57
|
||||
#define GPIO_PE10 58
|
||||
#define GPIO_PE11 59
|
||||
#define GPIO_PE12 60
|
||||
#define GPIO_PE13 61
|
||||
#define GPIO_PE14 62
|
||||
#define GPIO_PE15 63
|
||||
|
||||
#define PORT_F GPIO_PF0
|
||||
#define PORT_C GPIO_PC0
|
||||
#define PORT_D GPIO_PD0
|
||||
#define PORT_E GPIO_PE0
|
||||
|
||||
#include <mach-common/ports-c.h>
|
||||
#include <mach-common/ports-d.h>
|
||||
#include <mach-common/ports-e.h>
|
||||
#include <mach-common/ports-f.h>
|
||||
|
||||
#endif /* _MACH_GPIO_H_ */
|
||||
148
arch/blackfin/mach-bf538/include/mach/irq.h
Normal file
148
arch/blackfin/mach-bf538/include/mach/irq.h
Normal file
|
|
@ -0,0 +1,148 @@
|
|||
/*
|
||||
* Copyright 2008 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _BF538_IRQ_H_
|
||||
#define _BF538_IRQ_H_
|
||||
|
||||
#include <mach-common/irq.h>
|
||||
|
||||
#define NR_PERI_INTS (2 * 32)
|
||||
|
||||
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
|
||||
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
|
||||
#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */
|
||||
#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Status */
|
||||
#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Status */
|
||||
#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status */
|
||||
#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status */
|
||||
#define IRQ_RTC BFIN_IRQ(7) /* RTC */
|
||||
#define IRQ_PPI BFIN_IRQ(8) /* DMA Channel 0 (PPI) */
|
||||
#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA 1 Channel (SPORT0 RX) */
|
||||
#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA 2 Channel (SPORT0 TX) */
|
||||
#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA 3 Channel (SPORT1 RX) */
|
||||
#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA 4 Channel (SPORT1 TX) */
|
||||
#define IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */
|
||||
#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */
|
||||
#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */
|
||||
#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */
|
||||
#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */
|
||||
#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */
|
||||
#define IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */
|
||||
#define IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */
|
||||
#define IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */
|
||||
#define IRQ_MEM0_DMA1 BFIN_IRQ(22) /* MDMA0 Stream 1 */
|
||||
#define IRQ_WATCH BFIN_IRQ(23) /* Software Watchdog Timer */
|
||||
#define IRQ_DMA1_ERROR BFIN_IRQ(24) /* DMA Error 1 (generic) */
|
||||
#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Status */
|
||||
#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Status */
|
||||
#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status */
|
||||
#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status */
|
||||
#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status */
|
||||
#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status */
|
||||
#define IRQ_CAN_ERROR BFIN_IRQ(32) /* CAN Status (Error) Interrupt */
|
||||
#define IRQ_SPORT2_RX BFIN_IRQ(33) /* DMA 8 Channel (SPORT2 RX) */
|
||||
#define IRQ_SPORT2_TX BFIN_IRQ(34) /* DMA 9 Channel (SPORT2 TX) */
|
||||
#define IRQ_SPORT3_RX BFIN_IRQ(35) /* DMA 10 Channel (SPORT3 RX) */
|
||||
#define IRQ_SPORT3_TX BFIN_IRQ(36) /* DMA 11 Channel (SPORT3 TX) */
|
||||
#define IRQ_SPI1 BFIN_IRQ(39) /* DMA 14 Channel (SPI1) */
|
||||
#define IRQ_SPI2 BFIN_IRQ(40) /* DMA 15 Channel (SPI2) */
|
||||
#define IRQ_UART1_RX BFIN_IRQ(41) /* DMA 16 Channel (UART1 RX) */
|
||||
#define IRQ_UART1_TX BFIN_IRQ(42) /* DMA 17 Channel (UART1 TX) */
|
||||
#define IRQ_UART2_RX BFIN_IRQ(43) /* DMA 18 Channel (UART2 RX) */
|
||||
#define IRQ_UART2_TX BFIN_IRQ(44) /* DMA 19 Channel (UART2 TX) */
|
||||
#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 */
|
||||
#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 */
|
||||
#define IRQ_CAN_RX BFIN_IRQ(47) /* CAN Receive Interrupt */
|
||||
#define IRQ_CAN_TX BFIN_IRQ(48) /* CAN Transmit Interrupt */
|
||||
#define IRQ_MEM1_DMA0 BFIN_IRQ(49) /* MDMA1 Stream 0 */
|
||||
#define IRQ_MEM1_DMA1 BFIN_IRQ(50) /* MDMA1 Stream 1 */
|
||||
|
||||
#define SYS_IRQS BFIN_IRQ(63) /* 70 */
|
||||
|
||||
#define IRQ_PF0 71
|
||||
#define IRQ_PF1 72
|
||||
#define IRQ_PF2 73
|
||||
#define IRQ_PF3 74
|
||||
#define IRQ_PF4 75
|
||||
#define IRQ_PF5 76
|
||||
#define IRQ_PF6 77
|
||||
#define IRQ_PF7 78
|
||||
#define IRQ_PF8 79
|
||||
#define IRQ_PF9 80
|
||||
#define IRQ_PF10 81
|
||||
#define IRQ_PF11 82
|
||||
#define IRQ_PF12 83
|
||||
#define IRQ_PF13 84
|
||||
#define IRQ_PF14 85
|
||||
#define IRQ_PF15 86
|
||||
|
||||
#define GPIO_IRQ_BASE IRQ_PF0
|
||||
|
||||
#define NR_MACH_IRQS (IRQ_PF15 + 1)
|
||||
|
||||
/* IAR0 BIT FIELDS */
|
||||
#define IRQ_PLL_WAKEUP_POS 0
|
||||
#define IRQ_DMA0_ERROR_POS 4
|
||||
#define IRQ_PPI_ERROR_POS 8
|
||||
#define IRQ_SPORT0_ERROR_POS 12
|
||||
#define IRQ_SPORT1_ERROR_POS 16
|
||||
#define IRQ_SPI0_ERROR_POS 20
|
||||
#define IRQ_UART0_ERROR_POS 24
|
||||
#define IRQ_RTC_POS 28
|
||||
|
||||
/* IAR1 BIT FIELDS */
|
||||
#define IRQ_PPI_POS 0
|
||||
#define IRQ_SPORT0_RX_POS 4
|
||||
#define IRQ_SPORT0_TX_POS 8
|
||||
#define IRQ_SPORT1_RX_POS 12
|
||||
#define IRQ_SPORT1_TX_POS 16
|
||||
#define IRQ_SPI0_POS 20
|
||||
#define IRQ_UART0_RX_POS 24
|
||||
#define IRQ_UART0_TX_POS 28
|
||||
|
||||
/* IAR2 BIT FIELDS */
|
||||
#define IRQ_TIMER0_POS 0
|
||||
#define IRQ_TIMER1_POS 4
|
||||
#define IRQ_TIMER2_POS 8
|
||||
#define IRQ_PORTF_INTA_POS 12
|
||||
#define IRQ_PORTF_INTB_POS 16
|
||||
#define IRQ_MEM0_DMA0_POS 20
|
||||
#define IRQ_MEM0_DMA1_POS 24
|
||||
#define IRQ_WATCH_POS 28
|
||||
|
||||
/* IAR3 BIT FIELDS */
|
||||
#define IRQ_DMA1_ERROR_POS 0
|
||||
#define IRQ_SPORT2_ERROR_POS 4
|
||||
#define IRQ_SPORT3_ERROR_POS 8
|
||||
#define IRQ_SPI1_ERROR_POS 16
|
||||
#define IRQ_SPI2_ERROR_POS 20
|
||||
#define IRQ_UART1_ERROR_POS 24
|
||||
#define IRQ_UART2_ERROR_POS 28
|
||||
|
||||
/* IAR4 BIT FIELDS */
|
||||
#define IRQ_CAN_ERROR_POS 0
|
||||
#define IRQ_SPORT2_RX_POS 4
|
||||
#define IRQ_SPORT2_TX_POS 8
|
||||
#define IRQ_SPORT3_RX_POS 12
|
||||
#define IRQ_SPORT3_TX_POS 16
|
||||
#define IRQ_SPI1_POS 28
|
||||
|
||||
/* IAR5 BIT FIELDS */
|
||||
#define IRQ_SPI2_POS 0
|
||||
#define IRQ_UART1_RX_POS 4
|
||||
#define IRQ_UART1_TX_POS 8
|
||||
#define IRQ_UART2_RX_POS 12
|
||||
#define IRQ_UART2_TX_POS 16
|
||||
#define IRQ_TWI0_POS 20
|
||||
#define IRQ_TWI1_POS 24
|
||||
#define IRQ_CAN_RX_POS 28
|
||||
|
||||
/* IAR6 BIT FIELDS */
|
||||
#define IRQ_CAN_TX_POS 0
|
||||
#define IRQ_MEM1_DMA0_POS 4
|
||||
#define IRQ_MEM1_DMA1_POS 8
|
||||
|
||||
#endif
|
||||
74
arch/blackfin/mach-bf538/include/mach/mem_map.h
Normal file
74
arch/blackfin/mach-bf538/include/mach/mem_map.h
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* BF538 memory map
|
||||
*
|
||||
* Copyright 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_MACH_MEM_MAP_H__
|
||||
#define __BFIN_MACH_MEM_MAP_H__
|
||||
|
||||
#ifndef __BFIN_MEM_MAP_H__
|
||||
# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
|
||||
#endif
|
||||
|
||||
/* Async Memory Banks */
|
||||
#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
|
||||
#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
|
||||
#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
|
||||
#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
|
||||
#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
|
||||
#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
|
||||
#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
|
||||
#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
|
||||
|
||||
/* Boot ROM Memory */
|
||||
|
||||
#define BOOT_ROM_START 0xEF000000
|
||||
#define BOOT_ROM_LENGTH 0x400
|
||||
|
||||
/* Level 1 Memory */
|
||||
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
#define BFIN_ICACHESIZE (16*1024)
|
||||
#else
|
||||
#define BFIN_ICACHESIZE (0*1024)
|
||||
#endif
|
||||
|
||||
/* Memory Map for ADSP-BF538/9 processors */
|
||||
|
||||
#define L1_CODE_START 0xFFA00000
|
||||
#define L1_DATA_A_START 0xFF800000
|
||||
#define L1_DATA_B_START 0xFF900000
|
||||
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
#define L1_CODE_LENGTH (0x14000 - 0x4000)
|
||||
#else
|
||||
#define L1_CODE_LENGTH 0x14000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
|
||||
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BFIN_DCACHESIZE (16*1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
#else
|
||||
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
|
||||
#define BFIN_DCACHESIZE (32*1024)
|
||||
#define BFIN_DSUPBANKS 2
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x8000
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BFIN_DCACHESIZE (0*1024)
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE*/
|
||||
|
||||
#endif
|
||||
1
arch/blackfin/mach-bf538/include/mach/pll.h
Normal file
1
arch/blackfin/mach-bf538/include/mach/pll.h
Normal file
|
|
@ -0,0 +1 @@
|
|||
#include <mach-common/pll.h>
|
||||
114
arch/blackfin/mach-bf538/include/mach/portmux.h
Normal file
114
arch/blackfin/mach-bf538/include/mach/portmux.h
Normal file
|
|
@ -0,0 +1,114 @@
|
|||
/*
|
||||
* Copyright 2008-2009 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_PORTMUX_H_
|
||||
#define _MACH_PORTMUX_H_
|
||||
|
||||
#define MAX_RESOURCES 64
|
||||
|
||||
#define P_TMR2 (P_DONTCARE)
|
||||
#define P_TMR1 (P_DONTCARE)
|
||||
#define P_TMR0 (P_DONTCARE)
|
||||
#define P_TMRCLK (P_DONTCARE)
|
||||
#define P_PPI0_CLK (P_DONTCARE)
|
||||
#define P_PPI0_FS1 (P_DONTCARE)
|
||||
#define P_PPI0_FS2 (P_DONTCARE)
|
||||
|
||||
#define P_TWI0_SCL (P_DONTCARE)
|
||||
#define P_TWI0_SDA (P_DONTCARE)
|
||||
#define P_TWI1_SCL (P_DONTCARE)
|
||||
#define P_TWI1_SDA (P_DONTCARE)
|
||||
|
||||
#define P_SPORT1_TSCLK (P_DONTCARE)
|
||||
#define P_SPORT1_RSCLK (P_DONTCARE)
|
||||
#define P_SPORT0_TSCLK (P_DONTCARE)
|
||||
#define P_SPORT0_RSCLK (P_DONTCARE)
|
||||
#define P_SPORT1_DRSEC (P_DONTCARE)
|
||||
#define P_SPORT1_RFS (P_DONTCARE)
|
||||
#define P_SPORT1_DTPRI (P_DONTCARE)
|
||||
#define P_SPORT1_DTSEC (P_DONTCARE)
|
||||
#define P_SPORT1_TFS (P_DONTCARE)
|
||||
#define P_SPORT1_DRPRI (P_DONTCARE)
|
||||
#define P_SPORT0_DRSEC (P_DONTCARE)
|
||||
#define P_SPORT0_RFS (P_DONTCARE)
|
||||
#define P_SPORT0_DTPRI (P_DONTCARE)
|
||||
#define P_SPORT0_DTSEC (P_DONTCARE)
|
||||
#define P_SPORT0_TFS (P_DONTCARE)
|
||||
#define P_SPORT0_DRPRI (P_DONTCARE)
|
||||
|
||||
#define P_UART0_RX (P_DONTCARE)
|
||||
#define P_UART0_TX (P_DONTCARE)
|
||||
|
||||
#define P_SPI0_MOSI (P_DONTCARE)
|
||||
#define P_SPI0_MISO (P_DONTCARE)
|
||||
#define P_SPI0_SCK (P_DONTCARE)
|
||||
|
||||
#define P_PPI0_D0 (P_DONTCARE)
|
||||
#define P_PPI0_D1 (P_DONTCARE)
|
||||
#define P_PPI0_D2 (P_DONTCARE)
|
||||
#define P_PPI0_D3 (P_DONTCARE)
|
||||
|
||||
#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PC0))
|
||||
#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PC1))
|
||||
|
||||
#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD0))
|
||||
#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD1))
|
||||
#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD2))
|
||||
#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD3))
|
||||
#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD4))
|
||||
#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PD5))
|
||||
#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PD6))
|
||||
#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PD7))
|
||||
#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PD8))
|
||||
#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD9))
|
||||
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PD10))
|
||||
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PD11))
|
||||
#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PD12))
|
||||
#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PD13))
|
||||
|
||||
#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PE0))
|
||||
#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PE1))
|
||||
#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PE2))
|
||||
#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PE3))
|
||||
#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PE4))
|
||||
#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PE5))
|
||||
#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PE6))
|
||||
#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PE7))
|
||||
#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PE8))
|
||||
#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PE9))
|
||||
#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PE10))
|
||||
#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PE11))
|
||||
#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PE12))
|
||||
#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PE13))
|
||||
#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PE14))
|
||||
#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PE15))
|
||||
|
||||
#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
|
||||
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
|
||||
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
|
||||
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
|
||||
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
|
||||
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
|
||||
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
|
||||
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
|
||||
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
|
||||
|
||||
#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
|
||||
#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
|
||||
#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
|
||||
#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
|
||||
#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
|
||||
#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
|
||||
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
|
||||
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
|
||||
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
|
||||
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
|
||||
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
|
||||
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
|
||||
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
|
||||
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
|
||||
|
||||
#endif /* _MACH_PORTMUX_H_ */
|
||||
73
arch/blackfin/mach-bf538/ints-priority.c
Normal file
73
arch/blackfin/mach-bf538/ints-priority.c
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* Set up the interrupt priorities
|
||||
*
|
||||
* Copyright 2008 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/irq.h>
|
||||
#include <asm/blackfin.h>
|
||||
|
||||
void __init program_IAR(void)
|
||||
{
|
||||
|
||||
/* Program the IAR0 Register with the configured priority */
|
||||
bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
|
||||
((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
|
||||
((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
|
||||
((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
|
||||
((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
|
||||
((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS) |
|
||||
((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
|
||||
((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
|
||||
|
||||
bfin_write_SIC_IAR1(((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
|
||||
((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
|
||||
((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
|
||||
((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
|
||||
((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
|
||||
((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
|
||||
((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
|
||||
((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
|
||||
|
||||
bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
|
||||
((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
|
||||
((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
|
||||
((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
|
||||
((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
|
||||
((CONFIG_IRQ_MEM0_DMA0 - 7) << IRQ_MEM0_DMA0_POS) |
|
||||
((CONFIG_IRQ_MEM0_DMA1 - 7) << IRQ_MEM0_DMA1_POS) |
|
||||
((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
|
||||
|
||||
bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
|
||||
((CONFIG_IRQ_SPORT2_ERROR - 7) << IRQ_SPORT2_ERROR_POS) |
|
||||
((CONFIG_IRQ_SPORT3_ERROR - 7) << IRQ_SPORT3_ERROR_POS) |
|
||||
((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
|
||||
((CONFIG_IRQ_SPI2_ERROR - 7) << IRQ_SPI2_ERROR_POS) |
|
||||
((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
|
||||
((CONFIG_IRQ_UART2_ERROR - 7) << IRQ_UART2_ERROR_POS));
|
||||
|
||||
bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN_ERROR - 7) << IRQ_CAN_ERROR_POS) |
|
||||
((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
|
||||
((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
|
||||
((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
|
||||
((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
|
||||
((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
|
||||
|
||||
bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
|
||||
((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
|
||||
((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
|
||||
((CONFIG_IRQ_UART2_RX - 7) << IRQ_UART2_RX_POS) |
|
||||
((CONFIG_IRQ_UART2_TX - 7) << IRQ_UART2_TX_POS) |
|
||||
((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
|
||||
((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
|
||||
((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
|
||||
|
||||
bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
|
||||
((CONFIG_IRQ_MEM1_DMA0 - 7) << IRQ_MEM1_DMA0_POS) |
|
||||
((CONFIG_IRQ_MEM1_DMA1 - 7) << IRQ_MEM1_DMA1_POS));
|
||||
|
||||
SSYNC();
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue