mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 08:08:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
301
arch/blackfin/mach-bf548/include/mach/anomaly.h
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301
arch/blackfin/mach-bf548/include/mach/anomaly.h
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@ -0,0 +1,301 @@
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/*
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* DO NOT EDIT THIS FILE
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* This file is under version control at
|
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* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
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* and can be replaced with that version at any time
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* DO NOT EDIT THIS FILE
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*
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* Copyright 2004-2011 Analog Devices Inc.
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* Licensed under the Clear BSD license.
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*/
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/* This file should be up to date with:
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* - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
|
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*/
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|
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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|
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/* We do not support 0.0 or 0.1 silicon - sorry */
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#if __SILICON_REVISION__ < 2
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# error will not work on BF548 silicon version 0.0, or 0.1
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#endif
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|
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
|
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#define ANOMALY_05000074 (1)
|
||||
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
|
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#define ANOMALY_05000119 (1)
|
||||
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
|
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#define ANOMALY_05000122 (1)
|
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/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
|
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#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
|
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
|
||||
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
|
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#define ANOMALY_05000265 (1)
|
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/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
|
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#define ANOMALY_05000272 (1)
|
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
|
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#define ANOMALY_05000310 (1)
|
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/* FIFO Boot Mode Not Functional */
|
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#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
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/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
|
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/*
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* Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
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* shows that the fix itself does not cover all cases.
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*/
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#define ANOMALY_05000353 (1)
|
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (1)
|
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/* External Memory Read Access Hangs Core With PLL Bypass */
|
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#define ANOMALY_05000360 (1)
|
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/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
|
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#define ANOMALY_05000365 (1)
|
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/* Addressing Conflict between Boot ROM and Asynchronous Memory */
|
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#define ANOMALY_05000369 (1)
|
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
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#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
|
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/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
|
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#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
|
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/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
|
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#define ANOMALY_05000379 (1)
|
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/* Lockbox SESR Disallows Certain User Interrupts */
|
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#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
|
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/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
|
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#define ANOMALY_05000405 (1)
|
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/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
|
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#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
|
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/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
|
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#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
|
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/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
|
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#define ANOMALY_05000408 (1)
|
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/* Lockbox firmware leaves MDMA0 channel enabled */
|
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#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
|
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/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
|
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#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
|
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/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
|
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#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
|
||||
/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
|
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#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
|
||||
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
|
||||
#define ANOMALY_05000416 (1)
|
||||
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
|
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#define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
|
||||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
|
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#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
|
||||
/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
|
||||
#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
|
||||
/* Software System Reset Corrupts PLL_LOCKCNT Register */
|
||||
#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
|
||||
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
|
||||
#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
|
||||
/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
|
||||
#define ANOMALY_05000434 (1)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
|
||||
#define ANOMALY_05000446 (1)
|
||||
/* UART IrDA Receiver Fails on Extended Bit Pulses */
|
||||
#define ANOMALY_05000447 (1)
|
||||
/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
|
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#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
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||||
/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
|
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#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
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/* USB DMA Short Packet Data Corruption */
|
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#define ANOMALY_05000450 (1)
|
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/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
|
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#define ANOMALY_05000456 (1)
|
||||
/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
|
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#define ANOMALY_05000457 (1)
|
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/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
|
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#define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
|
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/* False Hardware Error when RETI Points to Invalid Memory */
|
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#define ANOMALY_05000461 (1)
|
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/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
|
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#define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
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/* USB DMA RX Data Corruption */
|
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#define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
|
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/* USB TX DMA Hang */
|
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#define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
|
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/* USB Rx DMA Hang */
|
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#define ANOMALY_05000465 (1)
|
||||
/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
|
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#define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
|
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/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
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#define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
|
||||
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
|
||||
#define ANOMALY_05000473 (1)
|
||||
/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
|
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#define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
|
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/* TESTSET Instruction Cannot Be Interrupted */
|
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#define ANOMALY_05000477 (1)
|
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
|
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#define ANOMALY_05000481 (1)
|
||||
/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
|
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#define ANOMALY_05000483 (1)
|
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/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
|
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#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
|
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/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
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#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
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/* PLL May Latch Incorrect Values Coming Out of Reset */
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#define ANOMALY_05000489 (1)
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/* SPI Master Boot Can Fail Under Certain Conditions */
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#define ANOMALY_05000490 (1)
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/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
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#define ANOMALY_05000491 (1)
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/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
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#define ANOMALY_05000494 (1)
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/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
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#define ANOMALY_05000498 (1)
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/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
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#define ANOMALY_05000500 (1)
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/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
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#define ANOMALY_05000501 (1)
|
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/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
|
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#define ANOMALY_05000502 (1)
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/*
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* These anomalies have been "phased" out of analog.com anomaly sheets and are
|
||||
* here to show running on older silicon just isn't feasible.
|
||||
*/
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/* False Hardware Error when ISR Context Is Not Restored */
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#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
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/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
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#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
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/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
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/* TWI Slave Boot Mode Is Not Functional */
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#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
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/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
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#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
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/* Incorrect Access of OTP_STATUS During otp_write() Function */
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#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
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/* Synchronous Burst Flash Boot Mode Is Not Functional */
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#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
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/* Host DMA Boot Modes Are Not Functional */
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#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
|
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/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
|
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#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
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/* Inadequate Rotary Debounce Logic Duration */
|
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#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
|
||||
/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
|
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#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
|
||||
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
|
||||
#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
|
||||
/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
|
||||
#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
|
||||
/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
|
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#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
|
||||
/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
|
||||
#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
|
||||
/* USB Calibration Value Is Not Initialized */
|
||||
#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
|
||||
/* USB Calibration Value to use */
|
||||
#define ANOMALY_05000346_value 0x5411
|
||||
/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
|
||||
#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
|
||||
/* Data Lost when Core Reads SDH Data FIFO */
|
||||
#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
|
||||
/* PLL Status Register Is Inaccurate */
|
||||
#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
|
||||
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
|
||||
#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
|
||||
/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
|
||||
#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
|
||||
/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
|
||||
#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
|
||||
/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
|
||||
#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
|
||||
/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
|
||||
#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
|
||||
/* 8-Bit NAND Flash Boot Mode Not Functional */
|
||||
#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
|
||||
/* Boot from OTP Memory Not Functional */
|
||||
#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
|
||||
/* bfrom_SysControl() Firmware Routine Not Functional */
|
||||
#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
|
||||
/* Programmable Preboot Settings Not Functional */
|
||||
#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
|
||||
/* CRC32 Checksum Support Not Functional */
|
||||
#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
|
||||
/* Reset Vector Must Not Be in SDRAM Memory Space */
|
||||
#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
|
||||
/* Changed Meaning of BCODE Field in SYSCR Register */
|
||||
#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
|
||||
/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
|
||||
#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
|
||||
/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
|
||||
#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
|
||||
/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
|
||||
#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
|
||||
/* Log Buffer Not Functional */
|
||||
#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
|
||||
/* Hook Routine Not Functional */
|
||||
#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
|
||||
/* Header Indirect Bit Not Functional */
|
||||
#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
|
||||
/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
|
||||
#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
|
||||
/* OTP Write Accesses Not Supported */
|
||||
#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
|
||||
/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
|
||||
#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000099 (0)
|
||||
#define ANOMALY_05000120 (0)
|
||||
#define ANOMALY_05000125 (0)
|
||||
#define ANOMALY_05000149 (0)
|
||||
#define ANOMALY_05000158 (0)
|
||||
#define ANOMALY_05000171 (0)
|
||||
#define ANOMALY_05000179 (0)
|
||||
#define ANOMALY_05000182 (0)
|
||||
#define ANOMALY_05000183 (0)
|
||||
#define ANOMALY_05000189 (0)
|
||||
#define ANOMALY_05000198 (0)
|
||||
#define ANOMALY_05000202 (0)
|
||||
#define ANOMALY_05000215 (0)
|
||||
#define ANOMALY_05000219 (0)
|
||||
#define ANOMALY_05000227 (0)
|
||||
#define ANOMALY_05000230 (0)
|
||||
#define ANOMALY_05000231 (0)
|
||||
#define ANOMALY_05000233 (0)
|
||||
#define ANOMALY_05000234 (0)
|
||||
#define ANOMALY_05000242 (0)
|
||||
#define ANOMALY_05000244 (0)
|
||||
#define ANOMALY_05000248 (0)
|
||||
#define ANOMALY_05000250 (0)
|
||||
#define ANOMALY_05000254 (0)
|
||||
#define ANOMALY_05000257 (0)
|
||||
#define ANOMALY_05000261 (0)
|
||||
#define ANOMALY_05000263 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000274 (0)
|
||||
#define ANOMALY_05000278 (0)
|
||||
#define ANOMALY_05000283 (0)
|
||||
#define ANOMALY_05000287 (0)
|
||||
#define ANOMALY_05000301 (0)
|
||||
#define ANOMALY_05000305 (0)
|
||||
#define ANOMALY_05000307 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000315 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000362 (1)
|
||||
#define ANOMALY_05000363 (0)
|
||||
#define ANOMALY_05000364 (0)
|
||||
#define ANOMALY_05000380 (0)
|
||||
#define ANOMALY_05000400 (0)
|
||||
#define ANOMALY_05000402 (0)
|
||||
#define ANOMALY_05000412 (0)
|
||||
#define ANOMALY_05000432 (0)
|
||||
#define ANOMALY_05000435 (0)
|
||||
#define ANOMALY_05000440 (0)
|
||||
#define ANOMALY_05000475 (0)
|
||||
#define ANOMALY_05000480 (0)
|
||||
#define ANOMALY_16000030 (0)
|
||||
|
||||
#endif
|
||||
105
arch/blackfin/mach-bf548/include/mach/bf548.h
Normal file
105
arch/blackfin/mach-bf548/include/mach/bf548.h
Normal file
|
|
@ -0,0 +1,105 @@
|
|||
/*
|
||||
* Copyright 2007-2009 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_BF548_H__
|
||||
#define __MACH_BF548_H__
|
||||
|
||||
#define OFFSET_(x) ((x) & 0x0000FFFF)
|
||||
|
||||
/*some misc defines*/
|
||||
#define IMASK_IVG15 0x8000
|
||||
#define IMASK_IVG14 0x4000
|
||||
#define IMASK_IVG13 0x2000
|
||||
#define IMASK_IVG12 0x1000
|
||||
|
||||
#define IMASK_IVG11 0x0800
|
||||
#define IMASK_IVG10 0x0400
|
||||
#define IMASK_IVG9 0x0200
|
||||
#define IMASK_IVG8 0x0100
|
||||
|
||||
#define IMASK_IVG7 0x0080
|
||||
#define IMASK_IVGTMR 0x0040
|
||||
#define IMASK_IVGHW 0x0020
|
||||
|
||||
/***************************/
|
||||
|
||||
|
||||
#define BFIN_DSUBBANKS 4
|
||||
#define BFIN_DWAYS 2
|
||||
#define BFIN_DLINES 64
|
||||
#define BFIN_ISUBBANKS 4
|
||||
#define BFIN_IWAYS 4
|
||||
#define BFIN_ILINES 32
|
||||
|
||||
#define WAY0_L 0x1
|
||||
#define WAY1_L 0x2
|
||||
#define WAY01_L 0x3
|
||||
#define WAY2_L 0x4
|
||||
#define WAY02_L 0x5
|
||||
#define WAY12_L 0x6
|
||||
#define WAY012_L 0x7
|
||||
|
||||
#define WAY3_L 0x8
|
||||
#define WAY03_L 0x9
|
||||
#define WAY13_L 0xA
|
||||
#define WAY013_L 0xB
|
||||
|
||||
#define WAY32_L 0xC
|
||||
#define WAY320_L 0xD
|
||||
#define WAY321_L 0xE
|
||||
#define WAYALL_L 0xF
|
||||
|
||||
#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
|
||||
|
||||
/********************************* EBIU Settings ************************************/
|
||||
#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
|
||||
#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
|
||||
|
||||
#ifdef CONFIG_C_AMBEN_ALL
|
||||
#define V_AMBEN AMBEN_ALL
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMBEN
|
||||
#define V_AMBEN 0x0
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMBEN_B0
|
||||
#define V_AMBEN AMBEN_B0
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMBEN_B0_B1
|
||||
#define V_AMBEN AMBEN_B0_B1
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMBEN_B0_B1_B2
|
||||
#define V_AMBEN AMBEN_B0_B1_B2
|
||||
#endif
|
||||
#ifdef CONFIG_C_AMCKEN
|
||||
#define V_AMCKEN AMCKEN
|
||||
#else
|
||||
#define V_AMCKEN 0x0
|
||||
#endif
|
||||
|
||||
#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
|
||||
|
||||
#if defined(CONFIG_BF542)
|
||||
# define CPU "BF542"
|
||||
# define CPUID 0x27de
|
||||
#elif defined(CONFIG_BF544)
|
||||
# define CPU "BF544"
|
||||
# define CPUID 0x27de
|
||||
#elif defined(CONFIG_BF547)
|
||||
# define CPU "BF547"
|
||||
# define CPUID 0x27de
|
||||
#elif defined(CONFIG_BF548)
|
||||
# define CPU "BF548"
|
||||
# define CPUID 0x27de
|
||||
#elif defined(CONFIG_BF549)
|
||||
# define CPU "BF549"
|
||||
# define CPUID 0x27de
|
||||
#endif
|
||||
|
||||
#ifndef CPU
|
||||
#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
|
||||
#endif
|
||||
|
||||
#endif /* __MACH_BF48_H__ */
|
||||
36
arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h
Normal file
36
arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright 2007-2008 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef BF54X_LQ043_H
|
||||
#define BF54X_LQ043_H
|
||||
|
||||
struct bfin_bf54xfb_val {
|
||||
unsigned int defval;
|
||||
unsigned int min;
|
||||
unsigned int max;
|
||||
};
|
||||
|
||||
struct bfin_bf54xfb_mach_info {
|
||||
unsigned char fixed_syncs; /* do not update sync/border */
|
||||
|
||||
/* LCD types */
|
||||
int type;
|
||||
|
||||
/* Screen size */
|
||||
int width;
|
||||
int height;
|
||||
|
||||
/* Screen info */
|
||||
struct bfin_bf54xfb_val xres;
|
||||
struct bfin_bf54xfb_val yres;
|
||||
struct bfin_bf54xfb_val bpp;
|
||||
|
||||
/* GPIOs */
|
||||
unsigned short disp;
|
||||
|
||||
};
|
||||
|
||||
#endif /* BF54X_LQ043_H */
|
||||
23
arch/blackfin/mach-bf548/include/mach/bf54x_keys.h
Normal file
23
arch/blackfin/mach-bf548/include/mach/bf54x_keys.h
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright 2007-2008 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _BFIN_KPAD_H
|
||||
#define _BFIN_KPAD_H
|
||||
|
||||
struct bfin_kpad_platform_data {
|
||||
int rows;
|
||||
int cols;
|
||||
const unsigned int *keymap;
|
||||
unsigned short keymapsize;
|
||||
unsigned short repeat;
|
||||
u32 debounce_time; /* in ns */
|
||||
u32 coldrive_time; /* in ns */
|
||||
u32 keyup_test_interval; /* in ms */
|
||||
};
|
||||
|
||||
#define KEYVAL(col, row, val) (((1 << col) << 24) | ((1 << row) << 16) | (val))
|
||||
|
||||
#endif
|
||||
16
arch/blackfin/mach-bf548/include/mach/bfin_serial.h
Normal file
16
arch/blackfin/mach-bf548/include/mach/bfin_serial.h
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* mach/bfin_serial.h - Blackfin UART/Serial definitions
|
||||
*
|
||||
* Copyright 2006-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_MACH_SERIAL_H__
|
||||
#define __BFIN_MACH_SERIAL_H__
|
||||
|
||||
#define BFIN_UART_NR_PORTS 4
|
||||
|
||||
#define BFIN_UART_BF54X_STYLE
|
||||
|
||||
#endif
|
||||
49
arch/blackfin/mach-bf548/include/mach/blackfin.h
Normal file
49
arch/blackfin/mach-bf548/include/mach/blackfin.h
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Copyright 2007-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_BLACKFIN_H_
|
||||
#define _MACH_BLACKFIN_H_
|
||||
|
||||
#include "bf548.h"
|
||||
#include "anomaly.h"
|
||||
|
||||
#include <asm/def_LPBlackfin.h>
|
||||
#ifdef CONFIG_BF542
|
||||
# include "defBF542.h"
|
||||
#endif
|
||||
#ifdef CONFIG_BF544
|
||||
# include "defBF544.h"
|
||||
#endif
|
||||
#ifdef CONFIG_BF547
|
||||
# include "defBF547.h"
|
||||
#endif
|
||||
#ifdef CONFIG_BF548
|
||||
# include "defBF548.h"
|
||||
#endif
|
||||
#ifdef CONFIG_BF549
|
||||
# include "defBF549.h"
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <asm/cdef_LPBlackfin.h>
|
||||
# ifdef CONFIG_BF542
|
||||
# include "cdefBF542.h"
|
||||
# endif
|
||||
# ifdef CONFIG_BF544
|
||||
# include "cdefBF544.h"
|
||||
# endif
|
||||
# ifdef CONFIG_BF547
|
||||
# include "cdefBF547.h"
|
||||
# endif
|
||||
# ifdef CONFIG_BF548
|
||||
# include "cdefBF548.h"
|
||||
# endif
|
||||
# ifdef CONFIG_BF549
|
||||
# include "cdefBF549.h"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
558
arch/blackfin/mach-bf548/include/mach/cdefBF542.h
Normal file
558
arch/blackfin/mach-bf548/include/mach/cdefBF542.h
Normal file
|
|
@ -0,0 +1,558 @@
|
|||
/*
|
||||
* Copyright 2007-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _CDEF_BF542_H
|
||||
#define _CDEF_BF542_H
|
||||
|
||||
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
|
||||
#include "cdefBF54x_base.h"
|
||||
|
||||
/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
|
||||
|
||||
/* ATAPI Registers */
|
||||
|
||||
#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
|
||||
#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
|
||||
#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
|
||||
#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
|
||||
#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
|
||||
#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
|
||||
#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
|
||||
#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
|
||||
#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
|
||||
#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
|
||||
#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
|
||||
#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
|
||||
#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
|
||||
#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
|
||||
#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
|
||||
#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
|
||||
#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
|
||||
#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
|
||||
#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
|
||||
#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
|
||||
#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
|
||||
#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
|
||||
#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
|
||||
#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
|
||||
#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
|
||||
#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
|
||||
#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
|
||||
#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
|
||||
#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
|
||||
#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
|
||||
#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
|
||||
#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
|
||||
#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
|
||||
#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
|
||||
#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
|
||||
#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
|
||||
#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
|
||||
#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
|
||||
#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
|
||||
#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
|
||||
#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
|
||||
#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
|
||||
#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
|
||||
#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
|
||||
#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
|
||||
#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
|
||||
#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
|
||||
#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
|
||||
#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
|
||||
#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
|
||||
|
||||
/* SDH Registers */
|
||||
|
||||
#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
|
||||
#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
|
||||
#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
|
||||
#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
|
||||
#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
|
||||
#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
|
||||
#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
|
||||
#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
|
||||
#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
|
||||
#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
|
||||
#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
|
||||
#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
|
||||
#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
|
||||
#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
|
||||
#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
|
||||
#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
|
||||
#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
|
||||
#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
|
||||
#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
|
||||
#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
|
||||
#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
|
||||
#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
|
||||
#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
|
||||
#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
|
||||
#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
|
||||
#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
|
||||
#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
|
||||
#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
|
||||
#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
|
||||
#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
|
||||
#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
|
||||
#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
|
||||
#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
|
||||
#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
|
||||
#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
|
||||
#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
|
||||
#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
|
||||
#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
|
||||
#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
|
||||
#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
|
||||
#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
|
||||
#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
|
||||
#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
|
||||
#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
|
||||
#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
|
||||
#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
|
||||
#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
|
||||
#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
|
||||
#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
|
||||
#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
|
||||
#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
|
||||
#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
|
||||
#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
|
||||
#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
|
||||
#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
|
||||
#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
|
||||
#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
|
||||
#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
|
||||
#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
|
||||
#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
|
||||
#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
|
||||
#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
|
||||
|
||||
/* USB Control Registers */
|
||||
|
||||
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
|
||||
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
|
||||
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
|
||||
#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
|
||||
#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
|
||||
#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
|
||||
#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
|
||||
#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
|
||||
#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
|
||||
#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
|
||||
#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
|
||||
#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
|
||||
#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
|
||||
#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
|
||||
#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
|
||||
#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
|
||||
#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
|
||||
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
|
||||
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
|
||||
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
|
||||
#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
|
||||
#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
|
||||
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
|
||||
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
|
||||
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
|
||||
#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
|
||||
|
||||
/* USB Packet Control Registers */
|
||||
|
||||
#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
|
||||
#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
|
||||
#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
|
||||
#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
|
||||
#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
|
||||
#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
|
||||
#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
|
||||
#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
|
||||
#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
|
||||
#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
|
||||
#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
|
||||
#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
|
||||
#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
|
||||
#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
|
||||
#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
|
||||
#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
|
||||
#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
|
||||
#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
|
||||
#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
|
||||
#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
|
||||
#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
|
||||
#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
|
||||
#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
|
||||
#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
|
||||
#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
|
||||
#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
|
||||
|
||||
/* USB Endbfin_read_()oint FIFO Registers */
|
||||
|
||||
#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
|
||||
#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
|
||||
#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
|
||||
#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
|
||||
#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
|
||||
#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
|
||||
#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
|
||||
#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
|
||||
#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
|
||||
#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
|
||||
#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
|
||||
#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
|
||||
#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
|
||||
#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
|
||||
#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
|
||||
#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
|
||||
|
||||
/* USB OTG Control Registers */
|
||||
|
||||
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
|
||||
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
|
||||
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
|
||||
#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
|
||||
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
|
||||
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
|
||||
|
||||
/* USB Phy Control Registers */
|
||||
|
||||
#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
|
||||
#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
|
||||
#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
|
||||
#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
|
||||
#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
|
||||
#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
|
||||
#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
|
||||
#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
|
||||
#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
|
||||
#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
|
||||
|
||||
/* (APHY_CNTRL is for ADI usage only) */
|
||||
|
||||
#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
|
||||
#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
|
||||
|
||||
/* (APHY_CALIB is for ADI usage only) */
|
||||
|
||||
#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
|
||||
#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
|
||||
#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
|
||||
#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
|
||||
|
||||
/* (PHY_TEST is for ADI usage only) */
|
||||
|
||||
#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
|
||||
#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
|
||||
#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
|
||||
#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
|
||||
#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
|
||||
#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 0 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
|
||||
#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
|
||||
#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 1 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
|
||||
#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
|
||||
#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 2 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
|
||||
#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
|
||||
#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 3 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
|
||||
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
|
||||
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 4 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
|
||||
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
|
||||
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 5 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
|
||||
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
|
||||
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 6 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
|
||||
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
|
||||
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 7 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
|
||||
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
|
||||
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
|
||||
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
|
||||
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
|
||||
|
||||
/* USB Channel 0 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
|
||||
#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
|
||||
#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
|
||||
#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
|
||||
#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
|
||||
#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
|
||||
#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 1 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
|
||||
#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
|
||||
#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
|
||||
#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
|
||||
#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
|
||||
#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
|
||||
#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 2 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
|
||||
#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
|
||||
#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
|
||||
#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
|
||||
#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
|
||||
#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
|
||||
#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 3 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
|
||||
#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
|
||||
#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
|
||||
#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
|
||||
#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
|
||||
#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
|
||||
#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 4 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
|
||||
#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
|
||||
#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
|
||||
#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
|
||||
#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
|
||||
#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
|
||||
#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 5 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
|
||||
#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
|
||||
#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
|
||||
#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
|
||||
#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
|
||||
#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
|
||||
#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 6 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
|
||||
#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
|
||||
#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
|
||||
#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
|
||||
#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
|
||||
#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
|
||||
#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 7 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
|
||||
#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
|
||||
#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
|
||||
#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
|
||||
#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
|
||||
#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
|
||||
#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
|
||||
|
||||
/* Keybfin_read_()ad Registers */
|
||||
|
||||
#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
|
||||
#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
|
||||
#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
|
||||
#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
|
||||
#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
|
||||
#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
|
||||
#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
|
||||
#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
|
||||
#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
|
||||
#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
|
||||
#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
|
||||
#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
|
||||
|
||||
#endif /* _CDEF_BF542_H */
|
||||
913
arch/blackfin/mach-bf548/include/mach/cdefBF544.h
Normal file
913
arch/blackfin/mach-bf548/include/mach/cdefBF544.h
Normal file
|
|
@ -0,0 +1,913 @@
|
|||
/*
|
||||
* Copyright 2007-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _CDEF_BF544_H
|
||||
#define _CDEF_BF544_H
|
||||
|
||||
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
|
||||
#include "cdefBF54x_base.h"
|
||||
|
||||
/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
|
||||
|
||||
/* Timer Registers */
|
||||
|
||||
#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
|
||||
#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
|
||||
#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
|
||||
#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
|
||||
#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
|
||||
#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
|
||||
#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
|
||||
#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
|
||||
#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
|
||||
#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
|
||||
#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
|
||||
#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
|
||||
#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
|
||||
#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
|
||||
#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
|
||||
#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
|
||||
#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
|
||||
#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
|
||||
#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
|
||||
#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
|
||||
#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
|
||||
#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
|
||||
#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
|
||||
#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
|
||||
|
||||
/* Timer Groubfin_read_() of 3 */
|
||||
|
||||
#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
|
||||
#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
|
||||
#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
|
||||
#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
|
||||
#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
|
||||
#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
|
||||
|
||||
/* EPPI0 Registers */
|
||||
|
||||
#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
|
||||
#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
|
||||
#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
|
||||
#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
|
||||
#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
|
||||
#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
|
||||
#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
|
||||
#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
|
||||
#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
|
||||
#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
|
||||
#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
|
||||
#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
|
||||
#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
|
||||
#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
|
||||
#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
|
||||
#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
|
||||
#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
|
||||
#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
|
||||
#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
|
||||
#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
|
||||
#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
|
||||
#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
|
||||
#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
|
||||
#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
|
||||
#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
|
||||
#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
|
||||
#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
|
||||
#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
|
||||
|
||||
/* Two Wire Interface Registers (TWI1) */
|
||||
|
||||
/* CAN Controller 1 Config 1 Registers */
|
||||
|
||||
#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
|
||||
#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
|
||||
#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
|
||||
#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
|
||||
#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
|
||||
#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
|
||||
#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
|
||||
#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
|
||||
#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
|
||||
#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
|
||||
#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
|
||||
#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
|
||||
#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
|
||||
#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
|
||||
#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
|
||||
#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
|
||||
#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
|
||||
#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
|
||||
#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
|
||||
#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
|
||||
#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
|
||||
#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
|
||||
#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
|
||||
#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
|
||||
#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
|
||||
#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
|
||||
|
||||
/* CAN Controller 1 Config 2 Registers */
|
||||
|
||||
#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
|
||||
#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
|
||||
#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
|
||||
#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
|
||||
#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
|
||||
#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
|
||||
#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
|
||||
#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
|
||||
#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
|
||||
#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
|
||||
#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
|
||||
#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
|
||||
#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
|
||||
#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
|
||||
#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
|
||||
#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
|
||||
#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
|
||||
#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
|
||||
#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
|
||||
#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
|
||||
#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
|
||||
#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
|
||||
#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
|
||||
#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
|
||||
#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
|
||||
#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
|
||||
|
||||
/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
|
||||
|
||||
#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
|
||||
#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
|
||||
#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
|
||||
#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
|
||||
#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
|
||||
#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
|
||||
#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
|
||||
#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
|
||||
#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
|
||||
#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
|
||||
#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
|
||||
#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
|
||||
#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
|
||||
#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
|
||||
#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
|
||||
#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
|
||||
#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
|
||||
#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
|
||||
#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
|
||||
#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
|
||||
#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
|
||||
#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
|
||||
#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
|
||||
#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
|
||||
#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
|
||||
#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
|
||||
#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
|
||||
#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
|
||||
#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
|
||||
#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
|
||||
#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
|
||||
#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
|
||||
|
||||
/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
|
||||
|
||||
#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
|
||||
#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
|
||||
#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
|
||||
#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
|
||||
#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
|
||||
#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
|
||||
#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
|
||||
#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
|
||||
#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
|
||||
#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
|
||||
#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
|
||||
#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
|
||||
#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
|
||||
#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
|
||||
#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
|
||||
#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
|
||||
#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
|
||||
#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
|
||||
#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
|
||||
#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
|
||||
#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
|
||||
#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
|
||||
#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
|
||||
#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
|
||||
#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
|
||||
#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
|
||||
#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
|
||||
#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
|
||||
#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
|
||||
#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
|
||||
#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
|
||||
#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
|
||||
#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
|
||||
#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
|
||||
#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
|
||||
#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
|
||||
#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
|
||||
#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
|
||||
#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
|
||||
#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
|
||||
#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
|
||||
#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
|
||||
#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
|
||||
#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
|
||||
#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
|
||||
#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
|
||||
#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
|
||||
#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
|
||||
#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
|
||||
#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
|
||||
#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
|
||||
#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
|
||||
#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
|
||||
#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
|
||||
#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
|
||||
#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
|
||||
#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
|
||||
#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
|
||||
#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
|
||||
#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
|
||||
#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
|
||||
#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
|
||||
#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
|
||||
#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
|
||||
|
||||
/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
|
||||
|
||||
#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
|
||||
#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
|
||||
#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
|
||||
#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
|
||||
#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
|
||||
#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
|
||||
#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
|
||||
#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
|
||||
#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
|
||||
#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
|
||||
#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
|
||||
#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
|
||||
#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
|
||||
#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
|
||||
#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
|
||||
#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
|
||||
#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
|
||||
#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
|
||||
#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
|
||||
#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
|
||||
#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
|
||||
#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
|
||||
#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
|
||||
#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
|
||||
#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
|
||||
#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
|
||||
#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
|
||||
#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
|
||||
#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
|
||||
#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
|
||||
#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
|
||||
#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
|
||||
#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
|
||||
#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
|
||||
#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
|
||||
#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
|
||||
#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
|
||||
#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
|
||||
#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
|
||||
#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
|
||||
#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
|
||||
#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
|
||||
#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
|
||||
#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
|
||||
#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
|
||||
#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
|
||||
#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
|
||||
#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
|
||||
#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
|
||||
#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
|
||||
#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
|
||||
#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
|
||||
#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
|
||||
#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
|
||||
#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
|
||||
#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
|
||||
#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
|
||||
#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
|
||||
#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
|
||||
#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
|
||||
#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
|
||||
#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
|
||||
#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
|
||||
#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
|
||||
|
||||
/* CAN Controller 1 Mailbox Data Registers */
|
||||
|
||||
#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
|
||||
#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
|
||||
#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
|
||||
#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
|
||||
#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
|
||||
#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
|
||||
#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
|
||||
#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
|
||||
#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
|
||||
#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
|
||||
#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
|
||||
#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
|
||||
#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
|
||||
#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
|
||||
#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
|
||||
#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
|
||||
#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
|
||||
#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
|
||||
#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
|
||||
#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
|
||||
#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
|
||||
#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
|
||||
#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
|
||||
#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
|
||||
#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
|
||||
#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
|
||||
#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
|
||||
#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
|
||||
#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
|
||||
#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
|
||||
#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
|
||||
#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
|
||||
#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
|
||||
#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
|
||||
#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
|
||||
#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
|
||||
#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
|
||||
#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
|
||||
#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
|
||||
#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
|
||||
#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
|
||||
#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
|
||||
#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
|
||||
#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
|
||||
#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
|
||||
#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
|
||||
#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
|
||||
#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
|
||||
#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
|
||||
#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
|
||||
#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
|
||||
#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
|
||||
#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
|
||||
#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
|
||||
#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
|
||||
#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
|
||||
#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
|
||||
#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
|
||||
#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
|
||||
#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
|
||||
#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
|
||||
#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
|
||||
#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
|
||||
#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
|
||||
#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
|
||||
#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
|
||||
#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
|
||||
#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
|
||||
#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
|
||||
#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
|
||||
#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
|
||||
#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
|
||||
#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
|
||||
#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
|
||||
#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
|
||||
#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
|
||||
#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
|
||||
#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
|
||||
#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
|
||||
#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
|
||||
#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
|
||||
#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
|
||||
#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
|
||||
#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
|
||||
#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
|
||||
#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
|
||||
#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
|
||||
#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
|
||||
#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
|
||||
#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
|
||||
#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
|
||||
#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
|
||||
#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
|
||||
#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
|
||||
#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
|
||||
#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
|
||||
#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
|
||||
#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
|
||||
#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
|
||||
#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
|
||||
#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
|
||||
#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
|
||||
#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
|
||||
#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
|
||||
#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
|
||||
#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
|
||||
#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
|
||||
#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
|
||||
#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
|
||||
#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
|
||||
#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
|
||||
#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
|
||||
#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
|
||||
#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
|
||||
#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
|
||||
#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
|
||||
#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
|
||||
#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
|
||||
#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
|
||||
#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
|
||||
#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
|
||||
#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
|
||||
#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
|
||||
#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
|
||||
#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
|
||||
#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
|
||||
#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
|
||||
#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
|
||||
#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
|
||||
#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
|
||||
#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
|
||||
#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
|
||||
#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
|
||||
#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
|
||||
#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
|
||||
#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
|
||||
#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
|
||||
#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
|
||||
#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
|
||||
#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
|
||||
#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
|
||||
#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
|
||||
#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
|
||||
#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
|
||||
#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
|
||||
#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
|
||||
#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
|
||||
#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
|
||||
#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
|
||||
#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
|
||||
#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
|
||||
#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
|
||||
#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
|
||||
#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
|
||||
#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
|
||||
#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
|
||||
#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
|
||||
#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
|
||||
#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
|
||||
#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
|
||||
#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
|
||||
#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
|
||||
#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
|
||||
#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
|
||||
#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
|
||||
#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
|
||||
#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
|
||||
#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
|
||||
#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
|
||||
#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
|
||||
#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
|
||||
#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
|
||||
#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
|
||||
#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
|
||||
#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
|
||||
#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
|
||||
#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
|
||||
#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
|
||||
#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
|
||||
#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
|
||||
#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
|
||||
#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
|
||||
#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
|
||||
#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
|
||||
#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
|
||||
#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
|
||||
#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
|
||||
#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
|
||||
#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
|
||||
#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
|
||||
#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
|
||||
#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
|
||||
#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
|
||||
#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
|
||||
#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
|
||||
#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
|
||||
#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
|
||||
#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
|
||||
#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
|
||||
#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
|
||||
#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
|
||||
#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
|
||||
#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
|
||||
#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
|
||||
#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
|
||||
#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
|
||||
#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
|
||||
#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
|
||||
|
||||
/* CAN Controller 1 Mailbox Data Registers */
|
||||
|
||||
#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
|
||||
#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
|
||||
#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
|
||||
#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
|
||||
#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
|
||||
#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
|
||||
#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
|
||||
#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
|
||||
#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
|
||||
#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
|
||||
#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
|
||||
#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
|
||||
#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
|
||||
#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
|
||||
#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
|
||||
#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
|
||||
#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
|
||||
#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
|
||||
#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
|
||||
#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
|
||||
#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
|
||||
#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
|
||||
#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
|
||||
#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
|
||||
#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
|
||||
#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
|
||||
#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
|
||||
#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
|
||||
#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
|
||||
#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
|
||||
#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
|
||||
#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
|
||||
#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
|
||||
#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
|
||||
#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
|
||||
#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
|
||||
#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
|
||||
#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
|
||||
#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
|
||||
#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
|
||||
#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
|
||||
#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
|
||||
#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
|
||||
#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
|
||||
#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
|
||||
#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
|
||||
#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
|
||||
#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
|
||||
#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
|
||||
#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
|
||||
#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
|
||||
#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
|
||||
#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
|
||||
#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
|
||||
#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
|
||||
#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
|
||||
#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
|
||||
#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
|
||||
#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
|
||||
#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
|
||||
#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
|
||||
#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
|
||||
#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
|
||||
#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
|
||||
#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
|
||||
#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
|
||||
#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
|
||||
#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
|
||||
#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
|
||||
#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
|
||||
#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
|
||||
#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
|
||||
#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
|
||||
#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
|
||||
#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
|
||||
#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
|
||||
#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
|
||||
#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
|
||||
#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
|
||||
#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
|
||||
#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
|
||||
#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
|
||||
#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
|
||||
#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
|
||||
#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
|
||||
#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
|
||||
#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
|
||||
#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
|
||||
#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
|
||||
#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
|
||||
#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
|
||||
#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
|
||||
#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
|
||||
#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
|
||||
#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
|
||||
#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
|
||||
#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
|
||||
#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
|
||||
#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
|
||||
#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
|
||||
#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
|
||||
#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
|
||||
#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
|
||||
#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
|
||||
#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
|
||||
#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
|
||||
#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
|
||||
#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
|
||||
#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
|
||||
#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
|
||||
#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
|
||||
#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
|
||||
#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
|
||||
#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
|
||||
#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
|
||||
#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
|
||||
#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
|
||||
#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
|
||||
#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
|
||||
#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
|
||||
#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
|
||||
#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
|
||||
#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
|
||||
#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
|
||||
#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
|
||||
#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
|
||||
#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
|
||||
#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
|
||||
#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
|
||||
#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
|
||||
#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
|
||||
#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
|
||||
#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
|
||||
#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
|
||||
#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
|
||||
#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
|
||||
#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
|
||||
#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
|
||||
#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
|
||||
#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
|
||||
#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
|
||||
#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
|
||||
#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
|
||||
#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
|
||||
#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
|
||||
#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
|
||||
#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
|
||||
#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
|
||||
#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
|
||||
#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
|
||||
#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
|
||||
#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
|
||||
#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
|
||||
#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
|
||||
#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
|
||||
#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
|
||||
#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
|
||||
#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
|
||||
#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
|
||||
#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
|
||||
#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
|
||||
#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
|
||||
#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
|
||||
#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
|
||||
#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
|
||||
#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
|
||||
#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
|
||||
#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
|
||||
#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
|
||||
#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
|
||||
#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
|
||||
#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
|
||||
#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
|
||||
#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
|
||||
#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
|
||||
#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
|
||||
#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
|
||||
#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
|
||||
#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
|
||||
#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
|
||||
#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
|
||||
#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
|
||||
#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
|
||||
#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
|
||||
#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
|
||||
#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
|
||||
#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
|
||||
#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
|
||||
#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
|
||||
#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
|
||||
#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
|
||||
#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
|
||||
#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
|
||||
#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
|
||||
#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
|
||||
#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
|
||||
#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
|
||||
#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
|
||||
#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
|
||||
#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
|
||||
#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
|
||||
#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
|
||||
#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
|
||||
#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
|
||||
#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
|
||||
#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
|
||||
#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
|
||||
#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
|
||||
|
||||
/* HOST Port Registers */
|
||||
|
||||
#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
|
||||
#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
|
||||
#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
|
||||
#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
|
||||
#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
|
||||
#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
|
||||
|
||||
/* Pixel Combfin_read_()ositor (PIXC) Registers */
|
||||
|
||||
#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
|
||||
#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
|
||||
#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
|
||||
#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
|
||||
#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
|
||||
#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
|
||||
#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
|
||||
#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
|
||||
#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
|
||||
#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
|
||||
#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
|
||||
#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
|
||||
#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
|
||||
#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
|
||||
#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
|
||||
#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
|
||||
#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
|
||||
#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
|
||||
#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
|
||||
#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
|
||||
#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
|
||||
#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
|
||||
#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
|
||||
#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
|
||||
#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
|
||||
#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
|
||||
#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
|
||||
#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
|
||||
#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
|
||||
#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
|
||||
#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
|
||||
#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
|
||||
#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
|
||||
#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
|
||||
#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
|
||||
#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
|
||||
#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
|
||||
#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
|
||||
|
||||
/* Handshake MDMA 0 Registers */
|
||||
|
||||
#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
|
||||
#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
|
||||
#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
|
||||
#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
|
||||
#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
|
||||
#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
|
||||
#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
|
||||
#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
|
||||
#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
|
||||
#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
|
||||
#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
|
||||
#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
|
||||
#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
|
||||
#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
|
||||
|
||||
/* Handshake MDMA 1 Registers */
|
||||
|
||||
#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
|
||||
#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
|
||||
#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
|
||||
#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
|
||||
#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
|
||||
#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
|
||||
#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
|
||||
#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
|
||||
#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
|
||||
#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
|
||||
#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
|
||||
#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
|
||||
#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
|
||||
#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
|
||||
|
||||
#endif /* _CDEF_BF544_H */
|
||||
800
arch/blackfin/mach-bf548/include/mach/cdefBF547.h
Normal file
800
arch/blackfin/mach-bf548/include/mach/cdefBF547.h
Normal file
|
|
@ -0,0 +1,800 @@
|
|||
/*
|
||||
* Copyright 2008-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _CDEF_BF547_H
|
||||
#define _CDEF_BF547_H
|
||||
|
||||
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
|
||||
#include "cdefBF54x_base.h"
|
||||
|
||||
/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
|
||||
|
||||
/* Timer Registers */
|
||||
|
||||
#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
|
||||
#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
|
||||
#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
|
||||
#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
|
||||
#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
|
||||
#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
|
||||
#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
|
||||
#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
|
||||
#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
|
||||
#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
|
||||
#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
|
||||
#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
|
||||
#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
|
||||
#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
|
||||
#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
|
||||
#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
|
||||
#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
|
||||
#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
|
||||
#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
|
||||
#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
|
||||
#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
|
||||
#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
|
||||
#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
|
||||
#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
|
||||
|
||||
/* Timer Groubfin_read_() of 3 */
|
||||
|
||||
#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
|
||||
#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
|
||||
#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
|
||||
#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
|
||||
#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
|
||||
#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
|
||||
|
||||
/* SPORT0 Registers */
|
||||
|
||||
#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
|
||||
#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
|
||||
#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
|
||||
#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
|
||||
#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
|
||||
#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
|
||||
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
|
||||
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
|
||||
#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
|
||||
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
|
||||
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
|
||||
#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
|
||||
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
|
||||
#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
|
||||
#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
|
||||
#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
|
||||
#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
|
||||
#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
|
||||
#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
|
||||
#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
|
||||
#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
|
||||
#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
|
||||
#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
|
||||
#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
|
||||
#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
|
||||
#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
|
||||
#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
|
||||
#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
|
||||
#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
|
||||
#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
|
||||
#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
|
||||
#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
|
||||
#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
|
||||
#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
|
||||
#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
|
||||
#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
|
||||
#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
|
||||
#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
|
||||
#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
|
||||
#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
|
||||
#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
|
||||
#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
|
||||
#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
|
||||
#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
|
||||
|
||||
/* EPPI0 Registers */
|
||||
|
||||
#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
|
||||
#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
|
||||
#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
|
||||
#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
|
||||
#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
|
||||
#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
|
||||
#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
|
||||
#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
|
||||
#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
|
||||
#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
|
||||
#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
|
||||
#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
|
||||
#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
|
||||
#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
|
||||
#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
|
||||
#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
|
||||
#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
|
||||
#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
|
||||
#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
|
||||
#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
|
||||
#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
|
||||
#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
|
||||
#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
|
||||
#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
|
||||
#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
|
||||
#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
|
||||
#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
|
||||
#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
|
||||
|
||||
/* UART2 Registers */
|
||||
|
||||
#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
|
||||
#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
|
||||
#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
|
||||
#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
|
||||
#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
|
||||
#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
|
||||
#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
|
||||
#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
|
||||
#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
|
||||
#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
|
||||
#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
|
||||
#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
|
||||
#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
|
||||
#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
|
||||
#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
|
||||
#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
|
||||
#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
|
||||
#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
|
||||
#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
|
||||
#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
|
||||
#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
|
||||
#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
|
||||
|
||||
/* Two Wire Interface Registers (TWI1) */
|
||||
|
||||
/* SPI2 Registers */
|
||||
|
||||
#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
|
||||
#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
|
||||
#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
|
||||
#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
|
||||
#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
|
||||
#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
|
||||
#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
|
||||
#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
|
||||
#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
|
||||
#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
|
||||
#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
|
||||
#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
|
||||
#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
|
||||
#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
|
||||
|
||||
/* ATAPI Registers */
|
||||
|
||||
#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
|
||||
#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
|
||||
#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
|
||||
#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
|
||||
#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
|
||||
#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
|
||||
#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
|
||||
#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
|
||||
#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
|
||||
#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
|
||||
#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
|
||||
#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
|
||||
#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
|
||||
#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
|
||||
#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
|
||||
#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
|
||||
#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
|
||||
#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
|
||||
#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
|
||||
#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
|
||||
#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
|
||||
#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
|
||||
#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
|
||||
#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
|
||||
#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
|
||||
#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
|
||||
#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
|
||||
#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
|
||||
#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
|
||||
#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
|
||||
#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
|
||||
#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
|
||||
#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
|
||||
#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
|
||||
#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
|
||||
#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
|
||||
#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
|
||||
#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
|
||||
#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
|
||||
#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
|
||||
#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
|
||||
#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
|
||||
#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
|
||||
#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
|
||||
#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
|
||||
#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
|
||||
#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
|
||||
#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
|
||||
#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
|
||||
#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
|
||||
|
||||
/* SDH Registers */
|
||||
|
||||
#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
|
||||
#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
|
||||
#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
|
||||
#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
|
||||
#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
|
||||
#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
|
||||
#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
|
||||
#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
|
||||
#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
|
||||
#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
|
||||
#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
|
||||
#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
|
||||
#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
|
||||
#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
|
||||
#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
|
||||
#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
|
||||
#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
|
||||
#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
|
||||
#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
|
||||
#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
|
||||
#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
|
||||
#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
|
||||
#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
|
||||
#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
|
||||
#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
|
||||
#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
|
||||
#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
|
||||
#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
|
||||
#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
|
||||
#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
|
||||
#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
|
||||
#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
|
||||
#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
|
||||
#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
|
||||
#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
|
||||
#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
|
||||
#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
|
||||
#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
|
||||
#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
|
||||
#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
|
||||
#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
|
||||
#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
|
||||
#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
|
||||
#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
|
||||
#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
|
||||
#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
|
||||
#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
|
||||
#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
|
||||
#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
|
||||
#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
|
||||
#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
|
||||
#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
|
||||
#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
|
||||
#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
|
||||
#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
|
||||
#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
|
||||
#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
|
||||
#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
|
||||
#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
|
||||
#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
|
||||
#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
|
||||
#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
|
||||
|
||||
/* HOST Port Registers */
|
||||
|
||||
#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
|
||||
#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
|
||||
#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
|
||||
#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
|
||||
#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
|
||||
#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
|
||||
|
||||
/* USB Control Registers */
|
||||
|
||||
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
|
||||
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
|
||||
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
|
||||
#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
|
||||
#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
|
||||
#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
|
||||
#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
|
||||
#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
|
||||
#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
|
||||
#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
|
||||
#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
|
||||
#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
|
||||
#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
|
||||
#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
|
||||
#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
|
||||
#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
|
||||
#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
|
||||
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
|
||||
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
|
||||
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
|
||||
#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
|
||||
#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
|
||||
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
|
||||
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
|
||||
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
|
||||
#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
|
||||
|
||||
/* USB Packet Control Registers */
|
||||
|
||||
#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
|
||||
#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
|
||||
#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
|
||||
#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
|
||||
#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
|
||||
#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
|
||||
#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
|
||||
#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
|
||||
#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
|
||||
#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
|
||||
#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
|
||||
#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
|
||||
#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
|
||||
#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
|
||||
#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
|
||||
#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
|
||||
#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
|
||||
#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
|
||||
#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
|
||||
#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
|
||||
#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
|
||||
#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
|
||||
#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
|
||||
#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
|
||||
#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
|
||||
#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
|
||||
|
||||
/* USB Endbfin_read_()oint FIFO Registers */
|
||||
|
||||
#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
|
||||
#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
|
||||
#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
|
||||
#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
|
||||
#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
|
||||
#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
|
||||
#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
|
||||
#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
|
||||
#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
|
||||
#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
|
||||
#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
|
||||
#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
|
||||
#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
|
||||
#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
|
||||
#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
|
||||
#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
|
||||
|
||||
/* USB OTG Control Registers */
|
||||
|
||||
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
|
||||
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
|
||||
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
|
||||
#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
|
||||
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
|
||||
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
|
||||
|
||||
/* USB Phy Control Registers */
|
||||
|
||||
#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
|
||||
#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
|
||||
#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
|
||||
#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
|
||||
#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
|
||||
#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
|
||||
#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
|
||||
#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
|
||||
#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
|
||||
#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
|
||||
|
||||
/* (APHY_CNTRL is for ADI usage only) */
|
||||
|
||||
#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
|
||||
#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
|
||||
|
||||
/* (APHY_CALIB is for ADI usage only) */
|
||||
|
||||
#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
|
||||
#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
|
||||
#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
|
||||
#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
|
||||
|
||||
/* (PHY_TEST is for ADI usage only) */
|
||||
|
||||
#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
|
||||
#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
|
||||
#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
|
||||
#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
|
||||
#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
|
||||
#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 0 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
|
||||
#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
|
||||
#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 1 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
|
||||
#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
|
||||
#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 2 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
|
||||
#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
|
||||
#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 3 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
|
||||
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
|
||||
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 4 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
|
||||
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
|
||||
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 5 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
|
||||
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
|
||||
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 6 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
|
||||
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
|
||||
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
|
||||
|
||||
/* USB Endbfin_read_()oint 7 Control Registers */
|
||||
|
||||
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
|
||||
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
|
||||
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
|
||||
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
|
||||
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
|
||||
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
|
||||
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
|
||||
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
|
||||
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
|
||||
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
|
||||
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
|
||||
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
|
||||
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
|
||||
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
|
||||
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
|
||||
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
|
||||
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
|
||||
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
|
||||
|
||||
/* USB Channel 0 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
|
||||
#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
|
||||
#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
|
||||
#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
|
||||
#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
|
||||
#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
|
||||
#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 1 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
|
||||
#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
|
||||
#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
|
||||
#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
|
||||
#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
|
||||
#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
|
||||
#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 2 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
|
||||
#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
|
||||
#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
|
||||
#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
|
||||
#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
|
||||
#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
|
||||
#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 3 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
|
||||
#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
|
||||
#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
|
||||
#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
|
||||
#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
|
||||
#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
|
||||
#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 4 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
|
||||
#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
|
||||
#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
|
||||
#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
|
||||
#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
|
||||
#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
|
||||
#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 5 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
|
||||
#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
|
||||
#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
|
||||
#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
|
||||
#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
|
||||
#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
|
||||
#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 6 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
|
||||
#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
|
||||
#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
|
||||
#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
|
||||
#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
|
||||
#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
|
||||
#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
|
||||
|
||||
/* USB Channel 7 Config Registers */
|
||||
|
||||
#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
|
||||
#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
|
||||
#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
|
||||
#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
|
||||
#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
|
||||
#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
|
||||
#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
|
||||
#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
|
||||
#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
|
||||
#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
|
||||
|
||||
/* Keybfin_read_()ad Registers */
|
||||
|
||||
#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
|
||||
#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
|
||||
#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
|
||||
#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
|
||||
#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
|
||||
#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
|
||||
#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
|
||||
#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
|
||||
#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
|
||||
#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
|
||||
#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
|
||||
#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
|
||||
|
||||
/* Pixel Combfin_read_()ositor (PIXC) Registers */
|
||||
|
||||
#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
|
||||
#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
|
||||
#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
|
||||
#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
|
||||
#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
|
||||
#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
|
||||
#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
|
||||
#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
|
||||
#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
|
||||
#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
|
||||
#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
|
||||
#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
|
||||
#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
|
||||
#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
|
||||
#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
|
||||
#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
|
||||
#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
|
||||
#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
|
||||
#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
|
||||
#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
|
||||
#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
|
||||
#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
|
||||
#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
|
||||
#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
|
||||
#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
|
||||
#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
|
||||
#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
|
||||
#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
|
||||
#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
|
||||
#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
|
||||
#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
|
||||
#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
|
||||
#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
|
||||
#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
|
||||
#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
|
||||
#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
|
||||
#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
|
||||
#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
|
||||
|
||||
/* Handshake MDMA 0 Registers */
|
||||
|
||||
#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
|
||||
#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
|
||||
#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
|
||||
#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
|
||||
#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
|
||||
#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
|
||||
#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
|
||||
#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
|
||||
#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
|
||||
#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
|
||||
#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
|
||||
#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
|
||||
#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
|
||||
#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
|
||||
|
||||
/* Handshake MDMA 1 Registers */
|
||||
|
||||
#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
|
||||
#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
|
||||
#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
|
||||
#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
|
||||
#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
|
||||
#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
|
||||
#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
|
||||
#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
|
||||
#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
|
||||
#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
|
||||
#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
|
||||
#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
|
||||
#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
|
||||
#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
|
||||
|
||||
#endif /* _CDEF_BF547_H */
|
||||
761
arch/blackfin/mach-bf548/include/mach/cdefBF548.h
Normal file
761
arch/blackfin/mach-bf548/include/mach/cdefBF548.h
Normal file
|
|
@ -0,0 +1,761 @@
|
|||
/*
|
||||
* Copyright 2007-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _CDEF_BF548_H
|
||||
#define _CDEF_BF548_H
|
||||
|
||||
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
|
||||
#include "cdefBF54x_base.h"
|
||||
|
||||
/* The BF548 is like the BF547, but has additional CANs */
|
||||
#include "cdefBF547.h"
|
||||
|
||||
/* CAN Controller 1 Config 1 Registers */
|
||||
|
||||
#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
|
||||
#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
|
||||
#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
|
||||
#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
|
||||
#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
|
||||
#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
|
||||
#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
|
||||
#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
|
||||
#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
|
||||
#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
|
||||
#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
|
||||
#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
|
||||
#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
|
||||
#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
|
||||
#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
|
||||
#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
|
||||
#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
|
||||
#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
|
||||
#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
|
||||
#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
|
||||
#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
|
||||
#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
|
||||
#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
|
||||
#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
|
||||
#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
|
||||
#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
|
||||
|
||||
/* CAN Controller 1 Config 2 Registers */
|
||||
|
||||
#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
|
||||
#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
|
||||
#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
|
||||
#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
|
||||
#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
|
||||
#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
|
||||
#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
|
||||
#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
|
||||
#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
|
||||
#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
|
||||
#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
|
||||
#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
|
||||
#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
|
||||
#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
|
||||
#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
|
||||
#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
|
||||
#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
|
||||
#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
|
||||
#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
|
||||
#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
|
||||
#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
|
||||
#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
|
||||
#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
|
||||
#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
|
||||
#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
|
||||
#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
|
||||
|
||||
/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
|
||||
|
||||
#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
|
||||
#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
|
||||
#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
|
||||
#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
|
||||
#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
|
||||
#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
|
||||
#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
|
||||
#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
|
||||
#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
|
||||
#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
|
||||
#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
|
||||
#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
|
||||
#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
|
||||
#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
|
||||
#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
|
||||
#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
|
||||
#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
|
||||
#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
|
||||
#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
|
||||
#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
|
||||
#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
|
||||
#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
|
||||
#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
|
||||
#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
|
||||
#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
|
||||
#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
|
||||
#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
|
||||
#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
|
||||
#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
|
||||
#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
|
||||
#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
|
||||
#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
|
||||
|
||||
/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
|
||||
|
||||
#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
|
||||
#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
|
||||
#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
|
||||
#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
|
||||
#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
|
||||
#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
|
||||
#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
|
||||
#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
|
||||
#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
|
||||
#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
|
||||
#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
|
||||
#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
|
||||
#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
|
||||
#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
|
||||
#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
|
||||
#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
|
||||
#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
|
||||
#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
|
||||
#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
|
||||
#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
|
||||
#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
|
||||
#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
|
||||
#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
|
||||
#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
|
||||
#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
|
||||
#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
|
||||
#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
|
||||
#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
|
||||
#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
|
||||
#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
|
||||
#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
|
||||
#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
|
||||
#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
|
||||
#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
|
||||
#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
|
||||
#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
|
||||
#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
|
||||
#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
|
||||
#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
|
||||
#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
|
||||
#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
|
||||
#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
|
||||
#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
|
||||
#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
|
||||
#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
|
||||
#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
|
||||
#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
|
||||
#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
|
||||
#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
|
||||
#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
|
||||
#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
|
||||
#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
|
||||
#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
|
||||
#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
|
||||
#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
|
||||
#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
|
||||
#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
|
||||
#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
|
||||
#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
|
||||
#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
|
||||
#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
|
||||
#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
|
||||
#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
|
||||
#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
|
||||
|
||||
/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
|
||||
|
||||
#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
|
||||
#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
|
||||
#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
|
||||
#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
|
||||
#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
|
||||
#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
|
||||
#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
|
||||
#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
|
||||
#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
|
||||
#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
|
||||
#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
|
||||
#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
|
||||
#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
|
||||
#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
|
||||
#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
|
||||
#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
|
||||
#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
|
||||
#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
|
||||
#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
|
||||
#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
|
||||
#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
|
||||
#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
|
||||
#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
|
||||
#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
|
||||
#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
|
||||
#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
|
||||
#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
|
||||
#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
|
||||
#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
|
||||
#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
|
||||
#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
|
||||
#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
|
||||
#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
|
||||
#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
|
||||
#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
|
||||
#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
|
||||
#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
|
||||
#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
|
||||
#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
|
||||
#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
|
||||
#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
|
||||
#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
|
||||
#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
|
||||
#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
|
||||
#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
|
||||
#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
|
||||
#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
|
||||
#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
|
||||
#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
|
||||
#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
|
||||
#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
|
||||
#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
|
||||
#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
|
||||
#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
|
||||
#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
|
||||
#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
|
||||
#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
|
||||
#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
|
||||
#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
|
||||
#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
|
||||
#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
|
||||
#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
|
||||
#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
|
||||
#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
|
||||
|
||||
/* CAN Controller 1 Mailbox Data Registers */
|
||||
|
||||
#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
|
||||
#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
|
||||
#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
|
||||
#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
|
||||
#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
|
||||
#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
|
||||
#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
|
||||
#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
|
||||
#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
|
||||
#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
|
||||
#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
|
||||
#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
|
||||
#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
|
||||
#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
|
||||
#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
|
||||
#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
|
||||
#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
|
||||
#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
|
||||
#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
|
||||
#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
|
||||
#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
|
||||
#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
|
||||
#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
|
||||
#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
|
||||
#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
|
||||
#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
|
||||
#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
|
||||
#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
|
||||
#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
|
||||
#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
|
||||
#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
|
||||
#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
|
||||
#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
|
||||
#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
|
||||
#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
|
||||
#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
|
||||
#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
|
||||
#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
|
||||
#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
|
||||
#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
|
||||
#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
|
||||
#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
|
||||
#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
|
||||
#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
|
||||
#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
|
||||
#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
|
||||
#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
|
||||
#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
|
||||
#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
|
||||
#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
|
||||
#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
|
||||
#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
|
||||
#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
|
||||
#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
|
||||
#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
|
||||
#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
|
||||
#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
|
||||
#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
|
||||
#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
|
||||
#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
|
||||
#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
|
||||
#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
|
||||
#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
|
||||
#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
|
||||
#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
|
||||
#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
|
||||
#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
|
||||
#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
|
||||
#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
|
||||
#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
|
||||
#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
|
||||
#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
|
||||
#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
|
||||
#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
|
||||
#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
|
||||
#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
|
||||
#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
|
||||
#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
|
||||
#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
|
||||
#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
|
||||
#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
|
||||
#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
|
||||
#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
|
||||
#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
|
||||
#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
|
||||
#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
|
||||
#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
|
||||
#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
|
||||
#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
|
||||
#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
|
||||
#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
|
||||
#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
|
||||
#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
|
||||
#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
|
||||
#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
|
||||
#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
|
||||
#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
|
||||
#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
|
||||
#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
|
||||
#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
|
||||
#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
|
||||
#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
|
||||
#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
|
||||
#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
|
||||
#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
|
||||
#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
|
||||
#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
|
||||
#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
|
||||
#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
|
||||
#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
|
||||
#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
|
||||
#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
|
||||
#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
|
||||
#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
|
||||
#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
|
||||
#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
|
||||
#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
|
||||
#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
|
||||
#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
|
||||
#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
|
||||
#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
|
||||
#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
|
||||
#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
|
||||
#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
|
||||
#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
|
||||
#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
|
||||
#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
|
||||
#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
|
||||
#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
|
||||
#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
|
||||
#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
|
||||
#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
|
||||
#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
|
||||
#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
|
||||
#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
|
||||
#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
|
||||
#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
|
||||
#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
|
||||
#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
|
||||
#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
|
||||
#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
|
||||
#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
|
||||
#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
|
||||
#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
|
||||
#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
|
||||
#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
|
||||
#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
|
||||
#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
|
||||
#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
|
||||
#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
|
||||
#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
|
||||
#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
|
||||
#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
|
||||
#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
|
||||
#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
|
||||
#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
|
||||
#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
|
||||
#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
|
||||
#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
|
||||
#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
|
||||
#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
|
||||
#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
|
||||
#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
|
||||
#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
|
||||
#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
|
||||
#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
|
||||
#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
|
||||
#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
|
||||
#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
|
||||
#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
|
||||
#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
|
||||
#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
|
||||
#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
|
||||
#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
|
||||
#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
|
||||
#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
|
||||
#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
|
||||
#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
|
||||
#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
|
||||
#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
|
||||
#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
|
||||
#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
|
||||
#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
|
||||
#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
|
||||
#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
|
||||
#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
|
||||
#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
|
||||
#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
|
||||
#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
|
||||
#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
|
||||
#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
|
||||
#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
|
||||
#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
|
||||
#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
|
||||
#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
|
||||
#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
|
||||
#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
|
||||
#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
|
||||
#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
|
||||
#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
|
||||
#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
|
||||
#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
|
||||
#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
|
||||
#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
|
||||
#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
|
||||
#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
|
||||
#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
|
||||
#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
|
||||
|
||||
/* CAN Controller 1 Mailbox Data Registers */
|
||||
|
||||
#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
|
||||
#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
|
||||
#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
|
||||
#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
|
||||
#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
|
||||
#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
|
||||
#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
|
||||
#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
|
||||
#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
|
||||
#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
|
||||
#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
|
||||
#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
|
||||
#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
|
||||
#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
|
||||
#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
|
||||
#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
|
||||
#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
|
||||
#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
|
||||
#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
|
||||
#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
|
||||
#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
|
||||
#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
|
||||
#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
|
||||
#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
|
||||
#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
|
||||
#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
|
||||
#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
|
||||
#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
|
||||
#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
|
||||
#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
|
||||
#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
|
||||
#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
|
||||
#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
|
||||
#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
|
||||
#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
|
||||
#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
|
||||
#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
|
||||
#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
|
||||
#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
|
||||
#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
|
||||
#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
|
||||
#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
|
||||
#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
|
||||
#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
|
||||
#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
|
||||
#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
|
||||
#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
|
||||
#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
|
||||
#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
|
||||
#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
|
||||
#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
|
||||
#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
|
||||
#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
|
||||
#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
|
||||
#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
|
||||
#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
|
||||
#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
|
||||
#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
|
||||
#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
|
||||
#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
|
||||
#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
|
||||
#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
|
||||
#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
|
||||
#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
|
||||
#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
|
||||
#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
|
||||
#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
|
||||
#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
|
||||
#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
|
||||
#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
|
||||
#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
|
||||
#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
|
||||
#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
|
||||
#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
|
||||
#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
|
||||
#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
|
||||
#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
|
||||
#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
|
||||
#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
|
||||
#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
|
||||
#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
|
||||
#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
|
||||
#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
|
||||
#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
|
||||
#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
|
||||
#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
|
||||
#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
|
||||
#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
|
||||
#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
|
||||
#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
|
||||
#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
|
||||
#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
|
||||
#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
|
||||
#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
|
||||
#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
|
||||
#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
|
||||
#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
|
||||
#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
|
||||
#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
|
||||
#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
|
||||
#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
|
||||
#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
|
||||
#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
|
||||
#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
|
||||
#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
|
||||
#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
|
||||
#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
|
||||
#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
|
||||
#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
|
||||
#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
|
||||
#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
|
||||
#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
|
||||
#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
|
||||
#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
|
||||
#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
|
||||
#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
|
||||
#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
|
||||
#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
|
||||
#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
|
||||
#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
|
||||
#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
|
||||
#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
|
||||
#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
|
||||
#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
|
||||
#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
|
||||
#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
|
||||
#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
|
||||
#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
|
||||
#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
|
||||
#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
|
||||
#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
|
||||
#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
|
||||
#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
|
||||
#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
|
||||
#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
|
||||
#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
|
||||
#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
|
||||
#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
|
||||
#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
|
||||
#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
|
||||
#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
|
||||
#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
|
||||
#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
|
||||
#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
|
||||
#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
|
||||
#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
|
||||
#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
|
||||
#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
|
||||
#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
|
||||
#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
|
||||
#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
|
||||
#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
|
||||
#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
|
||||
#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
|
||||
#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
|
||||
#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
|
||||
#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
|
||||
#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
|
||||
#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
|
||||
#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
|
||||
#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
|
||||
#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
|
||||
#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
|
||||
#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
|
||||
#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
|
||||
#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
|
||||
#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
|
||||
#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
|
||||
#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
|
||||
#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
|
||||
#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
|
||||
#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
|
||||
#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
|
||||
#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
|
||||
#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
|
||||
#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
|
||||
#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
|
||||
#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
|
||||
#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
|
||||
#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
|
||||
#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
|
||||
#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
|
||||
#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
|
||||
#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
|
||||
#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
|
||||
#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
|
||||
#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
|
||||
#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
|
||||
#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
|
||||
#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
|
||||
#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
|
||||
#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
|
||||
#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
|
||||
#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
|
||||
#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
|
||||
#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
|
||||
#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
|
||||
#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
|
||||
#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
|
||||
#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
|
||||
#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
|
||||
#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
|
||||
#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
|
||||
#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
|
||||
#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
|
||||
#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
|
||||
#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
|
||||
#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
|
||||
#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
|
||||
#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
|
||||
#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
|
||||
|
||||
#endif /* _CDEF_BF548_H */
|
||||
302
arch/blackfin/mach-bf548/include/mach/cdefBF549.h
Normal file
302
arch/blackfin/mach-bf548/include/mach/cdefBF549.h
Normal file
|
|
@ -0,0 +1,302 @@
|
|||
/*
|
||||
* Copyright 2007-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _CDEF_BF549_H
|
||||
#define _CDEF_BF549_H
|
||||
|
||||
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
|
||||
#include "cdefBF54x_base.h"
|
||||
|
||||
/* The BF549 is like the BF544, but has MXVR */
|
||||
#include "cdefBF547.h"
|
||||
|
||||
/* MXVR Registers */
|
||||
|
||||
#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG)
|
||||
#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
|
||||
#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0)
|
||||
#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
|
||||
#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1)
|
||||
#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
|
||||
#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0)
|
||||
#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
|
||||
#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1)
|
||||
#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
|
||||
#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0)
|
||||
#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
|
||||
#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1)
|
||||
#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
|
||||
#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION)
|
||||
#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
|
||||
#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION)
|
||||
#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
|
||||
#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY)
|
||||
#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
|
||||
#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY)
|
||||
#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
|
||||
#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)
|
||||
#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
|
||||
#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR)
|
||||
#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
|
||||
#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)
|
||||
#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
|
||||
|
||||
/* MXVR Allocation Table Registers */
|
||||
|
||||
#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0)
|
||||
#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
|
||||
#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1)
|
||||
#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
|
||||
#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2)
|
||||
#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val)
|
||||
#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3)
|
||||
#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val)
|
||||
#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4)
|
||||
#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val)
|
||||
#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5)
|
||||
#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val)
|
||||
#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6)
|
||||
#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val)
|
||||
#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7)
|
||||
#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val)
|
||||
#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8)
|
||||
#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val)
|
||||
#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9)
|
||||
#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val)
|
||||
#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10)
|
||||
#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val)
|
||||
#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11)
|
||||
#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val)
|
||||
#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12)
|
||||
#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val)
|
||||
#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13)
|
||||
#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val)
|
||||
#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14)
|
||||
#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val)
|
||||
|
||||
/* MXVR Channel Assign Registers */
|
||||
|
||||
#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0)
|
||||
#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
|
||||
#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1)
|
||||
#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
|
||||
#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2)
|
||||
#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
|
||||
#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3)
|
||||
#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
|
||||
#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4)
|
||||
#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
|
||||
#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5)
|
||||
#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
|
||||
#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6)
|
||||
#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
|
||||
#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7)
|
||||
#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
|
||||
|
||||
/* MXVR DMA0 Registers */
|
||||
|
||||
#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG)
|
||||
#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
|
||||
#define bfin_read_MXVR_DMA0_START_ADDR() bfin_read32(MXVR_DMA0_START_ADDR)
|
||||
#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_write32(MXVR_DMA0_START_ADDR)
|
||||
#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT)
|
||||
#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_read32(MXVR_DMA0_CURR_ADDR)
|
||||
#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_write32(MXVR_DMA0_CURR_ADDR)
|
||||
#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
|
||||
#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
|
||||
|
||||
/* MXVR DMA1 Registers */
|
||||
|
||||
#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG)
|
||||
#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
|
||||
#define bfin_read_MXVR_DMA1_START_ADDR() bfin_read32(MXVR_DMA1_START_ADDR)
|
||||
#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_write32(MXVR_DMA1_START_ADDR)
|
||||
#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT)
|
||||
#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_read32(MXVR_DMA1_CURR_ADDR)
|
||||
#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_write32(MXVR_DMA1_CURR_ADDR)
|
||||
#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
|
||||
#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
|
||||
|
||||
/* MXVR DMA2 Registers */
|
||||
|
||||
#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG)
|
||||
#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
|
||||
#define bfin_read_MXVR_DMA2_START_ADDR() bfin_read32(MXVR_DMA2_START_ADDR)
|
||||
#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_write32(MXVR_DMA2_START_ADDR)
|
||||
#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT)
|
||||
#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_read32(MXVR_DMA2_CURR_ADDR)
|
||||
#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_write32(MXVR_DMA2_CURR_ADDR)
|
||||
#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
|
||||
#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
|
||||
|
||||
/* MXVR DMA3 Registers */
|
||||
|
||||
#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG)
|
||||
#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
|
||||
#define bfin_read_MXVR_DMA3_START_ADDR() bfin_read32(MXVR_DMA3_START_ADDR)
|
||||
#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_write32(MXVR_DMA3_START_ADDR)
|
||||
#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT)
|
||||
#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_read32(MXVR_DMA3_CURR_ADDR)
|
||||
#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_write32(MXVR_DMA3_CURR_ADDR)
|
||||
#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
|
||||
#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
|
||||
|
||||
/* MXVR DMA4 Registers */
|
||||
|
||||
#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG)
|
||||
#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
|
||||
#define bfin_read_MXVR_DMA4_START_ADDR() bfin_read32(MXVR_DMA4_START_ADDR)
|
||||
#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_write32(MXVR_DMA4_START_ADDR)
|
||||
#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT)
|
||||
#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_read32(MXVR_DMA4_CURR_ADDR)
|
||||
#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_write32(MXVR_DMA4_CURR_ADDR)
|
||||
#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
|
||||
#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
|
||||
|
||||
/* MXVR DMA5 Registers */
|
||||
|
||||
#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG)
|
||||
#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
|
||||
#define bfin_read_MXVR_DMA5_START_ADDR() bfin_read32(MXVR_DMA5_START_ADDR)
|
||||
#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_write32(MXVR_DMA5_START_ADDR)
|
||||
#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT)
|
||||
#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_read32(MXVR_DMA5_CURR_ADDR)
|
||||
#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_write32(MXVR_DMA5_CURR_ADDR)
|
||||
#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
|
||||
#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
|
||||
|
||||
/* MXVR DMA6 Registers */
|
||||
|
||||
#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG)
|
||||
#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
|
||||
#define bfin_read_MXVR_DMA6_START_ADDR() bfin_read32(MXVR_DMA6_START_ADDR)
|
||||
#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_write32(MXVR_DMA6_START_ADDR)
|
||||
#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT)
|
||||
#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_read32(MXVR_DMA6_CURR_ADDR)
|
||||
#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_write32(MXVR_DMA6_CURR_ADDR)
|
||||
#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
|
||||
#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
|
||||
|
||||
/* MXVR DMA7 Registers */
|
||||
|
||||
#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG)
|
||||
#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
|
||||
#define bfin_read_MXVR_DMA7_START_ADDR() bfin_read32(MXVR_DMA7_START_ADDR)
|
||||
#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_write32(MXVR_DMA7_START_ADDR)
|
||||
#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT)
|
||||
#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
|
||||
#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_read32(MXVR_DMA7_CURR_ADDR)
|
||||
#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_write32(MXVR_DMA7_CURR_ADDR)
|
||||
#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
|
||||
#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
|
||||
|
||||
/* MXVR Asynch Packet Registers */
|
||||
|
||||
#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL)
|
||||
#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
|
||||
#define bfin_read_MXVR_APRB_START_ADDR() bfin_read32(MXVR_APRB_START_ADDR)
|
||||
#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_write32(MXVR_APRB_START_ADDR)
|
||||
#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_read32(MXVR_APRB_CURR_ADDR)
|
||||
#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_write32(MXVR_APRB_CURR_ADDR)
|
||||
#define bfin_read_MXVR_APTB_START_ADDR() bfin_read32(MXVR_APTB_START_ADDR)
|
||||
#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_write32(MXVR_APTB_START_ADDR)
|
||||
#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_read32(MXVR_APTB_CURR_ADDR)
|
||||
#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_write32(MXVR_APTB_CURR_ADDR)
|
||||
|
||||
/* MXVR Control Message Registers */
|
||||
|
||||
#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL)
|
||||
#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
|
||||
#define bfin_read_MXVR_CMRB_START_ADDR() bfin_read32(MXVR_CMRB_START_ADDR)
|
||||
#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_write32(MXVR_CMRB_START_ADDR)
|
||||
#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_read32(MXVR_CMRB_CURR_ADDR)
|
||||
#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_write32(MXVR_CMRB_CURR_ADDR)
|
||||
#define bfin_read_MXVR_CMTB_START_ADDR() bfin_read32(MXVR_CMTB_START_ADDR)
|
||||
#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_write32(MXVR_CMTB_START_ADDR)
|
||||
#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_read32(MXVR_CMTB_CURR_ADDR)
|
||||
#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_write32(MXVR_CMTB_CURR_ADDR)
|
||||
|
||||
/* MXVR Remote Read Registers */
|
||||
|
||||
#define bfin_read_MXVR_RRDB_START_ADDR() bfin_read32(MXVR_RRDB_START_ADDR)
|
||||
#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_write32(MXVR_RRDB_START_ADDR)
|
||||
#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_read32(MXVR_RRDB_CURR_ADDR)
|
||||
#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_write32(MXVR_RRDB_CURR_ADDR)
|
||||
|
||||
/* MXVR Pattern Data Registers */
|
||||
|
||||
#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0)
|
||||
#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
|
||||
#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0)
|
||||
#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val)
|
||||
#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1)
|
||||
#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
|
||||
#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1)
|
||||
#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val)
|
||||
|
||||
/* MXVR Frame Counter Registers */
|
||||
|
||||
#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0)
|
||||
#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
|
||||
#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1)
|
||||
#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
|
||||
|
||||
/* MXVR Routing Table Registers */
|
||||
|
||||
#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0)
|
||||
#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
|
||||
#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1)
|
||||
#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
|
||||
#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2)
|
||||
#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
|
||||
#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3)
|
||||
#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
|
||||
#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4)
|
||||
#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
|
||||
#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5)
|
||||
#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
|
||||
#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6)
|
||||
#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
|
||||
#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7)
|
||||
#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
|
||||
#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8)
|
||||
#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
|
||||
#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9)
|
||||
#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
|
||||
#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10)
|
||||
#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
|
||||
#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11)
|
||||
#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
|
||||
#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12)
|
||||
#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
|
||||
#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13)
|
||||
#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
|
||||
#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14)
|
||||
#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
|
||||
|
||||
/* MXVR Counter-Clock-Control Registers */
|
||||
|
||||
#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT)
|
||||
#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
|
||||
#define bfin_read_MXVR_CLK_CTL() bfin_read32(MXVR_CLK_CTL)
|
||||
#define bfin_write_MXVR_CLK_CTL(val) bfin_write32(MXVR_CLK_CTL, val)
|
||||
#define bfin_read_MXVR_CDRPLL_CTL() bfin_read32(MXVR_CDRPLL_CTL)
|
||||
#define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val)
|
||||
#define bfin_read_MXVR_FMPLL_CTL() bfin_read32(MXVR_FMPLL_CTL)
|
||||
#define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val)
|
||||
#define bfin_read_MXVR_PIN_CTL() bfin_read16(MXVR_PIN_CTL)
|
||||
#define bfin_write_MXVR_PIN_CTL(val) bfin_write16(MXVR_PIN_CTL, val)
|
||||
#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT)
|
||||
#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val)
|
||||
|
||||
#endif /* _CDEF_BF549_H */
|
||||
2633
arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
Normal file
2633
arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
Normal file
File diff suppressed because it is too large
Load diff
766
arch/blackfin/mach-bf548/include/mach/defBF542.h
Normal file
766
arch/blackfin/mach-bf548/include/mach/defBF542.h
Normal file
|
|
@ -0,0 +1,766 @@
|
|||
/*
|
||||
* Copyright 2007-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the Clear BSD license or the GPL-2 (or later)
|
||||
*/
|
||||
|
||||
#ifndef _DEF_BF542_H
|
||||
#define _DEF_BF542_H
|
||||
|
||||
/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
|
||||
#include "defBF54x_base.h"
|
||||
|
||||
/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
|
||||
|
||||
/* ATAPI Registers */
|
||||
|
||||
#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
|
||||
#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
|
||||
#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
|
||||
#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
|
||||
#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
|
||||
#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
|
||||
#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
|
||||
#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
|
||||
#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
|
||||
#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
|
||||
#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
|
||||
#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
|
||||
#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
|
||||
#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
|
||||
#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
|
||||
#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
|
||||
#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
|
||||
#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
|
||||
#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
|
||||
#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
|
||||
#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
|
||||
#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
|
||||
#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
|
||||
#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
|
||||
#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
|
||||
|
||||
/* SDH Registers */
|
||||
|
||||
#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
|
||||
#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
|
||||
#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
|
||||
#define SDH_COMMAND 0xffc0390c /* SDH Command */
|
||||
#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
|
||||
#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
|
||||
#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
|
||||
#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
|
||||
#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
|
||||
#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
|
||||
#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
|
||||
#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
|
||||
#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
|
||||
#define SDH_STATUS 0xffc03934 /* SDH Status */
|
||||
#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
|
||||
#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
|
||||
#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
|
||||
#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
|
||||
#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
|
||||
#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
|
||||
#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
|
||||
#define SDH_CFG 0xffc039c8 /* SDH Configuration */
|
||||
#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
|
||||
#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
|
||||
#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
|
||||
#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
|
||||
#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
|
||||
#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
|
||||
#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
|
||||
#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
|
||||
#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
|
||||
|
||||
/* USB Control Registers */
|
||||
|
||||
#define USB_FADDR 0xffc03c00 /* Function address register */
|
||||
#define USB_POWER 0xffc03c04 /* Power management register */
|
||||
#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
|
||||
#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
|
||||
#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
|
||||
#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
|
||||
#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
|
||||
#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
|
||||
#define USB_FRAME 0xffc03c20 /* USB frame number */
|
||||
#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
|
||||
#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
|
||||
#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
|
||||
#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
|
||||
|
||||
/* USB Packet Control Registers */
|
||||
|
||||
#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
|
||||
#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
|
||||
#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
|
||||
#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
|
||||
#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
|
||||
#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
|
||||
#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
|
||||
#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
|
||||
#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
|
||||
#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
|
||||
#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
|
||||
#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
|
||||
#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
|
||||
|
||||
/* USB Endpoint FIFO Registers */
|
||||
|
||||
#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
|
||||
#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
|
||||
#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
|
||||
#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
|
||||
#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
|
||||
#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
|
||||
#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
|
||||
#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
|
||||
|
||||
/* USB OTG Control Registers */
|
||||
|
||||
#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
|
||||
#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
|
||||
#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
|
||||
|
||||
/* USB Phy Control Registers */
|
||||
|
||||
#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
|
||||
#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
|
||||
#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
|
||||
#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
|
||||
#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
|
||||
|
||||
/* (APHY_CNTRL is for ADI usage only) */
|
||||
|
||||
#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
|
||||
|
||||
/* (APHY_CALIB is for ADI usage only) */
|
||||
|
||||
#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
|
||||
#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
|
||||
|
||||
/* (PHY_TEST is for ADI usage only) */
|
||||
|
||||
#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
|
||||
#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
|
||||
#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
|
||||
|
||||
/* USB Endpoint 0 Control Registers */
|
||||
|
||||
#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
|
||||
#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
|
||||
#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
|
||||
#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
|
||||
#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
|
||||
#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
|
||||
#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
|
||||
#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
|
||||
#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
|
||||
|
||||
/* USB Endpoint 1 Control Registers */
|
||||
|
||||
#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
|
||||
#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
|
||||
#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
|
||||
#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
|
||||
#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
|
||||
#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
|
||||
#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
|
||||
#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
|
||||
#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
|
||||
#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
|
||||
|
||||
/* USB Endpoint 2 Control Registers */
|
||||
|
||||
#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
|
||||
#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
|
||||
#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
|
||||
#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
|
||||
#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
|
||||
#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
|
||||
#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
|
||||
#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
|
||||
#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
|
||||
#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
|
||||
|
||||
/* USB Endpoint 3 Control Registers */
|
||||
|
||||
#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
|
||||
#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
|
||||
#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
|
||||
#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
|
||||
#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
|
||||
#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
|
||||
#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
|
||||
#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
|
||||
#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
|
||||
#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
|
||||
|
||||
/* USB Endpoint 4 Control Registers */
|
||||
|
||||
#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
|
||||
#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
|
||||
#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
|
||||
#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
|
||||
#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
|
||||
#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
|
||||
#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
|
||||
#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
|
||||
#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
|
||||
#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
|
||||
|
||||
/* USB Endpoint 5 Control Registers */
|
||||
|
||||
#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
|
||||
#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
|
||||
#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
|
||||
#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
|
||||
#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
|
||||
#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
|
||||
#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
|
||||
#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
|
||||
#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
|
||||
#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
|
||||
|
||||
/* USB Endpoint 6 Control Registers */
|
||||
|
||||
#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
|
||||
#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
|
||||
#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
|
||||
#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
|
||||
#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
|
||||
#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
|
||||
#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
|
||||
#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
|
||||
#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
|
||||
#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
|
||||
|
||||
/* USB Endpoint 7 Control Registers */
|
||||
|
||||
#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
|
||||
#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
|
||||
#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
|
||||
#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
|
||||
#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
|
||||
#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
|
||||
#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
|
||||
#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
|
||||
#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
|
||||
#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
|
||||
#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
|
||||
#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
|
||||
|
||||
/* USB Channel 0 Config Registers */
|
||||
|
||||
#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
|
||||
#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
|
||||
#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
|
||||
#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
|
||||
#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
|
||||
|
||||
/* USB Channel 1 Config Registers */
|
||||
|
||||
#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
|
||||
#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
|
||||
#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
|
||||
#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
|
||||
#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
|
||||
|
||||
/* USB Channel 2 Config Registers */
|
||||
|
||||
#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
|
||||
#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
|
||||
#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
|
||||
#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
|
||||
#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
|
||||
|
||||
/* USB Channel 3 Config Registers */
|
||||
|
||||
#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
|
||||
#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
|
||||
#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
|
||||
#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
|
||||
#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
|
||||
|
||||
/* USB Channel 4 Config Registers */
|
||||
|
||||
#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
|
||||
#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
|
||||
#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
|
||||
#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
|
||||
#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
|
||||
|
||||
/* USB Channel 5 Config Registers */
|
||||
|
||||
#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
|
||||
#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
|
||||
#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
|
||||
#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
|
||||
#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
|
||||
|
||||
/* USB Channel 6 Config Registers */
|
||||
|
||||
#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
|
||||
#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
|
||||
#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
|
||||
#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
|
||||
#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
|
||||
|
||||
/* USB Channel 7 Config Registers */
|
||||
|
||||
#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
|
||||
#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
|
||||
#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
|
||||
#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
|
||||
#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
|
||||
|
||||
/* Keypad Registers */
|
||||
|
||||
#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
|
||||
#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
|
||||
#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
|
||||
#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
|
||||
#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
|
||||
#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
|
||||
|
||||
|
||||
/* ********************************************************** */
|
||||
/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
|
||||
/* and MULTI BIT READ MACROS */
|
||||
/* ********************************************************** */
|
||||
|
||||
/* Bit masks for KPAD_CTL */
|
||||
|
||||
#define KPAD_EN 0x1 /* Keypad Enable */
|
||||
#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
|
||||
#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
|
||||
#define KPAD_COLEN 0xe000 /* Column Enable Width */
|
||||
|
||||
/* Bit masks for KPAD_PRESCALE */
|
||||
|
||||
#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
|
||||
|
||||
/* Bit masks for KPAD_MSEL */
|
||||
|
||||
#define DBON_SCALE 0xff /* Debounce Scale Value */
|
||||
#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
|
||||
|
||||
/* Bit masks for KPAD_ROWCOL */
|
||||
|
||||
#define KPAD_ROW 0xff /* Rows Pressed */
|
||||
#define KPAD_COL 0xff00 /* Columns Pressed */
|
||||
|
||||
/* Bit masks for KPAD_STAT */
|
||||
|
||||
#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
|
||||
#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
|
||||
#define KPAD_PRESSED 0x8 /* Key press current status */
|
||||
|
||||
/* Bit masks for KPAD_SOFTEVAL */
|
||||
|
||||
#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
|
||||
|
||||
/* Bit masks for ATAPI_CONTROL */
|
||||
|
||||
#define PIO_START 0x1 /* Start PIO/Reg Op */
|
||||
#define MULTI_START 0x2 /* Start Multi-DMA Op */
|
||||
#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
|
||||
#define XFER_DIR 0x8 /* Transfer Direction */
|
||||
#define IORDY_EN 0x10 /* IORDY Enable */
|
||||
#define FIFO_FLUSH 0x20 /* Flush FIFOs */
|
||||
#define SOFT_RST 0x40 /* Soft Reset */
|
||||
#define DEV_RST 0x80 /* Device Reset */
|
||||
#define TFRCNT_RST 0x100 /* Trans Count Reset */
|
||||
#define END_ON_TERM 0x200 /* End/Terminate Select */
|
||||
#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
|
||||
#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
|
||||
|
||||
/* Bit masks for ATAPI_STATUS */
|
||||
|
||||
#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
|
||||
#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
|
||||
#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
|
||||
#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
|
||||
|
||||
/* Bit masks for ATAPI_DEV_ADDR */
|
||||
|
||||
#define DEV_ADDR 0x1f /* Device Address */
|
||||
|
||||
/* Bit masks for ATAPI_INT_MASK */
|
||||
|
||||
#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
|
||||
#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
|
||||
#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
|
||||
#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
|
||||
#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
|
||||
#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
|
||||
#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
|
||||
#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
|
||||
#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
|
||||
|
||||
/* Bit masks for ATAPI_INT_STATUS */
|
||||
|
||||
#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
|
||||
#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
|
||||
#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
|
||||
#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
|
||||
#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
|
||||
#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
|
||||
#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
|
||||
#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
|
||||
#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
|
||||
|
||||
/* Bit masks for ATAPI_LINE_STATUS */
|
||||
|
||||
#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
|
||||
#define ATAPI_DASP 0x2 /* Device dasp to host line status */
|
||||
#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
|
||||
#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
|
||||
#define ATAPI_ADDR 0x70 /* ATAPI address line status */
|
||||
#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
|
||||
#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
|
||||
#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
|
||||
#define ATAPI_DIORN 0x400 /* ATAPI read line status */
|
||||
#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
|
||||
|
||||
/* Bit masks for ATAPI_SM_STATE */
|
||||
|
||||
#define PIO_CSTATE 0xf /* PIO mode state machine current state */
|
||||
#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
|
||||
#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
|
||||
#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
|
||||
|
||||
/* Bit masks for ATAPI_TERMINATE */
|
||||
|
||||
#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
|
||||
|
||||
/* Bit masks for ATAPI_REG_TIM_0 */
|
||||
|
||||
#define T2_REG 0xff /* End of cycle time for register access transfers */
|
||||
#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
|
||||
|
||||
/* Bit masks for ATAPI_PIO_TIM_0 */
|
||||
|
||||
#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
|
||||
#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
|
||||
#define T4_REG 0xf000 /* DIOW data hold */
|
||||
|
||||
/* Bit masks for ATAPI_PIO_TIM_1 */
|
||||
|
||||
#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
|
||||
|
||||
/* Bit masks for ATAPI_MULTI_TIM_0 */
|
||||
|
||||
#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
|
||||
#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
|
||||
|
||||
/* Bit masks for ATAPI_MULTI_TIM_1 */
|
||||
|
||||
#define TKW 0xff /* Selects DIOW negated pulsewidth */
|
||||
#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
|
||||
|
||||
/* Bit masks for ATAPI_MULTI_TIM_2 */
|
||||
|
||||
#define TH 0xff /* Selects DIOW data hold */
|
||||
#define TEOC 0xff00 /* Selects end of cycle for DMA */
|
||||
|
||||
/* Bit masks for ATAPI_ULTRA_TIM_0 */
|
||||
|
||||
#define TACK 0xff /* Selects setup and hold times for TACK */
|
||||
#define TENV 0xff00 /* Selects envelope time */
|
||||
|
||||
/* Bit masks for ATAPI_ULTRA_TIM_1 */
|
||||
|
||||
#define TDVS 0xff /* Selects data valid setup time */
|
||||
#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
|
||||
|
||||
/* Bit masks for ATAPI_ULTRA_TIM_2 */
|
||||
|
||||
#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
|
||||
#define TMLI 0xff00 /* Selects interlock time */
|
||||
|
||||
/* Bit masks for ATAPI_ULTRA_TIM_3 */
|
||||
|
||||
#define TZAH 0xff /* Selects minimum delay required for output */
|
||||
#define READY_PAUSE 0xff00 /* Selects ready to pause */
|
||||
|
||||
/* Bit masks for USB_FADDR */
|
||||
|
||||
#define FUNCTION_ADDRESS 0x7f /* Function address */
|
||||
|
||||
/* Bit masks for USB_POWER */
|
||||
|
||||
#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
|
||||
#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
|
||||
#define RESUME_MODE 0x4 /* DMA Mode */
|
||||
#define RESET 0x8 /* Reset indicator */
|
||||
#define HS_MODE 0x10 /* High Speed mode indicator */
|
||||
#define HS_ENABLE 0x20 /* high Speed Enable */
|
||||
#define SOFT_CONN 0x40 /* Soft connect */
|
||||
#define ISO_UPDATE 0x80 /* Isochronous update */
|
||||
|
||||
/* Bit masks for USB_INTRTX */
|
||||
|
||||
#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
|
||||
#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
|
||||
#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
|
||||
#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
|
||||
#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
|
||||
#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
|
||||
#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
|
||||
#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
|
||||
|
||||
/* Bit masks for USB_INTRRX */
|
||||
|
||||
#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
|
||||
#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
|
||||
#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
|
||||
#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
|
||||
#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
|
||||
#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
|
||||
#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
|
||||
|
||||
/* Bit masks for USB_INTRTXE */
|
||||
|
||||
#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
|
||||
#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
|
||||
#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
|
||||
#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
|
||||
#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
|
||||
#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
|
||||
#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
|
||||
#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
|
||||
|
||||
/* Bit masks for USB_INTRRXE */
|
||||
|
||||
#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
|
||||
#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
|
||||
#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
|
||||
#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
|
||||
#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
|
||||
#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
|
||||
#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
|
||||
|
||||
/* Bit masks for USB_INTRUSB */
|
||||
|
||||
#define SUSPEND_B 0x1 /* Suspend indicator */
|
||||
#define RESUME_B 0x2 /* Resume indicator */
|
||||
#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
|
||||
#define SOF_B 0x8 /* Start of frame */
|
||||
#define CONN_B 0x10 /* Connection indicator */
|
||||
#define DISCON_B 0x20 /* Disconnect indicator */
|
||||
#define SESSION_REQ_B 0x40 /* Session Request */
|
||||
#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
|
||||
|
||||
/* Bit masks for USB_INTRUSBE */
|
||||
|
||||
#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
|
||||
#define RESUME_BE 0x2 /* Resume indicator int enable */
|
||||
#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
|
||||
#define SOF_BE 0x8 /* Start of frame int enable */
|
||||
#define CONN_BE 0x10 /* Connection indicator int enable */
|
||||
#define DISCON_BE 0x20 /* Disconnect indicator int enable */
|
||||
#define SESSION_REQ_BE 0x40 /* Session Request int enable */
|
||||
#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
|
||||
|
||||
/* Bit masks for USB_FRAME */
|
||||
|
||||
#define FRAME_NUMBER 0x7ff /* Frame number */
|
||||
|
||||
/* Bit masks for USB_INDEX */
|
||||
|
||||
#define SELECTED_ENDPOINT 0xf /* selected endpoint */
|
||||
|
||||
/* Bit masks for USB_GLOBAL_CTL */
|
||||
|
||||
#define GLOBAL_ENA 0x1 /* enables USB module */
|
||||
#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
|
||||
#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
|
||||
#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
|
||||
#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
|
||||
#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
|
||||
#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
|
||||
#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
|
||||
#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
|
||||
#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
|
||||
#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
|
||||
#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
|
||||
#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
|
||||
#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
|
||||
#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
|
||||
|
||||
/* Bit masks for USB_OTG_DEV_CTL */
|
||||
|
||||
#define SESSION 0x1 /* session indicator */
|
||||
#define HOST_REQ 0x2 /* Host negotiation request */
|
||||
#define HOST_MODE 0x4 /* indicates USBDRC is a host */
|
||||
#define VBUS0 0x8 /* Vbus level indicator[0] */
|
||||
#define VBUS1 0x10 /* Vbus level indicator[1] */
|
||||
#define LSDEV 0x20 /* Low-speed indicator */
|
||||
#define FSDEV 0x40 /* Full or High-speed indicator */
|
||||
#define B_DEVICE 0x80 /* A' or 'B' device indicator */
|
||||
|
||||
/* Bit masks for USB_OTG_VBUS_IRQ */
|
||||
|
||||
#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
|
||||
#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
|
||||
#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
|
||||
#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
|
||||
#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
|
||||
#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
|
||||
|
||||
/* Bit masks for USB_OTG_VBUS_MASK */
|
||||
|
||||
#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
|
||||
#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
|
||||
#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
|
||||
#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
|
||||
#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
|
||||
#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
|
||||
|
||||
/* Bit masks for USB_CSR0 */
|
||||
|
||||
#define RXPKTRDY 0x1 /* data packet receive indicator */
|
||||
#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
|
||||
#define STALL_SENT 0x4 /* STALL handshake sent */
|
||||
#define DATAEND 0x8 /* Data end indicator */
|
||||
#define SETUPEND 0x10 /* Setup end */
|
||||
#define SENDSTALL 0x20 /* Send STALL handshake */
|
||||
#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
|
||||
#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
|
||||
#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
|
||||
#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
|
||||
#define SETUPPKT_H 0x8 /* send Setup token host mode */
|
||||
#define ERROR_H 0x10 /* timeout error indicator host mode */
|
||||
#define REQPKT_H 0x20 /* Request an IN transaction host mode */
|
||||
#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
|
||||
#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
|
||||
|
||||
/* Bit masks for USB_COUNT0 */
|
||||
|
||||
#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
|
||||
|
||||
/* Bit masks for USB_NAKLIMIT0 */
|
||||
|
||||
#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
|
||||
|
||||
/* Bit masks for USB_TX_MAX_PACKET */
|
||||
|
||||
#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
|
||||
|
||||
/* Bit masks for USB_RX_MAX_PACKET */
|
||||
|
||||
#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
|
||||
|
||||
/* Bit masks for USB_TXCSR */
|
||||
|
||||
#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
|
||||
#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
|
||||
#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
|
||||
#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
|
||||
#define STALL_SEND_T 0x10 /* issue a Stall handshake */
|
||||
#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
|
||||
#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
|
||||
#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
|
||||
#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
|
||||
#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
|
||||
#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
|
||||
#define ISO_T 0x4000 /* enable Isochronous transfers */
|
||||
#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
|
||||
#define ERROR_TH 0x4 /* error condition host mode */
|
||||
#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
|
||||
#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
|
||||
|
||||
/* Bit masks for USB_TXCOUNT */
|
||||
|
||||
#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
|
||||
|
||||
/* Bit masks for USB_RXCSR */
|
||||
|
||||
#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
|
||||
#define FIFO_FULL_R 0x2 /* FIFO not empty */
|
||||
#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
|
||||
#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
|
||||
#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
|
||||
#define STALL_SEND_R 0x20 /* issue a Stall handshake */
|
||||
#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
|
||||
#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
|
||||
#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
|
||||
#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
|
||||
#define DISNYET_R 0x1000 /* disable Nyet handshakes */
|
||||
#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
|
||||
#define ISO_R 0x4000 /* enable Isochronous transfers */
|
||||
#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
|
||||
#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
|
||||
#define REQPKT_RH 0x20 /* request an IN transaction host mode */
|
||||
#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
|
||||
#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
|
||||
#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
|
||||
#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
|
||||
|
||||
/* Bit masks for USB_RXCOUNT */
|
||||
|
||||
#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
|
||||
|
||||
/* Bit masks for USB_TXTYPE */
|
||||
|
||||
#define TARGET_EP_NO_T 0xf /* EP number */
|
||||
#define PROTOCOL_T 0xc /* transfer type */
|
||||
|
||||
/* Bit masks for USB_TXINTERVAL */
|
||||
|
||||
#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
|
||||
|
||||
/* Bit masks for USB_RXTYPE */
|
||||
|
||||
#define TARGET_EP_NO_R 0xf /* EP number */
|
||||
#define PROTOCOL_R 0xc /* transfer type */
|
||||
|
||||
/* Bit masks for USB_RXINTERVAL */
|
||||
|
||||
#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
|
||||
|
||||
/* Bit masks for USB_DMA_INTERRUPT */
|
||||
|
||||
#define DMA0_INT 0x1 /* DMA0 pending interrupt */
|
||||
#define DMA1_INT 0x2 /* DMA1 pending interrupt */
|
||||
#define DMA2_INT 0x4 /* DMA2 pending interrupt */
|
||||
#define DMA3_INT 0x8 /* DMA3 pending interrupt */
|
||||
#define DMA4_INT 0x10 /* DMA4 pending interrupt */
|
||||
#define DMA5_INT 0x20 /* DMA5 pending interrupt */
|
||||
#define DMA6_INT 0x40 /* DMA6 pending interrupt */
|
||||
#define DMA7_INT 0x80 /* DMA7 pending interrupt */
|
||||
|
||||
/* Bit masks for USB_DMAxCONTROL */
|
||||
|
||||
#define DMA_ENA 0x1 /* DMA enable */
|
||||
#define DIRECTION 0x2 /* direction of DMA transfer */
|
||||
#define MODE 0x4 /* DMA Bus error */
|
||||
#define INT_ENA 0x8 /* Interrupt enable */
|
||||
#define EPNUM 0xf0 /* EP number */
|
||||
#define BUSERROR 0x100 /* DMA Bus error */
|
||||
|
||||
/* Bit masks for USB_DMAxADDRHIGH */
|
||||
|
||||
#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
|
||||
|
||||
/* Bit masks for USB_DMAxADDRLOW */
|
||||
|
||||
#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
|
||||
|
||||
/* Bit masks for USB_DMAxCOUNTHIGH */
|
||||
|
||||
#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
|
||||
|
||||
/* Bit masks for USB_DMAxCOUNTLOW */
|
||||
|
||||
#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
|
||||
|
||||
|
||||
/* ******************************************* */
|
||||
/* MULTI BIT MACRO ENUMERATIONS */
|
||||
/* ******************************************* */
|
||||
|
||||
|
||||
#endif /* _DEF_BF542_H */
|
||||
630
arch/blackfin/mach-bf548/include/mach/defBF544.h
Normal file
630
arch/blackfin/mach-bf548/include/mach/defBF544.h
Normal file
|
|
@ -0,0 +1,630 @@
|
|||
/*
|
||||
* Copyright 2007-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the Clear BSD license or the GPL-2 (or later)
|
||||
*/
|
||||
|
||||
#ifndef _DEF_BF544_H
|
||||
#define _DEF_BF544_H
|
||||
|
||||
/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
|
||||
#include "defBF54x_base.h"
|
||||
|
||||
/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
|
||||
|
||||
/* Timer Registers */
|
||||
|
||||
#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
|
||||
#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
|
||||
#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
|
||||
#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
|
||||
#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
|
||||
#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
|
||||
#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
|
||||
#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
|
||||
#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
|
||||
#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
|
||||
#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
|
||||
#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
|
||||
|
||||
/* Timer Group of 3 Registers */
|
||||
|
||||
#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
|
||||
#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
|
||||
#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
|
||||
|
||||
/* EPPI0 Registers */
|
||||
|
||||
#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
|
||||
#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
|
||||
#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
|
||||
#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
|
||||
#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
|
||||
#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
|
||||
#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
|
||||
#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
|
||||
#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
|
||||
#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
|
||||
#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
|
||||
#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
|
||||
#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
|
||||
#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
|
||||
|
||||
/* Two Wire Interface Registers (TWI1) */
|
||||
|
||||
#define TWI1_REGBASE 0xffc02200
|
||||
#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
|
||||
#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
|
||||
#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
|
||||
#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
|
||||
#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
|
||||
#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
|
||||
#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
|
||||
#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
|
||||
#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
|
||||
#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
|
||||
#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
|
||||
#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
|
||||
#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
|
||||
#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
|
||||
#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
|
||||
#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
|
||||
|
||||
/* CAN Controller 1 Config 1 Registers */
|
||||
|
||||
#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
|
||||
#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
|
||||
#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
|
||||
#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
|
||||
#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
|
||||
#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
|
||||
#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
|
||||
#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
|
||||
#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
|
||||
#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
|
||||
#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
|
||||
#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
|
||||
#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
|
||||
|
||||
/* CAN Controller 1 Config 2 Registers */
|
||||
|
||||
#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
|
||||
#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
|
||||
#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
|
||||
#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
|
||||
#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
|
||||
#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
|
||||
#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
|
||||
#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
|
||||
#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
|
||||
#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
|
||||
#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
|
||||
#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
|
||||
#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
|
||||
|
||||
/* CAN Controller 1 Clock/Interrupt/Counter Registers */
|
||||
|
||||
#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
|
||||
#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
|
||||
#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
|
||||
#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
|
||||
#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
|
||||
#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
|
||||
#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
|
||||
#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
|
||||
#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
|
||||
#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
|
||||
#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
|
||||
#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
|
||||
#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
|
||||
#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
|
||||
#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
|
||||
#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
|
||||
|
||||
/* CAN Controller 1 Mailbox Acceptance Registers */
|
||||
|
||||
#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
|
||||
#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
|
||||
#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
|
||||
#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
|
||||
#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
|
||||
#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
|
||||
#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
|
||||
#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
|
||||
#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
|
||||
#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
|
||||
#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
|
||||
#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
|
||||
#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
|
||||
#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
|
||||
#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
|
||||
#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
|
||||
#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
|
||||
#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
|
||||
#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
|
||||
#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
|
||||
#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
|
||||
#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
|
||||
#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
|
||||
#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
|
||||
#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
|
||||
#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
|
||||
#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
|
||||
#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
|
||||
#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
|
||||
#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
|
||||
#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
|
||||
#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
|
||||
|
||||
/* CAN Controller 1 Mailbox Acceptance Registers */
|
||||
|
||||
#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
|
||||
#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
|
||||
#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
|
||||
#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
|
||||
#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
|
||||
#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
|
||||
#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
|
||||
#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
|
||||
#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
|
||||
#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
|
||||
#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
|
||||
#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
|
||||
#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
|
||||
#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
|
||||
#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
|
||||
#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
|
||||
#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
|
||||
#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
|
||||
#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
|
||||
#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
|
||||
#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
|
||||
#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
|
||||
#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
|
||||
#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
|
||||
#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
|
||||
#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
|
||||
#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
|
||||
#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
|
||||
#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
|
||||
#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
|
||||
#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
|
||||
#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
|
||||
|
||||
/* CAN Controller 1 Mailbox Data Registers */
|
||||
|
||||
#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
|
||||
#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
|
||||
#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
|
||||
#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
|
||||
#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
|
||||
#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
|
||||
#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
|
||||
#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
|
||||
#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
|
||||
#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
|
||||
#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
|
||||
#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
|
||||
#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
|
||||
#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
|
||||
#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
|
||||
#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
|
||||
#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
|
||||
#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
|
||||
#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
|
||||
#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
|
||||
#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
|
||||
#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
|
||||
#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
|
||||
#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
|
||||
#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
|
||||
#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
|
||||
#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
|
||||
#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
|
||||
#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
|
||||
#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
|
||||
#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
|
||||
#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
|
||||
#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
|
||||
#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
|
||||
#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
|
||||
#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
|
||||
#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
|
||||
#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
|
||||
#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
|
||||
#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
|
||||
#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
|
||||
#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
|
||||
#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
|
||||
#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
|
||||
#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
|
||||
#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
|
||||
#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
|
||||
#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
|
||||
#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
|
||||
#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
|
||||
#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
|
||||
#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
|
||||
#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
|
||||
#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
|
||||
#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
|
||||
#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
|
||||
#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
|
||||
#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
|
||||
#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
|
||||
#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
|
||||
#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
|
||||
#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
|
||||
#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
|
||||
#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
|
||||
#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
|
||||
#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
|
||||
#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
|
||||
#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
|
||||
#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
|
||||
#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
|
||||
#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
|
||||
#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
|
||||
#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
|
||||
#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
|
||||
#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
|
||||
#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
|
||||
#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
|
||||
#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
|
||||
#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
|
||||
#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
|
||||
#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
|
||||
#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
|
||||
#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
|
||||
#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
|
||||
#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
|
||||
#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
|
||||
#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
|
||||
#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
|
||||
#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
|
||||
#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
|
||||
#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
|
||||
#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
|
||||
#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
|
||||
#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
|
||||
#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
|
||||
#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
|
||||
#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
|
||||
#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
|
||||
#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
|
||||
#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
|
||||
#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
|
||||
#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
|
||||
#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
|
||||
#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
|
||||
#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
|
||||
#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
|
||||
#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
|
||||
#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
|
||||
#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
|
||||
#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
|
||||
#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
|
||||
#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
|
||||
#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
|
||||
#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
|
||||
#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
|
||||
#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
|
||||
#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
|
||||
#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
|
||||
#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
|
||||
#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
|
||||
#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
|
||||
#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
|
||||
#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
|
||||
#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
|
||||
#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
|
||||
#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
|
||||
#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
|
||||
#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
|
||||
|
||||
/* CAN Controller 1 Mailbox Data Registers */
|
||||
|
||||
#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
|
||||
#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
|
||||
#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
|
||||
#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
|
||||
#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
|
||||
#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
|
||||
#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
|
||||
#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
|
||||
#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
|
||||
#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
|
||||
#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
|
||||
#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
|
||||
#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
|
||||
#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
|
||||
#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
|
||||
#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
|
||||
#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
|
||||
#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
|
||||
#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
|
||||
#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
|
||||
#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
|
||||
#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
|
||||
#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
|
||||
#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
|
||||
#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
|
||||
#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
|
||||
#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
|
||||
#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
|
||||
#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
|
||||
#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
|
||||
#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
|
||||
#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
|
||||
#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
|
||||
#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
|
||||
#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
|
||||
#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
|
||||
#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
|
||||
#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
|
||||
#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
|
||||
#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
|
||||
#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
|
||||
#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
|
||||
#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
|
||||
#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
|
||||
#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
|
||||
#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
|
||||
#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
|
||||
#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
|
||||
#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
|
||||
#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
|
||||
#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
|
||||
#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
|
||||
#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
|
||||
#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
|
||||
#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
|
||||
#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
|
||||
#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
|
||||
#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
|
||||
#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
|
||||
#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
|
||||
#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
|
||||
#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
|
||||
#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
|
||||
#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
|
||||
#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
|
||||
#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
|
||||
#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
|
||||
#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
|
||||
#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
|
||||
#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
|
||||
#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
|
||||
#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
|
||||
#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
|
||||
#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
|
||||
#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
|
||||
#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
|
||||
#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
|
||||
#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
|
||||
#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
|
||||
#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
|
||||
#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
|
||||
#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
|
||||
#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
|
||||
#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
|
||||
#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
|
||||
#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
|
||||
#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
|
||||
#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
|
||||
#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
|
||||
#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
|
||||
#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
|
||||
#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
|
||||
#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
|
||||
#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
|
||||
#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
|
||||
#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
|
||||
#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
|
||||
#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
|
||||
#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
|
||||
#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
|
||||
#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
|
||||
#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
|
||||
#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
|
||||
#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
|
||||
#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
|
||||
#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
|
||||
#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
|
||||
#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
|
||||
#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
|
||||
#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
|
||||
#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
|
||||
#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
|
||||
#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
|
||||
#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
|
||||
#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
|
||||
#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
|
||||
#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
|
||||
#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
|
||||
#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
|
||||
#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
|
||||
#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
|
||||
#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
|
||||
#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
|
||||
#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
|
||||
#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
|
||||
#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
|
||||
#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
|
||||
#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
|
||||
|
||||
/* HOST Port Registers */
|
||||
|
||||
#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
|
||||
#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
|
||||
#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
|
||||
|
||||
/* Pixel Compositor (PIXC) Registers */
|
||||
|
||||
#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
|
||||
#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
|
||||
#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
|
||||
#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
|
||||
#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
|
||||
#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
|
||||
#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
|
||||
#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
|
||||
#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
|
||||
#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
|
||||
#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
|
||||
#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
|
||||
#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
|
||||
#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
|
||||
#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
|
||||
#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
|
||||
#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
|
||||
#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
|
||||
#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
|
||||
|
||||
/* Handshake MDMA 0 Registers */
|
||||
|
||||
#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
|
||||
#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
|
||||
#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
|
||||
#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
|
||||
#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
|
||||
#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
|
||||
#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
|
||||
|
||||
/* Handshake MDMA 1 Registers */
|
||||
|
||||
#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
|
||||
#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
|
||||
#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
|
||||
#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
|
||||
#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
|
||||
#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
|
||||
#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
|
||||
|
||||
|
||||
/* ********************************************************** */
|
||||
/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
|
||||
/* and MULTI BIT READ MACROS */
|
||||
/* ********************************************************** */
|
||||
|
||||
/* Bit masks for PIXC_CTL */
|
||||
|
||||
#define PIXC_EN 0x1 /* Pixel Compositor Enable */
|
||||
#define OVR_A_EN 0x2 /* Overlay A Enable */
|
||||
#define OVR_B_EN 0x4 /* Overlay B Enable */
|
||||
#define IMG_FORM 0x8 /* Image Data Format */
|
||||
#define OVR_FORM 0x10 /* Overlay Data Format */
|
||||
#define OUT_FORM 0x20 /* Output Data Format */
|
||||
#define UDS_MOD 0x40 /* Resampling Mode */
|
||||
#define TC_EN 0x80 /* Transparent Color Enable */
|
||||
#define IMG_STAT 0x300 /* Image FIFO Status */
|
||||
#define OVR_STAT 0xc00 /* Overlay FIFO Status */
|
||||
#define WM_LVL 0x3000 /* FIFO Watermark Level */
|
||||
|
||||
/* Bit masks for PIXC_AHSTART */
|
||||
|
||||
#define A_HSTART 0xfff /* Horizontal Start Coordinates */
|
||||
|
||||
/* Bit masks for PIXC_AHEND */
|
||||
|
||||
#define A_HEND 0xfff /* Horizontal End Coordinates */
|
||||
|
||||
/* Bit masks for PIXC_AVSTART */
|
||||
|
||||
#define A_VSTART 0x3ff /* Vertical Start Coordinates */
|
||||
|
||||
/* Bit masks for PIXC_AVEND */
|
||||
|
||||
#define A_VEND 0x3ff /* Vertical End Coordinates */
|
||||
|
||||
/* Bit masks for PIXC_ATRANSP */
|
||||
|
||||
#define A_TRANSP 0xf /* Transparency Value */
|
||||
|
||||
/* Bit masks for PIXC_BHSTART */
|
||||
|
||||
#define B_HSTART 0xfff /* Horizontal Start Coordinates */
|
||||
|
||||
/* Bit masks for PIXC_BHEND */
|
||||
|
||||
#define B_HEND 0xfff /* Horizontal End Coordinates */
|
||||
|
||||
/* Bit masks for PIXC_BVSTART */
|
||||
|
||||
#define B_VSTART 0x3ff /* Vertical Start Coordinates */
|
||||
|
||||
/* Bit masks for PIXC_BVEND */
|
||||
|
||||
#define B_VEND 0x3ff /* Vertical End Coordinates */
|
||||
|
||||
/* Bit masks for PIXC_BTRANSP */
|
||||
|
||||
#define B_TRANSP 0xf /* Transparency Value */
|
||||
|
||||
/* Bit masks for PIXC_INTRSTAT */
|
||||
|
||||
#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
|
||||
#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
|
||||
#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
|
||||
#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
|
||||
|
||||
/* Bit masks for PIXC_RYCON */
|
||||
|
||||
#define A11 0x3ff /* A11 in the Coefficient Matrix */
|
||||
#define A12 0xffc00 /* A12 in the Coefficient Matrix */
|
||||
#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
|
||||
#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
|
||||
|
||||
/* Bit masks for PIXC_GUCON */
|
||||
|
||||
#define A21 0x3ff /* A21 in the Coefficient Matrix */
|
||||
#define A22 0xffc00 /* A22 in the Coefficient Matrix */
|
||||
#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
|
||||
#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
|
||||
|
||||
/* Bit masks for PIXC_BVCON */
|
||||
|
||||
#define A31 0x3ff /* A31 in the Coefficient Matrix */
|
||||
#define A32 0xffc00 /* A32 in the Coefficient Matrix */
|
||||
#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
|
||||
#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
|
||||
|
||||
/* Bit masks for PIXC_CCBIAS */
|
||||
|
||||
#define A14 0x3ff /* A14 in the Bias Vector */
|
||||
#define A24 0xffc00 /* A24 in the Bias Vector */
|
||||
#define A34 0x3ff00000 /* A34 in the Bias Vector */
|
||||
|
||||
/* Bit masks for PIXC_TC */
|
||||
|
||||
#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
|
||||
#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
|
||||
#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
|
||||
|
||||
/* Bit masks for TIMER_ENABLE1 */
|
||||
|
||||
#define TIMEN8 0x1 /* Timer 8 Enable */
|
||||
#define TIMEN9 0x2 /* Timer 9 Enable */
|
||||
#define TIMEN10 0x4 /* Timer 10 Enable */
|
||||
|
||||
/* Bit masks for TIMER_DISABLE1 */
|
||||
|
||||
#define TIMDIS8 0x1 /* Timer 8 Disable */
|
||||
#define TIMDIS9 0x2 /* Timer 9 Disable */
|
||||
#define TIMDIS10 0x4 /* Timer 10 Disable */
|
||||
|
||||
/* Bit masks for TIMER_STATUS1 */
|
||||
|
||||
#define TIMIL8 0x1 /* Timer 8 Interrupt */
|
||||
#define TIMIL9 0x2 /* Timer 9 Interrupt */
|
||||
#define TIMIL10 0x4 /* Timer 10 Interrupt */
|
||||
#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
|
||||
#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
|
||||
#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
|
||||
#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
|
||||
#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
|
||||
#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
|
||||
|
||||
/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
|
||||
|
||||
#endif /* _DEF_BF544_H */
|
||||
1037
arch/blackfin/mach-bf548/include/mach/defBF547.h
Normal file
1037
arch/blackfin/mach-bf548/include/mach/defBF547.h
Normal file
File diff suppressed because it is too large
Load diff
399
arch/blackfin/mach-bf548/include/mach/defBF548.h
Normal file
399
arch/blackfin/mach-bf548/include/mach/defBF548.h
Normal file
|
|
@ -0,0 +1,399 @@
|
|||
/*
|
||||
* Copyright 2007-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the Clear BSD license or the GPL-2 (or later)
|
||||
*/
|
||||
|
||||
#ifndef _DEF_BF548_H
|
||||
#define _DEF_BF548_H
|
||||
|
||||
/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
|
||||
#include "defBF54x_base.h"
|
||||
|
||||
/* The BF548 is like the BF547, but has additional CANs */
|
||||
#include "defBF547.h"
|
||||
|
||||
/* CAN Controller 1 Config 1 Registers */
|
||||
|
||||
#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
|
||||
#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
|
||||
#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
|
||||
#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
|
||||
#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
|
||||
#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
|
||||
#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
|
||||
#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
|
||||
#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
|
||||
#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
|
||||
#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
|
||||
#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
|
||||
#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
|
||||
|
||||
/* CAN Controller 1 Config 2 Registers */
|
||||
|
||||
#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
|
||||
#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
|
||||
#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
|
||||
#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
|
||||
#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
|
||||
#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
|
||||
#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
|
||||
#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
|
||||
#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
|
||||
#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
|
||||
#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
|
||||
#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
|
||||
#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
|
||||
|
||||
/* CAN Controller 1 Clock/Interrupt/Counter Registers */
|
||||
|
||||
#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
|
||||
#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
|
||||
#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
|
||||
#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
|
||||
#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
|
||||
#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
|
||||
#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
|
||||
#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
|
||||
#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
|
||||
#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
|
||||
#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
|
||||
#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
|
||||
#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
|
||||
#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
|
||||
#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
|
||||
#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
|
||||
|
||||
/* CAN Controller 1 Mailbox Acceptance Registers */
|
||||
|
||||
#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
|
||||
#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
|
||||
#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
|
||||
#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
|
||||
#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
|
||||
#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
|
||||
#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
|
||||
#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
|
||||
#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
|
||||
#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
|
||||
#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
|
||||
#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
|
||||
#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
|
||||
#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
|
||||
#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
|
||||
#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
|
||||
#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
|
||||
#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
|
||||
#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
|
||||
#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
|
||||
#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
|
||||
#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
|
||||
#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
|
||||
#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
|
||||
#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
|
||||
#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
|
||||
#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
|
||||
#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
|
||||
#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
|
||||
#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
|
||||
#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
|
||||
#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
|
||||
|
||||
/* CAN Controller 1 Mailbox Acceptance Registers */
|
||||
|
||||
#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
|
||||
#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
|
||||
#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
|
||||
#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
|
||||
#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
|
||||
#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
|
||||
#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
|
||||
#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
|
||||
#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
|
||||
#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
|
||||
#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
|
||||
#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
|
||||
#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
|
||||
#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
|
||||
#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
|
||||
#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
|
||||
#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
|
||||
#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
|
||||
#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
|
||||
#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
|
||||
#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
|
||||
#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
|
||||
#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
|
||||
#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
|
||||
#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
|
||||
#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
|
||||
#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
|
||||
#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
|
||||
#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
|
||||
#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
|
||||
#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
|
||||
#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
|
||||
|
||||
/* CAN Controller 1 Mailbox Data Registers */
|
||||
|
||||
#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
|
||||
#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
|
||||
#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
|
||||
#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
|
||||
#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
|
||||
#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
|
||||
#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
|
||||
#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
|
||||
#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
|
||||
#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
|
||||
#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
|
||||
#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
|
||||
#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
|
||||
#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
|
||||
#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
|
||||
#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
|
||||
#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
|
||||
#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
|
||||
#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
|
||||
#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
|
||||
#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
|
||||
#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
|
||||
#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
|
||||
#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
|
||||
#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
|
||||
#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
|
||||
#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
|
||||
#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
|
||||
#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
|
||||
#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
|
||||
#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
|
||||
#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
|
||||
#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
|
||||
#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
|
||||
#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
|
||||
#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
|
||||
#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
|
||||
#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
|
||||
#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
|
||||
#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
|
||||
#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
|
||||
#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
|
||||
#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
|
||||
#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
|
||||
#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
|
||||
#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
|
||||
#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
|
||||
#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
|
||||
#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
|
||||
#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
|
||||
#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
|
||||
#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
|
||||
#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
|
||||
#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
|
||||
#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
|
||||
#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
|
||||
#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
|
||||
#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
|
||||
#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
|
||||
#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
|
||||
#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
|
||||
#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
|
||||
#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
|
||||
#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
|
||||
#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
|
||||
#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
|
||||
#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
|
||||
#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
|
||||
#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
|
||||
#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
|
||||
#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
|
||||
#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
|
||||
#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
|
||||
#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
|
||||
#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
|
||||
#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
|
||||
#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
|
||||
#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
|
||||
#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
|
||||
#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
|
||||
#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
|
||||
#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
|
||||
#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
|
||||
#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
|
||||
#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
|
||||
#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
|
||||
#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
|
||||
#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
|
||||
#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
|
||||
#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
|
||||
#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
|
||||
#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
|
||||
#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
|
||||
#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
|
||||
#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
|
||||
#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
|
||||
#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
|
||||
#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
|
||||
#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
|
||||
#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
|
||||
#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
|
||||
#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
|
||||
#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
|
||||
#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
|
||||
#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
|
||||
#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
|
||||
#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
|
||||
#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
|
||||
#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
|
||||
#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
|
||||
#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
|
||||
#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
|
||||
#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
|
||||
#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
|
||||
#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
|
||||
#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
|
||||
#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
|
||||
#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
|
||||
#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
|
||||
#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
|
||||
#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
|
||||
#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
|
||||
#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
|
||||
#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
|
||||
#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
|
||||
#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
|
||||
#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
|
||||
#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
|
||||
|
||||
/* CAN Controller 1 Mailbox Data Registers */
|
||||
|
||||
#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
|
||||
#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
|
||||
#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
|
||||
#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
|
||||
#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
|
||||
#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
|
||||
#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
|
||||
#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
|
||||
#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
|
||||
#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
|
||||
#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
|
||||
#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
|
||||
#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
|
||||
#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
|
||||
#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
|
||||
#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
|
||||
#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
|
||||
#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
|
||||
#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
|
||||
#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
|
||||
#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
|
||||
#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
|
||||
#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
|
||||
#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
|
||||
#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
|
||||
#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
|
||||
#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
|
||||
#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
|
||||
#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
|
||||
#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
|
||||
#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
|
||||
#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
|
||||
#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
|
||||
#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
|
||||
#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
|
||||
#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
|
||||
#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
|
||||
#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
|
||||
#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
|
||||
#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
|
||||
#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
|
||||
#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
|
||||
#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
|
||||
#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
|
||||
#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
|
||||
#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
|
||||
#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
|
||||
#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
|
||||
#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
|
||||
#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
|
||||
#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
|
||||
#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
|
||||
#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
|
||||
#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
|
||||
#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
|
||||
#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
|
||||
#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
|
||||
#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
|
||||
#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
|
||||
#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
|
||||
#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
|
||||
#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
|
||||
#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
|
||||
#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
|
||||
#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
|
||||
#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
|
||||
#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
|
||||
#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
|
||||
#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
|
||||
#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
|
||||
#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
|
||||
#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
|
||||
#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
|
||||
#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
|
||||
#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
|
||||
#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
|
||||
#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
|
||||
#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
|
||||
#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
|
||||
#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
|
||||
#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
|
||||
#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
|
||||
#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
|
||||
#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
|
||||
#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
|
||||
#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
|
||||
#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
|
||||
#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
|
||||
#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
|
||||
#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
|
||||
#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
|
||||
#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
|
||||
#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
|
||||
#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
|
||||
#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
|
||||
#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
|
||||
#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
|
||||
#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
|
||||
#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
|
||||
#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
|
||||
#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
|
||||
#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
|
||||
#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
|
||||
#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
|
||||
#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
|
||||
#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
|
||||
#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
|
||||
#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
|
||||
#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
|
||||
#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
|
||||
#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
|
||||
#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
|
||||
#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
|
||||
#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
|
||||
#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
|
||||
#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
|
||||
#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
|
||||
#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
|
||||
#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
|
||||
#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
|
||||
#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
|
||||
#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
|
||||
#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
|
||||
#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
|
||||
#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
|
||||
#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
|
||||
#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
|
||||
#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
|
||||
|
||||
#endif /* _DEF_BF548_H */
|
||||
186
arch/blackfin/mach-bf548/include/mach/defBF549.h
Normal file
186
arch/blackfin/mach-bf548/include/mach/defBF549.h
Normal file
|
|
@ -0,0 +1,186 @@
|
|||
/*
|
||||
* Copyright 2007-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the Clear BSD license or the GPL-2 (or later)
|
||||
*/
|
||||
|
||||
#ifndef _DEF_BF549_H
|
||||
#define _DEF_BF549_H
|
||||
|
||||
/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
|
||||
#include "defBF54x_base.h"
|
||||
|
||||
/* The BF549 is like the BF544, but has MXVR */
|
||||
#include "defBF547.h"
|
||||
|
||||
/* MXVR Registers */
|
||||
|
||||
#define MXVR_CONFIG 0xffc02700 /* MXVR Configuration Register */
|
||||
#define MXVR_STATE_0 0xffc02708 /* MXVR State Register 0 */
|
||||
#define MXVR_STATE_1 0xffc0270c /* MXVR State Register 1 */
|
||||
#define MXVR_INT_STAT_0 0xffc02710 /* MXVR Interrupt Status Register 0 */
|
||||
#define MXVR_INT_STAT_1 0xffc02714 /* MXVR Interrupt Status Register 1 */
|
||||
#define MXVR_INT_EN_0 0xffc02718 /* MXVR Interrupt Enable Register 0 */
|
||||
#define MXVR_INT_EN_1 0xffc0271c /* MXVR Interrupt Enable Register 1 */
|
||||
#define MXVR_POSITION 0xffc02720 /* MXVR Node Position Register */
|
||||
#define MXVR_MAX_POSITION 0xffc02724 /* MXVR Maximum Node Position Register */
|
||||
#define MXVR_DELAY 0xffc02728 /* MXVR Node Frame Delay Register */
|
||||
#define MXVR_MAX_DELAY 0xffc0272c /* MXVR Maximum Node Frame Delay Register */
|
||||
#define MXVR_LADDR 0xffc02730 /* MXVR Logical Address Register */
|
||||
#define MXVR_GADDR 0xffc02734 /* MXVR Group Address Register */
|
||||
#define MXVR_AADDR 0xffc02738 /* MXVR Alternate Address Register */
|
||||
|
||||
/* MXVR Allocation Table Registers */
|
||||
|
||||
#define MXVR_ALLOC_0 0xffc0273c /* MXVR Allocation Table Register 0 */
|
||||
#define MXVR_ALLOC_1 0xffc02740 /* MXVR Allocation Table Register 1 */
|
||||
#define MXVR_ALLOC_2 0xffc02744 /* MXVR Allocation Table Register 2 */
|
||||
#define MXVR_ALLOC_3 0xffc02748 /* MXVR Allocation Table Register 3 */
|
||||
#define MXVR_ALLOC_4 0xffc0274c /* MXVR Allocation Table Register 4 */
|
||||
#define MXVR_ALLOC_5 0xffc02750 /* MXVR Allocation Table Register 5 */
|
||||
#define MXVR_ALLOC_6 0xffc02754 /* MXVR Allocation Table Register 6 */
|
||||
#define MXVR_ALLOC_7 0xffc02758 /* MXVR Allocation Table Register 7 */
|
||||
#define MXVR_ALLOC_8 0xffc0275c /* MXVR Allocation Table Register 8 */
|
||||
#define MXVR_ALLOC_9 0xffc02760 /* MXVR Allocation Table Register 9 */
|
||||
#define MXVR_ALLOC_10 0xffc02764 /* MXVR Allocation Table Register 10 */
|
||||
#define MXVR_ALLOC_11 0xffc02768 /* MXVR Allocation Table Register 11 */
|
||||
#define MXVR_ALLOC_12 0xffc0276c /* MXVR Allocation Table Register 12 */
|
||||
#define MXVR_ALLOC_13 0xffc02770 /* MXVR Allocation Table Register 13 */
|
||||
#define MXVR_ALLOC_14 0xffc02774 /* MXVR Allocation Table Register 14 */
|
||||
|
||||
/* MXVR Channel Assign Registers */
|
||||
|
||||
#define MXVR_SYNC_LCHAN_0 0xffc02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
|
||||
#define MXVR_SYNC_LCHAN_1 0xffc0277c /* MXVR Sync Data Logical Channel Assign Register 1 */
|
||||
#define MXVR_SYNC_LCHAN_2 0xffc02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
|
||||
#define MXVR_SYNC_LCHAN_3 0xffc02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
|
||||
#define MXVR_SYNC_LCHAN_4 0xffc02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
|
||||
#define MXVR_SYNC_LCHAN_5 0xffc0278c /* MXVR Sync Data Logical Channel Assign Register 5 */
|
||||
#define MXVR_SYNC_LCHAN_6 0xffc02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
|
||||
#define MXVR_SYNC_LCHAN_7 0xffc02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
|
||||
|
||||
/* MXVR DMA0 Registers */
|
||||
|
||||
#define MXVR_DMA0_CONFIG 0xffc02798 /* MXVR Sync Data DMA0 Config Register */
|
||||
#define MXVR_DMA0_START_ADDR 0xffc0279c /* MXVR Sync Data DMA0 Start Address */
|
||||
#define MXVR_DMA0_COUNT 0xffc027a0 /* MXVR Sync Data DMA0 Loop Count Register */
|
||||
#define MXVR_DMA0_CURR_ADDR 0xffc027a4 /* MXVR Sync Data DMA0 Current Address */
|
||||
#define MXVR_DMA0_CURR_COUNT 0xffc027a8 /* MXVR Sync Data DMA0 Current Loop Count */
|
||||
|
||||
/* MXVR DMA1 Registers */
|
||||
|
||||
#define MXVR_DMA1_CONFIG 0xffc027ac /* MXVR Sync Data DMA1 Config Register */
|
||||
#define MXVR_DMA1_START_ADDR 0xffc027b0 /* MXVR Sync Data DMA1 Start Address */
|
||||
#define MXVR_DMA1_COUNT 0xffc027b4 /* MXVR Sync Data DMA1 Loop Count Register */
|
||||
#define MXVR_DMA1_CURR_ADDR 0xffc027b8 /* MXVR Sync Data DMA1 Current Address */
|
||||
#define MXVR_DMA1_CURR_COUNT 0xffc027bc /* MXVR Sync Data DMA1 Current Loop Count */
|
||||
|
||||
/* MXVR DMA2 Registers */
|
||||
|
||||
#define MXVR_DMA2_CONFIG 0xffc027c0 /* MXVR Sync Data DMA2 Config Register */
|
||||
#define MXVR_DMA2_START_ADDR 0xffc027c4 /* MXVR Sync Data DMA2 Start Address */
|
||||
#define MXVR_DMA2_COUNT 0xffc027c8 /* MXVR Sync Data DMA2 Loop Count Register */
|
||||
#define MXVR_DMA2_CURR_ADDR 0xffc027cc /* MXVR Sync Data DMA2 Current Address */
|
||||
#define MXVR_DMA2_CURR_COUNT 0xffc027d0 /* MXVR Sync Data DMA2 Current Loop Count */
|
||||
|
||||
/* MXVR DMA3 Registers */
|
||||
|
||||
#define MXVR_DMA3_CONFIG 0xffc027d4 /* MXVR Sync Data DMA3 Config Register */
|
||||
#define MXVR_DMA3_START_ADDR 0xffc027d8 /* MXVR Sync Data DMA3 Start Address */
|
||||
#define MXVR_DMA3_COUNT 0xffc027dc /* MXVR Sync Data DMA3 Loop Count Register */
|
||||
#define MXVR_DMA3_CURR_ADDR 0xffc027e0 /* MXVR Sync Data DMA3 Current Address */
|
||||
#define MXVR_DMA3_CURR_COUNT 0xffc027e4 /* MXVR Sync Data DMA3 Current Loop Count */
|
||||
|
||||
/* MXVR DMA4 Registers */
|
||||
|
||||
#define MXVR_DMA4_CONFIG 0xffc027e8 /* MXVR Sync Data DMA4 Config Register */
|
||||
#define MXVR_DMA4_START_ADDR 0xffc027ec /* MXVR Sync Data DMA4 Start Address */
|
||||
#define MXVR_DMA4_COUNT 0xffc027f0 /* MXVR Sync Data DMA4 Loop Count Register */
|
||||
#define MXVR_DMA4_CURR_ADDR 0xffc027f4 /* MXVR Sync Data DMA4 Current Address */
|
||||
#define MXVR_DMA4_CURR_COUNT 0xffc027f8 /* MXVR Sync Data DMA4 Current Loop Count */
|
||||
|
||||
/* MXVR DMA5 Registers */
|
||||
|
||||
#define MXVR_DMA5_CONFIG 0xffc027fc /* MXVR Sync Data DMA5 Config Register */
|
||||
#define MXVR_DMA5_START_ADDR 0xffc02800 /* MXVR Sync Data DMA5 Start Address */
|
||||
#define MXVR_DMA5_COUNT 0xffc02804 /* MXVR Sync Data DMA5 Loop Count Register */
|
||||
#define MXVR_DMA5_CURR_ADDR 0xffc02808 /* MXVR Sync Data DMA5 Current Address */
|
||||
#define MXVR_DMA5_CURR_COUNT 0xffc0280c /* MXVR Sync Data DMA5 Current Loop Count */
|
||||
|
||||
/* MXVR DMA6 Registers */
|
||||
|
||||
#define MXVR_DMA6_CONFIG 0xffc02810 /* MXVR Sync Data DMA6 Config Register */
|
||||
#define MXVR_DMA6_START_ADDR 0xffc02814 /* MXVR Sync Data DMA6 Start Address */
|
||||
#define MXVR_DMA6_COUNT 0xffc02818 /* MXVR Sync Data DMA6 Loop Count Register */
|
||||
#define MXVR_DMA6_CURR_ADDR 0xffc0281c /* MXVR Sync Data DMA6 Current Address */
|
||||
#define MXVR_DMA6_CURR_COUNT 0xffc02820 /* MXVR Sync Data DMA6 Current Loop Count */
|
||||
|
||||
/* MXVR DMA7 Registers */
|
||||
|
||||
#define MXVR_DMA7_CONFIG 0xffc02824 /* MXVR Sync Data DMA7 Config Register */
|
||||
#define MXVR_DMA7_START_ADDR 0xffc02828 /* MXVR Sync Data DMA7 Start Address */
|
||||
#define MXVR_DMA7_COUNT 0xffc0282c /* MXVR Sync Data DMA7 Loop Count Register */
|
||||
#define MXVR_DMA7_CURR_ADDR 0xffc02830 /* MXVR Sync Data DMA7 Current Address */
|
||||
#define MXVR_DMA7_CURR_COUNT 0xffc02834 /* MXVR Sync Data DMA7 Current Loop Count */
|
||||
|
||||
/* MXVR Asynch Packet Registers */
|
||||
|
||||
#define MXVR_AP_CTL 0xffc02838 /* MXVR Async Packet Control Register */
|
||||
#define MXVR_APRB_START_ADDR 0xffc0283c /* MXVR Async Packet RX Buffer Start Addr Register */
|
||||
#define MXVR_APRB_CURR_ADDR 0xffc02840 /* MXVR Async Packet RX Buffer Current Addr Register */
|
||||
#define MXVR_APTB_START_ADDR 0xffc02844 /* MXVR Async Packet TX Buffer Start Addr Register */
|
||||
#define MXVR_APTB_CURR_ADDR 0xffc02848 /* MXVR Async Packet TX Buffer Current Addr Register */
|
||||
|
||||
/* MXVR Control Message Registers */
|
||||
|
||||
#define MXVR_CM_CTL 0xffc0284c /* MXVR Control Message Control Register */
|
||||
#define MXVR_CMRB_START_ADDR 0xffc02850 /* MXVR Control Message RX Buffer Start Addr Register */
|
||||
#define MXVR_CMRB_CURR_ADDR 0xffc02854 /* MXVR Control Message RX Buffer Current Address */
|
||||
#define MXVR_CMTB_START_ADDR 0xffc02858 /* MXVR Control Message TX Buffer Start Addr Register */
|
||||
#define MXVR_CMTB_CURR_ADDR 0xffc0285c /* MXVR Control Message TX Buffer Current Address */
|
||||
|
||||
/* MXVR Remote Read Registers */
|
||||
|
||||
#define MXVR_RRDB_START_ADDR 0xffc02860 /* MXVR Remote Read Buffer Start Addr Register */
|
||||
#define MXVR_RRDB_CURR_ADDR 0xffc02864 /* MXVR Remote Read Buffer Current Addr Register */
|
||||
|
||||
/* MXVR Pattern Data Registers */
|
||||
|
||||
#define MXVR_PAT_DATA_0 0xffc02868 /* MXVR Pattern Data Register 0 */
|
||||
#define MXVR_PAT_EN_0 0xffc0286c /* MXVR Pattern Enable Register 0 */
|
||||
#define MXVR_PAT_DATA_1 0xffc02870 /* MXVR Pattern Data Register 1 */
|
||||
#define MXVR_PAT_EN_1 0xffc02874 /* MXVR Pattern Enable Register 1 */
|
||||
|
||||
/* MXVR Frame Counter Registers */
|
||||
|
||||
#define MXVR_FRAME_CNT_0 0xffc02878 /* MXVR Frame Counter 0 */
|
||||
#define MXVR_FRAME_CNT_1 0xffc0287c /* MXVR Frame Counter 1 */
|
||||
|
||||
/* MXVR Routing Table Registers */
|
||||
|
||||
#define MXVR_ROUTING_0 0xffc02880 /* MXVR Routing Table Register 0 */
|
||||
#define MXVR_ROUTING_1 0xffc02884 /* MXVR Routing Table Register 1 */
|
||||
#define MXVR_ROUTING_2 0xffc02888 /* MXVR Routing Table Register 2 */
|
||||
#define MXVR_ROUTING_3 0xffc0288c /* MXVR Routing Table Register 3 */
|
||||
#define MXVR_ROUTING_4 0xffc02890 /* MXVR Routing Table Register 4 */
|
||||
#define MXVR_ROUTING_5 0xffc02894 /* MXVR Routing Table Register 5 */
|
||||
#define MXVR_ROUTING_6 0xffc02898 /* MXVR Routing Table Register 6 */
|
||||
#define MXVR_ROUTING_7 0xffc0289c /* MXVR Routing Table Register 7 */
|
||||
#define MXVR_ROUTING_8 0xffc028a0 /* MXVR Routing Table Register 8 */
|
||||
#define MXVR_ROUTING_9 0xffc028a4 /* MXVR Routing Table Register 9 */
|
||||
#define MXVR_ROUTING_10 0xffc028a8 /* MXVR Routing Table Register 10 */
|
||||
#define MXVR_ROUTING_11 0xffc028ac /* MXVR Routing Table Register 11 */
|
||||
#define MXVR_ROUTING_12 0xffc028b0 /* MXVR Routing Table Register 12 */
|
||||
#define MXVR_ROUTING_13 0xffc028b4 /* MXVR Routing Table Register 13 */
|
||||
#define MXVR_ROUTING_14 0xffc028b8 /* MXVR Routing Table Register 14 */
|
||||
|
||||
/* MXVR Counter-Clock-Control Registers */
|
||||
|
||||
#define MXVR_BLOCK_CNT 0xffc028c0 /* MXVR Block Counter */
|
||||
#define MXVR_CLK_CTL 0xffc028d0 /* MXVR Clock Control Register */
|
||||
#define MXVR_CDRPLL_CTL 0xffc028d4 /* MXVR Clock/Data Recovery PLL Control Register */
|
||||
#define MXVR_FMPLL_CTL 0xffc028d8 /* MXVR Frequency Multiply PLL Control Register */
|
||||
#define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */
|
||||
#define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */
|
||||
|
||||
#endif /* _DEF_BF549_H */
|
||||
2294
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
Normal file
2294
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
Normal file
File diff suppressed because it is too large
Load diff
72
arch/blackfin/mach-bf548/include/mach/dma.h
Normal file
72
arch/blackfin/mach-bf548/include/mach/dma.h
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
/* mach/dma.h - arch-specific DMA defines
|
||||
*
|
||||
* Copyright 2004-2008 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_DMA_H_
|
||||
#define _MACH_DMA_H_
|
||||
|
||||
#define CH_SPORT0_RX 0
|
||||
#define CH_SPORT0_TX 1
|
||||
#define CH_SPORT1_RX 2
|
||||
#define CH_SPORT1_TX 3
|
||||
#define CH_SPI0 4
|
||||
#define CH_SPI1 5
|
||||
#define CH_UART0_RX 6
|
||||
#define CH_UART0_TX 7
|
||||
#define CH_UART1_RX 8
|
||||
#define CH_UART1_TX 9
|
||||
#define CH_ATAPI_RX 10
|
||||
#define CH_ATAPI_TX 11
|
||||
#define CH_EPPI0 12
|
||||
#define CH_EPPI1 13
|
||||
#define CH_EPPI2 14
|
||||
#define CH_PIXC_IMAGE 15
|
||||
#define CH_PIXC_OVERLAY 16
|
||||
#define CH_PIXC_OUTPUT 17
|
||||
#define CH_SPORT2_RX 18
|
||||
#define CH_SPORT2_TX 19
|
||||
#define CH_SPORT3_RX 20
|
||||
#define CH_SPORT3_TX 21
|
||||
#define CH_SDH 22
|
||||
#define CH_NFC 22
|
||||
#define CH_SPI2 23
|
||||
|
||||
#if defined(CONFIG_UART2_DMA_RX_ON_DMA13)
|
||||
#define CH_UART2_RX 13
|
||||
#define IRQ_UART2_RX BFIN_IRQ(37) /* UART2 RX USE EPP1 (DMA13) Interrupt */
|
||||
#define CH_UART2_TX 14
|
||||
#define IRQ_UART2_TX BFIN_IRQ(38) /* UART2 RX USE EPP1 (DMA14) Interrupt */
|
||||
#else /* Default USE SPORT2's DMA Channel */
|
||||
#define CH_UART2_RX 18
|
||||
#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
|
||||
#define CH_UART2_TX 19
|
||||
#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_UART3_DMA_RX_ON_DMA15)
|
||||
#define CH_UART3_RX 15
|
||||
#define IRQ_UART3_RX BFIN_IRQ(64) /* UART3 RX USE PIXC IN0 (DMA15) Interrupt */
|
||||
#define CH_UART3_TX 16
|
||||
#define IRQ_UART3_TX BFIN_IRQ(65) /* UART3 TX USE PIXC IN1 (DMA16) Interrupt */
|
||||
#else /* Default USE SPORT3's DMA Channel */
|
||||
#define CH_UART3_RX 20
|
||||
#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
|
||||
#define CH_UART3_TX 21
|
||||
#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
|
||||
#endif
|
||||
|
||||
#define CH_MEM_STREAM0_DEST 24
|
||||
#define CH_MEM_STREAM0_SRC 25
|
||||
#define CH_MEM_STREAM1_DEST 26
|
||||
#define CH_MEM_STREAM1_SRC 27
|
||||
#define CH_MEM_STREAM2_DEST 28
|
||||
#define CH_MEM_STREAM2_SRC 29
|
||||
#define CH_MEM_STREAM3_DEST 30
|
||||
#define CH_MEM_STREAM3_SRC 31
|
||||
|
||||
#define MAX_DMA_CHANNELS 32
|
||||
|
||||
#endif
|
||||
210
arch/blackfin/mach-bf548/include/mach/gpio.h
Normal file
210
arch/blackfin/mach-bf548/include/mach/gpio.h
Normal file
|
|
@ -0,0 +1,210 @@
|
|||
/*
|
||||
* Copyright 2007-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACH_GPIO_H_
|
||||
#define _MACH_GPIO_H_
|
||||
|
||||
#define GPIO_PA0 0
|
||||
#define GPIO_PA1 1
|
||||
#define GPIO_PA2 2
|
||||
#define GPIO_PA3 3
|
||||
#define GPIO_PA4 4
|
||||
#define GPIO_PA5 5
|
||||
#define GPIO_PA6 6
|
||||
#define GPIO_PA7 7
|
||||
#define GPIO_PA8 8
|
||||
#define GPIO_PA9 9
|
||||
#define GPIO_PA10 10
|
||||
#define GPIO_PA11 11
|
||||
#define GPIO_PA12 12
|
||||
#define GPIO_PA13 13
|
||||
#define GPIO_PA14 14
|
||||
#define GPIO_PA15 15
|
||||
#define GPIO_PB0 16
|
||||
#define GPIO_PB1 17
|
||||
#define GPIO_PB2 18
|
||||
#define GPIO_PB3 19
|
||||
#define GPIO_PB4 20
|
||||
#define GPIO_PB5 21
|
||||
#define GPIO_PB6 22
|
||||
#define GPIO_PB7 23
|
||||
#define GPIO_PB8 24
|
||||
#define GPIO_PB9 25
|
||||
#define GPIO_PB10 26
|
||||
#define GPIO_PB11 27
|
||||
#define GPIO_PB12 28
|
||||
#define GPIO_PB13 29
|
||||
#define GPIO_PB14 30
|
||||
#define GPIO_PB15 31 /* N/A */
|
||||
#define GPIO_PC0 32
|
||||
#define GPIO_PC1 33
|
||||
#define GPIO_PC2 34
|
||||
#define GPIO_PC3 35
|
||||
#define GPIO_PC4 36
|
||||
#define GPIO_PC5 37
|
||||
#define GPIO_PC6 38
|
||||
#define GPIO_PC7 39
|
||||
#define GPIO_PC8 40
|
||||
#define GPIO_PC9 41
|
||||
#define GPIO_PC10 42
|
||||
#define GPIO_PC11 43
|
||||
#define GPIO_PC12 44
|
||||
#define GPIO_PC13 45
|
||||
#define GPIO_PC14 46 /* N/A */
|
||||
#define GPIO_PC15 47 /* N/A */
|
||||
#define GPIO_PD0 48
|
||||
#define GPIO_PD1 49
|
||||
#define GPIO_PD2 50
|
||||
#define GPIO_PD3 51
|
||||
#define GPIO_PD4 52
|
||||
#define GPIO_PD5 53
|
||||
#define GPIO_PD6 54
|
||||
#define GPIO_PD7 55
|
||||
#define GPIO_PD8 56
|
||||
#define GPIO_PD9 57
|
||||
#define GPIO_PD10 58
|
||||
#define GPIO_PD11 59
|
||||
#define GPIO_PD12 60
|
||||
#define GPIO_PD13 61
|
||||
#define GPIO_PD14 62
|
||||
#define GPIO_PD15 63
|
||||
#define GPIO_PE0 64
|
||||
#define GPIO_PE1 65
|
||||
#define GPIO_PE2 66
|
||||
#define GPIO_PE3 67
|
||||
#define GPIO_PE4 68
|
||||
#define GPIO_PE5 69
|
||||
#define GPIO_PE6 70
|
||||
#define GPIO_PE7 71
|
||||
#define GPIO_PE8 72
|
||||
#define GPIO_PE9 73
|
||||
#define GPIO_PE10 74
|
||||
#define GPIO_PE11 75
|
||||
#define GPIO_PE12 76
|
||||
#define GPIO_PE13 77
|
||||
#define GPIO_PE14 78
|
||||
#define GPIO_PE15 79
|
||||
#define GPIO_PF0 80
|
||||
#define GPIO_PF1 81
|
||||
#define GPIO_PF2 82
|
||||
#define GPIO_PF3 83
|
||||
#define GPIO_PF4 84
|
||||
#define GPIO_PF5 85
|
||||
#define GPIO_PF6 86
|
||||
#define GPIO_PF7 87
|
||||
#define GPIO_PF8 88
|
||||
#define GPIO_PF9 89
|
||||
#define GPIO_PF10 90
|
||||
#define GPIO_PF11 91
|
||||
#define GPIO_PF12 92
|
||||
#define GPIO_PF13 93
|
||||
#define GPIO_PF14 94
|
||||
#define GPIO_PF15 95
|
||||
#define GPIO_PG0 96
|
||||
#define GPIO_PG1 97
|
||||
#define GPIO_PG2 98
|
||||
#define GPIO_PG3 99
|
||||
#define GPIO_PG4 100
|
||||
#define GPIO_PG5 101
|
||||
#define GPIO_PG6 102
|
||||
#define GPIO_PG7 103
|
||||
#define GPIO_PG8 104
|
||||
#define GPIO_PG9 105
|
||||
#define GPIO_PG10 106
|
||||
#define GPIO_PG11 107
|
||||
#define GPIO_PG12 108
|
||||
#define GPIO_PG13 109
|
||||
#define GPIO_PG14 110
|
||||
#define GPIO_PG15 111
|
||||
#define GPIO_PH0 112
|
||||
#define GPIO_PH1 113
|
||||
#define GPIO_PH2 114
|
||||
#define GPIO_PH3 115
|
||||
#define GPIO_PH4 116
|
||||
#define GPIO_PH5 117
|
||||
#define GPIO_PH6 118
|
||||
#define GPIO_PH7 119
|
||||
#define GPIO_PH8 120
|
||||
#define GPIO_PH9 121
|
||||
#define GPIO_PH10 122
|
||||
#define GPIO_PH11 123
|
||||
#define GPIO_PH12 124
|
||||
#define GPIO_PH13 125
|
||||
#define GPIO_PH14 126 /* N/A */
|
||||
#define GPIO_PH15 127 /* N/A */
|
||||
#define GPIO_PI0 128
|
||||
#define GPIO_PI1 129
|
||||
#define GPIO_PI2 130
|
||||
#define GPIO_PI3 131
|
||||
#define GPIO_PI4 132
|
||||
#define GPIO_PI5 133
|
||||
#define GPIO_PI6 134
|
||||
#define GPIO_PI7 135
|
||||
#define GPIO_PI8 136
|
||||
#define GPIO_PI9 137
|
||||
#define GPIO_PI10 138
|
||||
#define GPIO_PI11 139
|
||||
#define GPIO_PI12 140
|
||||
#define GPIO_PI13 141
|
||||
#define GPIO_PI14 142
|
||||
#define GPIO_PI15 143
|
||||
#define GPIO_PJ0 144
|
||||
#define GPIO_PJ1 145
|
||||
#define GPIO_PJ2 146
|
||||
#define GPIO_PJ3 147
|
||||
#define GPIO_PJ4 148
|
||||
#define GPIO_PJ5 149
|
||||
#define GPIO_PJ6 150
|
||||
#define GPIO_PJ7 151
|
||||
#define GPIO_PJ8 152
|
||||
#define GPIO_PJ9 153
|
||||
#define GPIO_PJ10 154
|
||||
#define GPIO_PJ11 155
|
||||
#define GPIO_PJ12 156
|
||||
#define GPIO_PJ13 157
|
||||
#define GPIO_PJ14 158 /* N/A */
|
||||
#define GPIO_PJ15 159 /* N/A */
|
||||
|
||||
#define MAX_BLACKFIN_GPIOS 160
|
||||
|
||||
#define BFIN_GPIO_PINT 1
|
||||
#define NR_PINT_SYS_IRQS 4
|
||||
#define NR_PINTS 160
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
struct gpio_port_t {
|
||||
unsigned short port_fer;
|
||||
unsigned short dummy1;
|
||||
unsigned short data;
|
||||
unsigned short dummy2;
|
||||
unsigned short data_set;
|
||||
unsigned short dummy3;
|
||||
unsigned short data_clear;
|
||||
unsigned short dummy4;
|
||||
unsigned short dir_set;
|
||||
unsigned short dummy5;
|
||||
unsigned short dir_clear;
|
||||
unsigned short dummy6;
|
||||
unsigned short inen;
|
||||
unsigned short dummy7;
|
||||
unsigned int port_mux;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#include <mach-common/ports-a.h>
|
||||
#include <mach-common/ports-b.h>
|
||||
#include <mach-common/ports-c.h>
|
||||
#include <mach-common/ports-d.h>
|
||||
#include <mach-common/ports-e.h>
|
||||
#include <mach-common/ports-f.h>
|
||||
#include <mach-common/ports-g.h>
|
||||
#include <mach-common/ports-h.h>
|
||||
#include <mach-common/ports-i.h>
|
||||
#include <mach-common/ports-j.h>
|
||||
|
||||
#endif /* _MACH_GPIO_H_ */
|
||||
454
arch/blackfin/mach-bf548/include/mach/irq.h
Normal file
454
arch/blackfin/mach-bf548/include/mach/irq.h
Normal file
|
|
@ -0,0 +1,454 @@
|
|||
/*
|
||||
* Copyright 2007-2009 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _BF548_IRQ_H_
|
||||
#define _BF548_IRQ_H_
|
||||
|
||||
#include <mach-common/irq.h>
|
||||
|
||||
#define NR_PERI_INTS (3 * 32)
|
||||
|
||||
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
|
||||
#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
|
||||
#define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */
|
||||
#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
|
||||
#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
|
||||
#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */
|
||||
#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */
|
||||
#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
|
||||
#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */
|
||||
#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */
|
||||
#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */
|
||||
#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */
|
||||
#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */
|
||||
#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */
|
||||
#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */
|
||||
#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */
|
||||
#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */
|
||||
#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */
|
||||
#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */
|
||||
#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */
|
||||
#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
|
||||
#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
|
||||
#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
|
||||
#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */
|
||||
#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
|
||||
#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
|
||||
#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
|
||||
#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */
|
||||
#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */
|
||||
#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */
|
||||
#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */
|
||||
#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
|
||||
#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
|
||||
#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
|
||||
#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
|
||||
#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
|
||||
#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
|
||||
#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
|
||||
#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
|
||||
#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
|
||||
#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */
|
||||
#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */
|
||||
#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */
|
||||
#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */
|
||||
#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */
|
||||
#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */
|
||||
#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */
|
||||
#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */
|
||||
#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */
|
||||
#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */
|
||||
#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */
|
||||
#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */
|
||||
#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */
|
||||
#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */
|
||||
#define IRQ_EPPI1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */
|
||||
#define IRQ_EPPI2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */
|
||||
#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */
|
||||
#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */
|
||||
#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */
|
||||
#define IRQ_NFC_ERROR BFIN_IRQ(60) /* NFC Error Interrupt */
|
||||
#define IRQ_ATAPI_ERROR BFIN_IRQ(61) /* ATAPI Error Interrupt */
|
||||
#define IRQ_CAN1_ERROR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */
|
||||
#define IRQ_HS_DMA_ERROR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */
|
||||
#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */
|
||||
#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */
|
||||
#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */
|
||||
#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */
|
||||
#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */
|
||||
#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */
|
||||
#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */
|
||||
#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */
|
||||
#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */
|
||||
#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */
|
||||
#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */
|
||||
#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */
|
||||
#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */
|
||||
#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */
|
||||
#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */
|
||||
#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */
|
||||
#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */
|
||||
#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */
|
||||
#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */
|
||||
#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */
|
||||
#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */
|
||||
#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */
|
||||
#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */
|
||||
#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
|
||||
#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */
|
||||
|
||||
#define SYS_IRQS IRQ_PINT3
|
||||
|
||||
#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
|
||||
#define IRQ_PA0 BFIN_PA_IRQ(0)
|
||||
#define IRQ_PA1 BFIN_PA_IRQ(1)
|
||||
#define IRQ_PA2 BFIN_PA_IRQ(2)
|
||||
#define IRQ_PA3 BFIN_PA_IRQ(3)
|
||||
#define IRQ_PA4 BFIN_PA_IRQ(4)
|
||||
#define IRQ_PA5 BFIN_PA_IRQ(5)
|
||||
#define IRQ_PA6 BFIN_PA_IRQ(6)
|
||||
#define IRQ_PA7 BFIN_PA_IRQ(7)
|
||||
#define IRQ_PA8 BFIN_PA_IRQ(8)
|
||||
#define IRQ_PA9 BFIN_PA_IRQ(9)
|
||||
#define IRQ_PA10 BFIN_PA_IRQ(10)
|
||||
#define IRQ_PA11 BFIN_PA_IRQ(11)
|
||||
#define IRQ_PA12 BFIN_PA_IRQ(12)
|
||||
#define IRQ_PA13 BFIN_PA_IRQ(13)
|
||||
#define IRQ_PA14 BFIN_PA_IRQ(14)
|
||||
#define IRQ_PA15 BFIN_PA_IRQ(15)
|
||||
|
||||
#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
|
||||
#define IRQ_PB0 BFIN_PB_IRQ(0)
|
||||
#define IRQ_PB1 BFIN_PB_IRQ(1)
|
||||
#define IRQ_PB2 BFIN_PB_IRQ(2)
|
||||
#define IRQ_PB3 BFIN_PB_IRQ(3)
|
||||
#define IRQ_PB4 BFIN_PB_IRQ(4)
|
||||
#define IRQ_PB5 BFIN_PB_IRQ(5)
|
||||
#define IRQ_PB6 BFIN_PB_IRQ(6)
|
||||
#define IRQ_PB7 BFIN_PB_IRQ(7)
|
||||
#define IRQ_PB8 BFIN_PB_IRQ(8)
|
||||
#define IRQ_PB9 BFIN_PB_IRQ(9)
|
||||
#define IRQ_PB10 BFIN_PB_IRQ(10)
|
||||
#define IRQ_PB11 BFIN_PB_IRQ(11)
|
||||
#define IRQ_PB12 BFIN_PB_IRQ(12)
|
||||
#define IRQ_PB13 BFIN_PB_IRQ(13)
|
||||
#define IRQ_PB14 BFIN_PB_IRQ(14)
|
||||
#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */
|
||||
|
||||
#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
|
||||
#define IRQ_PC0 BFIN_PC_IRQ(0)
|
||||
#define IRQ_PC1 BFIN_PC_IRQ(1)
|
||||
#define IRQ_PC2 BFIN_PC_IRQ(2)
|
||||
#define IRQ_PC3 BFIN_PC_IRQ(3)
|
||||
#define IRQ_PC4 BFIN_PC_IRQ(4)
|
||||
#define IRQ_PC5 BFIN_PC_IRQ(5)
|
||||
#define IRQ_PC6 BFIN_PC_IRQ(6)
|
||||
#define IRQ_PC7 BFIN_PC_IRQ(7)
|
||||
#define IRQ_PC8 BFIN_PC_IRQ(8)
|
||||
#define IRQ_PC9 BFIN_PC_IRQ(9)
|
||||
#define IRQ_PC10 BFIN_PC_IRQ(10)
|
||||
#define IRQ_PC11 BFIN_PC_IRQ(11)
|
||||
#define IRQ_PC12 BFIN_PC_IRQ(12)
|
||||
#define IRQ_PC13 BFIN_PC_IRQ(13)
|
||||
#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */
|
||||
#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */
|
||||
|
||||
#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)
|
||||
#define IRQ_PD0 BFIN_PD_IRQ(0)
|
||||
#define IRQ_PD1 BFIN_PD_IRQ(1)
|
||||
#define IRQ_PD2 BFIN_PD_IRQ(2)
|
||||
#define IRQ_PD3 BFIN_PD_IRQ(3)
|
||||
#define IRQ_PD4 BFIN_PD_IRQ(4)
|
||||
#define IRQ_PD5 BFIN_PD_IRQ(5)
|
||||
#define IRQ_PD6 BFIN_PD_IRQ(6)
|
||||
#define IRQ_PD7 BFIN_PD_IRQ(7)
|
||||
#define IRQ_PD8 BFIN_PD_IRQ(8)
|
||||
#define IRQ_PD9 BFIN_PD_IRQ(9)
|
||||
#define IRQ_PD10 BFIN_PD_IRQ(10)
|
||||
#define IRQ_PD11 BFIN_PD_IRQ(11)
|
||||
#define IRQ_PD12 BFIN_PD_IRQ(12)
|
||||
#define IRQ_PD13 BFIN_PD_IRQ(13)
|
||||
#define IRQ_PD14 BFIN_PD_IRQ(14)
|
||||
#define IRQ_PD15 BFIN_PD_IRQ(15)
|
||||
|
||||
#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)
|
||||
#define IRQ_PE0 BFIN_PE_IRQ(0)
|
||||
#define IRQ_PE1 BFIN_PE_IRQ(1)
|
||||
#define IRQ_PE2 BFIN_PE_IRQ(2)
|
||||
#define IRQ_PE3 BFIN_PE_IRQ(3)
|
||||
#define IRQ_PE4 BFIN_PE_IRQ(4)
|
||||
#define IRQ_PE5 BFIN_PE_IRQ(5)
|
||||
#define IRQ_PE6 BFIN_PE_IRQ(6)
|
||||
#define IRQ_PE7 BFIN_PE_IRQ(7)
|
||||
#define IRQ_PE8 BFIN_PE_IRQ(8)
|
||||
#define IRQ_PE9 BFIN_PE_IRQ(9)
|
||||
#define IRQ_PE10 BFIN_PE_IRQ(10)
|
||||
#define IRQ_PE11 BFIN_PE_IRQ(11)
|
||||
#define IRQ_PE12 BFIN_PE_IRQ(12)
|
||||
#define IRQ_PE13 BFIN_PE_IRQ(13)
|
||||
#define IRQ_PE14 BFIN_PE_IRQ(14)
|
||||
#define IRQ_PE15 BFIN_PE_IRQ(15)
|
||||
|
||||
#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)
|
||||
#define IRQ_PF0 BFIN_PF_IRQ(0)
|
||||
#define IRQ_PF1 BFIN_PF_IRQ(1)
|
||||
#define IRQ_PF2 BFIN_PF_IRQ(2)
|
||||
#define IRQ_PF3 BFIN_PF_IRQ(3)
|
||||
#define IRQ_PF4 BFIN_PF_IRQ(4)
|
||||
#define IRQ_PF5 BFIN_PF_IRQ(5)
|
||||
#define IRQ_PF6 BFIN_PF_IRQ(6)
|
||||
#define IRQ_PF7 BFIN_PF_IRQ(7)
|
||||
#define IRQ_PF8 BFIN_PF_IRQ(8)
|
||||
#define IRQ_PF9 BFIN_PF_IRQ(9)
|
||||
#define IRQ_PF10 BFIN_PF_IRQ(10)
|
||||
#define IRQ_PF11 BFIN_PF_IRQ(11)
|
||||
#define IRQ_PF12 BFIN_PF_IRQ(12)
|
||||
#define IRQ_PF13 BFIN_PF_IRQ(13)
|
||||
#define IRQ_PF14 BFIN_PF_IRQ(14)
|
||||
#define IRQ_PF15 BFIN_PF_IRQ(15)
|
||||
|
||||
#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)
|
||||
#define IRQ_PG0 BFIN_PG_IRQ(0)
|
||||
#define IRQ_PG1 BFIN_PG_IRQ(1)
|
||||
#define IRQ_PG2 BFIN_PG_IRQ(2)
|
||||
#define IRQ_PG3 BFIN_PG_IRQ(3)
|
||||
#define IRQ_PG4 BFIN_PG_IRQ(4)
|
||||
#define IRQ_PG5 BFIN_PG_IRQ(5)
|
||||
#define IRQ_PG6 BFIN_PG_IRQ(6)
|
||||
#define IRQ_PG7 BFIN_PG_IRQ(7)
|
||||
#define IRQ_PG8 BFIN_PG_IRQ(8)
|
||||
#define IRQ_PG9 BFIN_PG_IRQ(9)
|
||||
#define IRQ_PG10 BFIN_PG_IRQ(10)
|
||||
#define IRQ_PG11 BFIN_PG_IRQ(11)
|
||||
#define IRQ_PG12 BFIN_PG_IRQ(12)
|
||||
#define IRQ_PG13 BFIN_PG_IRQ(13)
|
||||
#define IRQ_PG14 BFIN_PG_IRQ(14)
|
||||
#define IRQ_PG15 BFIN_PG_IRQ(15)
|
||||
|
||||
#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1)
|
||||
#define IRQ_PH0 BFIN_PH_IRQ(0)
|
||||
#define IRQ_PH1 BFIN_PH_IRQ(1)
|
||||
#define IRQ_PH2 BFIN_PH_IRQ(2)
|
||||
#define IRQ_PH3 BFIN_PH_IRQ(3)
|
||||
#define IRQ_PH4 BFIN_PH_IRQ(4)
|
||||
#define IRQ_PH5 BFIN_PH_IRQ(5)
|
||||
#define IRQ_PH6 BFIN_PH_IRQ(6)
|
||||
#define IRQ_PH7 BFIN_PH_IRQ(7)
|
||||
#define IRQ_PH8 BFIN_PH_IRQ(8)
|
||||
#define IRQ_PH9 BFIN_PH_IRQ(9)
|
||||
#define IRQ_PH10 BFIN_PH_IRQ(10)
|
||||
#define IRQ_PH11 BFIN_PH_IRQ(11)
|
||||
#define IRQ_PH12 BFIN_PH_IRQ(12)
|
||||
#define IRQ_PH13 BFIN_PH_IRQ(13)
|
||||
#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */
|
||||
#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */
|
||||
|
||||
#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1)
|
||||
#define IRQ_PI0 BFIN_PI_IRQ(0)
|
||||
#define IRQ_PI1 BFIN_PI_IRQ(1)
|
||||
#define IRQ_PI2 BFIN_PI_IRQ(2)
|
||||
#define IRQ_PI3 BFIN_PI_IRQ(3)
|
||||
#define IRQ_PI4 BFIN_PI_IRQ(4)
|
||||
#define IRQ_PI5 BFIN_PI_IRQ(5)
|
||||
#define IRQ_PI6 BFIN_PI_IRQ(6)
|
||||
#define IRQ_PI7 BFIN_PI_IRQ(7)
|
||||
#define IRQ_PI8 BFIN_PI_IRQ(8)
|
||||
#define IRQ_PI9 BFIN_PI_IRQ(9)
|
||||
#define IRQ_PI10 BFIN_PI_IRQ(10)
|
||||
#define IRQ_PI11 BFIN_PI_IRQ(11)
|
||||
#define IRQ_PI12 BFIN_PI_IRQ(12)
|
||||
#define IRQ_PI13 BFIN_PI_IRQ(13)
|
||||
#define IRQ_PI14 BFIN_PI_IRQ(14)
|
||||
#define IRQ_PI15 BFIN_PI_IRQ(15)
|
||||
|
||||
#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1)
|
||||
#define IRQ_PJ0 BFIN_PJ_IRQ(0)
|
||||
#define IRQ_PJ1 BFIN_PJ_IRQ(1)
|
||||
#define IRQ_PJ2 BFIN_PJ_IRQ(2)
|
||||
#define IRQ_PJ3 BFIN_PJ_IRQ(3)
|
||||
#define IRQ_PJ4 BFIN_PJ_IRQ(4)
|
||||
#define IRQ_PJ5 BFIN_PJ_IRQ(5)
|
||||
#define IRQ_PJ6 BFIN_PJ_IRQ(6)
|
||||
#define IRQ_PJ7 BFIN_PJ_IRQ(7)
|
||||
#define IRQ_PJ8 BFIN_PJ_IRQ(8)
|
||||
#define IRQ_PJ9 BFIN_PJ_IRQ(9)
|
||||
#define IRQ_PJ10 BFIN_PJ_IRQ(10)
|
||||
#define IRQ_PJ11 BFIN_PJ_IRQ(11)
|
||||
#define IRQ_PJ12 BFIN_PJ_IRQ(12)
|
||||
#define IRQ_PJ13 BFIN_PJ_IRQ(13)
|
||||
#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */
|
||||
#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */
|
||||
|
||||
#define GPIO_IRQ_BASE IRQ_PA0
|
||||
|
||||
#define NR_MACH_IRQS (IRQ_PJ15 + 1)
|
||||
|
||||
/* For compatibility reasons with existing code */
|
||||
|
||||
#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR
|
||||
#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR
|
||||
#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR
|
||||
#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR
|
||||
#define IRQ_SPI0_ERR IRQ_SPI0_ERROR
|
||||
#define IRQ_UART0_ERR IRQ_UART0_ERROR
|
||||
#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR
|
||||
#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR
|
||||
#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR
|
||||
#define IRQ_SPI1_ERR IRQ_SPI1_ERROR
|
||||
#define IRQ_SPI2_ERR IRQ_SPI2_ERROR
|
||||
#define IRQ_UART1_ERR IRQ_UART1_ERROR
|
||||
#define IRQ_UART2_ERR IRQ_UART2_ERROR
|
||||
#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
|
||||
#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
|
||||
#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR
|
||||
#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR
|
||||
#define IRQ_UART3_ERR IRQ_UART3_ERROR
|
||||
#define IRQ_HOST_ERR IRQ_HOST_ERROR
|
||||
#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
|
||||
#define IRQ_NFC_ERR IRQ_NFC_ERROR
|
||||
#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR
|
||||
#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
|
||||
#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR
|
||||
|
||||
/* IAR0 BIT FIELDS */
|
||||
#define IRQ_PLL_WAKEUP_POS 0
|
||||
#define IRQ_DMAC0_ERR_POS 4
|
||||
#define IRQ_EPPI0_ERR_POS 8
|
||||
#define IRQ_SPORT0_ERR_POS 12
|
||||
#define IRQ_SPORT1_ERR_POS 16
|
||||
#define IRQ_SPI0_ERR_POS 20
|
||||
#define IRQ_UART0_ERR_POS 24
|
||||
#define IRQ_RTC_POS 28
|
||||
|
||||
/* IAR1 BIT FIELDS */
|
||||
#define IRQ_EPPI0_POS 0
|
||||
#define IRQ_SPORT0_RX_POS 4
|
||||
#define IRQ_SPORT0_TX_POS 8
|
||||
#define IRQ_SPORT1_RX_POS 12
|
||||
#define IRQ_SPORT1_TX_POS 16
|
||||
#define IRQ_SPI0_POS 20
|
||||
#define IRQ_UART0_RX_POS 24
|
||||
#define IRQ_UART0_TX_POS 28
|
||||
|
||||
/* IAR2 BIT FIELDS */
|
||||
#define IRQ_TIMER8_POS 0
|
||||
#define IRQ_TIMER9_POS 4
|
||||
#define IRQ_TIMER10_POS 8
|
||||
#define IRQ_PINT0_POS 12
|
||||
#define IRQ_PINT1_POS 16
|
||||
#define IRQ_MDMAS0_POS 20
|
||||
#define IRQ_MDMAS1_POS 24
|
||||
#define IRQ_WATCH_POS 28
|
||||
|
||||
/* IAR3 BIT FIELDS */
|
||||
#define IRQ_DMAC1_ERR_POS 0
|
||||
#define IRQ_SPORT2_ERR_POS 4
|
||||
#define IRQ_SPORT3_ERR_POS 8
|
||||
#define IRQ_MXVR_DATA_POS 12
|
||||
#define IRQ_SPI1_ERR_POS 16
|
||||
#define IRQ_SPI2_ERR_POS 20
|
||||
#define IRQ_UART1_ERR_POS 24
|
||||
#define IRQ_UART2_ERR_POS 28
|
||||
|
||||
/* IAR4 BIT FILEDS */
|
||||
#define IRQ_CAN0_ERR_POS 0
|
||||
#define IRQ_SPORT2_RX_POS 4
|
||||
#define IRQ_UART2_RX_POS 4
|
||||
#define IRQ_SPORT2_TX_POS 8
|
||||
#define IRQ_UART2_TX_POS 8
|
||||
#define IRQ_SPORT3_RX_POS 12
|
||||
#define IRQ_UART3_RX_POS 12
|
||||
#define IRQ_SPORT3_TX_POS 16
|
||||
#define IRQ_UART3_TX_POS 16
|
||||
#define IRQ_EPPI1_POS 20
|
||||
#define IRQ_EPPI2_POS 24
|
||||
#define IRQ_SPI1_POS 28
|
||||
|
||||
/* IAR5 BIT FIELDS */
|
||||
#define IRQ_SPI2_POS 0
|
||||
#define IRQ_UART1_RX_POS 4
|
||||
#define IRQ_UART1_TX_POS 8
|
||||
#define IRQ_ATAPI_RX_POS 12
|
||||
#define IRQ_ATAPI_TX_POS 16
|
||||
#define IRQ_TWI0_POS 20
|
||||
#define IRQ_TWI1_POS 24
|
||||
#define IRQ_CAN0_RX_POS 28
|
||||
|
||||
/* IAR6 BIT FIELDS */
|
||||
#define IRQ_CAN0_TX_POS 0
|
||||
#define IRQ_MDMAS2_POS 4
|
||||
#define IRQ_MDMAS3_POS 8
|
||||
#define IRQ_MXVR_ERR_POS 12
|
||||
#define IRQ_MXVR_MSG_POS 16
|
||||
#define IRQ_MXVR_PKT_POS 20
|
||||
#define IRQ_EPPI1_ERR_POS 24
|
||||
#define IRQ_EPPI2_ERR_POS 28
|
||||
|
||||
/* IAR7 BIT FIELDS */
|
||||
#define IRQ_UART3_ERR_POS 0
|
||||
#define IRQ_HOST_ERR_POS 4
|
||||
#define IRQ_PIXC_ERR_POS 12
|
||||
#define IRQ_NFC_ERR_POS 16
|
||||
#define IRQ_ATAPI_ERR_POS 20
|
||||
#define IRQ_CAN1_ERR_POS 24
|
||||
#define IRQ_HS_DMA_ERR_POS 28
|
||||
|
||||
/* IAR8 BIT FIELDS */
|
||||
#define IRQ_PIXC_IN0_POS 0
|
||||
#define IRQ_PIXC_IN1_POS 4
|
||||
#define IRQ_PIXC_OUT_POS 8
|
||||
#define IRQ_SDH_POS 12
|
||||
#define IRQ_CNT_POS 16
|
||||
#define IRQ_KEY_POS 20
|
||||
#define IRQ_CAN1_RX_POS 24
|
||||
#define IRQ_CAN1_TX_POS 28
|
||||
|
||||
/* IAR9 BIT FIELDS */
|
||||
#define IRQ_SDH_MASK0_POS 0
|
||||
#define IRQ_SDH_MASK1_POS 4
|
||||
#define IRQ_USB_INT0_POS 12
|
||||
#define IRQ_USB_INT1_POS 16
|
||||
#define IRQ_USB_INT2_POS 20
|
||||
#define IRQ_USB_DMA_POS 24
|
||||
#define IRQ_OTPSEC_POS 28
|
||||
|
||||
/* IAR10 BIT FIELDS */
|
||||
#define IRQ_TIMER0_POS 24
|
||||
#define IRQ_TIMER1_POS 28
|
||||
|
||||
/* IAR11 BIT FIELDS */
|
||||
#define IRQ_TIMER2_POS 0
|
||||
#define IRQ_TIMER3_POS 4
|
||||
#define IRQ_TIMER4_POS 8
|
||||
#define IRQ_TIMER5_POS 12
|
||||
#define IRQ_TIMER6_POS 16
|
||||
#define IRQ_TIMER7_POS 20
|
||||
#define IRQ_PINT2_POS 24
|
||||
#define IRQ_PINT3_POS 28
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/types.h>
|
||||
|
||||
/*
|
||||
* gpio pint registers layout
|
||||
*/
|
||||
struct bfin_pint_regs {
|
||||
u32 mask_set;
|
||||
u32 mask_clear;
|
||||
u32 request;
|
||||
u32 assign;
|
||||
u32 edge_set;
|
||||
u32 edge_clear;
|
||||
u32 invert_set;
|
||||
u32 invert_clear;
|
||||
u32 pinstate;
|
||||
u32 latch;
|
||||
u32 __pad0[2];
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
84
arch/blackfin/mach-bf548/include/mach/mem_map.h
Normal file
84
arch/blackfin/mach-bf548/include/mach/mem_map.h
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* BF548 memory map
|
||||
*
|
||||
* Copyright 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_MACH_MEM_MAP_H__
|
||||
#define __BFIN_MACH_MEM_MAP_H__
|
||||
|
||||
#ifndef __BFIN_MEM_MAP_H__
|
||||
# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
|
||||
#endif
|
||||
|
||||
/* Async Memory Banks */
|
||||
#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
|
||||
#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
|
||||
#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
|
||||
#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
|
||||
#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
|
||||
#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
|
||||
#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
|
||||
#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
|
||||
|
||||
/* Boot ROM Memory */
|
||||
|
||||
#define BOOT_ROM_START 0xEF000000
|
||||
#define BOOT_ROM_LENGTH 0x1000
|
||||
|
||||
/* L1 Instruction ROM */
|
||||
|
||||
#define L1_ROM_START 0xFFA14000
|
||||
#define L1_ROM_LENGTH 0x10000
|
||||
|
||||
/* Level 1 Memory */
|
||||
|
||||
/* Memory Map for ADSP-BF548 processors */
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
#define BFIN_ICACHESIZE (16*1024)
|
||||
#else
|
||||
#define BFIN_ICACHESIZE (0*1024)
|
||||
#endif
|
||||
|
||||
#define L1_CODE_START 0xFFA00000
|
||||
#define L1_DATA_A_START 0xFF800000
|
||||
#define L1_DATA_B_START 0xFF900000
|
||||
|
||||
#define L1_CODE_LENGTH 0xC000
|
||||
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
|
||||
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BFIN_DCACHESIZE (16*1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
#else
|
||||
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
|
||||
#define BFIN_DCACHESIZE (32*1024)
|
||||
#define BFIN_DSUPBANKS 2
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x8000
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BFIN_DCACHESIZE (0*1024)
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE*/
|
||||
|
||||
/* Level 2 Memory */
|
||||
#define L2_START 0xFEB00000
|
||||
#if defined(CONFIG_BF542)
|
||||
# define L2_LENGTH 0
|
||||
#elif defined(CONFIG_BF544)
|
||||
# define L2_LENGTH 0x10000
|
||||
#else
|
||||
# define L2_LENGTH 0x20000
|
||||
#endif
|
||||
|
||||
#endif
|
||||
1
arch/blackfin/mach-bf548/include/mach/pll.h
Normal file
1
arch/blackfin/mach-bf548/include/mach/pll.h
Normal file
|
|
@ -0,0 +1 @@
|
|||
#include <mach-common/pll.h>
|
||||
318
arch/blackfin/mach-bf548/include/mach/portmux.h
Normal file
318
arch/blackfin/mach-bf548/include/mach/portmux.h
Normal file
|
|
@ -0,0 +1,318 @@
|
|||
/*
|
||||
* Copyright 2007-2009 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_PORTMUX_H_
|
||||
#define _MACH_PORTMUX_H_
|
||||
|
||||
#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
|
||||
#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
|
||||
#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
|
||||
#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
|
||||
#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
|
||||
#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
|
||||
#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
|
||||
#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
|
||||
#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
|
||||
#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
|
||||
#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
|
||||
#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
|
||||
#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
|
||||
#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
|
||||
#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
|
||||
#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
|
||||
#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
|
||||
#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
|
||||
#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
|
||||
#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
|
||||
|
||||
#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
|
||||
#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
|
||||
#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
|
||||
#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
|
||||
#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
|
||||
#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
|
||||
#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
|
||||
#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
|
||||
#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
|
||||
#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0))
|
||||
#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
|
||||
#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
|
||||
#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0))
|
||||
#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
|
||||
#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
|
||||
#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
|
||||
#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1))
|
||||
#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1))
|
||||
#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1))
|
||||
|
||||
#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
|
||||
#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
|
||||
#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
|
||||
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
|
||||
#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
|
||||
#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
|
||||
#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
|
||||
#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
|
||||
#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0))
|
||||
#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
|
||||
#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0))
|
||||
#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0))
|
||||
#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
|
||||
#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
|
||||
#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
|
||||
#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
|
||||
|
||||
#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
|
||||
#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
|
||||
#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
|
||||
#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
|
||||
#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
|
||||
#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
|
||||
#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
|
||||
#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0))
|
||||
#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0))
|
||||
#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
|
||||
#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
|
||||
#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
|
||||
#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
|
||||
#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
|
||||
#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
|
||||
#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0))
|
||||
|
||||
#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
|
||||
#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
|
||||
#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1))
|
||||
#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1))
|
||||
#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1))
|
||||
#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1))
|
||||
#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
|
||||
#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
|
||||
#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
|
||||
#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
|
||||
#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
|
||||
#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1))
|
||||
#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
|
||||
#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1))
|
||||
#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1))
|
||||
#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
|
||||
#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
|
||||
#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
|
||||
#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2))
|
||||
#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2))
|
||||
#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2))
|
||||
#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2))
|
||||
#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2))
|
||||
#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2))
|
||||
#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2))
|
||||
#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
|
||||
#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
|
||||
#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2))
|
||||
#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
|
||||
#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2))
|
||||
#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2))
|
||||
#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
|
||||
#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3))
|
||||
#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3))
|
||||
#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3))
|
||||
#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3))
|
||||
#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3))
|
||||
#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3))
|
||||
#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3))
|
||||
#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3))
|
||||
#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3))
|
||||
#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
|
||||
#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
|
||||
#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3))
|
||||
#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
|
||||
#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
|
||||
|
||||
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PE4
|
||||
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
|
||||
#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
|
||||
#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
|
||||
#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
|
||||
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0))
|
||||
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0))
|
||||
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0))
|
||||
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
|
||||
#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
|
||||
#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0))
|
||||
#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0))
|
||||
#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
|
||||
#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
|
||||
#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
|
||||
#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
|
||||
#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
|
||||
#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
|
||||
#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
|
||||
#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
|
||||
#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
|
||||
#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
|
||||
#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
|
||||
#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
|
||||
#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
|
||||
#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
|
||||
|
||||
#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
|
||||
#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
|
||||
#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
|
||||
#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
|
||||
#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
|
||||
#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
|
||||
#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
|
||||
#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
|
||||
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
|
||||
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
|
||||
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
|
||||
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
|
||||
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
|
||||
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
|
||||
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
|
||||
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
|
||||
|
||||
#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
|
||||
# define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
|
||||
# define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
|
||||
# define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
|
||||
# define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
|
||||
# define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
|
||||
# define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
|
||||
# define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
|
||||
# define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
|
||||
# define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
|
||||
# define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
|
||||
# define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
|
||||
# define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
|
||||
# define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
|
||||
# define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
|
||||
# define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
|
||||
# define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
|
||||
#else
|
||||
# define P_ATAPI_D0A (P_DONTCARE)
|
||||
# define P_ATAPI_D1A (P_DONTCARE)
|
||||
# define P_ATAPI_D2A (P_DONTCARE)
|
||||
# define P_ATAPI_D3A (P_DONTCARE)
|
||||
# define P_ATAPI_D4A (P_DONTCARE)
|
||||
# define P_ATAPI_D5A (P_DONTCARE)
|
||||
# define P_ATAPI_D6A (P_DONTCARE)
|
||||
# define P_ATAPI_D7A (P_DONTCARE)
|
||||
# define P_ATAPI_D8A (P_DONTCARE)
|
||||
# define P_ATAPI_D9A (P_DONTCARE)
|
||||
# define P_ATAPI_D10A (P_DONTCARE)
|
||||
# define P_ATAPI_D11A (P_DONTCARE)
|
||||
# define P_ATAPI_D12A (P_DONTCARE)
|
||||
# define P_ATAPI_D13A (P_DONTCARE)
|
||||
# define P_ATAPI_D14A (P_DONTCARE)
|
||||
# define P_ATAPI_D15A (P_DONTCARE)
|
||||
#endif
|
||||
|
||||
#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
|
||||
#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
|
||||
#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
|
||||
#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
|
||||
#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
|
||||
#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
|
||||
#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
|
||||
#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
|
||||
#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
|
||||
#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
|
||||
#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
|
||||
#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
|
||||
#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
|
||||
#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
|
||||
#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
|
||||
#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
|
||||
#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
|
||||
# define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
|
||||
# define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
|
||||
# define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
|
||||
#else
|
||||
# define P_ATAPI_A0A (P_DONTCARE)
|
||||
# define P_ATAPI_A1A (P_DONTCARE)
|
||||
# define P_ATAPI_A2A (P_DONTCARE)
|
||||
#endif
|
||||
#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
|
||||
#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
|
||||
#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
|
||||
#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
|
||||
#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
|
||||
#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
|
||||
#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
|
||||
#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3))
|
||||
|
||||
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
|
||||
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
|
||||
#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
|
||||
#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
|
||||
#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
|
||||
#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
|
||||
#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
|
||||
#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
|
||||
#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
|
||||
#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
|
||||
#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
|
||||
#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
|
||||
#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
|
||||
#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
|
||||
#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
|
||||
#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
|
||||
#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
|
||||
#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
|
||||
#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
|
||||
#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
|
||||
#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
|
||||
#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
|
||||
#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
|
||||
#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
|
||||
|
||||
#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0))
|
||||
#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0))
|
||||
#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0))
|
||||
#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0))
|
||||
#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0))
|
||||
#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0))
|
||||
#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0))
|
||||
#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0))
|
||||
#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0))
|
||||
#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0))
|
||||
#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0))
|
||||
#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0))
|
||||
#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0))
|
||||
#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0))
|
||||
#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0))
|
||||
#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0))
|
||||
#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1))
|
||||
|
||||
#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0))
|
||||
#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0))
|
||||
#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0))
|
||||
#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0))
|
||||
#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0))
|
||||
#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0))
|
||||
#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0))
|
||||
#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0))
|
||||
#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0))
|
||||
#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0))
|
||||
#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0))
|
||||
#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0))
|
||||
#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
|
||||
#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
|
||||
|
||||
|
||||
#define P_NAND_D0 (P_DONTCARE)
|
||||
#define P_NAND_D1 (P_DONTCARE)
|
||||
#define P_NAND_D2 (P_DONTCARE)
|
||||
#define P_NAND_D3 (P_DONTCARE)
|
||||
#define P_NAND_D4 (P_DONTCARE)
|
||||
#define P_NAND_D5 (P_DONTCARE)
|
||||
#define P_NAND_D6 (P_DONTCARE)
|
||||
#define P_NAND_D7 (P_DONTCARE)
|
||||
#define P_NAND_WE (P_DONTCARE)
|
||||
#define P_NAND_RE (P_DONTCARE)
|
||||
#define P_NAND_CLE (P_DONTCARE)
|
||||
#define P_NAND_ALE (P_DONTCARE)
|
||||
|
||||
#endif /* _MACH_PORTMUX_H_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue