mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 01:12:45 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
212
arch/blackfin/mach-bf561/Kconfig
Normal file
212
arch/blackfin/mach-bf561/Kconfig
Normal file
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|
@ -0,0 +1,212 @@
|
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if (BF561)
|
||||
|
||||
source "arch/blackfin/mach-bf561/boards/Kconfig"
|
||||
|
||||
menu "BF561 Specific Configuration"
|
||||
|
||||
if (!SMP)
|
||||
|
||||
comment "Core B Support"
|
||||
|
||||
config BF561_COREB
|
||||
bool "Enable Core B loader"
|
||||
default y
|
||||
|
||||
endif
|
||||
|
||||
comment "Interrupt Priority Assignment"
|
||||
|
||||
menu "Priority"
|
||||
|
||||
config IRQ_PLL_WAKEUP
|
||||
int "PLL Wakeup Interrupt"
|
||||
default 7
|
||||
config IRQ_DMA1_ERROR
|
||||
int "DMA1 Error (generic)"
|
||||
default 7
|
||||
config IRQ_DMA2_ERROR
|
||||
int "DMA2 Error (generic)"
|
||||
default 7
|
||||
config IRQ_IMDMA_ERROR
|
||||
int "IMDMA Error (generic)"
|
||||
default 7
|
||||
config IRQ_PPI0_ERROR
|
||||
int "PPI0 Error Interrupt"
|
||||
default 7
|
||||
config IRQ_PPI1_ERROR
|
||||
int "PPI1 Error Interrupt"
|
||||
default 7
|
||||
config IRQ_SPORT0_ERROR
|
||||
int "SPORT0 Error Interrupt"
|
||||
default 7
|
||||
config IRQ_SPORT1_ERROR
|
||||
int "SPORT1 Error Interrupt"
|
||||
default 7
|
||||
config IRQ_SPI_ERROR
|
||||
int "SPI Error Interrupt"
|
||||
default 7
|
||||
config IRQ_UART_ERROR
|
||||
int "UART Error Interrupt"
|
||||
default 7
|
||||
config IRQ_RESERVED_ERROR
|
||||
int "Reserved Interrupt"
|
||||
default 7
|
||||
config IRQ_DMA1_0
|
||||
int "DMA1 0 Interrupt(PPI1)"
|
||||
default 8
|
||||
config IRQ_DMA1_1
|
||||
int "DMA1 1 Interrupt(PPI2)"
|
||||
default 8
|
||||
config IRQ_DMA1_2
|
||||
int "DMA1 2 Interrupt"
|
||||
default 8
|
||||
config IRQ_DMA1_3
|
||||
int "DMA1 3 Interrupt"
|
||||
default 8
|
||||
config IRQ_DMA1_4
|
||||
int "DMA1 4 Interrupt"
|
||||
default 8
|
||||
config IRQ_DMA1_5
|
||||
int "DMA1 5 Interrupt"
|
||||
default 8
|
||||
config IRQ_DMA1_6
|
||||
int "DMA1 6 Interrupt"
|
||||
default 8
|
||||
config IRQ_DMA1_7
|
||||
int "DMA1 7 Interrupt"
|
||||
default 8
|
||||
config IRQ_DMA1_8
|
||||
int "DMA1 8 Interrupt"
|
||||
default 8
|
||||
config IRQ_DMA1_9
|
||||
int "DMA1 9 Interrupt"
|
||||
default 8
|
||||
config IRQ_DMA1_10
|
||||
int "DMA1 10 Interrupt"
|
||||
default 8
|
||||
config IRQ_DMA1_11
|
||||
int "DMA1 11 Interrupt"
|
||||
default 8
|
||||
config IRQ_DMA2_0
|
||||
int "DMA2 0 (SPORT0 RX)"
|
||||
default 9
|
||||
config IRQ_DMA2_1
|
||||
int "DMA2 1 (SPORT0 TX)"
|
||||
default 9
|
||||
config IRQ_DMA2_2
|
||||
int "DMA2 2 (SPORT1 RX)"
|
||||
default 9
|
||||
config IRQ_DMA2_3
|
||||
int "DMA2 3 (SPORT2 TX)"
|
||||
default 9
|
||||
config IRQ_DMA2_4
|
||||
int "DMA2 4 (SPI)"
|
||||
default 9
|
||||
config IRQ_DMA2_5
|
||||
int "DMA2 5 (UART RX)"
|
||||
default 9
|
||||
config IRQ_DMA2_6
|
||||
int "DMA2 6 (UART TX)"
|
||||
default 9
|
||||
config IRQ_DMA2_7
|
||||
int "DMA2 7 Interrupt"
|
||||
default 9
|
||||
config IRQ_DMA2_8
|
||||
int "DMA2 8 Interrupt"
|
||||
default 9
|
||||
config IRQ_DMA2_9
|
||||
int "DMA2 9 Interrupt"
|
||||
default 9
|
||||
config IRQ_DMA2_10
|
||||
int "DMA2 10 Interrupt"
|
||||
default 9
|
||||
config IRQ_DMA2_11
|
||||
int "DMA2 11 Interrupt"
|
||||
default 9
|
||||
config IRQ_TIMER0
|
||||
int "TIMER 0 Interrupt"
|
||||
default 7 if TICKSOURCE_GPTMR0
|
||||
default 8
|
||||
config IRQ_TIMER1
|
||||
int "TIMER 1 Interrupt"
|
||||
default 10
|
||||
config IRQ_TIMER2
|
||||
int "TIMER 2 Interrupt"
|
||||
default 10
|
||||
config IRQ_TIMER3
|
||||
int "TIMER 3 Interrupt"
|
||||
default 10
|
||||
config IRQ_TIMER4
|
||||
int "TIMER 4 Interrupt"
|
||||
default 10
|
||||
config IRQ_TIMER5
|
||||
int "TIMER 5 Interrupt"
|
||||
default 10
|
||||
config IRQ_TIMER6
|
||||
int "TIMER 6 Interrupt"
|
||||
default 10
|
||||
config IRQ_TIMER7
|
||||
int "TIMER 7 Interrupt"
|
||||
default 10
|
||||
config IRQ_TIMER8
|
||||
int "TIMER 8 Interrupt"
|
||||
default 10
|
||||
config IRQ_TIMER9
|
||||
int "TIMER 9 Interrupt"
|
||||
default 10
|
||||
config IRQ_TIMER10
|
||||
int "TIMER 10 Interrupt"
|
||||
default 10
|
||||
config IRQ_TIMER11
|
||||
int "TIMER 11 Interrupt"
|
||||
default 10
|
||||
config IRQ_PROG0_INTA
|
||||
int "Programmable Flags0 A (8)"
|
||||
default 11
|
||||
config IRQ_PROG0_INTB
|
||||
int "Programmable Flags0 B (8)"
|
||||
default 11
|
||||
config IRQ_PROG1_INTA
|
||||
int "Programmable Flags1 A (8)"
|
||||
default 11
|
||||
config IRQ_PROG1_INTB
|
||||
int "Programmable Flags1 B (8)"
|
||||
default 11
|
||||
config IRQ_PROG2_INTA
|
||||
int "Programmable Flags2 A (8)"
|
||||
default 11
|
||||
config IRQ_PROG2_INTB
|
||||
int "Programmable Flags2 B (8)"
|
||||
default 11
|
||||
config IRQ_DMA1_WRRD0
|
||||
int "MDMA1 0 write/read INT"
|
||||
default 8
|
||||
config IRQ_DMA1_WRRD1
|
||||
int "MDMA1 1 write/read INT"
|
||||
default 8
|
||||
config IRQ_DMA2_WRRD0
|
||||
int "MDMA2 0 write/read INT"
|
||||
default 9
|
||||
config IRQ_DMA2_WRRD1
|
||||
int "MDMA2 1 write/read INT"
|
||||
default 9
|
||||
config IRQ_IMDMA_WRRD0
|
||||
int "IMDMA 0 write/read INT"
|
||||
default 12
|
||||
config IRQ_IMDMA_WRRD1
|
||||
int "IMDMA 1 write/read INT"
|
||||
default 12
|
||||
config IRQ_WDTIMER
|
||||
int "Watch Dog Timer"
|
||||
default 13
|
||||
|
||||
help
|
||||
Enter the priority numbers between 7-13 ONLY. Others are Reserved.
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This applies to all the above. It is not recommended to assign the
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highest priority number 7 to UART or any other device.
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|
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endmenu
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||||
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endmenu
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||||
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endif
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9
arch/blackfin/mach-bf561/Makefile
Normal file
9
arch/blackfin/mach-bf561/Makefile
Normal file
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@ -0,0 +1,9 @@
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|||
#
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||||
# arch/blackfin/mach-bf561/Makefile
|
||||
#
|
||||
|
||||
obj-y := ints-priority.o dma.o
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||||
|
||||
obj-$(CONFIG_BF561_COREB) += coreb.o
|
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obj-$(CONFIG_SMP) += smp.o secondary.o atomic.o
|
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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||||
926
arch/blackfin/mach-bf561/atomic.S
Normal file
926
arch/blackfin/mach-bf561/atomic.S
Normal file
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|
@ -0,0 +1,926 @@
|
|||
/*
|
||||
* Copyright 2007-2008 Analog Devices Inc.
|
||||
* Philippe Gerum <rpm@xenomai.org>
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||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
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||||
#include <linux/linkage.h>
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||||
#include <asm/blackfin.h>
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#include <asm/cache.h>
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#include <asm/asm-offsets.h>
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#include <asm/rwlock.h>
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#include <asm/cplb.h>
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.text
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.macro coreslot_loadaddr reg:req
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\reg\().l = _corelock;
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\reg\().h = _corelock;
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.endm
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||||
.macro safe_testset addr:req, scratch:req
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#if ANOMALY_05000477
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cli \scratch;
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testset (\addr);
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sti \scratch;
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#else
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testset (\addr);
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||||
#endif
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.endm
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|
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/*
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* r0 = address of atomic data to flush and invalidate (32bit).
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*
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* Clear interrupts and return the old mask.
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||||
* We assume that no atomic data can span cachelines.
|
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*
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* Clobbers: r2:0, p0
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*/
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ENTRY(_get_core_lock)
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||||
r1 = -L1_CACHE_BYTES;
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r1 = r0 & r1;
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||||
cli r0;
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||||
coreslot_loadaddr p0;
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.Lretry_corelock:
|
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safe_testset p0, r2;
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||||
if cc jump .Ldone_corelock;
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SSYNC(r2);
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jump .Lretry_corelock
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.Ldone_corelock:
|
||||
p0 = r1;
|
||||
/* flush core internal write buffer before invalidate dcache */
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CSYNC(r2);
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flushinv[p0];
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SSYNC(r2);
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rts;
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ENDPROC(_get_core_lock)
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|
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/*
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* r0 = address of atomic data in uncacheable memory region (32bit).
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*
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* Clear interrupts and return the old mask.
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*
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* Clobbers: r0, p0
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*/
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ENTRY(_get_core_lock_noflush)
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cli r0;
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coreslot_loadaddr p0;
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||||
.Lretry_corelock_noflush:
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safe_testset p0, r2;
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if cc jump .Ldone_corelock_noflush;
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SSYNC(r2);
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||||
jump .Lretry_corelock_noflush
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.Ldone_corelock_noflush:
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||||
/*
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* SMP kgdb runs into dead loop without NOP here, when one core
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* single steps over get_core_lock_noflush and the other executes
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* get_core_lock as a slave node.
|
||||
*/
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nop;
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CSYNC(r2);
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||||
rts;
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||||
ENDPROC(_get_core_lock_noflush)
|
||||
|
||||
/*
|
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* r0 = interrupt mask to restore.
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||||
* r1 = address of atomic data to flush and invalidate (32bit).
|
||||
*
|
||||
* Interrupts are masked on entry (see _get_core_lock).
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||||
* Clobbers: r2:0, p0
|
||||
*/
|
||||
ENTRY(_put_core_lock)
|
||||
/* Write-through cache assumed, so no flush needed here. */
|
||||
coreslot_loadaddr p0;
|
||||
r1 = 0;
|
||||
[p0] = r1;
|
||||
SSYNC(r2);
|
||||
sti r0;
|
||||
rts;
|
||||
ENDPROC(_put_core_lock)
|
||||
|
||||
#ifdef __ARCH_SYNC_CORE_DCACHE
|
||||
|
||||
ENTRY(___raw_smp_mark_barrier_asm)
|
||||
[--sp] = rets;
|
||||
[--sp] = ( r7:5 );
|
||||
[--sp] = r0;
|
||||
[--sp] = p1;
|
||||
[--sp] = p0;
|
||||
call _get_core_lock_noflush;
|
||||
|
||||
/*
|
||||
* Calculate current core mask
|
||||
*/
|
||||
GET_CPUID(p1, r7);
|
||||
r6 = 1;
|
||||
r6 <<= r7;
|
||||
|
||||
/*
|
||||
* Set bit of other cores in barrier mask. Don't change current core bit.
|
||||
*/
|
||||
p1.l = _barrier_mask;
|
||||
p1.h = _barrier_mask;
|
||||
r7 = [p1];
|
||||
r5 = r7 & r6;
|
||||
r7 = ~r6;
|
||||
cc = r5 == 0;
|
||||
if cc jump 1f;
|
||||
r7 = r7 | r6;
|
||||
1:
|
||||
[p1] = r7;
|
||||
SSYNC(r2);
|
||||
|
||||
call _put_core_lock;
|
||||
p0 = [sp++];
|
||||
p1 = [sp++];
|
||||
r0 = [sp++];
|
||||
( r7:5 ) = [sp++];
|
||||
rets = [sp++];
|
||||
rts;
|
||||
ENDPROC(___raw_smp_mark_barrier_asm)
|
||||
|
||||
ENTRY(___raw_smp_check_barrier_asm)
|
||||
[--sp] = rets;
|
||||
[--sp] = ( r7:5 );
|
||||
[--sp] = r0;
|
||||
[--sp] = p1;
|
||||
[--sp] = p0;
|
||||
call _get_core_lock_noflush;
|
||||
|
||||
/*
|
||||
* Calculate current core mask
|
||||
*/
|
||||
GET_CPUID(p1, r7);
|
||||
r6 = 1;
|
||||
r6 <<= r7;
|
||||
|
||||
/*
|
||||
* Clear current core bit in barrier mask if it is set.
|
||||
*/
|
||||
p1.l = _barrier_mask;
|
||||
p1.h = _barrier_mask;
|
||||
r7 = [p1];
|
||||
r5 = r7 & r6;
|
||||
cc = r5 == 0;
|
||||
if cc jump 1f;
|
||||
r6 = ~r6;
|
||||
r7 = r7 & r6;
|
||||
[p1] = r7;
|
||||
SSYNC(r2);
|
||||
|
||||
call _put_core_lock;
|
||||
|
||||
/*
|
||||
* Invalidate the entire D-cache of current core.
|
||||
*/
|
||||
sp += -12;
|
||||
call _resync_core_dcache
|
||||
sp += 12;
|
||||
jump 2f;
|
||||
1:
|
||||
call _put_core_lock;
|
||||
2:
|
||||
p0 = [sp++];
|
||||
p1 = [sp++];
|
||||
r0 = [sp++];
|
||||
( r7:5 ) = [sp++];
|
||||
rets = [sp++];
|
||||
rts;
|
||||
ENDPROC(___raw_smp_check_barrier_asm)
|
||||
|
||||
/*
|
||||
* r0 = irqflags
|
||||
* r1 = address of atomic data
|
||||
*
|
||||
* Clobbers: r2:0, p1:0
|
||||
*/
|
||||
_start_lock_coherent:
|
||||
|
||||
[--sp] = rets;
|
||||
[--sp] = ( r7:6 );
|
||||
r7 = r0;
|
||||
p1 = r1;
|
||||
|
||||
/*
|
||||
* Determine whether the atomic data was previously
|
||||
* owned by another CPU (=r6).
|
||||
*/
|
||||
GET_CPUID(p0, r2);
|
||||
r1 = 1;
|
||||
r1 <<= r2;
|
||||
r2 = ~r1;
|
||||
|
||||
r1 = [p1];
|
||||
r1 >>= 28; /* CPU fingerprints are stored in the high nibble. */
|
||||
r6 = r1 & r2;
|
||||
r1 = [p1];
|
||||
r1 <<= 4;
|
||||
r1 >>= 4;
|
||||
[p1] = r1;
|
||||
|
||||
/*
|
||||
* Release the core lock now, but keep IRQs disabled while we are
|
||||
* performing the remaining housekeeping chores for the current CPU.
|
||||
*/
|
||||
coreslot_loadaddr p0;
|
||||
r1 = 0;
|
||||
[p0] = r1;
|
||||
|
||||
/*
|
||||
* If another CPU has owned the same atomic section before us,
|
||||
* then our D-cached copy of the shared data protected by the
|
||||
* current spin/write_lock may be obsolete.
|
||||
*/
|
||||
cc = r6 == 0;
|
||||
if cc jump .Lcache_synced
|
||||
|
||||
/*
|
||||
* Invalidate the entire D-cache of the current core.
|
||||
*/
|
||||
sp += -12;
|
||||
call _resync_core_dcache
|
||||
sp += 12;
|
||||
|
||||
.Lcache_synced:
|
||||
SSYNC(r2);
|
||||
sti r7;
|
||||
( r7:6 ) = [sp++];
|
||||
rets = [sp++];
|
||||
rts
|
||||
|
||||
/*
|
||||
* r0 = irqflags
|
||||
* r1 = address of atomic data
|
||||
*
|
||||
* Clobbers: r2:0, p1:0
|
||||
*/
|
||||
_end_lock_coherent:
|
||||
|
||||
p1 = r1;
|
||||
GET_CPUID(p0, r2);
|
||||
r2 += 28;
|
||||
r1 = 1;
|
||||
r1 <<= r2;
|
||||
r2 = [p1];
|
||||
r2 = r1 | r2;
|
||||
[p1] = r2;
|
||||
r1 = p1;
|
||||
jump _put_core_lock;
|
||||
|
||||
#endif /* __ARCH_SYNC_CORE_DCACHE */
|
||||
|
||||
/*
|
||||
* r0 = &spinlock->lock
|
||||
*
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_spin_is_locked_asm)
|
||||
p1 = r0;
|
||||
[--sp] = rets;
|
||||
call _get_core_lock;
|
||||
r3 = [p1];
|
||||
cc = bittst( r3, 0 );
|
||||
r3 = cc;
|
||||
r1 = p1;
|
||||
call _put_core_lock;
|
||||
rets = [sp++];
|
||||
r0 = r3;
|
||||
rts;
|
||||
ENDPROC(___raw_spin_is_locked_asm)
|
||||
|
||||
/*
|
||||
* r0 = &spinlock->lock
|
||||
*
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_spin_lock_asm)
|
||||
p1 = r0;
|
||||
[--sp] = rets;
|
||||
.Lretry_spinlock:
|
||||
call _get_core_lock;
|
||||
r1 = p1;
|
||||
r2 = [p1];
|
||||
cc = bittst( r2, 0 );
|
||||
if cc jump .Lbusy_spinlock
|
||||
#ifdef __ARCH_SYNC_CORE_DCACHE
|
||||
r3 = p1;
|
||||
bitset ( r2, 0 ); /* Raise the lock bit. */
|
||||
[p1] = r2;
|
||||
call _start_lock_coherent
|
||||
#else
|
||||
r2 = 1;
|
||||
[p1] = r2;
|
||||
call _put_core_lock;
|
||||
#endif
|
||||
rets = [sp++];
|
||||
rts;
|
||||
|
||||
.Lbusy_spinlock:
|
||||
/* We don't touch the atomic area if busy, so that flush
|
||||
will behave like nop in _put_core_lock. */
|
||||
call _put_core_lock;
|
||||
SSYNC(r2);
|
||||
r0 = p1;
|
||||
jump .Lretry_spinlock
|
||||
ENDPROC(___raw_spin_lock_asm)
|
||||
|
||||
/*
|
||||
* r0 = &spinlock->lock
|
||||
*
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_spin_trylock_asm)
|
||||
p1 = r0;
|
||||
[--sp] = rets;
|
||||
call _get_core_lock;
|
||||
r1 = p1;
|
||||
r3 = [p1];
|
||||
cc = bittst( r3, 0 );
|
||||
if cc jump .Lfailed_trylock
|
||||
#ifdef __ARCH_SYNC_CORE_DCACHE
|
||||
bitset ( r3, 0 ); /* Raise the lock bit. */
|
||||
[p1] = r3;
|
||||
call _start_lock_coherent
|
||||
#else
|
||||
r2 = 1;
|
||||
[p1] = r2;
|
||||
call _put_core_lock;
|
||||
#endif
|
||||
r0 = 1;
|
||||
rets = [sp++];
|
||||
rts;
|
||||
.Lfailed_trylock:
|
||||
call _put_core_lock;
|
||||
r0 = 0;
|
||||
rets = [sp++];
|
||||
rts;
|
||||
ENDPROC(___raw_spin_trylock_asm)
|
||||
|
||||
/*
|
||||
* r0 = &spinlock->lock
|
||||
*
|
||||
* Clobbers: r2:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_spin_unlock_asm)
|
||||
p1 = r0;
|
||||
[--sp] = rets;
|
||||
call _get_core_lock;
|
||||
r2 = [p1];
|
||||
bitclr ( r2, 0 );
|
||||
[p1] = r2;
|
||||
r1 = p1;
|
||||
#ifdef __ARCH_SYNC_CORE_DCACHE
|
||||
call _end_lock_coherent
|
||||
#else
|
||||
call _put_core_lock;
|
||||
#endif
|
||||
rets = [sp++];
|
||||
rts;
|
||||
ENDPROC(___raw_spin_unlock_asm)
|
||||
|
||||
/*
|
||||
* r0 = &rwlock->lock
|
||||
*
|
||||
* Clobbers: r2:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_read_lock_asm)
|
||||
p1 = r0;
|
||||
[--sp] = rets;
|
||||
call _get_core_lock;
|
||||
.Lrdlock_try:
|
||||
r1 = [p1];
|
||||
r1 += -1;
|
||||
[p1] = r1;
|
||||
cc = r1 < 0;
|
||||
if cc jump .Lrdlock_failed
|
||||
r1 = p1;
|
||||
#ifdef __ARCH_SYNC_CORE_DCACHE
|
||||
call _start_lock_coherent
|
||||
#else
|
||||
call _put_core_lock;
|
||||
#endif
|
||||
rets = [sp++];
|
||||
rts;
|
||||
|
||||
.Lrdlock_failed:
|
||||
r1 += 1;
|
||||
[p1] = r1;
|
||||
.Lrdlock_wait:
|
||||
r1 = p1;
|
||||
call _put_core_lock;
|
||||
SSYNC(r2);
|
||||
r0 = p1;
|
||||
call _get_core_lock;
|
||||
r1 = [p1];
|
||||
cc = r1 < 2;
|
||||
if cc jump .Lrdlock_wait;
|
||||
jump .Lrdlock_try
|
||||
ENDPROC(___raw_read_lock_asm)
|
||||
|
||||
/*
|
||||
* r0 = &rwlock->lock
|
||||
*
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_read_trylock_asm)
|
||||
p1 = r0;
|
||||
[--sp] = rets;
|
||||
call _get_core_lock;
|
||||
r1 = [p1];
|
||||
cc = r1 <= 0;
|
||||
if cc jump .Lfailed_tryrdlock;
|
||||
r1 += -1;
|
||||
[p1] = r1;
|
||||
r1 = p1;
|
||||
#ifdef __ARCH_SYNC_CORE_DCACHE
|
||||
call _start_lock_coherent
|
||||
#else
|
||||
call _put_core_lock;
|
||||
#endif
|
||||
rets = [sp++];
|
||||
r0 = 1;
|
||||
rts;
|
||||
.Lfailed_tryrdlock:
|
||||
r1 = p1;
|
||||
call _put_core_lock;
|
||||
rets = [sp++];
|
||||
r0 = 0;
|
||||
rts;
|
||||
ENDPROC(___raw_read_trylock_asm)
|
||||
|
||||
/*
|
||||
* r0 = &rwlock->lock
|
||||
*
|
||||
* Note: Processing controlled by a reader lock should not have
|
||||
* any side-effect on cache issues with the other core, so we
|
||||
* just release the core lock and exit (no _end_lock_coherent).
|
||||
*
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_read_unlock_asm)
|
||||
p1 = r0;
|
||||
[--sp] = rets;
|
||||
call _get_core_lock;
|
||||
r1 = [p1];
|
||||
r1 += 1;
|
||||
[p1] = r1;
|
||||
r1 = p1;
|
||||
call _put_core_lock;
|
||||
rets = [sp++];
|
||||
rts;
|
||||
ENDPROC(___raw_read_unlock_asm)
|
||||
|
||||
/*
|
||||
* r0 = &rwlock->lock
|
||||
*
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_write_lock_asm)
|
||||
p1 = r0;
|
||||
r3.l = lo(RW_LOCK_BIAS);
|
||||
r3.h = hi(RW_LOCK_BIAS);
|
||||
[--sp] = rets;
|
||||
call _get_core_lock;
|
||||
.Lwrlock_try:
|
||||
r1 = [p1];
|
||||
r1 = r1 - r3;
|
||||
#ifdef __ARCH_SYNC_CORE_DCACHE
|
||||
r2 = r1;
|
||||
r2 <<= 4;
|
||||
r2 >>= 4;
|
||||
cc = r2 == 0;
|
||||
#else
|
||||
cc = r1 == 0;
|
||||
#endif
|
||||
if !cc jump .Lwrlock_wait
|
||||
[p1] = r1;
|
||||
r1 = p1;
|
||||
#ifdef __ARCH_SYNC_CORE_DCACHE
|
||||
call _start_lock_coherent
|
||||
#else
|
||||
call _put_core_lock;
|
||||
#endif
|
||||
rets = [sp++];
|
||||
rts;
|
||||
|
||||
.Lwrlock_wait:
|
||||
r1 = p1;
|
||||
call _put_core_lock;
|
||||
SSYNC(r2);
|
||||
r0 = p1;
|
||||
call _get_core_lock;
|
||||
r1 = [p1];
|
||||
#ifdef __ARCH_SYNC_CORE_DCACHE
|
||||
r1 <<= 4;
|
||||
r1 >>= 4;
|
||||
#endif
|
||||
cc = r1 == r3;
|
||||
if !cc jump .Lwrlock_wait;
|
||||
jump .Lwrlock_try
|
||||
ENDPROC(___raw_write_lock_asm)
|
||||
|
||||
/*
|
||||
* r0 = &rwlock->lock
|
||||
*
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_write_trylock_asm)
|
||||
p1 = r0;
|
||||
[--sp] = rets;
|
||||
call _get_core_lock;
|
||||
r1 = [p1];
|
||||
r2.l = lo(RW_LOCK_BIAS);
|
||||
r2.h = hi(RW_LOCK_BIAS);
|
||||
cc = r1 == r2;
|
||||
if !cc jump .Lfailed_trywrlock;
|
||||
#ifdef __ARCH_SYNC_CORE_DCACHE
|
||||
r1 >>= 28;
|
||||
r1 <<= 28;
|
||||
#else
|
||||
r1 = 0;
|
||||
#endif
|
||||
[p1] = r1;
|
||||
r1 = p1;
|
||||
#ifdef __ARCH_SYNC_CORE_DCACHE
|
||||
call _start_lock_coherent
|
||||
#else
|
||||
call _put_core_lock;
|
||||
#endif
|
||||
rets = [sp++];
|
||||
r0 = 1;
|
||||
rts;
|
||||
|
||||
.Lfailed_trywrlock:
|
||||
r1 = p1;
|
||||
call _put_core_lock;
|
||||
rets = [sp++];
|
||||
r0 = 0;
|
||||
rts;
|
||||
ENDPROC(___raw_write_trylock_asm)
|
||||
|
||||
/*
|
||||
* r0 = &rwlock->lock
|
||||
*
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_write_unlock_asm)
|
||||
p1 = r0;
|
||||
r3.l = lo(RW_LOCK_BIAS);
|
||||
r3.h = hi(RW_LOCK_BIAS);
|
||||
[--sp] = rets;
|
||||
call _get_core_lock;
|
||||
r1 = [p1];
|
||||
r1 = r1 + r3;
|
||||
[p1] = r1;
|
||||
r1 = p1;
|
||||
#ifdef __ARCH_SYNC_CORE_DCACHE
|
||||
call _end_lock_coherent
|
||||
#else
|
||||
call _put_core_lock;
|
||||
#endif
|
||||
rets = [sp++];
|
||||
rts;
|
||||
ENDPROC(___raw_write_unlock_asm)
|
||||
|
||||
/*
|
||||
* r0 = ptr
|
||||
* r1 = value
|
||||
*
|
||||
* Add a signed value to a 32bit word and return the new value atomically.
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_atomic_update_asm)
|
||||
p1 = r0;
|
||||
r3 = r1;
|
||||
[--sp] = rets;
|
||||
call _get_core_lock;
|
||||
r2 = [p1];
|
||||
r3 = r3 + r2;
|
||||
[p1] = r3;
|
||||
r1 = p1;
|
||||
call _put_core_lock;
|
||||
r0 = r3;
|
||||
rets = [sp++];
|
||||
rts;
|
||||
ENDPROC(___raw_atomic_update_asm)
|
||||
|
||||
/*
|
||||
* r0 = ptr
|
||||
* r1 = mask
|
||||
*
|
||||
* Clear the mask bits from a 32bit word and return the old 32bit value
|
||||
* atomically.
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_atomic_clear_asm)
|
||||
p1 = r0;
|
||||
r3 = ~r1;
|
||||
[--sp] = rets;
|
||||
call _get_core_lock;
|
||||
r2 = [p1];
|
||||
r3 = r2 & r3;
|
||||
[p1] = r3;
|
||||
r3 = r2;
|
||||
r1 = p1;
|
||||
call _put_core_lock;
|
||||
r0 = r3;
|
||||
rets = [sp++];
|
||||
rts;
|
||||
ENDPROC(___raw_atomic_clear_asm)
|
||||
|
||||
/*
|
||||
* r0 = ptr
|
||||
* r1 = mask
|
||||
*
|
||||
* Set the mask bits into a 32bit word and return the old 32bit value
|
||||
* atomically.
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_atomic_set_asm)
|
||||
p1 = r0;
|
||||
r3 = r1;
|
||||
[--sp] = rets;
|
||||
call _get_core_lock;
|
||||
r2 = [p1];
|
||||
r3 = r2 | r3;
|
||||
[p1] = r3;
|
||||
r3 = r2;
|
||||
r1 = p1;
|
||||
call _put_core_lock;
|
||||
r0 = r3;
|
||||
rets = [sp++];
|
||||
rts;
|
||||
ENDPROC(___raw_atomic_set_asm)
|
||||
|
||||
/*
|
||||
* r0 = ptr
|
||||
* r1 = mask
|
||||
*
|
||||
* XOR the mask bits with a 32bit word and return the old 32bit value
|
||||
* atomically.
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_atomic_xor_asm)
|
||||
p1 = r0;
|
||||
r3 = r1;
|
||||
[--sp] = rets;
|
||||
call _get_core_lock;
|
||||
r2 = [p1];
|
||||
r3 = r2 ^ r3;
|
||||
[p1] = r3;
|
||||
r3 = r2;
|
||||
r1 = p1;
|
||||
call _put_core_lock;
|
||||
r0 = r3;
|
||||
rets = [sp++];
|
||||
rts;
|
||||
ENDPROC(___raw_atomic_xor_asm)
|
||||
|
||||
/*
|
||||
* r0 = ptr
|
||||
* r1 = mask
|
||||
*
|
||||
* Perform a logical AND between the mask bits and a 32bit word, and
|
||||
* return the masked value. We need this on this architecture in
|
||||
* order to invalidate the local cache before testing.
|
||||
*
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_atomic_test_asm)
|
||||
p1 = r0;
|
||||
r3 = r1;
|
||||
r1 = -L1_CACHE_BYTES;
|
||||
r1 = r0 & r1;
|
||||
p0 = r1;
|
||||
/* flush core internal write buffer before invalidate dcache */
|
||||
CSYNC(r2);
|
||||
flushinv[p0];
|
||||
SSYNC(r2);
|
||||
r0 = [p1];
|
||||
r0 = r0 & r3;
|
||||
rts;
|
||||
ENDPROC(___raw_atomic_test_asm)
|
||||
|
||||
/*
|
||||
* r0 = ptr
|
||||
* r1 = value
|
||||
*
|
||||
* Swap *ptr with value and return the old 32bit value atomically.
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
#define __do_xchg(src, dst) \
|
||||
p1 = r0; \
|
||||
r3 = r1; \
|
||||
[--sp] = rets; \
|
||||
call _get_core_lock; \
|
||||
r2 = src; \
|
||||
dst = r3; \
|
||||
r3 = r2; \
|
||||
r1 = p1; \
|
||||
call _put_core_lock; \
|
||||
r0 = r3; \
|
||||
rets = [sp++]; \
|
||||
rts;
|
||||
|
||||
ENTRY(___raw_xchg_1_asm)
|
||||
__do_xchg(b[p1] (z), b[p1])
|
||||
ENDPROC(___raw_xchg_1_asm)
|
||||
|
||||
ENTRY(___raw_xchg_2_asm)
|
||||
__do_xchg(w[p1] (z), w[p1])
|
||||
ENDPROC(___raw_xchg_2_asm)
|
||||
|
||||
ENTRY(___raw_xchg_4_asm)
|
||||
__do_xchg([p1], [p1])
|
||||
ENDPROC(___raw_xchg_4_asm)
|
||||
|
||||
/*
|
||||
* r0 = ptr
|
||||
* r1 = new
|
||||
* r2 = old
|
||||
*
|
||||
* Swap *ptr with new if *ptr == old and return the previous *ptr
|
||||
* value atomically.
|
||||
*
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
#define __do_cmpxchg(src, dst) \
|
||||
[--sp] = rets; \
|
||||
[--sp] = r4; \
|
||||
p1 = r0; \
|
||||
r3 = r1; \
|
||||
r4 = r2; \
|
||||
call _get_core_lock; \
|
||||
r2 = src; \
|
||||
cc = r2 == r4; \
|
||||
if !cc jump 1f; \
|
||||
dst = r3; \
|
||||
1: r3 = r2; \
|
||||
r1 = p1; \
|
||||
call _put_core_lock; \
|
||||
r0 = r3; \
|
||||
r4 = [sp++]; \
|
||||
rets = [sp++]; \
|
||||
rts;
|
||||
|
||||
ENTRY(___raw_cmpxchg_1_asm)
|
||||
__do_cmpxchg(b[p1] (z), b[p1])
|
||||
ENDPROC(___raw_cmpxchg_1_asm)
|
||||
|
||||
ENTRY(___raw_cmpxchg_2_asm)
|
||||
__do_cmpxchg(w[p1] (z), w[p1])
|
||||
ENDPROC(___raw_cmpxchg_2_asm)
|
||||
|
||||
ENTRY(___raw_cmpxchg_4_asm)
|
||||
__do_cmpxchg([p1], [p1])
|
||||
ENDPROC(___raw_cmpxchg_4_asm)
|
||||
|
||||
/*
|
||||
* r0 = ptr
|
||||
* r1 = bitnr
|
||||
*
|
||||
* Set a bit in a 32bit word and return the old 32bit value atomically.
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_bit_set_asm)
|
||||
r2 = r1;
|
||||
r1 = 1;
|
||||
r1 <<= r2;
|
||||
jump ___raw_atomic_set_asm
|
||||
ENDPROC(___raw_bit_set_asm)
|
||||
|
||||
/*
|
||||
* r0 = ptr
|
||||
* r1 = bitnr
|
||||
*
|
||||
* Clear a bit in a 32bit word and return the old 32bit value atomically.
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_bit_clear_asm)
|
||||
r2 = r1;
|
||||
r1 = 1;
|
||||
r1 <<= r2;
|
||||
jump ___raw_atomic_clear_asm
|
||||
ENDPROC(___raw_bit_clear_asm)
|
||||
|
||||
/*
|
||||
* r0 = ptr
|
||||
* r1 = bitnr
|
||||
*
|
||||
* Toggle a bit in a 32bit word and return the old 32bit value atomically.
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_bit_toggle_asm)
|
||||
r2 = r1;
|
||||
r1 = 1;
|
||||
r1 <<= r2;
|
||||
jump ___raw_atomic_xor_asm
|
||||
ENDPROC(___raw_bit_toggle_asm)
|
||||
|
||||
/*
|
||||
* r0 = ptr
|
||||
* r1 = bitnr
|
||||
*
|
||||
* Test-and-set a bit in a 32bit word and return the old bit value atomically.
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_bit_test_set_asm)
|
||||
[--sp] = rets;
|
||||
[--sp] = r1;
|
||||
call ___raw_bit_set_asm
|
||||
r1 = [sp++];
|
||||
r2 = 1;
|
||||
r2 <<= r1;
|
||||
r0 = r0 & r2;
|
||||
cc = r0 == 0;
|
||||
if cc jump 1f
|
||||
r0 = 1;
|
||||
1:
|
||||
rets = [sp++];
|
||||
rts;
|
||||
ENDPROC(___raw_bit_test_set_asm)
|
||||
|
||||
/*
|
||||
* r0 = ptr
|
||||
* r1 = bitnr
|
||||
*
|
||||
* Test-and-clear a bit in a 32bit word and return the old bit value atomically.
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_bit_test_clear_asm)
|
||||
[--sp] = rets;
|
||||
[--sp] = r1;
|
||||
call ___raw_bit_clear_asm
|
||||
r1 = [sp++];
|
||||
r2 = 1;
|
||||
r2 <<= r1;
|
||||
r0 = r0 & r2;
|
||||
cc = r0 == 0;
|
||||
if cc jump 1f
|
||||
r0 = 1;
|
||||
1:
|
||||
rets = [sp++];
|
||||
rts;
|
||||
ENDPROC(___raw_bit_test_clear_asm)
|
||||
|
||||
/*
|
||||
* r0 = ptr
|
||||
* r1 = bitnr
|
||||
*
|
||||
* Test-and-toggle a bit in a 32bit word,
|
||||
* and return the old bit value atomically.
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_bit_test_toggle_asm)
|
||||
[--sp] = rets;
|
||||
[--sp] = r1;
|
||||
call ___raw_bit_toggle_asm
|
||||
r1 = [sp++];
|
||||
r2 = 1;
|
||||
r2 <<= r1;
|
||||
r0 = r0 & r2;
|
||||
cc = r0 == 0;
|
||||
if cc jump 1f
|
||||
r0 = 1;
|
||||
1:
|
||||
rets = [sp++];
|
||||
rts;
|
||||
ENDPROC(___raw_bit_test_toggle_asm)
|
||||
|
||||
/*
|
||||
* r0 = ptr
|
||||
* r1 = bitnr
|
||||
*
|
||||
* Test a bit in a 32bit word and return its value.
|
||||
* We need this on this architecture in order to invalidate
|
||||
* the local cache before testing.
|
||||
*
|
||||
* Clobbers: r3:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_bit_test_asm)
|
||||
r2 = r1;
|
||||
r1 = 1;
|
||||
r1 <<= r2;
|
||||
jump ___raw_atomic_test_asm
|
||||
ENDPROC(___raw_bit_test_asm)
|
||||
|
||||
/*
|
||||
* r0 = ptr
|
||||
*
|
||||
* Fetch and return an uncached 32bit value.
|
||||
*
|
||||
* Clobbers: r2:0, p1:0
|
||||
*/
|
||||
ENTRY(___raw_uncached_fetch_asm)
|
||||
p1 = r0;
|
||||
r1 = -L1_CACHE_BYTES;
|
||||
r1 = r0 & r1;
|
||||
p0 = r1;
|
||||
/* flush core internal write buffer before invalidate dcache */
|
||||
CSYNC(r2);
|
||||
flushinv[p0];
|
||||
SSYNC(r2);
|
||||
r0 = [p1];
|
||||
rts;
|
||||
ENDPROC(___raw_uncached_fetch_asm)
|
||||
29
arch/blackfin/mach-bf561/boards/Kconfig
Normal file
29
arch/blackfin/mach-bf561/boards/Kconfig
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
choice
|
||||
prompt "System type"
|
||||
default BFIN561_EZKIT
|
||||
help
|
||||
Select your board!
|
||||
|
||||
config BFIN561_EZKIT
|
||||
bool "BF561-EZKIT"
|
||||
help
|
||||
BF561-EZKIT-LITE board support.
|
||||
|
||||
config BFIN561_TEPLA
|
||||
bool "BF561-TEPLA"
|
||||
help
|
||||
BF561-TEPLA board support.
|
||||
|
||||
config BFIN561_BLUETECHNIX_CM
|
||||
bool "Bluetechnix CM-BF561"
|
||||
help
|
||||
CM-BF561 support for EVAL- and DEV-Board.
|
||||
|
||||
config BFIN561_ACVILON
|
||||
bool "BF561-ACVILON"
|
||||
help
|
||||
BF561-ACVILON System On Module support (SO-DIMM 144).
|
||||
For more information about Acvilon BF561 SoM
|
||||
please go to http://www.niistt.ru/
|
||||
|
||||
endchoice
|
||||
8
arch/blackfin/mach-bf561/boards/Makefile
Normal file
8
arch/blackfin/mach-bf561/boards/Makefile
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
#
|
||||
# arch/blackfin/mach-bf561/boards/Makefile
|
||||
#
|
||||
|
||||
obj-$(CONFIG_BFIN561_ACVILON) += acvilon.o
|
||||
obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o
|
||||
obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o
|
||||
obj-$(CONFIG_BFIN561_TEPLA) += tepla.o
|
||||
543
arch/blackfin/mach-bf561/boards/acvilon.c
Normal file
543
arch/blackfin/mach-bf561/boards/acvilon.c
Normal file
|
|
@ -0,0 +1,543 @@
|
|||
/*
|
||||
* File: arch/blackfin/mach-bf561/acvilon.c
|
||||
* Based on: arch/blackfin/mach-bf561/ezkit.c
|
||||
* Author:
|
||||
*
|
||||
* Created:
|
||||
* Description:
|
||||
*
|
||||
* Modified:
|
||||
* Copyright 2004-2006 Analog Devices Inc.
|
||||
* Copyright 2009 CJSC "NII STT"
|
||||
*
|
||||
* Bugs:
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*
|
||||
*
|
||||
* For more information about Acvilon BF561 SoM please
|
||||
* go to http://www.niistt.ru/
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/mtd/plat-ram.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/flash.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/i2c-pca-platform.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/bfin5xx_spi.h>
|
||||
#include <asm/portmux.h>
|
||||
#include <asm/dpmc.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <linux/i2c.h>
|
||||
|
||||
/*
|
||||
* Name the Board for the /proc/cpuinfo
|
||||
*/
|
||||
const char bfin_board_name[] = "Acvilon board";
|
||||
|
||||
#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
|
||||
#include <linux/usb/isp1760.h>
|
||||
static struct resource bfin_isp1760_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x20000000,
|
||||
.end = 0x20000000 + 0x000fffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_PF15,
|
||||
.end = IRQ_PF15,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct isp1760_platform_data isp1760_priv = {
|
||||
.is_isp1761 = 0,
|
||||
.port1_disable = 0,
|
||||
.bus_width_16 = 1,
|
||||
.port1_otg = 0,
|
||||
.analog_oc = 0,
|
||||
.dack_polarity_high = 0,
|
||||
.dreq_polarity_high = 0,
|
||||
};
|
||||
|
||||
static struct platform_device bfin_isp1760_device = {
|
||||
.name = "isp1760-hcd",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &isp1760_priv,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(bfin_isp1760_resources),
|
||||
.resource = bfin_isp1760_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct resource bfin_i2c_pca_resources[] = {
|
||||
{
|
||||
.name = "pca9564-regs",
|
||||
.start = 0x2C000000,
|
||||
.end = 0x2C000000 + 16,
|
||||
.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
|
||||
}, {
|
||||
|
||||
.start = IRQ_PF8,
|
||||
.end = IRQ_PF8,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
|
||||
},
|
||||
};
|
||||
|
||||
struct i2c_pca9564_pf_platform_data pca9564_platform_data = {
|
||||
.gpio = -1,
|
||||
.i2c_clock_speed = 330000,
|
||||
.timeout = HZ,
|
||||
};
|
||||
|
||||
/* PCA9564 I2C Bus driver */
|
||||
static struct platform_device bfin_i2c_pca_device = {
|
||||
.name = "i2c-pca-platform",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(bfin_i2c_pca_resources),
|
||||
.resource = bfin_i2c_pca_resources,
|
||||
.dev = {
|
||||
.platform_data = &pca9564_platform_data,
|
||||
}
|
||||
};
|
||||
|
||||
/* I2C devices fitted. */
|
||||
static struct i2c_board_info acvilon_i2c_devs[] __initdata = {
|
||||
{
|
||||
I2C_BOARD_INFO("ds1339", 0x68),
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("tcn75", 0x49),
|
||||
},
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_PLATRAM)
|
||||
static struct platdata_mtd_ram mtd_ram_data = {
|
||||
.mapname = "rootfs(RAM)",
|
||||
.bankwidth = 4,
|
||||
};
|
||||
|
||||
static struct resource mtd_ram_resource = {
|
||||
.start = 0x4000000,
|
||||
.end = 0x5ffffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct platform_device mtd_ram_device = {
|
||||
.name = "mtd-ram",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &mtd_ram_data,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &mtd_ram_resource,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SMSC911X)
|
||||
#include <linux/smsc911x.h>
|
||||
static struct resource smsc911x_resources[] = {
|
||||
{
|
||||
.name = "smsc911x-memory",
|
||||
.start = 0x28000000,
|
||||
.end = 0x28000000 + 0xFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_PF7,
|
||||
.end = IRQ_PF7,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct smsc911x_platform_config smsc911x_config = {
|
||||
.flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
|
||||
.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
|
||||
.phy_interface = PHY_INTERFACE_MODE_MII,
|
||||
};
|
||||
|
||||
static struct platform_device smsc911x_device = {
|
||||
.name = "smsc911x",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(smsc911x_resources),
|
||||
.resource = smsc911x_resources,
|
||||
.dev = {
|
||||
.platform_data = &smsc911x_config,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SERIAL_BFIN)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
static struct resource bfin_uart0_resources[] = {
|
||||
{
|
||||
.start = BFIN_UART_THR,
|
||||
.end = BFIN_UART_GCTL + 2,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART_TX,
|
||||
.end = IRQ_UART_TX,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART_RX,
|
||||
.end = IRQ_UART_RX,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART_ERROR,
|
||||
.end = IRQ_UART_ERROR,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = CH_UART_TX,
|
||||
.end = CH_UART_TX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.start = CH_UART_RX,
|
||||
.end = CH_UART_RX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static unsigned short bfin_uart0_peripherals[] = {
|
||||
P_UART0_TX, P_UART0_RX, 0
|
||||
};
|
||||
|
||||
static struct platform_device bfin_uart0_device = {
|
||||
.name = "bfin-uart",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(bfin_uart0_resources),
|
||||
.resource = bfin_uart0_resources,
|
||||
.dev = {
|
||||
/* Passed to driver */
|
||||
.platform_data = &bfin_uart0_peripherals,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
|
||||
|
||||
static struct mtd_partition bfin_plat_nand_partitions[] = {
|
||||
{
|
||||
.name = "params(nand)",
|
||||
.size = 32 * 1024 * 1024,
|
||||
.offset = 0,
|
||||
}, {
|
||||
.name = "userfs(nand)",
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
},
|
||||
};
|
||||
|
||||
#define BFIN_NAND_PLAT_CLE 2
|
||||
#define BFIN_NAND_PLAT_ALE 3
|
||||
|
||||
static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
|
||||
unsigned int ctrl)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
|
||||
if (cmd == NAND_CMD_NONE)
|
||||
return;
|
||||
|
||||
if (ctrl & NAND_CLE)
|
||||
writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
|
||||
else
|
||||
writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
|
||||
}
|
||||
|
||||
#define BFIN_NAND_PLAT_READY GPIO_PF10
|
||||
static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
return gpio_get_value(BFIN_NAND_PLAT_READY);
|
||||
}
|
||||
|
||||
static struct platform_nand_data bfin_plat_nand_data = {
|
||||
.chip = {
|
||||
.nr_chips = 1,
|
||||
.chip_delay = 30,
|
||||
.partitions = bfin_plat_nand_partitions,
|
||||
.nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
|
||||
},
|
||||
.ctrl = {
|
||||
.cmd_ctrl = bfin_plat_nand_cmd_ctrl,
|
||||
.dev_ready = bfin_plat_nand_dev_ready,
|
||||
},
|
||||
};
|
||||
|
||||
#define MAX(x, y) (x > y ? x : y)
|
||||
static struct resource bfin_plat_nand_resources = {
|
||||
.start = 0x24000000,
|
||||
.end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct platform_device bfin_async_nand_device = {
|
||||
.name = "gen_nand",
|
||||
.id = -1,
|
||||
.num_resources = 1,
|
||||
.resource = &bfin_plat_nand_resources,
|
||||
.dev = {
|
||||
.platform_data = &bfin_plat_nand_data,
|
||||
},
|
||||
};
|
||||
|
||||
static void bfin_plat_nand_init(void)
|
||||
{
|
||||
gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
|
||||
}
|
||||
#else
|
||||
static void bfin_plat_nand_init(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
|
||||
static struct mtd_partition bfin_spi_dataflash_partitions[] = {
|
||||
{
|
||||
.name = "bootloader",
|
||||
.size = 0x4200,
|
||||
.offset = 0,
|
||||
.mask_flags = MTD_CAP_ROM},
|
||||
{
|
||||
.name = "u-boot",
|
||||
.size = 0x42000,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
},
|
||||
{
|
||||
.name = "u-boot(params)",
|
||||
.size = 0x4200,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
},
|
||||
{
|
||||
.name = "kernel",
|
||||
.size = 0x294000,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
},
|
||||
{
|
||||
.name = "params",
|
||||
.size = 0x42000,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
},
|
||||
{
|
||||
.name = "rootfs",
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
}
|
||||
};
|
||||
|
||||
static struct flash_platform_data bfin_spi_dataflash_data = {
|
||||
.name = "SPI Dataflash",
|
||||
.parts = bfin_spi_dataflash_partitions,
|
||||
.nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
|
||||
};
|
||||
|
||||
/* DataFlash chip */
|
||||
static struct bfin5xx_spi_chip data_flash_chip_info = {
|
||||
.enable_dma = 0, /* use dma transfer with this chip */
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
|
||||
/* SPI (0) */
|
||||
static struct resource bfin_spi0_resource[] = {
|
||||
[0] = {
|
||||
.start = SPI0_REGBASE,
|
||||
.end = SPI0_REGBASE + 0xFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = CH_SPI,
|
||||
.end = CH_SPI,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[2] = {
|
||||
.start = IRQ_SPI,
|
||||
.end = IRQ_SPI,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
/* SPI controller data */
|
||||
static struct bfin5xx_spi_master bfin_spi0_info = {
|
||||
.num_chipselect = 8,
|
||||
.enable_dma = 1, /* master has the ability to do dma transfer */
|
||||
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
|
||||
};
|
||||
|
||||
static struct platform_device bfin_spi0_device = {
|
||||
.name = "bfin-spi",
|
||||
.id = 0, /* Bus number */
|
||||
.num_resources = ARRAY_SIZE(bfin_spi0_resource),
|
||||
.resource = bfin_spi0_resource,
|
||||
.dev = {
|
||||
.platform_data = &bfin_spi0_info, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
||||
#if IS_ENABLED(CONFIG_SPI_SPIDEV)
|
||||
{
|
||||
.modalias = "spidev",
|
||||
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 3,
|
||||
},
|
||||
#endif
|
||||
#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
|
||||
{ /* DataFlash chip */
|
||||
.modalias = "mtd_dataflash",
|
||||
.max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0, /* Framework bus number */
|
||||
.chip_select = 2, /* Framework chip select */
|
||||
.platform_data = &bfin_spi_dataflash_data,
|
||||
.controller_data = &data_flash_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct resource bfin_gpios_resources = {
|
||||
.start = 31,
|
||||
/* .end = MAX_BLACKFIN_GPIOS - 1, */
|
||||
.end = 32,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
};
|
||||
|
||||
static struct platform_device bfin_gpios_device = {
|
||||
.name = "simple-gpio",
|
||||
.id = -1,
|
||||
.num_resources = 1,
|
||||
.resource = &bfin_gpios_resources,
|
||||
};
|
||||
|
||||
static const unsigned int cclk_vlev_datasheet[] = {
|
||||
VRPAIR(VLEV_085, 250000000),
|
||||
VRPAIR(VLEV_090, 300000000),
|
||||
VRPAIR(VLEV_095, 313000000),
|
||||
VRPAIR(VLEV_100, 350000000),
|
||||
VRPAIR(VLEV_105, 400000000),
|
||||
VRPAIR(VLEV_110, 444000000),
|
||||
VRPAIR(VLEV_115, 450000000),
|
||||
VRPAIR(VLEV_120, 475000000),
|
||||
VRPAIR(VLEV_125, 500000000),
|
||||
VRPAIR(VLEV_130, 600000000),
|
||||
};
|
||||
|
||||
static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
|
||||
.tuple_tab = cclk_vlev_datasheet,
|
||||
.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
|
||||
.vr_settling_time = 25 /* us */ ,
|
||||
};
|
||||
|
||||
static struct platform_device bfin_dpmc = {
|
||||
.name = "bfin dpmc",
|
||||
.dev = {
|
||||
.platform_data = &bfin_dmpc_vreg_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *acvilon_devices[] __initdata = {
|
||||
&bfin_dpmc,
|
||||
|
||||
#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
|
||||
&bfin_spi0_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SERIAL_BFIN)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
&bfin_uart0_device,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
&bfin_gpios_device,
|
||||
|
||||
#if IS_ENABLED(CONFIG_SMSC911X)
|
||||
&smsc911x_device,
|
||||
#endif
|
||||
|
||||
&bfin_i2c_pca_device,
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
|
||||
&bfin_async_nand_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_PLATRAM)
|
||||
&mtd_ram_device,
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
static int __init acvilon_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
printk(KERN_INFO "%s(): registering device resources\n", __func__);
|
||||
|
||||
bfin_plat_nand_init();
|
||||
ret =
|
||||
platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices));
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
i2c_register_board_info(0, acvilon_i2c_devs,
|
||||
ARRAY_SIZE(acvilon_i2c_devs));
|
||||
|
||||
bfin_write_FIO0_FLAG_C(1 << 14);
|
||||
msleep(5);
|
||||
bfin_write_FIO0_FLAG_S(1 << 14);
|
||||
|
||||
spi_register_board_info(bfin_spi_board_info,
|
||||
ARRAY_SIZE(bfin_spi_board_info));
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(acvilon_init);
|
||||
|
||||
static struct platform_device *acvilon_early_devices[] __initdata = {
|
||||
#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
&bfin_uart0_device,
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
void __init native_machine_early_platform_add_devices(void)
|
||||
{
|
||||
printk(KERN_INFO "register early platform devices\n");
|
||||
early_platform_add_devices(acvilon_early_devices,
|
||||
ARRAY_SIZE(acvilon_early_devices));
|
||||
}
|
||||
555
arch/blackfin/mach-bf561/boards/cm_bf561.c
Normal file
555
arch/blackfin/mach-bf561/boards/cm_bf561.c
Normal file
|
|
@ -0,0 +1,555 @@
|
|||
/*
|
||||
* Copyright 2004-2009 Analog Devices Inc.
|
||||
* 2008-2009 Bluetechnix
|
||||
* 2005 National ICT Australia (NICTA)
|
||||
* Aidan Williams <aidan@nicta.com.au>
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/flash.h>
|
||||
#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
|
||||
#include <linux/usb/isp1362.h>
|
||||
#endif
|
||||
#include <linux/ata_platform.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/bfin5xx_spi.h>
|
||||
#include <asm/portmux.h>
|
||||
#include <asm/dpmc.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
|
||||
/*
|
||||
* Name the Board for the /proc/cpuinfo
|
||||
*/
|
||||
const char bfin_board_name[] = "Bluetechnix CM BF561";
|
||||
|
||||
#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
|
||||
/* all SPI peripherals info goes here */
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_M25P80)
|
||||
static struct mtd_partition bfin_spi_flash_partitions[] = {
|
||||
{
|
||||
.name = "bootloader(spi)",
|
||||
.size = 0x00020000,
|
||||
.offset = 0,
|
||||
.mask_flags = MTD_CAP_ROM
|
||||
}, {
|
||||
.name = "linux kernel(spi)",
|
||||
.size = 0xe0000,
|
||||
.offset = 0x20000
|
||||
}, {
|
||||
.name = "file system(spi)",
|
||||
.size = 0x700000,
|
||||
.offset = 0x00100000,
|
||||
}
|
||||
};
|
||||
|
||||
static struct flash_platform_data bfin_spi_flash_data = {
|
||||
.name = "m25p80",
|
||||
.parts = bfin_spi_flash_partitions,
|
||||
.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
|
||||
.type = "m25p64",
|
||||
};
|
||||
|
||||
/* SPI flash chip (m25p64) */
|
||||
static struct bfin5xx_spi_chip spi_flash_chip_info = {
|
||||
.enable_dma = 0, /* use dma transfer with this chip*/
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
||||
#if IS_ENABLED(CONFIG_MTD_M25P80)
|
||||
{
|
||||
/* the modalias must be the same as spi device driver name */
|
||||
.modalias = "m25p80", /* Name of spi_driver for this device */
|
||||
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0, /* Framework bus number */
|
||||
.chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
|
||||
.platform_data = &bfin_spi_flash_data,
|
||||
.controller_data = &spi_flash_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
|
||||
{
|
||||
.modalias = "ad183x",
|
||||
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 4,
|
||||
},
|
||||
#endif
|
||||
#if IS_ENABLED(CONFIG_MMC_SPI)
|
||||
{
|
||||
.modalias = "mmc_spi",
|
||||
.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 1,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
/* SPI (0) */
|
||||
static struct resource bfin_spi0_resource[] = {
|
||||
[0] = {
|
||||
.start = SPI0_REGBASE,
|
||||
.end = SPI0_REGBASE + 0xFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = CH_SPI,
|
||||
.end = CH_SPI,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[2] = {
|
||||
.start = IRQ_SPI,
|
||||
.end = IRQ_SPI,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
/* SPI controller data */
|
||||
static struct bfin5xx_spi_master bfin_spi0_info = {
|
||||
.num_chipselect = 8,
|
||||
.enable_dma = 1, /* master has the ability to do dma transfer */
|
||||
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
|
||||
};
|
||||
|
||||
static struct platform_device bfin_spi0_device = {
|
||||
.name = "bfin-spi",
|
||||
.id = 0, /* Bus number */
|
||||
.num_resources = ARRAY_SIZE(bfin_spi0_resource),
|
||||
.resource = bfin_spi0_resource,
|
||||
.dev = {
|
||||
.platform_data = &bfin_spi0_info, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif /* spi master and devices */
|
||||
|
||||
|
||||
#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
|
||||
static struct platform_device hitachi_fb_device = {
|
||||
.name = "hitachi-tx09",
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
#if IS_ENABLED(CONFIG_SMC91X)
|
||||
#include <linux/smc91x.h>
|
||||
|
||||
static struct smc91x_platdata smc91x_info = {
|
||||
.flags = SMC91X_USE_32BIT | SMC91X_NOWAIT,
|
||||
.leda = RPC_LED_100_10,
|
||||
.ledb = RPC_LED_TX_RX,
|
||||
};
|
||||
|
||||
static struct resource smc91x_resources[] = {
|
||||
{
|
||||
.name = "smc91x-regs",
|
||||
.start = 0x28000300,
|
||||
.end = 0x28000300 + 16,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_PF0,
|
||||
.end = IRQ_PF0,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
|
||||
},
|
||||
};
|
||||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
.dev = {
|
||||
.platform_data = &smc91x_info,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SMSC911X)
|
||||
#include <linux/smsc911x.h>
|
||||
|
||||
static struct resource smsc911x_resources[] = {
|
||||
{
|
||||
.name = "smsc911x-memory",
|
||||
.start = 0x24008000,
|
||||
.end = 0x24008000 + 0xFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_PF43,
|
||||
.end = IRQ_PF43,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct smsc911x_platform_config smsc911x_config = {
|
||||
.flags = SMSC911X_USE_16BIT,
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
|
||||
.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
|
||||
.phy_interface = PHY_INTERFACE_MODE_MII,
|
||||
};
|
||||
|
||||
static struct platform_device smsc911x_device = {
|
||||
.name = "smsc911x",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(smsc911x_resources),
|
||||
.resource = smsc911x_resources,
|
||||
.dev = {
|
||||
.platform_data = &smsc911x_config,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_USB_NET2272)
|
||||
static struct resource net2272_bfin_resources[] = {
|
||||
{
|
||||
.start = 0x24000000,
|
||||
.end = 0x24000000 + 0x100,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_PF45,
|
||||
.end = IRQ_PF45,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device net2272_bfin_device = {
|
||||
.name = "net2272",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(net2272_bfin_resources),
|
||||
.resource = net2272_bfin_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
|
||||
static struct resource isp1362_hcd_resources[] = {
|
||||
{
|
||||
.start = 0x24008000,
|
||||
.end = 0x24008000,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = 0x24008004,
|
||||
.end = 0x24008004,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_PF47,
|
||||
.end = IRQ_PF47,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct isp1362_platform_data isp1362_priv = {
|
||||
.sel15Kres = 1,
|
||||
.clknotstop = 0,
|
||||
.oc_enable = 0,
|
||||
.int_act_high = 0,
|
||||
.int_edge_triggered = 0,
|
||||
.remote_wakeup_connected = 0,
|
||||
.no_power_switching = 1,
|
||||
.power_switching_mode = 0,
|
||||
};
|
||||
|
||||
static struct platform_device isp1362_hcd_device = {
|
||||
.name = "isp1362-hcd",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &isp1362_priv,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
|
||||
.resource = isp1362_hcd_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SERIAL_BFIN)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
static struct resource bfin_uart0_resources[] = {
|
||||
{
|
||||
.start = BFIN_UART_THR,
|
||||
.end = BFIN_UART_GCTL+2,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART_TX,
|
||||
.end = IRQ_UART_TX,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART_RX,
|
||||
.end = IRQ_UART_RX,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART_ERROR,
|
||||
.end = IRQ_UART_ERROR,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = CH_UART_TX,
|
||||
.end = CH_UART_TX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.start = CH_UART_RX,
|
||||
.end = CH_UART_RX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static unsigned short bfin_uart0_peripherals[] = {
|
||||
P_UART0_TX, P_UART0_RX, 0
|
||||
};
|
||||
|
||||
static struct platform_device bfin_uart0_device = {
|
||||
.name = "bfin-uart",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(bfin_uart0_resources),
|
||||
.resource = bfin_uart0_resources,
|
||||
.dev = {
|
||||
.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_BFIN_SIR)
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
static struct resource bfin_sir0_resources[] = {
|
||||
{
|
||||
.start = 0xFFC00400,
|
||||
.end = 0xFFC004FF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART0_RX,
|
||||
.end = IRQ_UART0_RX+1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = CH_UART0_RX,
|
||||
.end = CH_UART0_RX+1,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device bfin_sir0_device = {
|
||||
.name = "bfin_sir",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(bfin_sir0_resources),
|
||||
.resource = bfin_sir0_resources,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_PATA_PLATFORM)
|
||||
#define PATA_INT IRQ_PF46
|
||||
|
||||
static struct pata_platform_info bfin_pata_platform_data = {
|
||||
.ioport_shift = 2,
|
||||
};
|
||||
|
||||
static struct resource bfin_pata_resources[] = {
|
||||
{
|
||||
.start = 0x2400C000,
|
||||
.end = 0x2400C001F,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = 0x2400D018,
|
||||
.end = 0x2400D01B,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = PATA_INT,
|
||||
.end = PATA_INT,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device bfin_pata_device = {
|
||||
.name = "pata_platform",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(bfin_pata_resources),
|
||||
.resource = bfin_pata_resources,
|
||||
.dev = {
|
||||
.platform_data = &bfin_pata_platform_data,
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
|
||||
static struct mtd_partition para_partitions[] = {
|
||||
{
|
||||
.name = "bootloader(nor)",
|
||||
.size = 0x40000,
|
||||
.offset = 0,
|
||||
}, {
|
||||
.name = "linux kernel(nor)",
|
||||
.size = 0x100000,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
}, {
|
||||
.name = "file system(nor)",
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
}
|
||||
};
|
||||
|
||||
static struct physmap_flash_data para_flash_data = {
|
||||
.width = 2,
|
||||
.parts = para_partitions,
|
||||
.nr_parts = ARRAY_SIZE(para_partitions),
|
||||
};
|
||||
|
||||
static struct resource para_flash_resource = {
|
||||
.start = 0x20000000,
|
||||
.end = 0x207fffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct platform_device para_flash_device = {
|
||||
.name = "physmap-flash",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = ¶_flash_data,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = ¶_flash_resource,
|
||||
};
|
||||
#endif
|
||||
|
||||
static const unsigned int cclk_vlev_datasheet[] =
|
||||
{
|
||||
VRPAIR(VLEV_085, 250000000),
|
||||
VRPAIR(VLEV_090, 300000000),
|
||||
VRPAIR(VLEV_095, 313000000),
|
||||
VRPAIR(VLEV_100, 350000000),
|
||||
VRPAIR(VLEV_105, 400000000),
|
||||
VRPAIR(VLEV_110, 444000000),
|
||||
VRPAIR(VLEV_115, 450000000),
|
||||
VRPAIR(VLEV_120, 475000000),
|
||||
VRPAIR(VLEV_125, 500000000),
|
||||
VRPAIR(VLEV_130, 600000000),
|
||||
};
|
||||
|
||||
static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
|
||||
.tuple_tab = cclk_vlev_datasheet,
|
||||
.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
|
||||
.vr_settling_time = 25 /* us */,
|
||||
};
|
||||
|
||||
static struct platform_device bfin_dpmc = {
|
||||
.name = "bfin dpmc",
|
||||
.dev = {
|
||||
.platform_data = &bfin_dmpc_vreg_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *cm_bf561_devices[] __initdata = {
|
||||
|
||||
&bfin_dpmc,
|
||||
|
||||
#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
|
||||
&hitachi_fb_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SERIAL_BFIN)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
&bfin_uart0_device,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_BFIN_SIR)
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
&bfin_sir0_device,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
|
||||
&isp1362_hcd_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SMC91X)
|
||||
&smc91x_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SMSC911X)
|
||||
&smsc911x_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_USB_NET2272)
|
||||
&net2272_bfin_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
|
||||
&bfin_spi0_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_PATA_PLATFORM)
|
||||
&bfin_pata_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
|
||||
¶_flash_device,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int __init net2272_init(void)
|
||||
{
|
||||
#if IS_ENABLED(CONFIG_USB_NET2272)
|
||||
int ret;
|
||||
|
||||
ret = gpio_request(GPIO_PF46, "net2272");
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Reset USB Chip, PF46 */
|
||||
gpio_direction_output(GPIO_PF46, 0);
|
||||
mdelay(2);
|
||||
gpio_set_value(GPIO_PF46, 1);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init cm_bf561_init(void)
|
||||
{
|
||||
printk(KERN_INFO "%s(): registering device resources\n", __func__);
|
||||
platform_add_devices(cm_bf561_devices, ARRAY_SIZE(cm_bf561_devices));
|
||||
#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
|
||||
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_PATA_PLATFORM)
|
||||
irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
|
||||
#endif
|
||||
|
||||
if (net2272_init())
|
||||
pr_warning("unable to configure net2272; it probably won't work\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(cm_bf561_init);
|
||||
|
||||
static struct platform_device *cm_bf561_early_devices[] __initdata = {
|
||||
#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
&bfin_uart0_device,
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
void __init native_machine_early_platform_add_devices(void)
|
||||
{
|
||||
printk(KERN_INFO "register early platform devices\n");
|
||||
early_platform_add_devices(cm_bf561_early_devices,
|
||||
ARRAY_SIZE(cm_bf561_early_devices));
|
||||
}
|
||||
677
arch/blackfin/mach-bf561/boards/ezkit.c
Normal file
677
arch/blackfin/mach-bf561/boards/ezkit.c
Normal file
|
|
@ -0,0 +1,677 @@
|
|||
/*
|
||||
* Copyright 2004-2009 Analog Devices Inc.
|
||||
* 2005 National ICT Australia (NICTA)
|
||||
* Aidan Williams <aidan@nicta.com.au>
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/delay.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/bfin5xx_spi.h>
|
||||
#include <asm/portmux.h>
|
||||
#include <asm/dpmc.h>
|
||||
|
||||
/*
|
||||
* Name the Board for the /proc/cpuinfo
|
||||
*/
|
||||
const char bfin_board_name[] = "ADI BF561-EZKIT";
|
||||
|
||||
#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
|
||||
#include <linux/usb/isp1760.h>
|
||||
static struct resource bfin_isp1760_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x2C0F0000,
|
||||
.end = 0x203C0000 + 0xfffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_PF10,
|
||||
.end = IRQ_PF10,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct isp1760_platform_data isp1760_priv = {
|
||||
.is_isp1761 = 0,
|
||||
.bus_width_16 = 1,
|
||||
.port1_otg = 0,
|
||||
.analog_oc = 0,
|
||||
.dack_polarity_high = 0,
|
||||
.dreq_polarity_high = 0,
|
||||
};
|
||||
|
||||
static struct platform_device bfin_isp1760_device = {
|
||||
.name = "isp1760",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &isp1760_priv,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(bfin_isp1760_resources),
|
||||
.resource = bfin_isp1760_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
|
||||
#include <linux/usb/isp1362.h>
|
||||
|
||||
static struct resource isp1362_hcd_resources[] = {
|
||||
{
|
||||
.start = 0x2c060000,
|
||||
.end = 0x2c060000,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = 0x2c060004,
|
||||
.end = 0x2c060004,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_PF8,
|
||||
.end = IRQ_PF8,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct isp1362_platform_data isp1362_priv = {
|
||||
.sel15Kres = 1,
|
||||
.clknotstop = 0,
|
||||
.oc_enable = 0,
|
||||
.int_act_high = 0,
|
||||
.int_edge_triggered = 0,
|
||||
.remote_wakeup_connected = 0,
|
||||
.no_power_switching = 1,
|
||||
.power_switching_mode = 0,
|
||||
};
|
||||
|
||||
static struct platform_device isp1362_hcd_device = {
|
||||
.name = "isp1362-hcd",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &isp1362_priv,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
|
||||
.resource = isp1362_hcd_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_USB_NET2272)
|
||||
static struct resource net2272_bfin_resources[] = {
|
||||
{
|
||||
.start = 0x2C000000,
|
||||
.end = 0x2C000000 + 0x7F,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = 1,
|
||||
.flags = IORESOURCE_BUS,
|
||||
}, {
|
||||
.start = IRQ_PF10,
|
||||
.end = IRQ_PF10,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device net2272_bfin_device = {
|
||||
.name = "net2272",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(net2272_bfin_resources),
|
||||
.resource = net2272_bfin_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB-LAN EzExtender board
|
||||
* Driver needs to know address, irq and flag pin.
|
||||
*/
|
||||
#if IS_ENABLED(CONFIG_SMC91X)
|
||||
#include <linux/smc91x.h>
|
||||
|
||||
static struct smc91x_platdata smc91x_info = {
|
||||
.flags = SMC91X_USE_32BIT | SMC91X_NOWAIT,
|
||||
.leda = RPC_LED_100_10,
|
||||
.ledb = RPC_LED_TX_RX,
|
||||
};
|
||||
|
||||
static struct resource smc91x_resources[] = {
|
||||
{
|
||||
.name = "smc91x-regs",
|
||||
.start = 0x2C010300,
|
||||
.end = 0x2C010300 + 16,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
|
||||
.start = IRQ_PF9,
|
||||
.end = IRQ_PF9,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
.dev = {
|
||||
.platform_data = &smc91x_info,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SERIAL_BFIN)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
static struct resource bfin_uart0_resources[] = {
|
||||
{
|
||||
.start = BFIN_UART_THR,
|
||||
.end = BFIN_UART_GCTL+2,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART_TX,
|
||||
.end = IRQ_UART_TX,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART_RX,
|
||||
.end = IRQ_UART_RX,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART_ERROR,
|
||||
.end = IRQ_UART_ERROR,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = CH_UART_TX,
|
||||
.end = CH_UART_TX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.start = CH_UART_RX,
|
||||
.end = CH_UART_RX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static unsigned short bfin_uart0_peripherals[] = {
|
||||
P_UART0_TX, P_UART0_RX, 0
|
||||
};
|
||||
|
||||
static struct platform_device bfin_uart0_device = {
|
||||
.name = "bfin-uart",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(bfin_uart0_resources),
|
||||
.resource = bfin_uart0_resources,
|
||||
.dev = {
|
||||
.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_BFIN_SIR)
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
static struct resource bfin_sir0_resources[] = {
|
||||
{
|
||||
.start = 0xFFC00400,
|
||||
.end = 0xFFC004FF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART0_RX,
|
||||
.end = IRQ_UART0_RX+1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = CH_UART0_RX,
|
||||
.end = CH_UART0_RX+1,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device bfin_sir0_device = {
|
||||
.name = "bfin_sir",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(bfin_sir0_resources),
|
||||
.resource = bfin_sir0_resources,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
|
||||
static struct mtd_partition ezkit_partitions[] = {
|
||||
{
|
||||
.name = "bootloader(nor)",
|
||||
.size = 0x40000,
|
||||
.offset = 0,
|
||||
}, {
|
||||
.name = "linux kernel(nor)",
|
||||
.size = 0x1C0000,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
}, {
|
||||
.name = "file system(nor)",
|
||||
.size = 0x800000 - 0x40000 - 0x1C0000 - 0x2000 * 8,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
}, {
|
||||
.name = "config(nor)",
|
||||
.size = 0x2000 * 7,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
}, {
|
||||
.name = "u-boot env(nor)",
|
||||
.size = 0x2000,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
}
|
||||
};
|
||||
|
||||
static struct physmap_flash_data ezkit_flash_data = {
|
||||
.width = 2,
|
||||
.parts = ezkit_partitions,
|
||||
.nr_parts = ARRAY_SIZE(ezkit_partitions),
|
||||
};
|
||||
|
||||
static struct resource ezkit_flash_resource = {
|
||||
.start = 0x20000000,
|
||||
.end = 0x207fffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct platform_device ezkit_flash_device = {
|
||||
.name = "physmap-flash",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &ezkit_flash_data,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &ezkit_flash_resource,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
|
||||
/* SPI (0) */
|
||||
static struct resource bfin_spi0_resource[] = {
|
||||
[0] = {
|
||||
.start = SPI0_REGBASE,
|
||||
.end = SPI0_REGBASE + 0xFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = CH_SPI,
|
||||
.end = CH_SPI,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
[2] = {
|
||||
.start = IRQ_SPI,
|
||||
.end = IRQ_SPI,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
/* SPI controller data */
|
||||
static struct bfin5xx_spi_master bfin_spi0_info = {
|
||||
.num_chipselect = 8,
|
||||
.enable_dma = 1, /* master has the ability to do dma transfer */
|
||||
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
|
||||
};
|
||||
|
||||
static struct platform_device bfin_spi0_device = {
|
||||
.name = "bfin-spi",
|
||||
.id = 0, /* Bus number */
|
||||
.num_resources = ARRAY_SIZE(bfin_spi0_resource),
|
||||
.resource = bfin_spi0_resource,
|
||||
.dev = {
|
||||
.platform_data = &bfin_spi0_info, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
||||
#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
|
||||
{
|
||||
.modalias = "ad183x",
|
||||
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 4,
|
||||
.platform_data = "ad1836", /* only includes chip name for the moment */
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
#if IS_ENABLED(CONFIG_SPI_SPIDEV)
|
||||
{
|
||||
.modalias = "spidev",
|
||||
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
|
||||
.bus_num = 0,
|
||||
.chip_select = 1,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
|
||||
#include <linux/input.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
|
||||
static struct gpio_keys_button bfin_gpio_keys_table[] = {
|
||||
{BTN_0, GPIO_PF5, 1, "gpio-keys: BTN0"},
|
||||
{BTN_1, GPIO_PF6, 1, "gpio-keys: BTN1"},
|
||||
{BTN_2, GPIO_PF7, 1, "gpio-keys: BTN2"},
|
||||
{BTN_3, GPIO_PF8, 1, "gpio-keys: BTN3"},
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data bfin_gpio_keys_data = {
|
||||
.buttons = bfin_gpio_keys_table,
|
||||
.nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
|
||||
};
|
||||
|
||||
static struct platform_device bfin_device_gpiokeys = {
|
||||
.name = "gpio-keys",
|
||||
.dev = {
|
||||
.platform_data = &bfin_gpio_keys_data,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_I2C_GPIO)
|
||||
#include <linux/i2c-gpio.h>
|
||||
|
||||
static struct i2c_gpio_platform_data i2c_gpio_data = {
|
||||
.sda_pin = GPIO_PF1,
|
||||
.scl_pin = GPIO_PF0,
|
||||
.sda_is_open_drain = 0,
|
||||
.scl_is_open_drain = 0,
|
||||
.udelay = 10,
|
||||
};
|
||||
|
||||
static struct platform_device i2c_gpio_device = {
|
||||
.name = "i2c-gpio",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &i2c_gpio_data,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
static const unsigned int cclk_vlev_datasheet[] =
|
||||
{
|
||||
VRPAIR(VLEV_085, 250000000),
|
||||
VRPAIR(VLEV_090, 300000000),
|
||||
VRPAIR(VLEV_095, 313000000),
|
||||
VRPAIR(VLEV_100, 350000000),
|
||||
VRPAIR(VLEV_105, 400000000),
|
||||
VRPAIR(VLEV_110, 444000000),
|
||||
VRPAIR(VLEV_115, 450000000),
|
||||
VRPAIR(VLEV_120, 475000000),
|
||||
VRPAIR(VLEV_125, 500000000),
|
||||
VRPAIR(VLEV_130, 600000000),
|
||||
};
|
||||
|
||||
static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
|
||||
.tuple_tab = cclk_vlev_datasheet,
|
||||
.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
|
||||
.vr_settling_time = 25 /* us */,
|
||||
};
|
||||
|
||||
static struct platform_device bfin_dpmc = {
|
||||
.name = "bfin dpmc",
|
||||
.dev = {
|
||||
.platform_data = &bfin_dmpc_vreg_data,
|
||||
},
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
|
||||
#include <linux/videodev2.h>
|
||||
#include <media/blackfin/bfin_capture.h>
|
||||
#include <media/blackfin/ppi.h>
|
||||
|
||||
static const unsigned short ppi_req[] = {
|
||||
P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
|
||||
P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
|
||||
P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
|
||||
0,
|
||||
};
|
||||
|
||||
static const struct ppi_info ppi_info = {
|
||||
.type = PPI_TYPE_PPI,
|
||||
.dma_ch = CH_PPI0,
|
||||
.irq_err = IRQ_PPI1_ERROR,
|
||||
.base = (void __iomem *)PPI0_CONTROL,
|
||||
.pin_req = ppi_req,
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_VIDEO_ADV7183)
|
||||
#include <media/adv7183.h>
|
||||
static struct v4l2_input adv7183_inputs[] = {
|
||||
{
|
||||
.index = 0,
|
||||
.name = "Composite",
|
||||
.type = V4L2_INPUT_TYPE_CAMERA,
|
||||
.std = V4L2_STD_ALL,
|
||||
.capabilities = V4L2_IN_CAP_STD,
|
||||
},
|
||||
{
|
||||
.index = 1,
|
||||
.name = "S-Video",
|
||||
.type = V4L2_INPUT_TYPE_CAMERA,
|
||||
.std = V4L2_STD_ALL,
|
||||
.capabilities = V4L2_IN_CAP_STD,
|
||||
},
|
||||
{
|
||||
.index = 2,
|
||||
.name = "Component",
|
||||
.type = V4L2_INPUT_TYPE_CAMERA,
|
||||
.std = V4L2_STD_ALL,
|
||||
.capabilities = V4L2_IN_CAP_STD,
|
||||
},
|
||||
};
|
||||
|
||||
static struct bcap_route adv7183_routes[] = {
|
||||
{
|
||||
.input = ADV7183_COMPOSITE4,
|
||||
.output = ADV7183_8BIT_OUT,
|
||||
},
|
||||
{
|
||||
.input = ADV7183_SVIDEO0,
|
||||
.output = ADV7183_8BIT_OUT,
|
||||
},
|
||||
{
|
||||
.input = ADV7183_COMPONENT0,
|
||||
.output = ADV7183_8BIT_OUT,
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
static const unsigned adv7183_gpio[] = {
|
||||
GPIO_PF13, /* reset pin */
|
||||
GPIO_PF2, /* output enable pin */
|
||||
};
|
||||
|
||||
static struct bfin_capture_config bfin_capture_data = {
|
||||
.card_name = "BF561",
|
||||
.inputs = adv7183_inputs,
|
||||
.num_inputs = ARRAY_SIZE(adv7183_inputs),
|
||||
.routes = adv7183_routes,
|
||||
.i2c_adapter_id = 0,
|
||||
.board_info = {
|
||||
.type = "adv7183",
|
||||
.addr = 0x20,
|
||||
.platform_data = (void *)adv7183_gpio,
|
||||
},
|
||||
.ppi_info = &ppi_info,
|
||||
.ppi_control = (PACK_EN | DLEN_8 | DMA32 | FLD_SEL),
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct platform_device bfin_capture_device = {
|
||||
.name = "bfin_capture",
|
||||
.dev = {
|
||||
.platform_data = &bfin_capture_data,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
|
||||
static struct platform_device bfin_i2s = {
|
||||
.name = "bfin-i2s",
|
||||
.id = CONFIG_SND_BF5XX_SPORT_NUM,
|
||||
/* TODO: add platform data here */
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
|
||||
static struct platform_device bfin_ac97 = {
|
||||
.name = "bfin-ac97",
|
||||
.id = CONFIG_SND_BF5XX_SPORT_NUM,
|
||||
/* TODO: add platform data here */
|
||||
};
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
|
||||
static const char * const ad1836_link[] = {
|
||||
"bfin-i2s.0",
|
||||
"spi0.4",
|
||||
};
|
||||
static struct platform_device bfin_ad1836_machine = {
|
||||
.name = "bfin-snd-ad1836",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = (void *)ad1836_link,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct platform_device *ezkit_devices[] __initdata = {
|
||||
|
||||
&bfin_dpmc,
|
||||
|
||||
#if IS_ENABLED(CONFIG_SMC91X)
|
||||
&smc91x_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_USB_NET2272)
|
||||
&net2272_bfin_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
|
||||
&bfin_isp1760_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
|
||||
&bfin_spi0_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SERIAL_BFIN)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
&bfin_uart0_device,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_BFIN_SIR)
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
&bfin_sir0_device,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
|
||||
&bfin_device_gpiokeys,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_I2C_GPIO)
|
||||
&i2c_gpio_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
|
||||
&isp1362_hcd_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
|
||||
&ezkit_flash_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
|
||||
&bfin_capture_device,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
|
||||
&bfin_i2s,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
|
||||
&bfin_ac97,
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
|
||||
&bfin_ad1836_machine,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int __init net2272_init(void)
|
||||
{
|
||||
#if IS_ENABLED(CONFIG_USB_NET2272)
|
||||
int ret;
|
||||
|
||||
ret = gpio_request(GPIO_PF11, "net2272");
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Reset the USB chip */
|
||||
gpio_direction_output(GPIO_PF11, 0);
|
||||
mdelay(2);
|
||||
gpio_set_value(GPIO_PF11, 1);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init ezkit_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
printk(KERN_INFO "%s(): registering device resources\n", __func__);
|
||||
|
||||
ret = platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
#if IS_ENABLED(CONFIG_SMC91X)
|
||||
bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 12));
|
||||
SSYNC();
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
|
||||
bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 15));
|
||||
bfin_write_FIO0_FLAG_S(1 << 15);
|
||||
SSYNC();
|
||||
/*
|
||||
* This initialization lasts for approximately 4500 MCLKs.
|
||||
* MCLK = 12.288MHz
|
||||
*/
|
||||
udelay(400);
|
||||
#endif
|
||||
|
||||
if (net2272_init())
|
||||
pr_warning("unable to configure net2272; it probably won't work\n");
|
||||
|
||||
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(ezkit_init);
|
||||
|
||||
static struct platform_device *ezkit_early_devices[] __initdata = {
|
||||
#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
&bfin_uart0_device,
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
void __init native_machine_early_platform_add_devices(void)
|
||||
{
|
||||
printk(KERN_INFO "register early platform devices\n");
|
||||
early_platform_add_devices(ezkit_early_devices,
|
||||
ARRAY_SIZE(ezkit_early_devices));
|
||||
}
|
||||
162
arch/blackfin/mach-bf561/boards/tepla.c
Normal file
162
arch/blackfin/mach-bf561/boards/tepla.c
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
/*
|
||||
* Copyright 2004-2007 Analog Devices Inc.
|
||||
* 2005 National ICT Australia (NICTA)
|
||||
* Aidan Williams <aidan@nicta.com.au>
|
||||
*
|
||||
* Thanks to Jamey Hicks.
|
||||
*
|
||||
* Only SMSC91C1111 was registered, may do more later.
|
||||
*
|
||||
* Licensed under the GPL-2
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
const char bfin_board_name[] = "Tepla-BF561";
|
||||
|
||||
/*
|
||||
* Driver needs to know address, irq and flag pin.
|
||||
*/
|
||||
static struct resource smc91x_resources[] = {
|
||||
{
|
||||
.start = 0x2C000300,
|
||||
.end = 0x2C000320,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_PROG_INTB,
|
||||
.end = IRQ_PROG_INTB,
|
||||
.flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
|
||||
}, {
|
||||
.start = IRQ_PF7,
|
||||
.end = IRQ_PF7,
|
||||
.flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_SERIAL_BFIN)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
static struct resource bfin_uart0_resources[] = {
|
||||
{
|
||||
.start = BFIN_UART_THR,
|
||||
.end = BFIN_UART_GCTL+2,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART_TX,
|
||||
.end = IRQ_UART_TX,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART_RX,
|
||||
.end = IRQ_UART_RX,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART_ERROR,
|
||||
.end = IRQ_UART_ERROR,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = CH_UART_TX,
|
||||
.end = CH_UART_TX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
{
|
||||
.start = CH_UART_RX,
|
||||
.end = CH_UART_RX,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static unsigned short bfin_uart0_peripherals[] = {
|
||||
P_UART0_TX, P_UART0_RX, 0
|
||||
};
|
||||
|
||||
static struct platform_device bfin_uart0_device = {
|
||||
.name = "bfin-uart",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(bfin_uart0_resources),
|
||||
.resource = bfin_uart0_resources,
|
||||
.dev = {
|
||||
.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_BFIN_SIR)
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
static struct resource bfin_sir0_resources[] = {
|
||||
{
|
||||
.start = 0xFFC00400,
|
||||
.end = 0xFFC004FF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_UART0_RX,
|
||||
.end = IRQ_UART0_RX+1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = CH_UART0_RX,
|
||||
.end = CH_UART0_RX+1,
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device bfin_sir0_device = {
|
||||
.name = "bfin_sir",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(bfin_sir0_resources),
|
||||
.resource = bfin_sir0_resources,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
static struct platform_device *tepla_devices[] __initdata = {
|
||||
&smc91x_device,
|
||||
|
||||
#if IS_ENABLED(CONFIG_SERIAL_BFIN)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
&bfin_uart0_device,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_BFIN_SIR)
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
&bfin_sir0_device,
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
static int __init tepla_init(void)
|
||||
{
|
||||
printk(KERN_INFO "%s(): registering device resources\n", __func__);
|
||||
return platform_add_devices(tepla_devices, ARRAY_SIZE(tepla_devices));
|
||||
}
|
||||
|
||||
arch_initcall(tepla_init);
|
||||
|
||||
static struct platform_device *tepla_early_devices[] __initdata = {
|
||||
#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
&bfin_uart0_device,
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
void __init native_machine_early_platform_add_devices(void)
|
||||
{
|
||||
printk(KERN_INFO "register early platform devices\n");
|
||||
early_platform_add_devices(tepla_early_devices,
|
||||
ARRAY_SIZE(tepla_early_devices));
|
||||
}
|
||||
77
arch/blackfin/mach-bf561/coreb.c
Normal file
77
arch/blackfin/mach-bf561/coreb.c
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
/* Load firmware into Core B on a BF561
|
||||
*
|
||||
* Copyright 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
/* The Core B reset func requires code in the application that is loaded into
|
||||
* Core B. In order to reset, the application needs to install an interrupt
|
||||
* handler for Supplemental Interrupt 0, that sets RETI to 0xff600000 and
|
||||
* writes bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. This causes Core
|
||||
* B to stall when Supplemental Interrupt 0 is set, and will reset PC to
|
||||
* 0xff600000 when COREB_SRAM_INIT is cleared.
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/miscdevice.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#define CMD_COREB_START _IO('b', 0)
|
||||
#define CMD_COREB_STOP _IO('b', 1)
|
||||
#define CMD_COREB_RESET _IO('b', 2)
|
||||
|
||||
static long
|
||||
coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
switch (cmd) {
|
||||
case CMD_COREB_START:
|
||||
bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
|
||||
break;
|
||||
case CMD_COREB_STOP:
|
||||
bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020);
|
||||
bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
|
||||
break;
|
||||
case CMD_COREB_RESET:
|
||||
bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
CSYNC();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct file_operations coreb_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.unlocked_ioctl = coreb_ioctl,
|
||||
.llseek = noop_llseek,
|
||||
};
|
||||
|
||||
static struct miscdevice coreb_dev = {
|
||||
.minor = MISC_DYNAMIC_MINOR,
|
||||
.name = "coreb",
|
||||
.fops = &coreb_fops,
|
||||
};
|
||||
|
||||
static int __init bf561_coreb_init(void)
|
||||
{
|
||||
return misc_register(&coreb_dev);
|
||||
}
|
||||
module_init(bf561_coreb_init);
|
||||
|
||||
static void __exit bf561_coreb_exit(void)
|
||||
{
|
||||
misc_deregister(&coreb_dev);
|
||||
}
|
||||
module_exit(bf561_coreb_exit);
|
||||
|
||||
MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>");
|
||||
MODULE_DESCRIPTION("BF561 Core B Support");
|
||||
MODULE_LICENSE("GPL");
|
||||
114
arch/blackfin/mach-bf561/dma.c
Normal file
114
arch/blackfin/mach-bf561/dma.c
Normal file
|
|
@ -0,0 +1,114 @@
|
|||
/*
|
||||
* the simple DMA Implementation for Blackfin
|
||||
*
|
||||
* Copyright 2007-2008 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/dma.h>
|
||||
|
||||
struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
|
||||
(struct dma_register *) DMA1_0_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA1_1_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA1_2_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA1_3_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA1_4_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA1_5_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA1_6_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA1_7_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA1_8_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA1_9_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA1_10_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA1_11_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA2_0_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA2_1_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA2_2_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA2_3_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA2_4_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA2_5_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA2_6_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA2_7_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA2_8_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA2_9_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA2_10_NEXT_DESC_PTR,
|
||||
(struct dma_register *) DMA2_11_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
|
||||
(struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
|
||||
(struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
|
||||
(struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
|
||||
(struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
|
||||
(struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
|
||||
};
|
||||
EXPORT_SYMBOL(dma_io_base_addr);
|
||||
|
||||
int channel2irq(unsigned int channel)
|
||||
{
|
||||
int ret_irq = -1;
|
||||
|
||||
switch (channel) {
|
||||
case CH_PPI0:
|
||||
ret_irq = IRQ_PPI0;
|
||||
break;
|
||||
case CH_PPI1:
|
||||
ret_irq = IRQ_PPI1;
|
||||
break;
|
||||
case CH_SPORT0_RX:
|
||||
ret_irq = IRQ_SPORT0_RX;
|
||||
break;
|
||||
case CH_SPORT0_TX:
|
||||
ret_irq = IRQ_SPORT0_TX;
|
||||
break;
|
||||
case CH_SPORT1_RX:
|
||||
ret_irq = IRQ_SPORT1_RX;
|
||||
break;
|
||||
case CH_SPORT1_TX:
|
||||
ret_irq = IRQ_SPORT1_TX;
|
||||
break;
|
||||
case CH_SPI:
|
||||
ret_irq = IRQ_SPI;
|
||||
break;
|
||||
case CH_UART_RX:
|
||||
ret_irq = IRQ_UART_RX;
|
||||
break;
|
||||
case CH_UART_TX:
|
||||
ret_irq = IRQ_UART_TX;
|
||||
break;
|
||||
|
||||
case CH_MEM_STREAM0_SRC:
|
||||
case CH_MEM_STREAM0_DEST:
|
||||
ret_irq = IRQ_MEM_DMA0;
|
||||
break;
|
||||
case CH_MEM_STREAM1_SRC:
|
||||
case CH_MEM_STREAM1_DEST:
|
||||
ret_irq = IRQ_MEM_DMA1;
|
||||
break;
|
||||
case CH_MEM_STREAM2_SRC:
|
||||
case CH_MEM_STREAM2_DEST:
|
||||
ret_irq = IRQ_MEM_DMA2;
|
||||
break;
|
||||
case CH_MEM_STREAM3_SRC:
|
||||
case CH_MEM_STREAM3_DEST:
|
||||
ret_irq = IRQ_MEM_DMA3;
|
||||
break;
|
||||
|
||||
case CH_IMEM_STREAM0_SRC:
|
||||
case CH_IMEM_STREAM0_DEST:
|
||||
ret_irq = IRQ_IMEM_DMA0;
|
||||
break;
|
||||
case CH_IMEM_STREAM1_SRC:
|
||||
case CH_IMEM_STREAM1_DEST:
|
||||
ret_irq = IRQ_IMEM_DMA1;
|
||||
break;
|
||||
}
|
||||
return ret_irq;
|
||||
}
|
||||
40
arch/blackfin/mach-bf561/hotplug.c
Normal file
40
arch/blackfin/mach-bf561/hotplug.c
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Copyright 2007-2009 Analog Devices Inc.
|
||||
* Graff Yang <graf.yang@analog.com>
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/smp.h>
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <mach/pll.h>
|
||||
|
||||
int hotplug_coreb;
|
||||
|
||||
void platform_cpu_die(void)
|
||||
{
|
||||
unsigned long iwr;
|
||||
|
||||
hotplug_coreb = 1;
|
||||
|
||||
/*
|
||||
* When CoreB wakes up, the code in _coreb_trampoline_start cannot
|
||||
* turn off the data cache. This causes the CoreB failed to boot.
|
||||
* As a workaround, we invalidate all the data cache before sleep.
|
||||
*/
|
||||
blackfin_invalidate_entire_dcache();
|
||||
|
||||
/* disable core timer */
|
||||
bfin_write_TCNTL(0);
|
||||
|
||||
/* clear ipi interrupt IRQ_SUPPLE_0 of CoreB */
|
||||
bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + 1)));
|
||||
SSYNC();
|
||||
|
||||
/* set CoreB wakeup by ipi0, iwr will be discarded */
|
||||
bfin_iwr_set_sup0(&iwr, &iwr, &iwr);
|
||||
SSYNC();
|
||||
|
||||
coreb_die();
|
||||
}
|
||||
353
arch/blackfin/mach-bf561/include/mach/anomaly.h
Normal file
353
arch/blackfin/mach-bf561/include/mach/anomaly.h
Normal file
|
|
@ -0,0 +1,353 @@
|
|||
/*
|
||||
* DO NOT EDIT THIS FILE
|
||||
* This file is under version control at
|
||||
* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
|
||||
* and can be replaced with that version at any time
|
||||
* DO NOT EDIT THIS FILE
|
||||
*
|
||||
* Copyright 2004-2011 Analog Devices Inc.
|
||||
* Licensed under the Clear BSD license.
|
||||
*/
|
||||
|
||||
/* This file should be up to date with:
|
||||
* - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
#define _MACH_ANOMALY_H_
|
||||
|
||||
/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
|
||||
#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
|
||||
# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
|
||||
#endif
|
||||
|
||||
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
|
||||
#define ANOMALY_05000074 (1)
|
||||
/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
|
||||
#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
|
||||
/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
|
||||
#define ANOMALY_05000120 (1)
|
||||
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
|
||||
#define ANOMALY_05000122 (1)
|
||||
/* SIGNBITS Instruction Not Functional under Certain Conditions */
|
||||
#define ANOMALY_05000127 (1)
|
||||
/* IMDMA S1/D1 Channel May Stall */
|
||||
#define ANOMALY_05000149 (1)
|
||||
/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
|
||||
#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
|
||||
/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
|
||||
#define ANOMALY_05000166 (1)
|
||||
/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
|
||||
#define ANOMALY_05000167 (1)
|
||||
/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
|
||||
#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
|
||||
/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
|
||||
#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
|
||||
/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
|
||||
#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
|
||||
/* Cache Fill Buffer Data lost */
|
||||
#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
|
||||
/* Overlapping Sequencer and Memory Stalls */
|
||||
#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
|
||||
/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
|
||||
#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
|
||||
/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
|
||||
#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
|
||||
/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
|
||||
#define ANOMALY_05000180 (1)
|
||||
/* Disabling the PPI Resets the PPI Configuration Registers */
|
||||
#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
|
||||
/* Internal Memory DMA Does Not Operate at Full Speed */
|
||||
#define ANOMALY_05000182 (1)
|
||||
/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
|
||||
#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
|
||||
/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
|
||||
#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
|
||||
/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */
|
||||
#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
|
||||
/* IMDMA Corrupted Data after a Halt */
|
||||
#define ANOMALY_05000187 (1)
|
||||
/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
|
||||
#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
|
||||
/* False Protection Exceptions when Speculative Fetch Is Cancelled */
|
||||
#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
|
||||
/* PPI Not Functional at Core Voltage < 1Volt */
|
||||
#define ANOMALY_05000190 (1)
|
||||
/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
|
||||
#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
|
||||
/* Restarting SPORT in Specific Modes May Cause Data Corruption */
|
||||
#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
|
||||
/* Failing MMR Accesses when Preceding Memory Read Stalls */
|
||||
#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
|
||||
/* Current DMA Address Shows Wrong Value During Carry Fix */
|
||||
#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
|
||||
/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
|
||||
#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
|
||||
/* Possible Infinite Stall with Specific Dual-DAG Situation */
|
||||
#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
|
||||
/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
|
||||
#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
|
||||
/* Specific Sequence that Can Cause DMA Error or DMA Stopping */
|
||||
#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
|
||||
/* Recovery from "Brown-Out" Condition */
|
||||
#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
|
||||
/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
|
||||
#define ANOMALY_05000208 (1)
|
||||
/* Speed Path in Computational Unit Affects Certain Instructions */
|
||||
#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
|
||||
/* UART TX Interrupt Masked Erroneously */
|
||||
#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
|
||||
/* NMI Event at Boot Time Results in Unpredictable State */
|
||||
#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
|
||||
/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
|
||||
#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
|
||||
/* Incorrect Pulse-Width of UART Start Bit */
|
||||
#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
|
||||
/* Scratchpad Memory Bank Reads May Return Incorrect Data */
|
||||
#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
|
||||
/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
|
||||
#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
|
||||
/* UART STB Bit Incorrectly Affects Receiver Setting */
|
||||
#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
|
||||
/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */
|
||||
#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
|
||||
/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
|
||||
#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
|
||||
/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
|
||||
#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
|
||||
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
|
||||
#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
|
||||
/* TESTSET Operation Forces Stall on the Other Core */
|
||||
#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
|
||||
/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
|
||||
#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
|
||||
/* Exception Not Generated for MMR Accesses in Reserved Region */
|
||||
#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
|
||||
/* Maximum External Clock Speed for Timers */
|
||||
#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
|
||||
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
|
||||
#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
|
||||
/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
|
||||
/* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception
|
||||
* without handling anomaly 05000257 properly on bf561 v0.5. This work around may change
|
||||
* after the behavior and the root cause are confirmed with hardware team.
|
||||
*/
|
||||
#define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP))
|
||||
/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
|
||||
#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
|
||||
/* ICPLB_STATUS MMR Register May Be Corrupted */
|
||||
#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
|
||||
/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
|
||||
#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
|
||||
/* Stores To Data Cache May Be Lost */
|
||||
#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
|
||||
/* Hardware Loop Corrupted When Taking an ICPLB Exception */
|
||||
#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
|
||||
/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
|
||||
#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
|
||||
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
|
||||
#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
|
||||
/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */
|
||||
#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
|
||||
/* IMDMA May Corrupt Data under Certain Conditions */
|
||||
#define ANOMALY_05000267 (1)
|
||||
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
|
||||
#define ANOMALY_05000269 (1)
|
||||
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
|
||||
#define ANOMALY_05000270 (1)
|
||||
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
|
||||
#define ANOMALY_05000272 (1)
|
||||
/* Data Cache Write Back to External Synchronous Memory May Be Lost */
|
||||
#define ANOMALY_05000274 (1)
|
||||
/* PPI Timing and Sampling Information Updates */
|
||||
#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
|
||||
/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
|
||||
#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
|
||||
/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
|
||||
#define ANOMALY_05000277 (__SILICON_REVISION__ < 5)
|
||||
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
|
||||
#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
|
||||
/* False Hardware Error when ISR Context Is Not Restored */
|
||||
/* Temporarily walk around for bug 5423 till this issue is confirmed by
|
||||
* official anomaly document. It looks 05000281 still exists on bf561
|
||||
* v0.5.
|
||||
*/
|
||||
#define ANOMALY_05000281 (__SILICON_REVISION__ <= 5)
|
||||
/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
|
||||
#define ANOMALY_05000283 (1)
|
||||
/* Reads Will Receive Incorrect Data under Certain Conditions */
|
||||
#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
|
||||
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
|
||||
#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
|
||||
/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
|
||||
#define ANOMALY_05000301 (1)
|
||||
/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
|
||||
#define ANOMALY_05000302 (1)
|
||||
/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
|
||||
#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
|
||||
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
|
||||
#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
|
||||
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
|
||||
#define ANOMALY_05000310 (1)
|
||||
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
#define ANOMALY_05000312 (1)
|
||||
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
|
||||
#define ANOMALY_05000313 (1)
|
||||
/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
|
||||
#define ANOMALY_05000315 (1)
|
||||
/* PF2 Output Remains Asserted after SPI Master Boot */
|
||||
#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
|
||||
/* Erroneous GPIO Flag Pin Operations under Specific Sequences */
|
||||
#define ANOMALY_05000323 (1)
|
||||
/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */
|
||||
#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
|
||||
/* 24-Bit SPI Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
|
||||
/* Slave SPI Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
|
||||
/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */
|
||||
#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
|
||||
/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */
|
||||
#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
|
||||
/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
|
||||
#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
|
||||
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
|
||||
#define ANOMALY_05000357 (1)
|
||||
/* Conflicting Column Address Widths Causes SDRAM Errors */
|
||||
#define ANOMALY_05000362 (1)
|
||||
/* UART Break Signal Issues */
|
||||
#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
|
||||
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
|
||||
#define ANOMALY_05000366 (1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (1)
|
||||
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
|
||||
#define ANOMALY_05000403 (1)
|
||||
/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
|
||||
#define ANOMALY_05000412 (1)
|
||||
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
|
||||
#define ANOMALY_05000416 (1)
|
||||
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
|
||||
#define ANOMALY_05000425 (1)
|
||||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
|
||||
#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
/* SCKELOW Feature Is Not Functional */
|
||||
#define ANOMALY_05000458 (1)
|
||||
/* False Hardware Error when RETI Points to Invalid Memory */
|
||||
#define ANOMALY_05000461 (1)
|
||||
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
|
||||
#define ANOMALY_05000462 (1)
|
||||
/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
|
||||
#define ANOMALY_05000471 (1)
|
||||
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
|
||||
#define ANOMALY_05000473 (1)
|
||||
/* Possible Lockup Condition when Modifying PLL from External Memory */
|
||||
#define ANOMALY_05000475 (1)
|
||||
/* TESTSET Instruction Cannot Be Interrupted */
|
||||
#define ANOMALY_05000477 (1)
|
||||
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
|
||||
#define ANOMALY_05000481 (1)
|
||||
/* PLL May Latch Incorrect Values Coming Out of Reset */
|
||||
#define ANOMALY_05000489 (1)
|
||||
/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
|
||||
#define ANOMALY_05000491 (1)
|
||||
/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
|
||||
#define ANOMALY_05000494 (1)
|
||||
/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
|
||||
#define ANOMALY_05000501 (1)
|
||||
|
||||
/*
|
||||
* These anomalies have been "phased" out of analog.com anomaly sheets and are
|
||||
* here to show running on older silicon just isn't feasible.
|
||||
*/
|
||||
|
||||
/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
|
||||
#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
|
||||
/* Erroneous Exception when Enabling Cache */
|
||||
#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
|
||||
/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
|
||||
#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
|
||||
/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
|
||||
#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
|
||||
/* Stall in multi-unit DMA operations */
|
||||
#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
|
||||
/* Allowing the SPORT RX FIFO to fill will cause an overflow */
|
||||
#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
|
||||
/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
|
||||
#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
|
||||
/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
|
||||
#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
|
||||
/* DMA and TESTSET conflict when both are accessing external memory */
|
||||
#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
|
||||
/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
|
||||
#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
|
||||
/* MDMA may lose the first few words of a descriptor chain */
|
||||
#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
|
||||
/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
|
||||
#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
|
||||
/* DMA engine may lose data due to incorrect handshaking */
|
||||
#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
|
||||
/* DMA stalls when all three controllers read data from the same source */
|
||||
#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
|
||||
/* Execution stall when executing in L2 and doing external accesses */
|
||||
#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
|
||||
/* Frame Delay in SPORT Multichannel Mode */
|
||||
#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
|
||||
/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
|
||||
#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
|
||||
/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
|
||||
#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
|
||||
/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
|
||||
#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
|
||||
/* A read from external memory may return a wrong value with data cache enabled */
|
||||
#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
|
||||
/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
|
||||
#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
|
||||
/* DMEM_CONTROL<12> is not set on Reset */
|
||||
#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
|
||||
/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
|
||||
#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
|
||||
/* DSPID register values incorrect */
|
||||
#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
|
||||
/* DMA vs Core accesses to external memory */
|
||||
#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
|
||||
/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
|
||||
#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
|
||||
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
|
||||
#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000119 (0)
|
||||
#define ANOMALY_05000158 (0)
|
||||
#define ANOMALY_05000183 (0)
|
||||
#define ANOMALY_05000233 (0)
|
||||
#define ANOMALY_05000234 (0)
|
||||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
#define ANOMALY_05000364 (0)
|
||||
#define ANOMALY_05000380 (0)
|
||||
#define ANOMALY_05000383 (0)
|
||||
#define ANOMALY_05000386 (1)
|
||||
#define ANOMALY_05000389 (0)
|
||||
#define ANOMALY_05000400 (0)
|
||||
#define ANOMALY_05000430 (0)
|
||||
#define ANOMALY_05000432 (0)
|
||||
#define ANOMALY_05000435 (0)
|
||||
#define ANOMALY_05000440 (0)
|
||||
#define ANOMALY_05000447 (0)
|
||||
#define ANOMALY_05000448 (0)
|
||||
#define ANOMALY_05000456 (0)
|
||||
#define ANOMALY_05000450 (0)
|
||||
#define ANOMALY_05000465 (0)
|
||||
#define ANOMALY_05000467 (0)
|
||||
#define ANOMALY_05000474 (0)
|
||||
#define ANOMALY_05000480 (0)
|
||||
#define ANOMALY_05000485 (0)
|
||||
#define ANOMALY_16000030 (0)
|
||||
|
||||
#endif
|
||||
200
arch/blackfin/mach-bf561/include/mach/bf561.h
Normal file
200
arch/blackfin/mach-bf561/include/mach/bf561.h
Normal file
|
|
@ -0,0 +1,200 @@
|
|||
/*
|
||||
* SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
|
||||
*
|
||||
* Copyright 2005-2008 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_BF561_H__
|
||||
#define __MACH_BF561_H__
|
||||
|
||||
#define OFFSET_(x) ((x) & 0x0000FFFF)
|
||||
|
||||
/*some misc defines*/
|
||||
#define IMASK_IVG15 0x8000
|
||||
#define IMASK_IVG14 0x4000
|
||||
#define IMASK_IVG13 0x2000
|
||||
#define IMASK_IVG12 0x1000
|
||||
|
||||
#define IMASK_IVG11 0x0800
|
||||
#define IMASK_IVG10 0x0400
|
||||
#define IMASK_IVG9 0x0200
|
||||
#define IMASK_IVG8 0x0100
|
||||
|
||||
#define IMASK_IVG7 0x0080
|
||||
#define IMASK_IVGTMR 0x0040
|
||||
#define IMASK_IVGHW 0x0020
|
||||
|
||||
/***************************
|
||||
* Blackfin Cache setup
|
||||
*/
|
||||
|
||||
|
||||
#define BFIN_ISUBBANKS 4
|
||||
#define BFIN_IWAYS 4
|
||||
#define BFIN_ILINES 32
|
||||
|
||||
#define BFIN_DSUBBANKS 4
|
||||
#define BFIN_DWAYS 2
|
||||
#define BFIN_DLINES 64
|
||||
|
||||
#define WAY0_L 0x1
|
||||
#define WAY1_L 0x2
|
||||
#define WAY01_L 0x3
|
||||
#define WAY2_L 0x4
|
||||
#define WAY02_L 0x5
|
||||
#define WAY12_L 0x6
|
||||
#define WAY012_L 0x7
|
||||
|
||||
#define WAY3_L 0x8
|
||||
#define WAY03_L 0x9
|
||||
#define WAY13_L 0xA
|
||||
#define WAY013_L 0xB
|
||||
|
||||
#define WAY32_L 0xC
|
||||
#define WAY320_L 0xD
|
||||
#define WAY321_L 0xE
|
||||
#define WAYALL_L 0xF
|
||||
|
||||
#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
|
||||
|
||||
/* IAR0 BIT FIELDS */
|
||||
#define PLL_WAKEUP_BIT 0xFFFFFFFF
|
||||
#define DMA1_ERROR_BIT 0xFFFFFF0F
|
||||
#define DMA2_ERROR_BIT 0xFFFFF0FF
|
||||
#define IMDMA_ERROR_BIT 0xFFFF0FFF
|
||||
#define PPI1_ERROR_BIT 0xFFF0FFFF
|
||||
#define PPI2_ERROR_BIT 0xFF0FFFFF
|
||||
#define SPORT0_ERROR_BIT 0xF0FFFFFF
|
||||
#define SPORT1_ERROR_BIT 0x0FFFFFFF
|
||||
/* IAR1 BIT FIELDS */
|
||||
#define SPI_ERROR_BIT 0xFFFFFFFF
|
||||
#define UART_ERROR_BIT 0xFFFFFF0F
|
||||
#define RESERVED_ERROR_BIT 0xFFFFF0FF
|
||||
#define DMA1_0_BIT 0xFFFF0FFF
|
||||
#define DMA1_1_BIT 0xFFF0FFFF
|
||||
#define DMA1_2_BIT 0xFF0FFFFF
|
||||
#define DMA1_3_BIT 0xF0FFFFFF
|
||||
#define DMA1_4_BIT 0x0FFFFFFF
|
||||
/* IAR2 BIT FIELDS */
|
||||
#define DMA1_5_BIT 0xFFFFFFFF
|
||||
#define DMA1_6_BIT 0xFFFFFF0F
|
||||
#define DMA1_7_BIT 0xFFFFF0FF
|
||||
#define DMA1_8_BIT 0xFFFF0FFF
|
||||
#define DMA1_9_BIT 0xFFF0FFFF
|
||||
#define DMA1_10_BIT 0xFF0FFFFF
|
||||
#define DMA1_11_BIT 0xF0FFFFFF
|
||||
#define DMA2_0_BIT 0x0FFFFFFF
|
||||
/* IAR3 BIT FIELDS */
|
||||
#define DMA2_1_BIT 0xFFFFFFFF
|
||||
#define DMA2_2_BIT 0xFFFFFF0F
|
||||
#define DMA2_3_BIT 0xFFFFF0FF
|
||||
#define DMA2_4_BIT 0xFFFF0FFF
|
||||
#define DMA2_5_BIT 0xFFF0FFFF
|
||||
#define DMA2_6_BIT 0xFF0FFFFF
|
||||
#define DMA2_7_BIT 0xF0FFFFFF
|
||||
#define DMA2_8_BIT 0x0FFFFFFF
|
||||
/* IAR4 BIT FIELDS */
|
||||
#define DMA2_9_BIT 0xFFFFFFFF
|
||||
#define DMA2_10_BIT 0xFFFFFF0F
|
||||
#define DMA2_11_BIT 0xFFFFF0FF
|
||||
#define TIMER0_BIT 0xFFFF0FFF
|
||||
#define TIMER1_BIT 0xFFF0FFFF
|
||||
#define TIMER2_BIT 0xFF0FFFFF
|
||||
#define TIMER3_BIT 0xF0FFFFFF
|
||||
#define TIMER4_BIT 0x0FFFFFFF
|
||||
/* IAR5 BIT FIELDS */
|
||||
#define TIMER5_BIT 0xFFFFFFFF
|
||||
#define TIMER6_BIT 0xFFFFFF0F
|
||||
#define TIMER7_BIT 0xFFFFF0FF
|
||||
#define TIMER8_BIT 0xFFFF0FFF
|
||||
#define TIMER9_BIT 0xFFF0FFFF
|
||||
#define TIMER10_BIT 0xFF0FFFFF
|
||||
#define TIMER11_BIT 0xF0FFFFFF
|
||||
#define PROG0_INTA_BIT 0x0FFFFFFF
|
||||
/* IAR6 BIT FIELDS */
|
||||
#define PROG0_INTB_BIT 0xFFFFFFFF
|
||||
#define PROG1_INTA_BIT 0xFFFFFF0F
|
||||
#define PROG1_INTB_BIT 0xFFFFF0FF
|
||||
#define PROG2_INTA_BIT 0xFFFF0FFF
|
||||
#define PROG2_INTB_BIT 0xFFF0FFFF
|
||||
#define DMA1_WRRD0_BIT 0xFF0FFFFF
|
||||
#define DMA1_WRRD1_BIT 0xF0FFFFFF
|
||||
#define DMA2_WRRD0_BIT 0x0FFFFFFF
|
||||
/* IAR7 BIT FIELDS */
|
||||
#define DMA2_WRRD1_BIT 0xFFFFFFFF
|
||||
#define IMDMA_WRRD0_BIT 0xFFFFFF0F
|
||||
#define IMDMA_WRRD1_BIT 0xFFFFF0FF
|
||||
#define WATCH_BIT 0xFFFF0FFF
|
||||
#define RESERVED_1_BIT 0xFFF0FFFF
|
||||
#define RESERVED_2_BIT 0xFF0FFFFF
|
||||
#define SUPPLE_0_BIT 0xF0FFFFFF
|
||||
#define SUPPLE_1_BIT 0x0FFFFFFF
|
||||
|
||||
/* Miscellaneous Values */
|
||||
|
||||
/****************************** EBIU Settings ********************************/
|
||||
#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
|
||||
#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
|
||||
|
||||
#if defined(CONFIG_C_AMBEN_ALL)
|
||||
#define V_AMBEN AMBEN_ALL
|
||||
#elif defined(CONFIG_C_AMBEN)
|
||||
#define V_AMBEN 0x0
|
||||
#elif defined(CONFIG_C_AMBEN_B0)
|
||||
#define V_AMBEN AMBEN_B0
|
||||
#elif defined(CONFIG_C_AMBEN_B0_B1)
|
||||
#define V_AMBEN AMBEN_B0_B1
|
||||
#elif defined(CONFIG_C_AMBEN_B0_B1_B2)
|
||||
#define V_AMBEN AMBEN_B0_B1_B2
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_C_AMCKEN
|
||||
#define V_AMCKEN AMCKEN
|
||||
#else
|
||||
#define V_AMCKEN 0x0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_C_B0PEN
|
||||
#define V_B0PEN 0x10
|
||||
#else
|
||||
#define V_B0PEN 0x00
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_C_B1PEN
|
||||
#define V_B1PEN 0x20
|
||||
#else
|
||||
#define V_B1PEN 0x00
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_C_B2PEN
|
||||
#define V_B2PEN 0x40
|
||||
#else
|
||||
#define V_B2PEN 0x00
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_C_B3PEN
|
||||
#define V_B3PEN 0x80
|
||||
#else
|
||||
#define V_B3PEN 0x00
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_C_CDPRIO
|
||||
#define V_CDPRIO 0x100
|
||||
#else
|
||||
#define V_CDPRIO 0x0
|
||||
#endif
|
||||
|
||||
#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
|
||||
|
||||
#ifdef CONFIG_BF561
|
||||
#define CPU "BF561"
|
||||
#define CPUID 0x27bb
|
||||
#endif
|
||||
|
||||
#ifndef CPU
|
||||
#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
|
||||
#endif
|
||||
|
||||
#endif /* __MACH_BF561_H__ */
|
||||
14
arch/blackfin/mach-bf561/include/mach/bfin_serial.h
Normal file
14
arch/blackfin/mach-bf561/include/mach/bfin_serial.h
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* mach/bfin_serial.h - Blackfin UART/Serial definitions
|
||||
*
|
||||
* Copyright 2006-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_MACH_SERIAL_H__
|
||||
#define __BFIN_MACH_SERIAL_H__
|
||||
|
||||
#define BFIN_UART_NR_PORTS 1
|
||||
|
||||
#endif
|
||||
41
arch/blackfin/mach-bf561/include/mach/blackfin.h
Normal file
41
arch/blackfin/mach-bf561/include/mach/blackfin.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright 2005-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_BLACKFIN_H_
|
||||
#define _MACH_BLACKFIN_H_
|
||||
|
||||
#define BF561_FAMILY
|
||||
|
||||
#include "bf561.h"
|
||||
#include "anomaly.h"
|
||||
|
||||
#include <asm/def_LPBlackfin.h>
|
||||
#include "defBF561.h"
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <asm/cdef_LPBlackfin.h>
|
||||
# include "cdefBF561.h"
|
||||
#endif
|
||||
|
||||
#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
|
||||
#define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val)
|
||||
#define bfin_read_FIO_DIR() bfin_read_FIO0_DIR()
|
||||
#define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val)
|
||||
#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
|
||||
#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
|
||||
|
||||
/* Weird muxer funcs which pick SIC regs from IMASK base */
|
||||
#define __SIC_MUX(base, x) ((base) + ((x) << 2))
|
||||
#define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x))
|
||||
#define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val)
|
||||
#define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x))
|
||||
#define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val)
|
||||
#define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x))
|
||||
#define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val)
|
||||
#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x))
|
||||
#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
|
||||
|
||||
#endif /* _MACH_BLACKFIN_H_ */
|
||||
1460
arch/blackfin/mach-bf561/include/mach/cdefBF561.h
Normal file
1460
arch/blackfin/mach-bf561/include/mach/cdefBF561.h
Normal file
File diff suppressed because it is too large
Load diff
1402
arch/blackfin/mach-bf561/include/mach/defBF561.h
Normal file
1402
arch/blackfin/mach-bf561/include/mach/defBF561.h
Normal file
File diff suppressed because it is too large
Load diff
39
arch/blackfin/mach-bf561/include/mach/dma.h
Normal file
39
arch/blackfin/mach-bf561/include/mach/dma.h
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/* mach/dma.h - arch-specific DMA defines
|
||||
*
|
||||
* Copyright 2004-2008 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_DMA_H_
|
||||
#define _MACH_DMA_H_
|
||||
|
||||
#define MAX_DMA_CHANNELS 36
|
||||
|
||||
/* [#4267] IMDMA channels have no PERIPHERAL_MAP MMR */
|
||||
#define MAX_DMA_SUSPEND_CHANNELS 32
|
||||
|
||||
#define CH_PPI0 0
|
||||
#define CH_PPI (CH_PPI0)
|
||||
#define CH_PPI1 1
|
||||
#define CH_SPORT0_RX 12
|
||||
#define CH_SPORT0_TX 13
|
||||
#define CH_SPORT1_RX 14
|
||||
#define CH_SPORT1_TX 15
|
||||
#define CH_SPI 16
|
||||
#define CH_UART_RX 17
|
||||
#define CH_UART_TX 18
|
||||
#define CH_MEM_STREAM0_DEST 24 /* TX */
|
||||
#define CH_MEM_STREAM0_SRC 25 /* RX */
|
||||
#define CH_MEM_STREAM1_DEST 26 /* TX */
|
||||
#define CH_MEM_STREAM1_SRC 27 /* RX */
|
||||
#define CH_MEM_STREAM2_DEST 28
|
||||
#define CH_MEM_STREAM2_SRC 29
|
||||
#define CH_MEM_STREAM3_DEST 30
|
||||
#define CH_MEM_STREAM3_SRC 31
|
||||
#define CH_IMEM_STREAM0_DEST 32
|
||||
#define CH_IMEM_STREAM0_SRC 33
|
||||
#define CH_IMEM_STREAM1_DEST 34
|
||||
#define CH_IMEM_STREAM1_SRC 35
|
||||
|
||||
#endif
|
||||
67
arch/blackfin/mach-bf561/include/mach/gpio.h
Normal file
67
arch/blackfin/mach-bf561/include/mach/gpio.h
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* Copyright (C) 2008 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACH_GPIO_H_
|
||||
#define _MACH_GPIO_H_
|
||||
|
||||
#define MAX_BLACKFIN_GPIOS 48
|
||||
|
||||
#define GPIO_PF0 0
|
||||
#define GPIO_PF1 1
|
||||
#define GPIO_PF2 2
|
||||
#define GPIO_PF3 3
|
||||
#define GPIO_PF4 4
|
||||
#define GPIO_PF5 5
|
||||
#define GPIO_PF6 6
|
||||
#define GPIO_PF7 7
|
||||
#define GPIO_PF8 8
|
||||
#define GPIO_PF9 9
|
||||
#define GPIO_PF10 10
|
||||
#define GPIO_PF11 11
|
||||
#define GPIO_PF12 12
|
||||
#define GPIO_PF13 13
|
||||
#define GPIO_PF14 14
|
||||
#define GPIO_PF15 15
|
||||
#define GPIO_PF16 16
|
||||
#define GPIO_PF17 17
|
||||
#define GPIO_PF18 18
|
||||
#define GPIO_PF19 19
|
||||
#define GPIO_PF20 20
|
||||
#define GPIO_PF21 21
|
||||
#define GPIO_PF22 22
|
||||
#define GPIO_PF23 23
|
||||
#define GPIO_PF24 24
|
||||
#define GPIO_PF25 25
|
||||
#define GPIO_PF26 26
|
||||
#define GPIO_PF27 27
|
||||
#define GPIO_PF28 28
|
||||
#define GPIO_PF29 29
|
||||
#define GPIO_PF30 30
|
||||
#define GPIO_PF31 31
|
||||
#define GPIO_PF32 32
|
||||
#define GPIO_PF33 33
|
||||
#define GPIO_PF34 34
|
||||
#define GPIO_PF35 35
|
||||
#define GPIO_PF36 36
|
||||
#define GPIO_PF37 37
|
||||
#define GPIO_PF38 38
|
||||
#define GPIO_PF39 39
|
||||
#define GPIO_PF40 40
|
||||
#define GPIO_PF41 41
|
||||
#define GPIO_PF42 42
|
||||
#define GPIO_PF43 43
|
||||
#define GPIO_PF44 44
|
||||
#define GPIO_PF45 45
|
||||
#define GPIO_PF46 46
|
||||
#define GPIO_PF47 47
|
||||
|
||||
#define PORT_FIO0 GPIO_PF0
|
||||
#define PORT_FIO1 GPIO_PF16
|
||||
#define PORT_FIO2 GPIO_PF32
|
||||
|
||||
#include <mach-common/ports-f.h>
|
||||
|
||||
#endif /* _MACH_GPIO_H_ */
|
||||
236
arch/blackfin/mach-bf561/include/mach/irq.h
Normal file
236
arch/blackfin/mach-bf561/include/mach/irq.h
Normal file
|
|
@ -0,0 +1,236 @@
|
|||
/*
|
||||
* Copyright 2005-2008 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _BF561_IRQ_H_
|
||||
#define _BF561_IRQ_H_
|
||||
|
||||
#include <mach-common/irq.h>
|
||||
|
||||
#define NR_PERI_INTS (2 * 32)
|
||||
|
||||
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
|
||||
#define IRQ_DMA1_ERROR BFIN_IRQ(1) /* DMA1 Error (general) */
|
||||
#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
|
||||
#define IRQ_DMA2_ERROR BFIN_IRQ(2) /* DMA2 Error (general) */
|
||||
#define IRQ_IMDMA_ERROR BFIN_IRQ(3) /* IMDMA Error Interrupt */
|
||||
#define IRQ_PPI1_ERROR BFIN_IRQ(4) /* PPI1 Error Interrupt */
|
||||
#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
|
||||
#define IRQ_PPI2_ERROR BFIN_IRQ(5) /* PPI2 Error Interrupt */
|
||||
#define IRQ_SPORT0_ERROR BFIN_IRQ(6) /* SPORT0 Error Interrupt */
|
||||
#define IRQ_SPORT1_ERROR BFIN_IRQ(7) /* SPORT1 Error Interrupt */
|
||||
#define IRQ_SPI_ERROR BFIN_IRQ(8) /* SPI Error Interrupt */
|
||||
#define IRQ_UART_ERROR BFIN_IRQ(9) /* UART Error Interrupt */
|
||||
#define IRQ_RESERVED_ERROR BFIN_IRQ(10) /* Reversed */
|
||||
#define IRQ_DMA1_0 BFIN_IRQ(11) /* DMA1 0 Interrupt(PPI1) */
|
||||
#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
|
||||
#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
|
||||
#define IRQ_DMA1_1 BFIN_IRQ(12) /* DMA1 1 Interrupt(PPI2) */
|
||||
#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
|
||||
#define IRQ_DMA1_2 BFIN_IRQ(13) /* DMA1 2 Interrupt */
|
||||
#define IRQ_DMA1_3 BFIN_IRQ(14) /* DMA1 3 Interrupt */
|
||||
#define IRQ_DMA1_4 BFIN_IRQ(15) /* DMA1 4 Interrupt */
|
||||
#define IRQ_DMA1_5 BFIN_IRQ(16) /* DMA1 5 Interrupt */
|
||||
#define IRQ_DMA1_6 BFIN_IRQ(17) /* DMA1 6 Interrupt */
|
||||
#define IRQ_DMA1_7 BFIN_IRQ(18) /* DMA1 7 Interrupt */
|
||||
#define IRQ_DMA1_8 BFIN_IRQ(19) /* DMA1 8 Interrupt */
|
||||
#define IRQ_DMA1_9 BFIN_IRQ(20) /* DMA1 9 Interrupt */
|
||||
#define IRQ_DMA1_10 BFIN_IRQ(21) /* DMA1 10 Interrupt */
|
||||
#define IRQ_DMA1_11 BFIN_IRQ(22) /* DMA1 11 Interrupt */
|
||||
#define IRQ_DMA2_0 BFIN_IRQ(23) /* DMA2 0 (SPORT0 RX) */
|
||||
#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
|
||||
#define IRQ_DMA2_1 BFIN_IRQ(24) /* DMA2 1 (SPORT0 TX) */
|
||||
#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
|
||||
#define IRQ_DMA2_2 BFIN_IRQ(25) /* DMA2 2 (SPORT1 RX) */
|
||||
#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
|
||||
#define IRQ_DMA2_3 BFIN_IRQ(26) /* DMA2 3 (SPORT2 TX) */
|
||||
#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
|
||||
#define IRQ_DMA2_4 BFIN_IRQ(27) /* DMA2 4 (SPI) */
|
||||
#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
|
||||
#define IRQ_DMA2_5 BFIN_IRQ(28) /* DMA2 5 (UART RX) */
|
||||
#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
|
||||
#define IRQ_DMA2_6 BFIN_IRQ(29) /* DMA2 6 (UART TX) */
|
||||
#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
|
||||
#define IRQ_DMA2_7 BFIN_IRQ(30) /* DMA2 7 Interrupt */
|
||||
#define IRQ_DMA2_8 BFIN_IRQ(31) /* DMA2 8 Interrupt */
|
||||
#define IRQ_DMA2_9 BFIN_IRQ(32) /* DMA2 9 Interrupt */
|
||||
#define IRQ_DMA2_10 BFIN_IRQ(33) /* DMA2 10 Interrupt */
|
||||
#define IRQ_DMA2_11 BFIN_IRQ(34) /* DMA2 11 Interrupt */
|
||||
#define IRQ_TIMER0 BFIN_IRQ(35) /* TIMER 0 Interrupt */
|
||||
#define IRQ_TIMER1 BFIN_IRQ(36) /* TIMER 1 Interrupt */
|
||||
#define IRQ_TIMER2 BFIN_IRQ(37) /* TIMER 2 Interrupt */
|
||||
#define IRQ_TIMER3 BFIN_IRQ(38) /* TIMER 3 Interrupt */
|
||||
#define IRQ_TIMER4 BFIN_IRQ(39) /* TIMER 4 Interrupt */
|
||||
#define IRQ_TIMER5 BFIN_IRQ(40) /* TIMER 5 Interrupt */
|
||||
#define IRQ_TIMER6 BFIN_IRQ(41) /* TIMER 6 Interrupt */
|
||||
#define IRQ_TIMER7 BFIN_IRQ(42) /* TIMER 7 Interrupt */
|
||||
#define IRQ_TIMER8 BFIN_IRQ(43) /* TIMER 8 Interrupt */
|
||||
#define IRQ_TIMER9 BFIN_IRQ(44) /* TIMER 9 Interrupt */
|
||||
#define IRQ_TIMER10 BFIN_IRQ(45) /* TIMER 10 Interrupt */
|
||||
#define IRQ_TIMER11 BFIN_IRQ(46) /* TIMER 11 Interrupt */
|
||||
#define IRQ_PROG0_INTA BFIN_IRQ(47) /* Programmable Flags0 A (8) */
|
||||
#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
|
||||
#define IRQ_PROG0_INTB BFIN_IRQ(48) /* Programmable Flags0 B (8) */
|
||||
#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
|
||||
#define IRQ_PROG1_INTA BFIN_IRQ(49) /* Programmable Flags1 A (8) */
|
||||
#define IRQ_PROG1_INTB BFIN_IRQ(50) /* Programmable Flags1 B (8) */
|
||||
#define IRQ_PROG2_INTA BFIN_IRQ(51) /* Programmable Flags2 A (8) */
|
||||
#define IRQ_PROG2_INTB BFIN_IRQ(52) /* Programmable Flags2 B (8) */
|
||||
#define IRQ_DMA1_WRRD0 BFIN_IRQ(53) /* MDMA1 0 write/read INT */
|
||||
#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
|
||||
#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
|
||||
#define IRQ_DMA1_WRRD1 BFIN_IRQ(54) /* MDMA1 1 write/read INT */
|
||||
#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
|
||||
#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
|
||||
#define IRQ_DMA2_WRRD0 BFIN_IRQ(55) /* MDMA2 0 write/read INT */
|
||||
#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
|
||||
#define IRQ_DMA2_WRRD1 BFIN_IRQ(56) /* MDMA2 1 write/read INT */
|
||||
#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
|
||||
#define IRQ_IMDMA_WRRD0 BFIN_IRQ(57) /* IMDMA 0 write/read INT */
|
||||
#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
|
||||
#define IRQ_IMDMA_WRRD1 BFIN_IRQ(58) /* IMDMA 1 write/read INT */
|
||||
#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
|
||||
#define IRQ_WATCH BFIN_IRQ(59) /* Watch Dog Timer */
|
||||
#define IRQ_RESERVED_1 BFIN_IRQ(60) /* Reserved interrupt */
|
||||
#define IRQ_RESERVED_2 BFIN_IRQ(61) /* Reserved interrupt */
|
||||
#define IRQ_SUPPLE_0 BFIN_IRQ(62) /* Supplemental interrupt 0 */
|
||||
#define IRQ_SUPPLE_1 BFIN_IRQ(63) /* supplemental interrupt 1 */
|
||||
|
||||
#define SYS_IRQS 71
|
||||
|
||||
#define IRQ_PF0 73
|
||||
#define IRQ_PF1 74
|
||||
#define IRQ_PF2 75
|
||||
#define IRQ_PF3 76
|
||||
#define IRQ_PF4 77
|
||||
#define IRQ_PF5 78
|
||||
#define IRQ_PF6 79
|
||||
#define IRQ_PF7 80
|
||||
#define IRQ_PF8 81
|
||||
#define IRQ_PF9 82
|
||||
#define IRQ_PF10 83
|
||||
#define IRQ_PF11 84
|
||||
#define IRQ_PF12 85
|
||||
#define IRQ_PF13 86
|
||||
#define IRQ_PF14 87
|
||||
#define IRQ_PF15 88
|
||||
#define IRQ_PF16 89
|
||||
#define IRQ_PF17 90
|
||||
#define IRQ_PF18 91
|
||||
#define IRQ_PF19 92
|
||||
#define IRQ_PF20 93
|
||||
#define IRQ_PF21 94
|
||||
#define IRQ_PF22 95
|
||||
#define IRQ_PF23 96
|
||||
#define IRQ_PF24 97
|
||||
#define IRQ_PF25 98
|
||||
#define IRQ_PF26 99
|
||||
#define IRQ_PF27 100
|
||||
#define IRQ_PF28 101
|
||||
#define IRQ_PF29 102
|
||||
#define IRQ_PF30 103
|
||||
#define IRQ_PF31 104
|
||||
#define IRQ_PF32 105
|
||||
#define IRQ_PF33 106
|
||||
#define IRQ_PF34 107
|
||||
#define IRQ_PF35 108
|
||||
#define IRQ_PF36 109
|
||||
#define IRQ_PF37 110
|
||||
#define IRQ_PF38 111
|
||||
#define IRQ_PF39 112
|
||||
#define IRQ_PF40 113
|
||||
#define IRQ_PF41 114
|
||||
#define IRQ_PF42 115
|
||||
#define IRQ_PF43 116
|
||||
#define IRQ_PF44 117
|
||||
#define IRQ_PF45 118
|
||||
#define IRQ_PF46 119
|
||||
#define IRQ_PF47 120
|
||||
|
||||
#define GPIO_IRQ_BASE IRQ_PF0
|
||||
|
||||
#define NR_MACH_IRQS (IRQ_PF47 + 1)
|
||||
|
||||
/* IAR0 BIT FIELDS */
|
||||
#define IRQ_PLL_WAKEUP_POS 0
|
||||
#define IRQ_DMA1_ERROR_POS 4
|
||||
#define IRQ_DMA2_ERROR_POS 8
|
||||
#define IRQ_IMDMA_ERROR_POS 12
|
||||
#define IRQ_PPI0_ERROR_POS 16
|
||||
#define IRQ_PPI1_ERROR_POS 20
|
||||
#define IRQ_SPORT0_ERROR_POS 24
|
||||
#define IRQ_SPORT1_ERROR_POS 28
|
||||
|
||||
/* IAR1 BIT FIELDS */
|
||||
#define IRQ_SPI_ERROR_POS 0
|
||||
#define IRQ_UART_ERROR_POS 4
|
||||
#define IRQ_RESERVED_ERROR_POS 8
|
||||
#define IRQ_DMA1_0_POS 12
|
||||
#define IRQ_DMA1_1_POS 16
|
||||
#define IRQ_DMA1_2_POS 20
|
||||
#define IRQ_DMA1_3_POS 24
|
||||
#define IRQ_DMA1_4_POS 28
|
||||
|
||||
/* IAR2 BIT FIELDS */
|
||||
#define IRQ_DMA1_5_POS 0
|
||||
#define IRQ_DMA1_6_POS 4
|
||||
#define IRQ_DMA1_7_POS 8
|
||||
#define IRQ_DMA1_8_POS 12
|
||||
#define IRQ_DMA1_9_POS 16
|
||||
#define IRQ_DMA1_10_POS 20
|
||||
#define IRQ_DMA1_11_POS 24
|
||||
#define IRQ_DMA2_0_POS 28
|
||||
|
||||
/* IAR3 BIT FIELDS */
|
||||
#define IRQ_DMA2_1_POS 0
|
||||
#define IRQ_DMA2_2_POS 4
|
||||
#define IRQ_DMA2_3_POS 8
|
||||
#define IRQ_DMA2_4_POS 12
|
||||
#define IRQ_DMA2_5_POS 16
|
||||
#define IRQ_DMA2_6_POS 20
|
||||
#define IRQ_DMA2_7_POS 24
|
||||
#define IRQ_DMA2_8_POS 28
|
||||
|
||||
/* IAR4 BIT FIELDS */
|
||||
#define IRQ_DMA2_9_POS 0
|
||||
#define IRQ_DMA2_10_POS 4
|
||||
#define IRQ_DMA2_11_POS 8
|
||||
#define IRQ_TIMER0_POS 12
|
||||
#define IRQ_TIMER1_POS 16
|
||||
#define IRQ_TIMER2_POS 20
|
||||
#define IRQ_TIMER3_POS 24
|
||||
#define IRQ_TIMER4_POS 28
|
||||
|
||||
/* IAR5 BIT FIELDS */
|
||||
#define IRQ_TIMER5_POS 0
|
||||
#define IRQ_TIMER6_POS 4
|
||||
#define IRQ_TIMER7_POS 8
|
||||
#define IRQ_TIMER8_POS 12
|
||||
#define IRQ_TIMER9_POS 16
|
||||
#define IRQ_TIMER10_POS 20
|
||||
#define IRQ_TIMER11_POS 24
|
||||
#define IRQ_PROG0_INTA_POS 28
|
||||
|
||||
/* IAR6 BIT FIELDS */
|
||||
#define IRQ_PROG0_INTB_POS 0
|
||||
#define IRQ_PROG1_INTA_POS 4
|
||||
#define IRQ_PROG1_INTB_POS 8
|
||||
#define IRQ_PROG2_INTA_POS 12
|
||||
#define IRQ_PROG2_INTB_POS 16
|
||||
#define IRQ_DMA1_WRRD0_POS 20
|
||||
#define IRQ_DMA1_WRRD1_POS 24
|
||||
#define IRQ_DMA2_WRRD0_POS 28
|
||||
|
||||
/* IAR7 BIT FIELDS */
|
||||
#define IRQ_DMA2_WRRD1_POS 0
|
||||
#define IRQ_IMDMA_WRRD0_POS 4
|
||||
#define IRQ_IMDMA_WRRD1_POS 8
|
||||
#define IRQ_WDTIMER_POS 12
|
||||
#define IRQ_RESERVED_1_POS 16
|
||||
#define IRQ_RESERVED_2_POS 20
|
||||
#define IRQ_SUPPLE_0_POS 24
|
||||
#define IRQ_SUPPLE_1_POS 28
|
||||
|
||||
#endif
|
||||
219
arch/blackfin/mach-bf561/include/mach/mem_map.h
Normal file
219
arch/blackfin/mach-bf561/include/mach/mem_map.h
Normal file
|
|
@ -0,0 +1,219 @@
|
|||
/*
|
||||
* BF561 memory map
|
||||
*
|
||||
* Copyright 2004-2009 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_MACH_MEM_MAP_H__
|
||||
#define __BFIN_MACH_MEM_MAP_H__
|
||||
|
||||
#ifndef __BFIN_MEM_MAP_H__
|
||||
# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
|
||||
#endif
|
||||
|
||||
/* Async Memory Banks */
|
||||
#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
|
||||
#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
|
||||
#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
|
||||
#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
|
||||
#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
|
||||
#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
|
||||
#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
|
||||
#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
|
||||
|
||||
/* Boot ROM Memory */
|
||||
|
||||
#define BOOT_ROM_START 0xEF000000
|
||||
#define BOOT_ROM_LENGTH 0x800
|
||||
|
||||
/* Level 1 Memory */
|
||||
|
||||
#ifdef CONFIG_BFIN_ICACHE
|
||||
#define BFIN_ICACHESIZE (16*1024)
|
||||
#else
|
||||
#define BFIN_ICACHESIZE (0*1024)
|
||||
#endif
|
||||
|
||||
/* Memory Map for ADSP-BF561 processors */
|
||||
|
||||
#define COREA_L1_CODE_START 0xFFA00000
|
||||
#define COREA_L1_DATA_A_START 0xFF800000
|
||||
#define COREA_L1_DATA_B_START 0xFF900000
|
||||
#define COREB_L1_CODE_START 0xFF600000
|
||||
#define COREB_L1_DATA_A_START 0xFF400000
|
||||
#define COREB_L1_DATA_B_START 0xFF500000
|
||||
|
||||
#define L1_CODE_START COREA_L1_CODE_START
|
||||
#define L1_DATA_A_START COREA_L1_DATA_A_START
|
||||
#define L1_DATA_B_START COREA_L1_DATA_B_START
|
||||
|
||||
#define L1_CODE_LENGTH 0x4000
|
||||
|
||||
#ifdef CONFIG_BFIN_DCACHE
|
||||
|
||||
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BFIN_DCACHESIZE (16*1024)
|
||||
#define BFIN_DSUPBANKS 1
|
||||
#else
|
||||
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
|
||||
#define BFIN_DCACHESIZE (32*1024)
|
||||
#define BFIN_DSUPBANKS 2
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||
#define L1_DATA_A_LENGTH 0x8000
|
||||
#define L1_DATA_B_LENGTH 0x8000
|
||||
#define BFIN_DCACHESIZE (0*1024)
|
||||
#define BFIN_DSUPBANKS 0
|
||||
#endif /*CONFIG_BFIN_DCACHE*/
|
||||
|
||||
/*
|
||||
* If we are in SMP mode, then the cache settings of Core B will match
|
||||
* the settings of Core A. If we aren't, then we assume Core B is not
|
||||
* using any cache. This allows the rest of the kernel to work with
|
||||
* the core in either mode as we are only loading user code into it and
|
||||
* it is the user's problem to make sure they aren't doing something
|
||||
* stupid there.
|
||||
*
|
||||
* Note that we treat the L1 code region as a contiguous blob to make
|
||||
* the rest of the kernel simpler. Easier to check one region than a
|
||||
* bunch of small ones. Again, possible misbehavior here is the fault
|
||||
* of the user -- don't try to use memory that doesn't exist.
|
||||
*/
|
||||
#ifdef CONFIG_SMP
|
||||
# define COREB_L1_CODE_LENGTH L1_CODE_LENGTH
|
||||
# define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH
|
||||
# define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH
|
||||
#else
|
||||
# define COREB_L1_CODE_LENGTH 0x14000
|
||||
# define COREB_L1_DATA_A_LENGTH 0x8000
|
||||
# define COREB_L1_DATA_B_LENGTH 0x8000
|
||||
#endif
|
||||
|
||||
/* Level 2 Memory */
|
||||
#define L2_START 0xFEB00000
|
||||
#define L2_LENGTH 0x20000
|
||||
|
||||
/* Scratch Pad Memory */
|
||||
|
||||
#define COREA_L1_SCRATCH_START 0xFFB00000
|
||||
#define COREB_L1_SCRATCH_START 0xFF700000
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
|
||||
/*
|
||||
* The following macros both return the address of the PDA for the
|
||||
* current core.
|
||||
*
|
||||
* In its first safe (and hairy) form, the macro neither clobbers any
|
||||
* register aside of the output Preg, nor uses the stack, since it
|
||||
* could be called with an invalid stack pointer, or the current stack
|
||||
* space being uncovered by any CPLB (e.g. early exception handling).
|
||||
*
|
||||
* The constraints on the second form are a bit relaxed, and the code
|
||||
* is allowed to use the specified Dreg for determining the PDA
|
||||
* address to be returned into Preg.
|
||||
*/
|
||||
# define GET_PDA_SAFE(preg) \
|
||||
preg.l = lo(DSPID); \
|
||||
preg.h = hi(DSPID); \
|
||||
preg = [preg]; \
|
||||
preg = preg << 2; \
|
||||
preg = preg << 2; \
|
||||
preg = preg << 2; \
|
||||
preg = preg << 2; \
|
||||
preg = preg << 2; \
|
||||
preg = preg << 2; \
|
||||
preg = preg << 2; \
|
||||
preg = preg << 2; \
|
||||
preg = preg << 2; \
|
||||
preg = preg << 2; \
|
||||
preg = preg << 2; \
|
||||
preg = preg << 2; \
|
||||
if cc jump 2f; \
|
||||
cc = preg == 0x0; \
|
||||
preg.l = _cpu_pda; \
|
||||
preg.h = _cpu_pda; \
|
||||
if !cc jump 3f; \
|
||||
1: \
|
||||
/* preg = 0x0; */ \
|
||||
cc = !cc; /* restore cc to 0 */ \
|
||||
jump 4f; \
|
||||
2: \
|
||||
cc = preg == 0x0; \
|
||||
preg.l = _cpu_pda; \
|
||||
preg.h = _cpu_pda; \
|
||||
if cc jump 4f; \
|
||||
/* preg = 0x1000000; */ \
|
||||
cc = !cc; /* restore cc to 1 */ \
|
||||
3: \
|
||||
preg = [preg]; \
|
||||
4:
|
||||
|
||||
# define GET_PDA(preg, dreg) \
|
||||
preg.l = lo(DSPID); \
|
||||
preg.h = hi(DSPID); \
|
||||
dreg = [preg]; \
|
||||
preg.l = _cpu_pda; \
|
||||
preg.h = _cpu_pda; \
|
||||
cc = bittst(dreg, 0); \
|
||||
if !cc jump 1f; \
|
||||
preg = [preg]; \
|
||||
1: \
|
||||
|
||||
# define GET_CPUID(preg, dreg) \
|
||||
preg.l = lo(DSPID); \
|
||||
preg.h = hi(DSPID); \
|
||||
dreg = [preg]; \
|
||||
dreg = ROT dreg BY -1; \
|
||||
dreg = CC;
|
||||
|
||||
# ifndef __ASSEMBLY__
|
||||
|
||||
# include <asm/processor.h>
|
||||
|
||||
static inline unsigned long get_l1_scratch_start_cpu(int cpu)
|
||||
{
|
||||
return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
|
||||
}
|
||||
static inline unsigned long get_l1_code_start_cpu(int cpu)
|
||||
{
|
||||
return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START;
|
||||
}
|
||||
static inline unsigned long get_l1_data_a_start_cpu(int cpu)
|
||||
{
|
||||
return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
|
||||
}
|
||||
static inline unsigned long get_l1_data_b_start_cpu(int cpu)
|
||||
{
|
||||
return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
|
||||
}
|
||||
|
||||
static inline unsigned long get_l1_scratch_start(void)
|
||||
{
|
||||
return get_l1_scratch_start_cpu(blackfin_core_id());
|
||||
}
|
||||
static inline unsigned long get_l1_code_start(void)
|
||||
{
|
||||
return get_l1_code_start_cpu(blackfin_core_id());
|
||||
}
|
||||
static inline unsigned long get_l1_data_a_start(void)
|
||||
{
|
||||
return get_l1_data_a_start_cpu(blackfin_core_id());
|
||||
}
|
||||
static inline unsigned long get_l1_data_b_start(void)
|
||||
{
|
||||
return get_l1_data_b_start_cpu(blackfin_core_id());
|
||||
}
|
||||
|
||||
# endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
#endif
|
||||
56
arch/blackfin/mach-bf561/include/mach/pll.h
Normal file
56
arch/blackfin/mach-bf561/include/mach/pll.h
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* Copyright 2005-2010 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_PLL_H
|
||||
#define _MACH_PLL_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/irqflags.h>
|
||||
#include <mach/irq.h>
|
||||
|
||||
#define SUPPLE_0_WAKEUP ((IRQ_SUPPLE_0 - (IRQ_CORETMR + 1)) % 32)
|
||||
#define SUPPLE_1_WAKEUP ((IRQ_SUPPLE_1 - (IRQ_CORETMR + 1)) % 32)
|
||||
|
||||
static inline void
|
||||
bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
|
||||
{
|
||||
unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
|
||||
|
||||
bfin_write32(SIC_IWR0 + SICA_SICB_OFF, iwr0);
|
||||
bfin_write32(SIC_IWR1 + SICA_SICB_OFF, iwr1);
|
||||
}
|
||||
#define bfin_iwr_restore bfin_iwr_restore
|
||||
|
||||
static inline void
|
||||
bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
|
||||
unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
|
||||
{
|
||||
unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
|
||||
|
||||
*iwr0 = bfin_read32(SIC_IWR0 + SICA_SICB_OFF);
|
||||
*iwr1 = bfin_read32(SIC_IWR1 + SICA_SICB_OFF);
|
||||
bfin_iwr_restore(niwr0, niwr1, niwr2);
|
||||
}
|
||||
#define bfin_iwr_save bfin_iwr_save
|
||||
|
||||
static inline void
|
||||
bfin_iwr_set_sup0(unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
|
||||
{
|
||||
bfin_iwr_save(0, IWR_ENABLE(SUPPLE_0_WAKEUP) |
|
||||
IWR_ENABLE(SUPPLE_1_WAKEUP), 0, iwr0, iwr1, iwr2);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include <mach-common/pll.h>
|
||||
|
||||
#endif
|
||||
97
arch/blackfin/mach-bf561/include/mach/portmux.h
Normal file
97
arch/blackfin/mach-bf561/include/mach/portmux.h
Normal file
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* Copyright 2007-2009 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_PORTMUX_H_
|
||||
#define _MACH_PORTMUX_H_
|
||||
|
||||
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
|
||||
|
||||
#define P_PPI0_CLK (P_DONTCARE)
|
||||
#define P_PPI0_FS1 (P_DONTCARE)
|
||||
#define P_PPI0_FS2 (P_DONTCARE)
|
||||
#define P_PPI0_FS3 (P_DONTCARE)
|
||||
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47))
|
||||
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46))
|
||||
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45))
|
||||
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44))
|
||||
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43))
|
||||
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42))
|
||||
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41))
|
||||
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40))
|
||||
#define P_PPI0_D0 (P_DONTCARE)
|
||||
#define P_PPI0_D1 (P_DONTCARE)
|
||||
#define P_PPI0_D2 (P_DONTCARE)
|
||||
#define P_PPI0_D3 (P_DONTCARE)
|
||||
#define P_PPI0_D4 (P_DONTCARE)
|
||||
#define P_PPI0_D5 (P_DONTCARE)
|
||||
#define P_PPI0_D6 (P_DONTCARE)
|
||||
#define P_PPI0_D7 (P_DONTCARE)
|
||||
#define P_PPI1_CLK (P_DONTCARE)
|
||||
#define P_PPI1_FS1 (P_DONTCARE)
|
||||
#define P_PPI1_FS2 (P_DONTCARE)
|
||||
#define P_PPI1_FS3 (P_DONTCARE)
|
||||
#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39))
|
||||
#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38))
|
||||
#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37))
|
||||
#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36))
|
||||
#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35))
|
||||
#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34))
|
||||
#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33))
|
||||
#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32))
|
||||
#define P_PPI1_D0 (P_DONTCARE)
|
||||
#define P_PPI1_D1 (P_DONTCARE)
|
||||
#define P_PPI1_D2 (P_DONTCARE)
|
||||
#define P_PPI1_D3 (P_DONTCARE)
|
||||
#define P_PPI1_D4 (P_DONTCARE)
|
||||
#define P_PPI1_D5 (P_DONTCARE)
|
||||
#define P_PPI1_D6 (P_DONTCARE)
|
||||
#define P_PPI1_D7 (P_DONTCARE)
|
||||
#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31))
|
||||
#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30))
|
||||
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29))
|
||||
#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28))
|
||||
#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27))
|
||||
#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26))
|
||||
#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25))
|
||||
#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24))
|
||||
#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23))
|
||||
#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22))
|
||||
#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21))
|
||||
#define P_SPORT1_DRPRI (P_DONTCARE)
|
||||
#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20))
|
||||
#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19))
|
||||
#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18))
|
||||
#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17))
|
||||
#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16))
|
||||
#define P_SPORT0_DRPRI (P_DONTCARE)
|
||||
#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15))
|
||||
#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
|
||||
#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
|
||||
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
|
||||
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
|
||||
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
|
||||
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
|
||||
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
|
||||
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
|
||||
#define P_TMR11 (P_DONTCARE)
|
||||
#define P_TMR10 (P_DONTCARE)
|
||||
#define P_TMR9 (P_DONTCARE)
|
||||
#define P_TMR8 (P_DONTCARE)
|
||||
#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7))
|
||||
#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6))
|
||||
#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5))
|
||||
#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4))
|
||||
#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3))
|
||||
#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2))
|
||||
#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1))
|
||||
#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0))
|
||||
#define P_SPI0_MOSI (P_DONTCARE)
|
||||
#define P_SPI0_MISO (P_DONTCARE)
|
||||
#define P_SPI0_SCK (P_DONTCARE)
|
||||
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
|
||||
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
|
||||
|
||||
#endif /* _MACH_PORTMUX_H_ */
|
||||
32
arch/blackfin/mach-bf561/include/mach/smp.h
Normal file
32
arch/blackfin/mach-bf561/include/mach/smp.h
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright 2007-2008 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_BF561_SMP
|
||||
#define _MACH_BF561_SMP
|
||||
|
||||
/* This header has to stand alone to avoid circular deps */
|
||||
|
||||
struct task_struct;
|
||||
|
||||
void platform_init_cpus(void);
|
||||
|
||||
void platform_prepare_cpus(unsigned int max_cpus);
|
||||
|
||||
int platform_boot_secondary(unsigned int cpu, struct task_struct *idle);
|
||||
|
||||
void platform_secondary_init(unsigned int cpu);
|
||||
|
||||
void platform_request_ipi(int irq, /*irq_handler_t*/ void *handler);
|
||||
|
||||
void platform_send_ipi(cpumask_t callmap, int irq);
|
||||
|
||||
void platform_send_ipi_cpu(unsigned int cpu, int irq);
|
||||
|
||||
void platform_clear_ipi(unsigned int cpu, int irq);
|
||||
|
||||
void bfin_local_timer_setup(void);
|
||||
|
||||
#endif /* !_MACH_BF561_SMP */
|
||||
87
arch/blackfin/mach-bf561/ints-priority.c
Normal file
87
arch/blackfin/mach-bf561/ints-priority.c
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Set up the interrupt priorities
|
||||
*
|
||||
* Copyright 2005-2009 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/irq.h>
|
||||
#include <asm/blackfin.h>
|
||||
|
||||
void __init program_IAR(void)
|
||||
{
|
||||
/* Program the IAR0 Register with the configured priority */
|
||||
bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
|
||||
((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
|
||||
((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) |
|
||||
((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) |
|
||||
((CONFIG_IRQ_PPI0_ERROR - 7) << IRQ_PPI0_ERROR_POS) |
|
||||
((CONFIG_IRQ_PPI1_ERROR - 7) << IRQ_PPI1_ERROR_POS) |
|
||||
((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
|
||||
((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS));
|
||||
|
||||
bfin_write_SIC_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) |
|
||||
((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) |
|
||||
((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) |
|
||||
((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) |
|
||||
((CONFIG_IRQ_DMA1_1 - 7) << IRQ_DMA1_1_POS) |
|
||||
((CONFIG_IRQ_DMA1_2 - 7) << IRQ_DMA1_2_POS) |
|
||||
((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) |
|
||||
((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS));
|
||||
|
||||
bfin_write_SIC_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) |
|
||||
((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) |
|
||||
((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) |
|
||||
((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) |
|
||||
((CONFIG_IRQ_DMA1_9 - 7) << IRQ_DMA1_9_POS) |
|
||||
((CONFIG_IRQ_DMA1_10 - 7) << IRQ_DMA1_10_POS) |
|
||||
((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) |
|
||||
((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS));
|
||||
|
||||
bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) |
|
||||
((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) |
|
||||
((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) |
|
||||
((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) |
|
||||
((CONFIG_IRQ_DMA2_5 - 7) << IRQ_DMA2_5_POS) |
|
||||
((CONFIG_IRQ_DMA2_6 - 7) << IRQ_DMA2_6_POS) |
|
||||
((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) |
|
||||
((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS));
|
||||
|
||||
bfin_write_SIC_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) |
|
||||
((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) |
|
||||
((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) |
|
||||
((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
|
||||
((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
|
||||
((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
|
||||
((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
|
||||
((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
|
||||
|
||||
bfin_write_SIC_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
|
||||
((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
|
||||
((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
|
||||
((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
|
||||
((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
|
||||
((CONFIG_IRQ_TIMER10 - 7) << IRQ_TIMER10_POS) |
|
||||
((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) |
|
||||
((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS));
|
||||
|
||||
bfin_write_SIC_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) |
|
||||
((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) |
|
||||
((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) |
|
||||
((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) |
|
||||
((CONFIG_IRQ_PROG2_INTB - 7) << IRQ_PROG2_INTB_POS) |
|
||||
((CONFIG_IRQ_DMA1_WRRD0 - 7) << IRQ_DMA1_WRRD0_POS) |
|
||||
((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) |
|
||||
((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS));
|
||||
|
||||
bfin_write_SIC_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) |
|
||||
((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) |
|
||||
((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) |
|
||||
((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) |
|
||||
(0 << IRQ_RESERVED_1_POS) | (0 << IRQ_RESERVED_2_POS) |
|
||||
(0 << IRQ_SUPPLE_0_POS) | (0 << IRQ_SUPPLE_1_POS));
|
||||
|
||||
SSYNC();
|
||||
}
|
||||
192
arch/blackfin/mach-bf561/secondary.S
Normal file
192
arch/blackfin/mach-bf561/secondary.S
Normal file
|
|
@ -0,0 +1,192 @@
|
|||
/*
|
||||
* BF561 coreB bootstrap file
|
||||
*
|
||||
* Copyright 2007-2009 Analog Devices Inc.
|
||||
* Philippe Gerum <rpm@xenomai.org>
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/trace.h>
|
||||
|
||||
/*
|
||||
* This code must come first as CoreB is hardcoded (in hardware)
|
||||
* to start at the beginning of its L1 instruction memory.
|
||||
*/
|
||||
.section .l1.text.head
|
||||
|
||||
/* Lay the initial stack into the L1 scratch area of Core B */
|
||||
#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
|
||||
|
||||
ENTRY(_coreb_trampoline_start)
|
||||
/* Enable Cycle Counter and Nesting Of Interrupts */
|
||||
#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
|
||||
R0 = SYSCFG_SNEN;
|
||||
#else
|
||||
R0 = SYSCFG_SNEN | SYSCFG_CCEN;
|
||||
#endif
|
||||
SYSCFG = R0;
|
||||
|
||||
/* Optimization register tricks: keep a base value in the
|
||||
* reserved P registers so we use the load/store with an
|
||||
* offset syntax. R0 = [P5 + <constant>];
|
||||
* P5 - core MMR base
|
||||
* R6 - 0
|
||||
*/
|
||||
r6 = 0;
|
||||
p5.l = 0;
|
||||
p5.h = hi(COREMMR_BASE);
|
||||
|
||||
/* Zero out registers required by Blackfin ABI */
|
||||
|
||||
/* Disable circular buffers */
|
||||
L0 = r6;
|
||||
L1 = r6;
|
||||
L2 = r6;
|
||||
L3 = r6;
|
||||
|
||||
/* Disable hardware loops in case we were started by 'go' */
|
||||
LC0 = r6;
|
||||
LC1 = r6;
|
||||
|
||||
/*
|
||||
* Clear ITEST_COMMAND and DTEST_COMMAND registers,
|
||||
* Leaving these as non-zero can confuse the emulator
|
||||
*/
|
||||
[p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6;
|
||||
[p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6;
|
||||
CSYNC;
|
||||
|
||||
trace_buffer_init(p0,r0);
|
||||
|
||||
/* Turn off the icache */
|
||||
r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)];
|
||||
BITCLR (r1, ENICPLB_P);
|
||||
[p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
|
||||
SSYNC;
|
||||
|
||||
/* Turn off the dcache */
|
||||
r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
|
||||
BITCLR (r1, ENDCPLB_P);
|
||||
[p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
|
||||
SSYNC;
|
||||
|
||||
/* in case of double faults, save a few things */
|
||||
p1.l = _initial_pda_coreb;
|
||||
p1.h = _initial_pda_coreb;
|
||||
r4 = RETX;
|
||||
#ifdef CONFIG_DEBUG_DOUBLEFAULT
|
||||
/* Only save these if we are storing them,
|
||||
* This happens here, since L1 gets clobbered
|
||||
* below
|
||||
*/
|
||||
GET_PDA(p0, r0);
|
||||
r0 = [p0 + PDA_DF_RETX];
|
||||
r1 = [p0 + PDA_DF_DCPLB];
|
||||
r2 = [p0 + PDA_DF_ICPLB];
|
||||
r3 = [p0 + PDA_DF_SEQSTAT];
|
||||
[p1 + PDA_INIT_DF_RETX] = r0;
|
||||
[p1 + PDA_INIT_DF_DCPLB] = r1;
|
||||
[p1 + PDA_INIT_DF_ICPLB] = r2;
|
||||
[p1 + PDA_INIT_DF_SEQSTAT] = r3;
|
||||
#endif
|
||||
[p1 + PDA_INIT_RETX] = r4;
|
||||
|
||||
/* Initialize stack pointer */
|
||||
sp.l = lo(INITIAL_STACK);
|
||||
sp.h = hi(INITIAL_STACK);
|
||||
fp = sp;
|
||||
usp = sp;
|
||||
|
||||
/* This section keeps the processor in supervisor mode
|
||||
* during core B startup. Branches to the idle task.
|
||||
*/
|
||||
|
||||
/* EVT15 = _real_start */
|
||||
|
||||
p1.l = _coreb_start;
|
||||
p1.h = _coreb_start;
|
||||
[p5 + (EVT15 - COREMMR_BASE)] = p1;
|
||||
csync;
|
||||
|
||||
r0 = EVT_IVG15 (z);
|
||||
sti r0;
|
||||
|
||||
raise 15;
|
||||
p0.l = .LWAIT_HERE;
|
||||
p0.h = .LWAIT_HERE;
|
||||
reti = p0;
|
||||
#if defined(ANOMALY_05000281)
|
||||
nop; nop; nop;
|
||||
#endif
|
||||
rti;
|
||||
|
||||
.LWAIT_HERE:
|
||||
jump .LWAIT_HERE;
|
||||
ENDPROC(_coreb_trampoline_start)
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.section ".text"
|
||||
ENTRY(_coreb_die)
|
||||
sp.l = lo(INITIAL_STACK);
|
||||
sp.h = hi(INITIAL_STACK);
|
||||
fp = sp;
|
||||
usp = sp;
|
||||
|
||||
CLI R2;
|
||||
SSYNC;
|
||||
IDLE;
|
||||
STI R2;
|
||||
|
||||
R0 = IWR_DISABLE_ALL;
|
||||
P0.H = hi(SYSMMR_BASE);
|
||||
P0.L = lo(SYSMMR_BASE);
|
||||
[P0 + (SICB_IWR0 - SYSMMR_BASE)] = R0;
|
||||
[P0 + (SICB_IWR1 - SYSMMR_BASE)] = R0;
|
||||
SSYNC;
|
||||
|
||||
p0.h = hi(COREB_L1_CODE_START);
|
||||
p0.l = lo(COREB_L1_CODE_START);
|
||||
jump (p0);
|
||||
ENDPROC(_coreb_die)
|
||||
#endif
|
||||
|
||||
__INIT
|
||||
ENTRY(_coreb_start)
|
||||
[--sp] = reti;
|
||||
|
||||
p0.l = lo(WDOGB_CTL);
|
||||
p0.h = hi(WDOGB_CTL);
|
||||
r0 = 0xAD6(z);
|
||||
w[p0] = r0; /* Clear the watchdog. */
|
||||
ssync;
|
||||
|
||||
/*
|
||||
* switch to IDLE stack.
|
||||
*/
|
||||
p0.l = _secondary_stack;
|
||||
p0.h = _secondary_stack;
|
||||
sp = [p0];
|
||||
usp = sp;
|
||||
fp = sp;
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
p0.l = _hotplug_coreb;
|
||||
p0.h = _hotplug_coreb;
|
||||
r0 = [p0];
|
||||
cc = BITTST(r0, 0);
|
||||
if cc jump 3f;
|
||||
#endif
|
||||
sp += -12;
|
||||
call _init_pda
|
||||
sp += 12;
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
3:
|
||||
#endif
|
||||
call _secondary_start_kernel;
|
||||
.L_exit:
|
||||
jump.s .L_exit;
|
||||
ENDPROC(_coreb_start)
|
||||
172
arch/blackfin/mach-bf561/smp.c
Normal file
172
arch/blackfin/mach-bf561/smp.c
Normal file
|
|
@ -0,0 +1,172 @@
|
|||
/*
|
||||
* Copyright 2007-2009 Analog Devices Inc.
|
||||
* Philippe Gerum <rpm@xenomai.org>
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/delay.h>
|
||||
#include <asm/smp.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
static DEFINE_SPINLOCK(boot_lock);
|
||||
|
||||
/*
|
||||
* platform_init_cpus() - Tell the world about how many cores we
|
||||
* have. This is called while setting up the architecture support
|
||||
* (setup_arch()), so don't be too demanding here with respect to
|
||||
* available kernel services.
|
||||
*/
|
||||
|
||||
void __init platform_init_cpus(void)
|
||||
{
|
||||
struct cpumask mask;
|
||||
|
||||
cpumask_set_cpu(0, &mask); /* CoreA */
|
||||
cpumask_set_cpu(1, &mask); /* CoreB */
|
||||
init_cpu_possible(&mask);
|
||||
}
|
||||
|
||||
void __init platform_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
struct cpumask mask;
|
||||
|
||||
bfin_relocate_coreb_l1_mem();
|
||||
|
||||
/* Both cores ought to be present on a bf561! */
|
||||
cpumask_set_cpu(0, &mask); /* CoreA */
|
||||
cpumask_set_cpu(1, &mask); /* CoreB */
|
||||
init_cpu_present(&mask);
|
||||
}
|
||||
|
||||
int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
void platform_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/* Clone setup for peripheral interrupt sources from CoreA. */
|
||||
bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0());
|
||||
bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1());
|
||||
SSYNC();
|
||||
|
||||
/* Clone setup for IARs from CoreA. */
|
||||
bfin_write_SICB_IAR0(bfin_read_SIC_IAR0());
|
||||
bfin_write_SICB_IAR1(bfin_read_SIC_IAR1());
|
||||
bfin_write_SICB_IAR2(bfin_read_SIC_IAR2());
|
||||
bfin_write_SICB_IAR3(bfin_read_SIC_IAR3());
|
||||
bfin_write_SICB_IAR4(bfin_read_SIC_IAR4());
|
||||
bfin_write_SICB_IAR5(bfin_read_SIC_IAR5());
|
||||
bfin_write_SICB_IAR6(bfin_read_SIC_IAR6());
|
||||
bfin_write_SICB_IAR7(bfin_read_SIC_IAR7());
|
||||
bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
|
||||
bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
|
||||
SSYNC();
|
||||
|
||||
/* We are done with local CPU inits, unblock the boot CPU. */
|
||||
spin_lock(&boot_lock);
|
||||
spin_unlock(&boot_lock);
|
||||
}
|
||||
|
||||
int platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
unsigned long timeout;
|
||||
|
||||
printk(KERN_INFO "Booting Core B.\n");
|
||||
|
||||
spin_lock(&boot_lock);
|
||||
|
||||
if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) {
|
||||
/* CoreB already running, sending ipi to wakeup it */
|
||||
smp_send_reschedule(cpu);
|
||||
} else {
|
||||
/* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
|
||||
bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT);
|
||||
SSYNC();
|
||||
}
|
||||
|
||||
timeout = jiffies + HZ;
|
||||
/* release the lock and let coreb run */
|
||||
spin_unlock(&boot_lock);
|
||||
while (time_before(jiffies, timeout)) {
|
||||
if (cpu_online(cpu))
|
||||
break;
|
||||
udelay(100);
|
||||
barrier();
|
||||
}
|
||||
|
||||
if (cpu_online(cpu)) {
|
||||
return 0;
|
||||
} else
|
||||
panic("CPU%u: processor failed to boot\n", cpu);
|
||||
}
|
||||
|
||||
static const char supple0[] = "IRQ_SUPPLE_0";
|
||||
static const char supple1[] = "IRQ_SUPPLE_1";
|
||||
void __init platform_request_ipi(int irq, void *handler)
|
||||
{
|
||||
int ret;
|
||||
const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1;
|
||||
|
||||
ret = request_irq(irq, handler, IRQF_PERCPU | IRQF_NO_SUSPEND |
|
||||
IRQF_FORCE_RESUME, name, handler);
|
||||
if (ret)
|
||||
panic("Cannot request %s for IPI service", name);
|
||||
}
|
||||
|
||||
void platform_send_ipi(cpumask_t callmap, int irq)
|
||||
{
|
||||
unsigned int cpu;
|
||||
int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
|
||||
|
||||
for_each_cpu_mask(cpu, callmap) {
|
||||
BUG_ON(cpu >= 2);
|
||||
SSYNC();
|
||||
bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
|
||||
SSYNC();
|
||||
}
|
||||
}
|
||||
|
||||
void platform_send_ipi_cpu(unsigned int cpu, int irq)
|
||||
{
|
||||
int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
|
||||
BUG_ON(cpu >= 2);
|
||||
SSYNC();
|
||||
bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
|
||||
SSYNC();
|
||||
}
|
||||
|
||||
void platform_clear_ipi(unsigned int cpu, int irq)
|
||||
{
|
||||
int offset = (irq == IRQ_SUPPLE_0) ? 10 : 12;
|
||||
BUG_ON(cpu >= 2);
|
||||
SSYNC();
|
||||
bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
|
||||
SSYNC();
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup core B's local core timer.
|
||||
* In SMP, core timer is used for clock event device.
|
||||
*/
|
||||
void bfin_local_timer_setup(void)
|
||||
{
|
||||
#if defined(CONFIG_TICKSOURCE_CORETMR)
|
||||
struct irq_data *data = irq_get_irq_data(IRQ_CORETMR);
|
||||
struct irq_chip *chip = irq_data_get_irq_chip(data);
|
||||
|
||||
bfin_coretmr_init();
|
||||
bfin_coretmr_clockevent_init();
|
||||
|
||||
chip->irq_unmask(data);
|
||||
#else
|
||||
/* Power down the core timer, just to play safe. */
|
||||
bfin_write_TCNTL(0);
|
||||
#endif
|
||||
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue