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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
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137
arch/blackfin/mach-bf609/include/mach/anomaly.h Normal file
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/*
* DO NOT EDIT THIS FILE
* This file is under version control at
* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2012 Analog Devices Inc.
* Licensed under the Clear BSD license.
*/
/* This file should be up to date with:
* - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
*/
#if __SILICON_REVISION__ < 0
# error will not work on BF609 silicon version
#endif
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
#define ANOMALY_16000003 (1)
/* The EPPI Data Enable (DEN) Signal is Not Functional */
#define ANOMALY_16000004 (__SILICON_REVISION__ < 1)
/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
#define ANOMALY_16000005 (__SILICON_REVISION__ < 1)
/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
#define ANOMALY_16000006 (__SILICON_REVISION__ < 1)
/* DDR2 Memory Reads May Fail Intermittently */
#define ANOMALY_16000007 (1)
/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
#define ANOMALY_16000008 (1)
/* TestSET Instruction Cannot Be Interrupted */
#define ANOMALY_16000009 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_16000010 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_16000011 (1)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_16000012 (1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_16000013 (1)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_16000014 (1)
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_16000015 (1)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_16000017 (1)
/* RSI Boot Cleanup Routine Does Not Clear Registers */
#define ANOMALY_16000018 (__SILICON_REVISION__ < 1)
/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
#define ANOMALY_16000019 (__SILICON_REVISION__ < 1)
/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
#define ANOMALY_16000020 (__SILICON_REVISION__ < 1)
/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */
#define ANOMALY_16000021 (__SILICON_REVISION__ < 1)
/* Boot Code Fails to Enable Parity Fault Detection */
#define ANOMALY_16000022 (__SILICON_REVISION__ < 1)
/* Rom_SysControl Does not Update CGU0_CLKOUTSEL */
#define ANOMALY_16000023 (__SILICON_REVISION__ < 1)
/* Spurious Fault Signaled After Clearing an Externally Generated Fault */
#define ANOMALY_16000024 (1)
/* SPORT May Drive Data Pins During Inactive Channels in Multichannel Mode */
#define ANOMALY_16000025 (1)
/* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */
#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
/* Default SPI Master Boot Mode Setting is Incorrect */
#define ANOMALY_16000028 (__SILICON_REVISION__ < 1)
/* PPI tDFSPI Timing Does Not Meet Data Sheet Specification */
#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
/* Interrupted Core Reads of MMRs May Cause Data Loss */
#define ANOMALY_16000030 (__SILICON_REVISION__ < 1)
/* Incorrect Default USB_PLL_OSC.PLLM Value */
#define ANOMALY_16000031 (__SILICON_REVISION__ < 1)
/* Core Reads of System MMRs May Cause the Core to Hang */
#define ANOMALY_16000032 (__SILICON_REVISION__ < 1)
/* PPI Data Underflow on First Word Not Reported in Certain Modes */
#define ANOMALY_16000033 (1)
/* CNV1 Red Pixel Substitution feature not functional in the PVP */
#define ANOMALY_16000034 (__SILICON_REVISION__ < 1)
/* IPF0 Output Port Color Separation feature not functional */
#define ANOMALY_16000035 (__SILICON_REVISION__ < 1)
/* Spurious USB Wake From Hibernate May Occur When USB_VBUS is Low */
#define ANOMALY_16000036 (__SILICON_REVISION__ < 1)
/* Core RAISE 2 Instruction Not Latched When Executed at Priority Level 0, 1, or 2 */
#define ANOMALY_16000037 (__SILICON_REVISION__ < 1)
/* Spurious Unhandled NMI or L1 Memory Parity Error Interrupt May Occur Upon Entering the NMI ISR */
#define ANOMALY_16000038 (__SILICON_REVISION__ < 1)
/* CGU_STAT.PLOCKERR Bit May be Unreliable */
#define ANOMALY_16000039 (1)
/* JTAG Emulator Reads of SDU_IDCODE Alter Register Contents */
#define ANOMALY_16000040 (1)
/* IFLUSH Instruction Causes Parity Error When Parity Is Enabled */
#define ANOMALY_16000041 (1)
/* Instruction Cache Failure When Parity Is Enabled */
#define ANOMALY_16000042 (__SILICON_REVISION__ == 1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000158 (0)
#define ANOMALY_05000189 (0)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
#define ANOMALY_05000244 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0)
#define ANOMALY_05000281 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000363 (0)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000450 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000480 (0)
#define ANOMALY_05000481 (1)
/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
#define ANOMALY_05000491 ANOMALY_16000008
#define ANOMALY_05000477 ANOMALY_16000009
#define ANOMALY_05000443 ANOMALY_16000010
#define ANOMALY_05000461 ANOMALY_16000011
#define ANOMALY_05000426 ANOMALY_16000012
#define ANOMALY_05000310 ANOMALY_16000013
#define ANOMALY_05000245 ANOMALY_16000014
#define ANOMALY_05000074 ANOMALY_16000015
#define ANOMALY_05000416 ANOMALY_16000017
#endif

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/*
* Copyright 2011 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __MACH_BF609_H__
#define __MACH_BF609_H__
#define OFFSET_(x) ((x) & 0x0000FFFF)
/*some misc defines*/
#define IMASK_IVG15 0x8000
#define IMASK_IVG14 0x4000
#define IMASK_IVG13 0x2000
#define IMASK_IVG12 0x1000
#define IMASK_IVG11 0x0800
#define IMASK_IVG10 0x0400
#define IMASK_IVG9 0x0200
#define IMASK_IVG8 0x0100
#define IMASK_IVG7 0x0080
#define IMASK_IVGTMR 0x0040
#define IMASK_IVGHW 0x0020
/***************************/
#define BFIN_DSUBBANKS 4
#define BFIN_DWAYS 2
#define BFIN_DLINES 64
#define BFIN_ISUBBANKS 4
#define BFIN_IWAYS 4
#define BFIN_ILINES 32
#define WAY0_L 0x1
#define WAY1_L 0x2
#define WAY01_L 0x3
#define WAY2_L 0x4
#define WAY02_L 0x5
#define WAY12_L 0x6
#define WAY012_L 0x7
#define WAY3_L 0x8
#define WAY03_L 0x9
#define WAY13_L 0xA
#define WAY013_L 0xB
#define WAY32_L 0xC
#define WAY320_L 0xD
#define WAY321_L 0xE
#define WAYALL_L 0xF
#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
/********************************* EBIU Settings ************************************/
#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
#ifdef CONFIG_C_AMBEN_ALL
#define V_AMBEN AMBEN_ALL
#endif
#ifdef CONFIG_C_AMBEN
#define V_AMBEN 0x0
#endif
#ifdef CONFIG_C_AMBEN_B0
#define V_AMBEN AMBEN_B0
#endif
#ifdef CONFIG_C_AMBEN_B0_B1
#define V_AMBEN AMBEN_B0_B1
#endif
#ifdef CONFIG_C_AMBEN_B0_B1_B2
#define V_AMBEN AMBEN_B0_B1_B2
#endif
#ifdef CONFIG_C_AMCKEN
#define V_AMCKEN AMCKEN
#else
#define V_AMCKEN 0x0
#endif
#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
#if defined(CONFIG_BF609)
# define CPU "BF609"
# define CPUID 0x27fe /* temperary fake value */
#endif
#ifndef CPU
#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
#endif
#endif /* __MACH_BF609_H__ */

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/*
* mach/bfin_serial.h - Blackfin UART/Serial definitions
*
* Copyright 2011 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __BFIN_MACH_SERIAL_H__
#define __BFIN_MACH_SERIAL_H__
#define BFIN_UART_NR_PORTS 2
#define BFIN_UART_TX_FIFO_SIZE 8
#define BFIN_UART_BF60X_STYLE
#endif

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/*
* Copyright 2011 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_BLACKFIN_H_
#define _MACH_BLACKFIN_H_
#include "bf609.h"
#include "anomaly.h"
#include <asm/def_LPBlackfin.h>
#ifdef CONFIG_BF609
# include "defBF609.h"
#endif
#ifndef __ASSEMBLY__
# include <asm/cdef_LPBlackfin.h>
# ifdef CONFIG_BF609
# include "cdefBF609.h"
# endif
#endif
#endif

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/*
* Copyright 2011 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _CDEF_BF609_H
#define _CDEF_BF609_H
/* include cdefBF60x_base.h for the set of #defines that are common to all ADSP-BF60x bfin_read_()rocessors */
#include "cdefBF60x_base.h"
/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
#endif /* _CDEF_BF609_H */

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/*
* Copyright 2011 Analog Devices Inc.
*
* Licensed under the Clear BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF609_H
#define _DEF_BF609_H
/* Include defBF60x_base.h for the set of #defines that are common to all ADSP-BF60x processors */
#include "defBF60x_base.h"
/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
/* =========================
PIXC Registers
========================= */
/* =========================
PIXC0
========================= */
#define PIXC0_CTL 0xFFC19000 /* PIXC0 Control Register */
#define PIXC0_PPL 0xFFC19004 /* PIXC0 Pixels Per Line Register */
#define PIXC0_LPF 0xFFC19008 /* PIXC0 Line Per Frame Register */
#define PIXC0_HSTART_A 0xFFC1900C /* PIXC0 Overlay A Horizontal Start Register */
#define PIXC0_HEND_A 0xFFC19010 /* PIXC0 Overlay A Horizontal End Register */
#define PIXC0_VSTART_A 0xFFC19014 /* PIXC0 Overlay A Vertical Start Register */
#define PIXC0_VEND_A 0xFFC19018 /* PIXC0 Overlay A Vertical End Register */
#define PIXC0_TRANSP_A 0xFFC1901C /* PIXC0 Overlay A Transparency Ratio Register */
#define PIXC0_HSTART_B 0xFFC19020 /* PIXC0 Overlay B Horizontal Start Register */
#define PIXC0_HEND_B 0xFFC19024 /* PIXC0 Overlay B Horizontal End Register */
#define PIXC0_VSTART_B 0xFFC19028 /* PIXC0 Overlay B Vertical Start Register */
#define PIXC0_VEND_B 0xFFC1902C /* PIXC0 Overlay B Vertical End Register */
#define PIXC0_TRANSP_B 0xFFC19030 /* PIXC0 Overlay B Transparency Ratio Register */
#define PIXC0_IRQSTAT 0xFFC1903C /* PIXC0 Interrupt Status Register */
#define PIXC0_CONRY 0xFFC19040 /* PIXC0 RY Conversion Component Register */
#define PIXC0_CONGU 0xFFC19044 /* PIXC0 GU Conversion Component Register */
#define PIXC0_CONBV 0xFFC19048 /* PIXC0 BV Conversion Component Register */
#define PIXC0_CCBIAS 0xFFC1904C /* PIXC0 Conversion Bias Register */
#define PIXC0_TC 0xFFC19050 /* PIXC0 Transparency Register */
#define PIXC0_REVID 0xFFC19054 /* PIXC0 PIXC Revision Id */
/* =========================
PVP Registers
========================= */
/* =========================
PVP0
========================= */
#define PVP0_REVID 0xFFC1A000 /* PVP0 Revision ID */
#define PVP0_CTL 0xFFC1A004 /* PVP0 Control */
#define PVP0_IMSK0 0xFFC1A008 /* PVP0 INTn interrupt line masks */
#define PVP0_IMSK1 0xFFC1A00C /* PVP0 INTn interrupt line masks */
#define PVP0_STAT 0xFFC1A010 /* PVP0 Status */
#define PVP0_ILAT 0xFFC1A014 /* PVP0 Latched status */
#define PVP0_IREQ0 0xFFC1A018 /* PVP0 INT0 masked latched status */
#define PVP0_IREQ1 0xFFC1A01C /* PVP0 INT0 masked latched status */
#define PVP0_OPF0_CFG 0xFFC1A020 /* PVP0 Config */
#define PVP0_OPF1_CFG 0xFFC1A040 /* PVP0 Config */
#define PVP0_OPF2_CFG 0xFFC1A060 /* PVP0 Config */
#define PVP0_OPF0_CTL 0xFFC1A024 /* PVP0 Control */
#define PVP0_OPF1_CTL 0xFFC1A044 /* PVP0 Control */
#define PVP0_OPF2_CTL 0xFFC1A064 /* PVP0 Control */
#define PVP0_OPF3_CFG 0xFFC1A080 /* PVP0 Config */
#define PVP0_OPF3_CTL 0xFFC1A084 /* PVP0 Control */
#define PVP0_PEC_CFG 0xFFC1A0A0 /* PVP0 Config */
#define PVP0_PEC_CTL 0xFFC1A0A4 /* PVP0 Control */
#define PVP0_PEC_D1TH0 0xFFC1A0A8 /* PVP0 Lower Hysteresis Threshold */
#define PVP0_PEC_D1TH1 0xFFC1A0AC /* PVP0 Upper Hysteresis Threshold */
#define PVP0_PEC_D2TH0 0xFFC1A0B0 /* PVP0 Weak Zero Crossing Threshold */
#define PVP0_PEC_D2TH1 0xFFC1A0B4 /* PVP0 Strong Zero Crossing Threshold */
#define PVP0_IIM0_CFG 0xFFC1A0C0 /* PVP0 Config */
#define PVP0_IIM1_CFG 0xFFC1A0E0 /* PVP0 Config */
#define PVP0_IIM0_CTL 0xFFC1A0C4 /* PVP0 Control */
#define PVP0_IIM1_CTL 0xFFC1A0E4 /* PVP0 Control */
#define PVP0_IIM0_SCALE 0xFFC1A0C8 /* PVP0 Scaler Values */
#define PVP0_IIM1_SCALE 0xFFC1A0E8 /* PVP0 Scaler Values */
#define PVP0_IIM0_SOVF_STAT 0xFFC1A0CC /* PVP0 Signed Overflow Status */
#define PVP0_IIM1_SOVF_STAT 0xFFC1A0EC /* PVP0 Signed Overflow Status */
#define PVP0_IIM0_UOVF_STAT 0xFFC1A0D0 /* PVP0 Unsigned Overflow Status */
#define PVP0_IIM1_UOVF_STAT 0xFFC1A0F0 /* PVP0 Unsigned Overflow Status */
#define PVP0_ACU_CFG 0xFFC1A100 /* PVP0 ACU Configuration Register */
#define PVP0_ACU_CTL 0xFFC1A104 /* PVP0 ACU Control Register */
#define PVP0_ACU_OFFSET 0xFFC1A108 /* PVP0 SUM constant register */
#define PVP0_ACU_FACTOR 0xFFC1A10C /* PVP0 PROD constant register */
#define PVP0_ACU_SHIFT 0xFFC1A110 /* PVP0 Shift constant register */
#define PVP0_ACU_MIN 0xFFC1A114 /* PVP0 Lower saturation threshold set to MIN */
#define PVP0_ACU_MAX 0xFFC1A118 /* PVP0 Upper saturation threshold set to MAX */
#define PVP0_UDS_CFG 0xFFC1A140 /* PVP0 UDS Configuration Register */
#define PVP0_UDS_CTL 0xFFC1A144 /* PVP0 UDS Control Register */
#define PVP0_UDS_OHCNT 0xFFC1A148 /* PVP0 UDS Output H Dimension */
#define PVP0_UDS_OVCNT 0xFFC1A14C /* PVP0 UDS Output V Dimension */
#define PVP0_UDS_HAVG 0xFFC1A150 /* PVP0 UDS H Taps */
#define PVP0_UDS_VAVG 0xFFC1A154 /* PVP0 UDS V Taps */
#define PVP0_IPF0_CFG 0xFFC1A180 /* PVP0 Configuration */
#define PVP0_IPF0_PIPECTL 0xFFC1A184 /* PVP0 Pipe Control */
#define PVP0_IPF1_PIPECTL 0xFFC1A1C4 /* PVP0 Pipe Control */
#define PVP0_IPF0_CTL 0xFFC1A188 /* PVP0 Control */
#define PVP0_IPF1_CTL 0xFFC1A1C8 /* PVP0 Control */
#define PVP0_IPF0_TAG 0xFFC1A18C /* PVP0 TAG Value */
#define PVP0_IPF1_TAG 0xFFC1A1CC /* PVP0 TAG Value */
#define PVP0_IPF0_FCNT 0xFFC1A190 /* PVP0 Frame Count */
#define PVP0_IPF1_FCNT 0xFFC1A1D0 /* PVP0 Frame Count */
#define PVP0_IPF0_HCNT 0xFFC1A194 /* PVP0 Horizontal Count */
#define PVP0_IPF1_HCNT 0xFFC1A1D4 /* PVP0 Horizontal Count */
#define PVP0_IPF0_VCNT 0xFFC1A198 /* PVP0 Vertical Count */
#define PVP0_IPF1_VCNT 0xFFC1A1D8 /* PVP0 Vertical Count */
#define PVP0_IPF0_HPOS 0xFFC1A19C /* PVP0 Horizontal Position */
#define PVP0_IPF0_VPOS 0xFFC1A1A0 /* PVP0 Vertical Position */
#define PVP0_IPF0_TAG_STAT 0xFFC1A1A4 /* PVP0 TAG Status */
#define PVP0_IPF1_TAG_STAT 0xFFC1A1E4 /* PVP0 TAG Status */
#define PVP0_IPF1_CFG 0xFFC1A1C0 /* PVP0 Configuration */
#define PVP0_CNV0_CFG 0xFFC1A200 /* PVP0 Configuration */
#define PVP0_CNV1_CFG 0xFFC1A280 /* PVP0 Configuration */
#define PVP0_CNV2_CFG 0xFFC1A300 /* PVP0 Configuration */
#define PVP0_CNV3_CFG 0xFFC1A380 /* PVP0 Configuration */
#define PVP0_CNV0_CTL 0xFFC1A204 /* PVP0 Control */
#define PVP0_CNV1_CTL 0xFFC1A284 /* PVP0 Control */
#define PVP0_CNV2_CTL 0xFFC1A304 /* PVP0 Control */
#define PVP0_CNV3_CTL 0xFFC1A384 /* PVP0 Control */
#define PVP0_CNV0_C00C01 0xFFC1A208 /* PVP0 Coefficients 0, 0 and 0, 1 */
#define PVP0_CNV1_C00C01 0xFFC1A288 /* PVP0 Coefficients 0, 0 and 0, 1 */
#define PVP0_CNV2_C00C01 0xFFC1A308 /* PVP0 Coefficients 0, 0 and 0, 1 */
#define PVP0_CNV3_C00C01 0xFFC1A388 /* PVP0 Coefficients 0, 0 and 0, 1 */
#define PVP0_CNV0_C02C03 0xFFC1A20C /* PVP0 Coefficients 0, 2 and 0, 3 */
#define PVP0_CNV1_C02C03 0xFFC1A28C /* PVP0 Coefficients 0, 2 and 0, 3 */
#define PVP0_CNV2_C02C03 0xFFC1A30C /* PVP0 Coefficients 0, 2 and 0, 3 */
#define PVP0_CNV3_C02C03 0xFFC1A38C /* PVP0 Coefficients 0, 2 and 0, 3 */
#define PVP0_CNV0_C04 0xFFC1A210 /* PVP0 Coefficient 0, 4 */
#define PVP0_CNV1_C04 0xFFC1A290 /* PVP0 Coefficient 0, 4 */
#define PVP0_CNV2_C04 0xFFC1A310 /* PVP0 Coefficient 0, 4 */
#define PVP0_CNV3_C04 0xFFC1A390 /* PVP0 Coefficient 0, 4 */
#define PVP0_CNV0_C10C11 0xFFC1A214 /* PVP0 Coefficients 1, 0 and 1, 1 */
#define PVP0_CNV1_C10C11 0xFFC1A294 /* PVP0 Coefficients 1, 0 and 1, 1 */
#define PVP0_CNV2_C10C11 0xFFC1A314 /* PVP0 Coefficients 1, 0 and 1, 1 */
#define PVP0_CNV3_C10C11 0xFFC1A394 /* PVP0 Coefficients 1, 0 and 1, 1 */
#define PVP0_CNV0_C12C13 0xFFC1A218 /* PVP0 Coefficients 1, 2 and 1, 3 */
#define PVP0_CNV1_C12C13 0xFFC1A298 /* PVP0 Coefficients 1, 2 and 1, 3 */
#define PVP0_CNV2_C12C13 0xFFC1A318 /* PVP0 Coefficients 1, 2 and 1, 3 */
#define PVP0_CNV3_C12C13 0xFFC1A398 /* PVP0 Coefficients 1, 2 and 1, 3 */
#define PVP0_CNV0_C14 0xFFC1A21C /* PVP0 Coefficient 1, 4 */
#define PVP0_CNV1_C14 0xFFC1A29C /* PVP0 Coefficient 1, 4 */
#define PVP0_CNV2_C14 0xFFC1A31C /* PVP0 Coefficient 1, 4 */
#define PVP0_CNV3_C14 0xFFC1A39C /* PVP0 Coefficient 1, 4 */
#define PVP0_CNV0_C20C21 0xFFC1A220 /* PVP0 Coefficients 2, 0 and 2, 1 */
#define PVP0_CNV1_C20C21 0xFFC1A2A0 /* PVP0 Coefficients 2, 0 and 2, 1 */
#define PVP0_CNV2_C20C21 0xFFC1A320 /* PVP0 Coefficients 2, 0 and 2, 1 */
#define PVP0_CNV3_C20C21 0xFFC1A3A0 /* PVP0 Coefficients 2, 0 and 2, 1 */
#define PVP0_CNV0_C22C23 0xFFC1A224 /* PVP0 Coefficients 2, 2 and 2, 3 */
#define PVP0_CNV1_C22C23 0xFFC1A2A4 /* PVP0 Coefficients 2, 2 and 2, 3 */
#define PVP0_CNV2_C22C23 0xFFC1A324 /* PVP0 Coefficients 2, 2 and 2, 3 */
#define PVP0_CNV3_C22C23 0xFFC1A3A4 /* PVP0 Coefficients 2, 2 and 2, 3 */
#define PVP0_CNV0_C24 0xFFC1A228 /* PVP0 Coefficient 2,4 */
#define PVP0_CNV1_C24 0xFFC1A2A8 /* PVP0 Coefficient 2,4 */
#define PVP0_CNV2_C24 0xFFC1A328 /* PVP0 Coefficient 2,4 */
#define PVP0_CNV3_C24 0xFFC1A3A8 /* PVP0 Coefficient 2,4 */
#define PVP0_CNV0_C30C31 0xFFC1A22C /* PVP0 Coefficients 3, 0 and 3, 1 */
#define PVP0_CNV1_C30C31 0xFFC1A2AC /* PVP0 Coefficients 3, 0 and 3, 1 */
#define PVP0_CNV2_C30C31 0xFFC1A32C /* PVP0 Coefficients 3, 0 and 3, 1 */
#define PVP0_CNV3_C30C31 0xFFC1A3AC /* PVP0 Coefficients 3, 0 and 3, 1 */
#define PVP0_CNV0_C32C33 0xFFC1A230 /* PVP0 Coefficients 3, 2 and 3, 3 */
#define PVP0_CNV1_C32C33 0xFFC1A2B0 /* PVP0 Coefficients 3, 2 and 3, 3 */
#define PVP0_CNV2_C32C33 0xFFC1A330 /* PVP0 Coefficients 3, 2 and 3, 3 */
#define PVP0_CNV3_C32C33 0xFFC1A3B0 /* PVP0 Coefficients 3, 2 and 3, 3 */
#define PVP0_CNV0_C34 0xFFC1A234 /* PVP0 Coefficient 3, 4 */
#define PVP0_CNV1_C34 0xFFC1A2B4 /* PVP0 Coefficient 3, 4 */
#define PVP0_CNV2_C34 0xFFC1A334 /* PVP0 Coefficient 3, 4 */
#define PVP0_CNV3_C34 0xFFC1A3B4 /* PVP0 Coefficient 3, 4 */
#define PVP0_CNV0_C40C41 0xFFC1A238 /* PVP0 Coefficients 4, 0 and 4, 1 */
#define PVP0_CNV1_C40C41 0xFFC1A2B8 /* PVP0 Coefficients 4, 0 and 4, 1 */
#define PVP0_CNV2_C40C41 0xFFC1A338 /* PVP0 Coefficients 4, 0 and 4, 1 */
#define PVP0_CNV3_C40C41 0xFFC1A3B8 /* PVP0 Coefficients 4, 0 and 4, 1 */
#define PVP0_CNV0_C42C43 0xFFC1A23C /* PVP0 Coefficients 4, 2 and 4, 3 */
#define PVP0_CNV1_C42C43 0xFFC1A2BC /* PVP0 Coefficients 4, 2 and 4, 3 */
#define PVP0_CNV2_C42C43 0xFFC1A33C /* PVP0 Coefficients 4, 2 and 4, 3 */
#define PVP0_CNV3_C42C43 0xFFC1A3BC /* PVP0 Coefficients 4, 2 and 4, 3 */
#define PVP0_CNV0_C44 0xFFC1A240 /* PVP0 Coefficient 4, 4 */
#define PVP0_CNV1_C44 0xFFC1A2C0 /* PVP0 Coefficient 4, 4 */
#define PVP0_CNV2_C44 0xFFC1A340 /* PVP0 Coefficient 4, 4 */
#define PVP0_CNV3_C44 0xFFC1A3C0 /* PVP0 Coefficient 4, 4 */
#define PVP0_CNV0_SCALE 0xFFC1A244 /* PVP0 Scaling factor */
#define PVP0_CNV1_SCALE 0xFFC1A2C4 /* PVP0 Scaling factor */
#define PVP0_CNV2_SCALE 0xFFC1A344 /* PVP0 Scaling factor */
#define PVP0_CNV3_SCALE 0xFFC1A3C4 /* PVP0 Scaling factor */
#define PVP0_THC0_CFG 0xFFC1A400 /* PVP0 Configuration */
#define PVP0_THC1_CFG 0xFFC1A500 /* PVP0 Configuration */
#define PVP0_THC0_CTL 0xFFC1A404 /* PVP0 Control */
#define PVP0_THC1_CTL 0xFFC1A504 /* PVP0 Control */
#define PVP0_THC0_HFCNT 0xFFC1A408 /* PVP0 Number of frames */
#define PVP0_THC1_HFCNT 0xFFC1A508 /* PVP0 Number of frames */
#define PVP0_THC0_RMAXREP 0xFFC1A40C /* PVP0 Maximum number of RLE reports */
#define PVP0_THC1_RMAXREP 0xFFC1A50C /* PVP0 Maximum number of RLE reports */
#define PVP0_THC0_CMINVAL 0xFFC1A410 /* PVP0 Min clip value */
#define PVP0_THC1_CMINVAL 0xFFC1A510 /* PVP0 Min clip value */
#define PVP0_THC0_CMINTH 0xFFC1A414 /* PVP0 Clip Min Threshold */
#define PVP0_THC1_CMINTH 0xFFC1A514 /* PVP0 Clip Min Threshold */
#define PVP0_THC0_CMAXTH 0xFFC1A418 /* PVP0 Clip Max Threshold */
#define PVP0_THC1_CMAXTH 0xFFC1A518 /* PVP0 Clip Max Threshold */
#define PVP0_THC0_CMAXVAL 0xFFC1A41C /* PVP0 Max clip value */
#define PVP0_THC1_CMAXVAL 0xFFC1A51C /* PVP0 Max clip value */
#define PVP0_THC0_TH0 0xFFC1A420 /* PVP0 Threshold Value */
#define PVP0_THC1_TH0 0xFFC1A520 /* PVP0 Threshold Value */
#define PVP0_THC0_TH1 0xFFC1A424 /* PVP0 Threshold Value */
#define PVP0_THC1_TH1 0xFFC1A524 /* PVP0 Threshold Value */
#define PVP0_THC0_TH2 0xFFC1A428 /* PVP0 Threshold Value */
#define PVP0_THC1_TH2 0xFFC1A528 /* PVP0 Threshold Value */
#define PVP0_THC0_TH3 0xFFC1A42C /* PVP0 Threshold Value */
#define PVP0_THC1_TH3 0xFFC1A52C /* PVP0 Threshold Value */
#define PVP0_THC0_TH4 0xFFC1A430 /* PVP0 Threshold Value */
#define PVP0_THC1_TH4 0xFFC1A530 /* PVP0 Threshold Value */
#define PVP0_THC0_TH5 0xFFC1A434 /* PVP0 Threshold Value */
#define PVP0_THC1_TH5 0xFFC1A534 /* PVP0 Threshold Value */
#define PVP0_THC0_TH6 0xFFC1A438 /* PVP0 Threshold Value */
#define PVP0_THC1_TH6 0xFFC1A538 /* PVP0 Threshold Value */
#define PVP0_THC0_TH7 0xFFC1A43C /* PVP0 Threshold Value */
#define PVP0_THC1_TH7 0xFFC1A53C /* PVP0 Threshold Value */
#define PVP0_THC0_TH8 0xFFC1A440 /* PVP0 Threshold Value */
#define PVP0_THC1_TH8 0xFFC1A540 /* PVP0 Threshold Value */
#define PVP0_THC0_TH9 0xFFC1A444 /* PVP0 Threshold Value */
#define PVP0_THC1_TH9 0xFFC1A544 /* PVP0 Threshold Value */
#define PVP0_THC0_TH10 0xFFC1A448 /* PVP0 Threshold Value */
#define PVP0_THC1_TH10 0xFFC1A548 /* PVP0 Threshold Value */
#define PVP0_THC0_TH11 0xFFC1A44C /* PVP0 Threshold Value */
#define PVP0_THC1_TH11 0xFFC1A54C /* PVP0 Threshold Value */
#define PVP0_THC0_TH12 0xFFC1A450 /* PVP0 Threshold Value */
#define PVP0_THC1_TH12 0xFFC1A550 /* PVP0 Threshold Value */
#define PVP0_THC0_TH13 0xFFC1A454 /* PVP0 Threshold Value */
#define PVP0_THC1_TH13 0xFFC1A554 /* PVP0 Threshold Value */
#define PVP0_THC0_TH14 0xFFC1A458 /* PVP0 Threshold Value */
#define PVP0_THC1_TH14 0xFFC1A558 /* PVP0 Threshold Value */
#define PVP0_THC0_TH15 0xFFC1A45C /* PVP0 Threshold Value */
#define PVP0_THC1_TH15 0xFFC1A55C /* PVP0 Threshold Value */
#define PVP0_THC0_HHPOS 0xFFC1A460 /* PVP0 Window start X-coordinate */
#define PVP0_THC1_HHPOS 0xFFC1A560 /* PVP0 Window start X-coordinate */
#define PVP0_THC0_HVPOS 0xFFC1A464 /* PVP0 Window start Y-coordinate */
#define PVP0_THC1_HVPOS 0xFFC1A564 /* PVP0 Window start Y-coordinate */
#define PVP0_THC0_HHCNT 0xFFC1A468 /* PVP0 Window width in X dimension */
#define PVP0_THC1_HHCNT 0xFFC1A568 /* PVP0 Window width in X dimension */
#define PVP0_THC0_HVCNT 0xFFC1A46C /* PVP0 Window width in Y dimension */
#define PVP0_THC1_HVCNT 0xFFC1A56C /* PVP0 Window width in Y dimension */
#define PVP0_THC0_RHPOS 0xFFC1A470 /* PVP0 Window start X-coordinate */
#define PVP0_THC1_RHPOS 0xFFC1A570 /* PVP0 Window start X-coordinate */
#define PVP0_THC0_RVPOS 0xFFC1A474 /* PVP0 Window start Y-coordinate */
#define PVP0_THC1_RVPOS 0xFFC1A574 /* PVP0 Window start Y-coordinate */
#define PVP0_THC0_RHCNT 0xFFC1A478 /* PVP0 Window width in X dimension */
#define PVP0_THC1_RHCNT 0xFFC1A578 /* PVP0 Window width in X dimension */
#define PVP0_THC0_RVCNT 0xFFC1A47C /* PVP0 Window width in Y dimension */
#define PVP0_THC1_RVCNT 0xFFC1A57C /* PVP0 Window width in Y dimension */
#define PVP0_THC0_HFCNT_STAT 0xFFC1A480 /* PVP0 Current Frame counter */
#define PVP0_THC1_HFCNT_STAT 0xFFC1A580 /* PVP0 Current Frame counter */
#define PVP0_THC0_HCNT0_STAT 0xFFC1A484 /* PVP0 Histogram counter value */
#define PVP0_THC1_HCNT0_STAT 0xFFC1A584 /* PVP0 Histogram counter value */
#define PVP0_THC0_HCNT1_STAT 0xFFC1A488 /* PVP0 Histogram counter value */
#define PVP0_THC1_HCNT1_STAT 0xFFC1A588 /* PVP0 Histogram counter value */
#define PVP0_THC0_HCNT2_STAT 0xFFC1A48C /* PVP0 Histogram counter value */
#define PVP0_THC1_HCNT2_STAT 0xFFC1A58C /* PVP0 Histogram counter value */
#define PVP0_THC0_HCNT3_STAT 0xFFC1A490 /* PVP0 Histogram counter value */
#define PVP0_THC1_HCNT3_STAT 0xFFC1A590 /* PVP0 Histogram counter value */
#define PVP0_THC0_HCNT4_STAT 0xFFC1A494 /* PVP0 Histogram counter value */
#define PVP0_THC1_HCNT4_STAT 0xFFC1A594 /* PVP0 Histogram counter value */
#define PVP0_THC0_HCNT5_STAT 0xFFC1A498 /* PVP0 Histogram counter value */
#define PVP0_THC1_HCNT5_STAT 0xFFC1A598 /* PVP0 Histogram counter value */
#define PVP0_THC0_HCNT6_STAT 0xFFC1A49C /* PVP0 Histogram counter value */
#define PVP0_THC1_HCNT6_STAT 0xFFC1A59C /* PVP0 Histogram counter value */
#define PVP0_THC0_HCNT7_STAT 0xFFC1A4A0 /* PVP0 Histogram counter value */
#define PVP0_THC1_HCNT7_STAT 0xFFC1A5A0 /* PVP0 Histogram counter value */
#define PVP0_THC0_HCNT8_STAT 0xFFC1A4A4 /* PVP0 Histogram counter value */
#define PVP0_THC1_HCNT8_STAT 0xFFC1A5A4 /* PVP0 Histogram counter value */
#define PVP0_THC0_HCNT9_STAT 0xFFC1A4A8 /* PVP0 Histogram counter value */
#define PVP0_THC1_HCNT9_STAT 0xFFC1A5A8 /* PVP0 Histogram counter value */
#define PVP0_THC0_HCNT10_STAT 0xFFC1A4AC /* PVP0 Histogram counter value */
#define PVP0_THC1_HCNT10_STAT 0xFFC1A5AC /* PVP0 Histogram counter value */
#define PVP0_THC0_HCNT11_STAT 0xFFC1A4B0 /* PVP0 Histogram counter value */
#define PVP0_THC1_HCNT11_STAT 0xFFC1A5B0 /* PVP0 Histogram counter value */
#define PVP0_THC0_HCNT12_STAT 0xFFC1A4B4 /* PVP0 Histogram counter value */
#define PVP0_THC1_HCNT12_STAT 0xFFC1A5B4 /* PVP0 Histogram counter value */
#define PVP0_THC0_HCNT13_STAT 0xFFC1A4B8 /* PVP0 Histogram counter value */
#define PVP0_THC1_HCNT13_STAT 0xFFC1A5B8 /* PVP0 Histogram counter value */
#define PVP0_THC0_HCNT14_STAT 0xFFC1A4BC /* PVP0 Histogram counter value */
#define PVP0_THC1_HCNT14_STAT 0xFFC1A5BC /* PVP0 Histogram counter value */
#define PVP0_THC0_HCNT15_STAT 0xFFC1A4C0 /* PVP0 Histogram counter value */
#define PVP0_THC1_HCNT15_STAT 0xFFC1A5C0 /* PVP0 Histogram counter value */
#define PVP0_THC0_RREP_STAT 0xFFC1A4C4 /* PVP0 Number of RLE Reports */
#define PVP0_THC1_RREP_STAT 0xFFC1A5C4 /* PVP0 Number of RLE Reports */
#define PVP0_PMA_CFG 0xFFC1A600 /* PVP0 PMA Configuration Register */
#endif /* _DEF_BF609_H */

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arch/blackfin/mach-bf609/include/mach/dma.h Normal file
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/* mach/dma.h - arch-specific DMA defines
*
* Copyright 2011 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_DMA_H_
#define _MACH_DMA_H_
#define CH_SPORT0_TX 0
#define CH_SPORT0_RX 1
#define CH_SPORT1_TX 2
#define CH_SPORT1_RX 3
#define CH_SPORT2_TX 4
#define CH_SPORT2_RX 5
#define CH_SPI0_TX 6
#define CH_SPI0_RX 7
#define CH_SPI1_TX 8
#define CH_SPI1_RX 9
#define CH_RSI 10
#define CH_SDU 11
#define CH_LP0 13
#define CH_LP1 14
#define CH_LP2 15
#define CH_LP3 16
#define CH_UART0_TX 17
#define CH_UART0_RX 18
#define CH_UART1_TX 19
#define CH_UART1_RX 20
#define CH_MEM_STREAM0_SRC_CRC0 21
#define CH_MEM_STREAM0_SRC CH_MEM_STREAM0_SRC_CRC0
#define CH_MEM_STREAM0_DEST_CRC0 22
#define CH_MEM_STREAM0_DEST CH_MEM_STREAM0_DEST_CRC0
#define CH_MEM_STREAM1_SRC_CRC1 23
#define CH_MEM_STREAM1_SRC CH_MEM_STREAM1_SRC_CRC1
#define CH_MEM_STREAM1_DEST_CRC1 24
#define CH_MEM_STREAM1_DEST CH_MEM_STREAM1_DEST_CRC1
#define CH_MEM_STREAM2_SRC 25
#define CH_MEM_STREAM2_DEST 26
#define CH_MEM_STREAM3_SRC 27
#define CH_MEM_STREAM3_DEST 28
#define CH_EPPI0_CH0 29
#define CH_EPPI0_CH1 30
#define CH_EPPI1_CH0 31
#define CH_EPPI1_CH1 32
#define CH_EPPI2_CH0 33
#define CH_EPPI2_CH1 34
#define CH_PIXC_CH0 35
#define CH_PIXC_CH1 36
#define CH_PIXC_CH2 37
#define CH_PVP_CPDOB 38
#define CH_PVP_CPDOC 39
#define CH_PVP_CPSTAT 40
#define CH_PVP_CPCI 41
#define CH_PVP_MPDO 42
#define CH_PVP_MPDI 43
#define CH_PVP_MPSTAT 44
#define CH_PVP_MPCI 45
#define CH_PVP_CPDOA 46
#define MAX_DMA_CHANNELS 47
#define MAX_DMA_SUSPEND_CHANNELS 0
#define DMA_MMR_SIZE_32
#define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_SRC_CRC0_CONFIG
#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_SRC_CRC0_CONFIG
#define bfin_read_MDMA_S0_IRQ_STATUS bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS
#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS
#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_SRC_CRC0_START_ADDR
#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_SRC_CRC0_X_COUNT
#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_SRC_CRC0_X_MODIFY
#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_SRC_CRC0_Y_COUNT
#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_SRC_CRC0_Y_MODIFY
#define bfin_read_MDMA_D0_CONFIG bfin_read_MDMA0_DEST_CRC0_CONFIG
#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_DEST_CRC0_CONFIG
#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS
#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS
#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_DEST_CRC0_START_ADDR
#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_DEST_CRC0_X_COUNT
#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_DEST_CRC0_X_MODIFY
#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_DEST_CRC0_Y_COUNT
#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_DEST_CRC0_Y_MODIFY
#define bfin_read_MDMA_S1_CONFIG bfin_read_MDMA1_SRC_CRC1_CONFIG
#define bfin_write_MDMA_S1_CONFIG bfin_write_MDMA1_SRC_CRC1_CONFIG
#define bfin_read_MDMA_D1_CONFIG bfin_read_MDMA1_DEST_CRC1_CONFIG
#define bfin_write_MDMA_D1_CONFIG bfin_write_MDMA1_DEST_CRC1_CONFIG
#define bfin_read_MDMA_D1_IRQ_STATUS bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS
#define bfin_write_MDMA_D1_IRQ_STATUS bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS
#define bfin_read_MDMA_S3_CONFIG bfin_read_MDMA3_SRC_CONFIG
#define bfin_write_MDMA_S3_CONFIG bfin_write_MDMA3_SRC_CONFIG
#define bfin_read_MDMA_S3_IRQ_STATUS bfin_read_MDMA3_SRC_IRQ_STATUS
#define bfin_write_MDMA_S3_IRQ_STATUS bfin_write_MDMA3_SRC_IRQ_STATUS
#define bfin_write_MDMA_S3_START_ADDR bfin_write_MDMA3_SRC_START_ADDR
#define bfin_write_MDMA_S3_X_COUNT bfin_write_MDMA3_SRC_X_COUNT
#define bfin_write_MDMA_S3_X_MODIFY bfin_write_MDMA3_SRC_X_MODIFY
#define bfin_write_MDMA_S3_Y_COUNT bfin_write_MDMA3_SRC_Y_COUNT
#define bfin_write_MDMA_S3_Y_MODIFY bfin_write_MDMA3_SRC_Y_MODIFY
#define bfin_read_MDMA_D3_CONFIG bfin_read_MDMA3_DEST_CONFIG
#define bfin_write_MDMA_D3_CONFIG bfin_write_MDMA3_DEST_CONFIG
#define bfin_read_MDMA_D3_IRQ_STATUS bfin_read_MDMA3_DEST_IRQ_STATUS
#define bfin_write_MDMA_D3_IRQ_STATUS bfin_write_MDMA3_DEST_IRQ_STATUS
#define bfin_write_MDMA_D3_START_ADDR bfin_write_MDMA3_DEST_START_ADDR
#define bfin_write_MDMA_D3_X_COUNT bfin_write_MDMA3_DEST_X_COUNT
#define bfin_write_MDMA_D3_X_MODIFY bfin_write_MDMA3_DEST_X_MODIFY
#define bfin_write_MDMA_D3_Y_COUNT bfin_write_MDMA3_DEST_Y_COUNT
#define bfin_write_MDMA_D3_Y_MODIFY bfin_write_MDMA3_DEST_Y_MODIFY
#define MDMA_S0_NEXT_DESC_PTR MDMA0_SRC_CRC0_NEXT_DESC_PTR
#define MDMA_D0_NEXT_DESC_PTR MDMA0_DEST_CRC0_NEXT_DESC_PTR
#define MDMA_S1_NEXT_DESC_PTR MDMA1_SRC_CRC1_NEXT_DESC_PTR
#define MDMA_D1_NEXT_DESC_PTR MDMA1_DEST_CRC1_NEXT_DESC_PTR
#endif

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/*
* Copyright 2007-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_GPIO_H_
#define _MACH_GPIO_H_
#define MAX_BLACKFIN_GPIOS 112
#define GPIO_PA0 0
#define GPIO_PA1 1
#define GPIO_PA2 2
#define GPIO_PA3 3
#define GPIO_PA4 4
#define GPIO_PA5 5
#define GPIO_PA6 6
#define GPIO_PA7 7
#define GPIO_PA8 8
#define GPIO_PA9 9
#define GPIO_PA10 10
#define GPIO_PA11 11
#define GPIO_PA12 12
#define GPIO_PA13 13
#define GPIO_PA14 14
#define GPIO_PA15 15
#define GPIO_PB0 16
#define GPIO_PB1 17
#define GPIO_PB2 18
#define GPIO_PB3 19
#define GPIO_PB4 20
#define GPIO_PB5 21
#define GPIO_PB6 22
#define GPIO_PB7 23
#define GPIO_PB8 24
#define GPIO_PB9 25
#define GPIO_PB10 26
#define GPIO_PB11 27
#define GPIO_PB12 28
#define GPIO_PB13 29
#define GPIO_PB14 30
#define GPIO_PB15 31
#define GPIO_PC0 32
#define GPIO_PC1 33
#define GPIO_PC2 34
#define GPIO_PC3 35
#define GPIO_PC4 36
#define GPIO_PC5 37
#define GPIO_PC6 38
#define GPIO_PC7 39
#define GPIO_PC8 40
#define GPIO_PC9 41
#define GPIO_PC10 42
#define GPIO_PC11 43
#define GPIO_PC12 44
#define GPIO_PC13 45
#define GPIO_PC14 46
#define GPIO_PC15 47
#define GPIO_PD0 48
#define GPIO_PD1 49
#define GPIO_PD2 50
#define GPIO_PD3 51
#define GPIO_PD4 52
#define GPIO_PD5 53
#define GPIO_PD6 54
#define GPIO_PD7 55
#define GPIO_PD8 56
#define GPIO_PD9 57
#define GPIO_PD10 58
#define GPIO_PD11 59
#define GPIO_PD12 60
#define GPIO_PD13 61
#define GPIO_PD14 62
#define GPIO_PD15 63
#define GPIO_PE0 64
#define GPIO_PE1 65
#define GPIO_PE2 66
#define GPIO_PE3 67
#define GPIO_PE4 68
#define GPIO_PE5 69
#define GPIO_PE6 70
#define GPIO_PE7 71
#define GPIO_PE8 72
#define GPIO_PE9 73
#define GPIO_PE10 74
#define GPIO_PE11 75
#define GPIO_PE12 76
#define GPIO_PE13 77
#define GPIO_PE14 78
#define GPIO_PE15 79
#define GPIO_PF0 80
#define GPIO_PF1 81
#define GPIO_PF2 82
#define GPIO_PF3 83
#define GPIO_PF4 84
#define GPIO_PF5 85
#define GPIO_PF6 86
#define GPIO_PF7 87
#define GPIO_PF8 88
#define GPIO_PF9 89
#define GPIO_PF10 90
#define GPIO_PF11 91
#define GPIO_PF12 92
#define GPIO_PF13 93
#define GPIO_PF14 94
#define GPIO_PF15 95
#define GPIO_PG0 96
#define GPIO_PG1 97
#define GPIO_PG2 98
#define GPIO_PG3 99
#define GPIO_PG4 100
#define GPIO_PG5 101
#define GPIO_PG6 102
#define GPIO_PG7 103
#define GPIO_PG8 104
#define GPIO_PG9 105
#define GPIO_PG10 106
#define GPIO_PG11 107
#define GPIO_PG12 108
#define GPIO_PG13 109
#define GPIO_PG14 110
#define GPIO_PG15 111
#define BFIN_GPIO_PINT 1
#define NR_PINT_SYS_IRQS 6
#define NR_PINTS 112
#ifndef __ASSEMBLY__
struct gpio_port_t {
unsigned long port_fer;
unsigned long port_fer_set;
unsigned long port_fer_clear;
unsigned long data;
unsigned long data_set;
unsigned long data_clear;
unsigned long dir;
unsigned long dir_set;
unsigned long dir_clear;
unsigned long inen;
unsigned long inen_set;
unsigned long inen_clear;
unsigned long port_mux;
unsigned long toggle;
unsigned long polar;
unsigned long polar_set;
unsigned long polar_clear;
unsigned long lock;
unsigned long spare;
unsigned long revid;
};
#endif
#include <mach-common/ports-a.h>
#include <mach-common/ports-b.h>
#include <mach-common/ports-c.h>
#include <mach-common/ports-d.h>
#include <mach-common/ports-e.h>
#include <mach-common/ports-f.h>
#include <mach-common/ports-g.h>
#endif /* _MACH_GPIO_H_ */

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/*
* Copyright 2011 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _BF60x_IRQ_H_
#define _BF60x_IRQ_H_
#include <mach-common/irq.h>
#define NR_PERI_INTS (5 * 32)
#define IRQ_SEC_ERR BFIN_IRQ(0) /* SEC Error */
#define IRQ_CGU_EVT BFIN_IRQ(1) /* CGU Event */
#define IRQ_WATCH0 BFIN_IRQ(2) /* Watchdog0 Interrupt */
#define IRQ_WATCH1 BFIN_IRQ(3) /* Watchdog1 Interrupt */
#define IRQ_L2CTL0_ECC_ERR BFIN_IRQ(4) /* L2 ECC Error */
#define IRQ_L2CTL0_ECC_WARN BFIN_IRQ(5) /* L2 ECC Waring */
#define IRQ_C0_DBL_FAULT BFIN_IRQ(6) /* Core 0 Double Fault */
#define IRQ_C1_DBL_FAULT BFIN_IRQ(7) /* Core 1 Double Fault */
#define IRQ_C0_HW_ERR BFIN_IRQ(8) /* Core 0 Hardware Error */
#define IRQ_C1_HW_ERR BFIN_IRQ(9) /* Core 1 Hardware Error */
#define IRQ_C0_NMI_L1_PARITY_ERR BFIN_IRQ(10) /* Core 0 Unhandled NMI or L1 Memory Parity Error */
#define IRQ_C1_NMI_L1_PARITY_ERR BFIN_IRQ(11) /* Core 1 Unhandled NMI or L1 Memory Parity Error */
#define CORE_IRQS (IRQ_C1_NMI_L1_PARITY_ERR + 1)
#define IRQ_TIMER0 BFIN_IRQ(12) /* Timer 0 Interrupt */
#define IRQ_TIMER1 BFIN_IRQ(13) /* Timer 1 Interrupt */
#define IRQ_TIMER2 BFIN_IRQ(14) /* Timer 2 Interrupt */
#define IRQ_TIMER3 BFIN_IRQ(15) /* Timer 3 Interrupt */
#define IRQ_TIMER4 BFIN_IRQ(16) /* Timer 4 Interrupt */
#define IRQ_TIMER5 BFIN_IRQ(17) /* Timer 5 Interrupt */
#define IRQ_TIMER6 BFIN_IRQ(18) /* Timer 6 Interrupt */
#define IRQ_TIMER7 BFIN_IRQ(19) /* Timer 7 Interrupt */
#define IRQ_TIMER_STAT BFIN_IRQ(20) /* Timer Block Status */
#define IRQ_PINT0 BFIN_IRQ(21) /* PINT0 Interrupt */
#define IRQ_PINT1 BFIN_IRQ(22) /* PINT1 Interrupt */
#define IRQ_PINT2 BFIN_IRQ(23) /* PINT2 Interrupt */
#define IRQ_PINT3 BFIN_IRQ(24) /* PINT3 Interrupt */
#define IRQ_PINT4 BFIN_IRQ(25) /* PINT4 Interrupt */
#define IRQ_PINT5 BFIN_IRQ(26) /* PINT5 Interrupt */
#define IRQ_CNT BFIN_IRQ(27) /* CNT Interrupt */
#define IRQ_PWM0_TRIP BFIN_IRQ(28) /* PWM0 Trip Interrupt */
#define IRQ_PWM0_SYNC BFIN_IRQ(29) /* PWM0 Sync Interrupt */
#define IRQ_PWM1_TRIP BFIN_IRQ(30) /* PWM1 Trip Interrupt */
#define IRQ_PWM1_SYNC BFIN_IRQ(31) /* PWM1 Sync Interrupt */
#define IRQ_TWI0 BFIN_IRQ(32) /* TWI0 Interrupt */
#define IRQ_TWI1 BFIN_IRQ(33) /* TWI1 Interrupt */
#define IRQ_SOFT0 BFIN_IRQ(34) /* Software-Driven Interrupt 0 */
#define IRQ_SOFT1 BFIN_IRQ(35) /* Software-Driven Interrupt 1 */
#define IRQ_SOFT2 BFIN_IRQ(36) /* Software-Driven Interrupt 2 */
#define IRQ_SOFT3 BFIN_IRQ(37) /* Software-Driven Interrupt 3 */
#define IRQ_ACM_EVT_MISS BFIN_IRQ(38) /* ACM Event Miss */
#define IRQ_ACM_EVT_COMPLETE BFIN_IRQ(39) /* ACM Event Complete */
#define IRQ_CAN0_RX BFIN_IRQ(40) /* CAN0 Receive Interrupt */
#define IRQ_CAN0_TX BFIN_IRQ(41) /* CAN0 Transmit Interrupt */
#define IRQ_CAN0_STAT BFIN_IRQ(42) /* CAN0 Status */
#define IRQ_SPORT0_TX BFIN_IRQ(43) /* SPORT0 TX Interrupt (DMA0) */
#define IRQ_SPORT0_TX_STAT BFIN_IRQ(44) /* SPORT0 TX Status Interrupt */
#define IRQ_SPORT0_RX BFIN_IRQ(45) /* SPORT0 RX Interrupt (DMA1) */
#define IRQ_SPORT0_RX_STAT BFIN_IRQ(46) /* SPORT0 RX Status Interrupt */
#define IRQ_SPORT1_TX BFIN_IRQ(47) /* SPORT1 TX Interrupt (DMA2) */
#define IRQ_SPORT1_TX_STAT BFIN_IRQ(48) /* SPORT1 TX Status Interrupt */
#define IRQ_SPORT1_RX BFIN_IRQ(49) /* SPORT1 RX Interrupt (DMA3) */
#define IRQ_SPORT1_RX_STAT BFIN_IRQ(50) /* SPORT1 RX Status Interrupt */
#define IRQ_SPORT2_TX BFIN_IRQ(51) /* SPORT2 TX Interrupt (DMA4) */
#define IRQ_SPORT2_TX_STAT BFIN_IRQ(52) /* SPORT2 TX Status Interrupt */
#define IRQ_SPORT2_RX BFIN_IRQ(53) /* SPORT2 RX Interrupt (DMA5) */
#define IRQ_SPORT2_RX_STAT BFIN_IRQ(54) /* SPORT2 RX Status Interrupt */
#define IRQ_SPI0_TX BFIN_IRQ(55) /* SPI0 TX Interrupt (DMA6) */
#define IRQ_SPI0_RX BFIN_IRQ(56) /* SPI0 RX Interrupt (DMA7) */
#define IRQ_SPI0_STAT BFIN_IRQ(57) /* SPI0 Status Interrupt */
#define IRQ_SPI1_TX BFIN_IRQ(58) /* SPI1 TX Interrupt (DMA8) */
#define IRQ_SPI1_RX BFIN_IRQ(59) /* SPI1 RX Interrupt (DMA9) */
#define IRQ_SPI1_STAT BFIN_IRQ(60) /* SPI1 Status Interrupt */
#define IRQ_RSI BFIN_IRQ(61) /* RSI (DMA10) Interrupt */
#define IRQ_RSI_INT0 BFIN_IRQ(62) /* RSI Interrupt0 */
#define IRQ_RSI_INT1 BFIN_IRQ(63) /* RSI Interrupt1 */
#define IRQ_SDU BFIN_IRQ(64) /* DMA11 Data (SDU) */
/* -- RESERVED -- 65 DMA12 Data (Reserved) */
/* -- RESERVED -- 66 Reserved */
/* -- RESERVED -- 67 Reserved */
#define IRQ_EMAC0_STAT BFIN_IRQ(68) /* EMAC0 Status */
/* -- RESERVED -- 69 EMAC0 Power (Reserved) */
#define IRQ_EMAC1_STAT BFIN_IRQ(70) /* EMAC1 Status */
/* -- RESERVED -- 71 EMAC1 Power (Reserved) */
#define IRQ_LP0 BFIN_IRQ(72) /* DMA13 Data (Link Port 0) */
#define IRQ_LP0_STAT BFIN_IRQ(73) /* Link Port 0 Status */
#define IRQ_LP1 BFIN_IRQ(74) /* DMA14 Data (Link Port 1) */
#define IRQ_LP1_STAT BFIN_IRQ(75) /* Link Port 1 Status */
#define IRQ_LP2 BFIN_IRQ(76) /* DMA15 Data (Link Port 2) */
#define IRQ_LP2_STAT BFIN_IRQ(77) /* Link Port 2 Status */
#define IRQ_LP3 BFIN_IRQ(78) /* DMA16 Data(Link Port 3) */
#define IRQ_LP3_STAT BFIN_IRQ(79) /* Link Port 3 Status */
#define IRQ_UART0_TX BFIN_IRQ(80) /* UART0 TX Interrupt (DMA17) */
#define IRQ_UART0_RX BFIN_IRQ(81) /* UART0 RX Interrupt (DMA18) */
#define IRQ_UART0_STAT BFIN_IRQ(82) /* UART0 Status(Error) Interrupt */
#define IRQ_UART1_TX BFIN_IRQ(83) /* UART1 TX Interrupt (DMA19) */
#define IRQ_UART1_RX BFIN_IRQ(84) /* UART1 RX Interrupt (DMA20) */
#define IRQ_UART1_STAT BFIN_IRQ(85) /* UART1 Status(Error) Interrupt */
#define IRQ_MDMA0_SRC_CRC0 BFIN_IRQ(86) /* DMA21 Data (MDMA Stream 0 Source/CRC0 Input Channel) */
#define IRQ_MDMA0_DEST_CRC0 BFIN_IRQ(87) /* DMA22 Data (MDMA Stream 0 Destination/CRC0 Output Channel) */
#define IRQ_MDMAS0 IRQ_MDMA0_DEST_CRC0
#define IRQ_CRC0_DCNTEXP BFIN_IRQ(88) /* CRC0 DATACOUNT Expiration */
#define IRQ_CRC0_ERR BFIN_IRQ(89) /* CRC0 Error */
#define IRQ_MDMA1_SRC_CRC1 BFIN_IRQ(90) /* DMA23 Data (MDMA Stream 1 Source/CRC1 Input Channel) */
#define IRQ_MDMA1_DEST_CRC1 BFIN_IRQ(91) /* DMA24 Data (MDMA Stream 1 Destination/CRC1 Output Channel) */
#define IRQ_MDMAS1 IRQ_MDMA1_DEST_CRC1
#define IRQ_CRC1_DCNTEXP BFIN_IRQ(92) /* CRC1 DATACOUNT Expiration */
#define IRQ_CRC1_ERR BFIN_IRQ(93) /* CRC1 Error */
#define IRQ_MDMA2_SRC BFIN_IRQ(94) /* DMA25 Data (MDMA Stream 2 Source Channel) */
#define IRQ_MDMA2_DEST BFIN_IRQ(95) /* DMA26 Data (MDMA Stream 2 Destination Channel) */
#define IRQ_MDMAS2 IRQ_MDMA2_DEST
#define IRQ_MDMA3_SRC BFIN_IRQ(96) /* DMA27 Data (MDMA Stream 3 Source Channel) */
#define IRQ_MDMA3_DEST BFIN_IRQ(97) /* DMA28 Data (MDMA Stream 3 Destination Channel) */
#define IRQ_MDMAS3 IRQ_MDMA3_DEST
#define IRQ_EPPI0_CH0 BFIN_IRQ(98) /* DMA29 Data (EPPI0 Channel 0) */
#define IRQ_EPPI0_CH1 BFIN_IRQ(99) /* DMA30 Data (EPPI0 Channel 1) */
#define IRQ_EPPI0_STAT BFIN_IRQ(100) /* EPPI0 Status */
#define IRQ_EPPI2_CH0 BFIN_IRQ(101) /* DMA31 Data (EPPI2 Channel 0) */
#define IRQ_EPPI2_CH1 BFIN_IRQ(102) /* DMA32 Data (EPPI2 Channel 1) */
#define IRQ_EPPI2_STAT BFIN_IRQ(103) /* EPPI2 Status */
#define IRQ_EPPI1_CH0 BFIN_IRQ(104) /* DMA33 Data (EPPI1 Channel 0) */
#define IRQ_EPPI1_CH1 BFIN_IRQ(105) /* DMA34 Data (EPPI1 Channel 1) */
#define IRQ_EPPI1_STAT BFIN_IRQ(106) /* EPPI1 Status */
#define IRQ_PIXC_CH0 BFIN_IRQ(107) /* DMA35 Data (PIXC Channel 0) */
#define IRQ_PIXC_CH1 BFIN_IRQ(108) /* DMA36 Data (PIXC Channel 1) */
#define IRQ_PIXC_CH2 BFIN_IRQ(109) /* DMA37 Data (PIXC Channel 2) */
#define IRQ_PIXC_STAT BFIN_IRQ(110) /* PIXC Status */
#define IRQ_PVP_CPDOB BFIN_IRQ(111) /* DMA38 Data (PVP0 Camera Pipe Data Out B) */
#define IRQ_PVP_CPDOC BFIN_IRQ(112) /* DMA39 Data (PVP0 Camera Pipe Data Out C) */
#define IRQ_PVP_CPSTAT BFIN_IRQ(113) /* DMA40 Data (PVP0 Camera Pipe Status Out) */
#define IRQ_PVP_CPCI BFIN_IRQ(114) /* DMA41 Data (PVP0 Camera Pipe Control In) */
#define IRQ_PVP_STAT0 BFIN_IRQ(115) /* PVP0 Status 0 */
#define IRQ_PVP_MPDO BFIN_IRQ(116) /* DMA42 Data (PVP0 Memory Pipe Data Out) */
#define IRQ_PVP_MPDI BFIN_IRQ(117) /* DMA43 Data (PVP0 Memory Pipe Data In) */
#define IRQ_PVP_MPSTAT BFIN_IRQ(118) /* DMA44 Data (PVP0 Memory Pipe Status Out) */
#define IRQ_PVP_MPCI BFIN_IRQ(119) /* DMA45 Data (PVP0 Memory Pipe Control In) */
#define IRQ_PVP_CPDOA BFIN_IRQ(120) /* DMA46 Data (PVP0 Camera Pipe Data Out A) */
#define IRQ_PVP_STAT1 BFIN_IRQ(121) /* PVP0 Status 1 */
#define IRQ_USB_STAT BFIN_IRQ(122) /* USB Status Interrupt */
#define IRQ_USB_DMA BFIN_IRQ(123) /* USB DMA Interrupt */
#define IRQ_TRU_INT0 BFIN_IRQ(124) /* TRU0 Interrupt 0 */
#define IRQ_TRU_INT1 BFIN_IRQ(125) /* TRU0 Interrupt 1 */
#define IRQ_TRU_INT2 BFIN_IRQ(126) /* TRU0 Interrupt 2 */
#define IRQ_TRU_INT3 BFIN_IRQ(127) /* TRU0 Interrupt 3 */
#define IRQ_DMAC0_ERROR BFIN_IRQ(128) /* DMAC0 Status Interrupt */
#define IRQ_CGU0_ERROR BFIN_IRQ(129) /* CGU0 Error */
/* -- RESERVED -- 130 Reserved */
#define IRQ_DPM BFIN_IRQ(131) /* DPM0 Event */
/* -- RESERVED -- 132 Reserved */
#define IRQ_SWU0 BFIN_IRQ(133) /* SWU0 */
#define IRQ_SWU1 BFIN_IRQ(134) /* SWU1 */
#define IRQ_SWU2 BFIN_IRQ(135) /* SWU2 */
#define IRQ_SWU3 BFIN_IRQ(136) /* SWU3 */
#define IRQ_SWU4 BFIN_IRQ(137) /* SWU4 */
#define IRQ_SWU5 BFIN_IRQ(138) /* SWU5 */
#define IRQ_SWU6 BFIN_IRQ(139) /* SWU6 */
#define SYS_IRQS IRQ_SWU6
#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
#define IRQ_PA0 BFIN_PA_IRQ(0)
#define IRQ_PA1 BFIN_PA_IRQ(1)
#define IRQ_PA2 BFIN_PA_IRQ(2)
#define IRQ_PA3 BFIN_PA_IRQ(3)
#define IRQ_PA4 BFIN_PA_IRQ(4)
#define IRQ_PA5 BFIN_PA_IRQ(5)
#define IRQ_PA6 BFIN_PA_IRQ(6)
#define IRQ_PA7 BFIN_PA_IRQ(7)
#define IRQ_PA8 BFIN_PA_IRQ(8)
#define IRQ_PA9 BFIN_PA_IRQ(9)
#define IRQ_PA10 BFIN_PA_IRQ(10)
#define IRQ_PA11 BFIN_PA_IRQ(11)
#define IRQ_PA12 BFIN_PA_IRQ(12)
#define IRQ_PA13 BFIN_PA_IRQ(13)
#define IRQ_PA14 BFIN_PA_IRQ(14)
#define IRQ_PA15 BFIN_PA_IRQ(15)
#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
#define IRQ_PB0 BFIN_PB_IRQ(0)
#define IRQ_PB1 BFIN_PB_IRQ(1)
#define IRQ_PB2 BFIN_PB_IRQ(2)
#define IRQ_PB3 BFIN_PB_IRQ(3)
#define IRQ_PB4 BFIN_PB_IRQ(4)
#define IRQ_PB5 BFIN_PB_IRQ(5)
#define IRQ_PB6 BFIN_PB_IRQ(6)
#define IRQ_PB7 BFIN_PB_IRQ(7)
#define IRQ_PB8 BFIN_PB_IRQ(8)
#define IRQ_PB9 BFIN_PB_IRQ(9)
#define IRQ_PB10 BFIN_PB_IRQ(10)
#define IRQ_PB11 BFIN_PB_IRQ(11)
#define IRQ_PB12 BFIN_PB_IRQ(12)
#define IRQ_PB13 BFIN_PB_IRQ(13)
#define IRQ_PB14 BFIN_PB_IRQ(14)
#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */
#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
#define IRQ_PC0 BFIN_PC_IRQ(0)
#define IRQ_PC1 BFIN_PC_IRQ(1)
#define IRQ_PC2 BFIN_PC_IRQ(2)
#define IRQ_PC3 BFIN_PC_IRQ(3)
#define IRQ_PC4 BFIN_PC_IRQ(4)
#define IRQ_PC5 BFIN_PC_IRQ(5)
#define IRQ_PC6 BFIN_PC_IRQ(6)
#define IRQ_PC7 BFIN_PC_IRQ(7)
#define IRQ_PC8 BFIN_PC_IRQ(8)
#define IRQ_PC9 BFIN_PC_IRQ(9)
#define IRQ_PC10 BFIN_PC_IRQ(10)
#define IRQ_PC11 BFIN_PC_IRQ(11)
#define IRQ_PC12 BFIN_PC_IRQ(12)
#define IRQ_PC13 BFIN_PC_IRQ(13)
#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */
#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */
#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)
#define IRQ_PD0 BFIN_PD_IRQ(0)
#define IRQ_PD1 BFIN_PD_IRQ(1)
#define IRQ_PD2 BFIN_PD_IRQ(2)
#define IRQ_PD3 BFIN_PD_IRQ(3)
#define IRQ_PD4 BFIN_PD_IRQ(4)
#define IRQ_PD5 BFIN_PD_IRQ(5)
#define IRQ_PD6 BFIN_PD_IRQ(6)
#define IRQ_PD7 BFIN_PD_IRQ(7)
#define IRQ_PD8 BFIN_PD_IRQ(8)
#define IRQ_PD9 BFIN_PD_IRQ(9)
#define IRQ_PD10 BFIN_PD_IRQ(10)
#define IRQ_PD11 BFIN_PD_IRQ(11)
#define IRQ_PD12 BFIN_PD_IRQ(12)
#define IRQ_PD13 BFIN_PD_IRQ(13)
#define IRQ_PD14 BFIN_PD_IRQ(14)
#define IRQ_PD15 BFIN_PD_IRQ(15)
#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)
#define IRQ_PE0 BFIN_PE_IRQ(0)
#define IRQ_PE1 BFIN_PE_IRQ(1)
#define IRQ_PE2 BFIN_PE_IRQ(2)
#define IRQ_PE3 BFIN_PE_IRQ(3)
#define IRQ_PE4 BFIN_PE_IRQ(4)
#define IRQ_PE5 BFIN_PE_IRQ(5)
#define IRQ_PE6 BFIN_PE_IRQ(6)
#define IRQ_PE7 BFIN_PE_IRQ(7)
#define IRQ_PE8 BFIN_PE_IRQ(8)
#define IRQ_PE9 BFIN_PE_IRQ(9)
#define IRQ_PE10 BFIN_PE_IRQ(10)
#define IRQ_PE11 BFIN_PE_IRQ(11)
#define IRQ_PE12 BFIN_PE_IRQ(12)
#define IRQ_PE13 BFIN_PE_IRQ(13)
#define IRQ_PE14 BFIN_PE_IRQ(14)
#define IRQ_PE15 BFIN_PE_IRQ(15)
#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)
#define IRQ_PF0 BFIN_PF_IRQ(0)
#define IRQ_PF1 BFIN_PF_IRQ(1)
#define IRQ_PF2 BFIN_PF_IRQ(2)
#define IRQ_PF3 BFIN_PF_IRQ(3)
#define IRQ_PF4 BFIN_PF_IRQ(4)
#define IRQ_PF5 BFIN_PF_IRQ(5)
#define IRQ_PF6 BFIN_PF_IRQ(6)
#define IRQ_PF7 BFIN_PF_IRQ(7)
#define IRQ_PF8 BFIN_PF_IRQ(8)
#define IRQ_PF9 BFIN_PF_IRQ(9)
#define IRQ_PF10 BFIN_PF_IRQ(10)
#define IRQ_PF11 BFIN_PF_IRQ(11)
#define IRQ_PF12 BFIN_PF_IRQ(12)
#define IRQ_PF13 BFIN_PF_IRQ(13)
#define IRQ_PF14 BFIN_PF_IRQ(14)
#define IRQ_PF15 BFIN_PF_IRQ(15)
#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)
#define IRQ_PG0 BFIN_PG_IRQ(0)
#define IRQ_PG1 BFIN_PG_IRQ(1)
#define IRQ_PG2 BFIN_PG_IRQ(2)
#define IRQ_PG3 BFIN_PG_IRQ(3)
#define IRQ_PG4 BFIN_PG_IRQ(4)
#define IRQ_PG5 BFIN_PG_IRQ(5)
#define IRQ_PG6 BFIN_PG_IRQ(6)
#define IRQ_PG7 BFIN_PG_IRQ(7)
#define IRQ_PG8 BFIN_PG_IRQ(8)
#define IRQ_PG9 BFIN_PG_IRQ(9)
#define IRQ_PG10 BFIN_PG_IRQ(10)
#define IRQ_PG11 BFIN_PG_IRQ(11)
#define IRQ_PG12 BFIN_PG_IRQ(12)
#define IRQ_PG13 BFIN_PG_IRQ(13)
#define IRQ_PG14 BFIN_PG_IRQ(14)
#define IRQ_PG15 BFIN_PG_IRQ(15)
#define GPIO_IRQ_BASE IRQ_PA0
#define NR_MACH_IRQS (IRQ_PG15 + 1)
#define SEC_SCTL_PRIO_OFFSET 8
#ifndef __ASSEMBLY__
#include <linux/types.h>
extern u8 sec_int_priority[];
/*
* gpio pint registers layout
*/
struct bfin_pint_regs {
u32 mask_set;
u32 mask_clear;
u32 request;
u32 assign;
u32 edge_set;
u32 edge_clear;
u32 invert_set;
u32 invert_clear;
u32 pinstate;
u32 latch;
u32 __pad0[2];
};
#endif
#endif

86
arch/blackfin/mach-bf609/include/mach/mem_map.h Normal file
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/*
* BF60x memory map
*
* Copyright 2011 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
#ifndef __BFIN_MACH_MEM_MAP_H__
#define __BFIN_MACH_MEM_MAP_H__
#ifndef __BFIN_MEM_MAP_H__
# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
#endif
/* Async Memory Banks */
#define ASYNC_BANK3_BASE 0xBC000000 /* Async Bank 3 */
#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
#define ASYNC_BANK2_BASE 0xB8000000 /* Async Bank 2 */
#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
#define ASYNC_BANK1_BASE 0xB4000000 /* Async Bank 1 */
#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
#define ASYNC_BANK0_BASE 0xB0000000 /* Async Bank 0 */
#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
/* Boot ROM Memory */
#define BOOT_ROM_START 0xC8000000
#define BOOT_ROM_LENGTH 0x8000
/* Level 1 Memory */
/* Memory Map for ADSP-BF60x processors */
#ifdef CONFIG_BFIN_ICACHE
#define BFIN_ICACHESIZE (16*1024)
#define L1_CODE_LENGTH 0x10000
#else
#define BFIN_ICACHESIZE (0*1024)
#define L1_CODE_LENGTH 0x14000
#endif
#define L1_CODE_START 0xFFA00000
#define L1_DATA_A_START 0xFF800000
#define L1_DATA_B_START 0xFF900000
#define COREA_L1_SCRATCH_START 0xFFB00000
#define COREB_L1_SCRATCH_START 0xFF700000
#define COREB_L1_CODE_START 0xFF600000
#define COREB_L1_DATA_A_START 0xFF400000
#define COREB_L1_DATA_B_START 0xFF500000
#define COREB_L1_CODE_LENGTH 0x14000
#define COREB_L1_DATA_A_LENGTH 0x8000
#define COREB_L1_DATA_B_LENGTH 0x8000
#ifdef CONFIG_BFIN_DCACHE
#ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH 0x8000
#define BFIN_DCACHESIZE (16*1024)
#define BFIN_DSUPBANKS 1
#else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
#define BFIN_DCACHESIZE (32*1024)
#define BFIN_DSUPBANKS 2
#endif
#else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH 0x8000
#define L1_DATA_B_LENGTH 0x8000
#define BFIN_DCACHESIZE (0*1024)
#define BFIN_DSUPBANKS 0
#endif /*CONFIG_BFIN_DCACHE*/
/* Level 2 Memory */
#define L2_START 0xC8080000
#define L2_LENGTH 0x40000
#endif

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arch/blackfin/mach-bf609/include/mach/pll.h Normal file
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/* #include <mach-common/pll.h> */

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arch/blackfin/mach-bf609/include/mach/pm.h Normal file
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/*
* Blackfin bf609 power management
*
* Copyright 2011 Analog Devices Inc.
*
* Licensed under the GPL-2
*/
#ifndef __MACH_BF609_PM_H__
#define __MACH_BF609_PM_H__
#include <linux/suspend.h>
#include <linux/platform_device.h>
extern int bfin609_pm_enter(suspend_state_t state);
extern int bf609_pm_prepare(void);
extern void bf609_pm_finish(void);
void bf609_hibernate(void);
void bfin_sec_raise_irq(unsigned int sid);
void coreb_enable(void);
int bf609_nor_flash_init(struct platform_device *pdev);
void bf609_nor_flash_exit(struct platform_device *pdev);
#endif

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arch/blackfin/mach-bf609/include/mach/portmux.h Normal file
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/*
* Copyright 2011 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
/* EMAC RMII Port Mux */
#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
#define P_MII0_PTPPPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
#define P_RMII0 {\
P_MII0_ETxD0, \
P_MII0_ETxD1, \
P_MII0_ETxEN, \
P_MII0_ERxD0, \
P_MII0_ERxD1, \
P_MII0_ERxER, \
P_MII0_TxCLK, \
P_MII0_PHYINT, \
P_MII0_CRS, \
P_MII0_PTPPPS, \
P_MII0_MDC, \
P_MII0_MDIO, 0}
#define P_MII1_MDC (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
#define P_MII1_MDIO (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
#define P_MII1_ETxD0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
#define P_MII1_ERxD0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
#define P_MII1_ETxD1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
#define P_MII1_ERxD1 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
#define P_MII1_ETxEN (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
#define P_MII1_PHYINT (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
#define P_MII1_PTPPPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
#define P_RMII1 {\
P_MII1_ETxD0, \
P_MII1_ETxD1, \
P_MII1_ETxEN, \
P_MII1_ERxD0, \
P_MII1_ERxD1, \
P_MII1_ERxER, \
P_MII1_TxCLK, \
P_MII1_PHYINT, \
P_MII1_CRS, \
P_MII1_PTPPPS, \
P_MII1_MDC, \
P_MII1_MDIO, 0}
/* PPI Port Mux */
#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(1))
#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(1))
#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(1))
#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(1))
#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(1))
#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(1))
#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(1))
#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(1))
#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(1))
#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(1))
#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(1))
#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(1))
#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(1))
#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(1))
#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(1))
#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(1))
#define P_PPI1_D16 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
#define P_PPI1_D17 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(1))
#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(1))
#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(1))
#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(1))
#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(1))
#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(1))
#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(1))
#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(1))
#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(1))
#define P_PPI2_D8 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(1))
#define P_PPI2_D9 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
#define P_PPI2_D10 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(1))
#define P_PPI2_D11 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(1))
#define P_PPI2_D12 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(1))
#define P_PPI2_D13 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
#define P_PPI2_D14 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(1))
#define P_PPI2_D15 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(1))
#define P_PPI2_D16 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(1))
#define P_PPI2_D17 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(1))
#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(1))
#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(1))
#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(1))
/* SPI Port Mux */
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
#define P_SPI0_RDY (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
#define P_SPI0_D2 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
#define P_SPI0_D3 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(0))
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
#define P_SPI1_RDY (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
#define P_SPI1_D2 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
#define P_SPI1_D3 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
#define P_SPI1_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
#define P_SPI1_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(0))
#define GPIO_DEFAULT_BOOT_SPI_CS
#define P_DEFAULT_BOOT_SPI_CS
/* CORE IDLE */
#define P_IDLEA (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
#define P_IDLEB (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
#define P_SLEEP (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
/* UART Port Mux */
#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
#define P_UART0_RTS (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
#define P_UART0_CTS (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
/* Timer */
#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(3))
#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(2))
#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
/* RSI */
#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(2))
#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(2))
#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(2))
#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(2))
#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(2))
#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
/* PTP */
#define P_PTP0_PPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
#define P_PTP0_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
#define P_PTP0_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
#define P_PTP1_PPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
#define P_PTP1_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
#define P_PTP1_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
/* SMC Port Mux */
#define P_A3 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
#define P_A4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
#define P_A5 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
#define P_A6 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
#define P_A7 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
#define P_A8 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
#define P_A9 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
#define P_A10 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
#define P_A11 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
#define P_A12 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
#define P_A13 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
#define P_A14 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
#define P_A15 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
#define P_A16 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
#define P_A17 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
#define P_A18 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
#define P_A19 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
#define P_A20 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
#define P_A21 (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
#define P_A22 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
#define P_A23 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
#define P_A24 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
#define P_A25 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
#define P_NORCK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
#define P_AMS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
/* CAN */
#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
/* SPORT */
#define P_SPORT0_ACLK (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(2))
#define P_SPORT0_AFS (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(2))
#define P_SPORT0_AD0 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(2))
#define P_SPORT0_AD1 (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(2))
#define P_SPORT0_ATDV (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(1))
#define P_SPORT0_BCLK (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(2))
#define P_SPORT0_BFS (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(2))
#define P_SPORT0_BD0 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(2))
#define P_SPORT0_BD1 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(2))
#define P_SPORT0_BTDV (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(1))
#define P_SPORT1_ACLK (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(2))
#define P_SPORT1_AFS (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(2))
#define P_SPORT1_AD0 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
#define P_SPORT1_AD1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
#define P_SPORT1_ATDV (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
#define P_SPORT1_BCLK (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(2))
#define P_SPORT1_BFS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(2))
#define P_SPORT1_BD0 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(2))
#define P_SPORT1_BD1 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(2))
#define P_SPORT1_BTDV (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
#define P_SPORT2_ACLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
#define P_SPORT2_AFS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
#define P_SPORT2_AD0 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
#define P_SPORT2_AD1 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
#define P_SPORT2_ATDV (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(1))
#define P_SPORT2_BCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
#define P_SPORT2_BFS (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
#define P_SPORT2_BD0 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
#define P_SPORT2_BD1 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
#define P_SPORT2_BTDV (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
/* LINK PORT */
#define P_LP0_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(2))
#define P_LP0_ACK (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(2))
#define P_LP0_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(2))
#define P_LP0_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(2))
#define P_LP0_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(2))
#define P_LP0_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(2))
#define P_LP0_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(2))
#define P_LP0_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(2))
#define P_LP0_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(2))
#define P_LP0_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(2))
#define P_LP1_CLK (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(2))
#define P_LP1_ACK (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(2))
#define P_LP1_D0 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(2))
#define P_LP1_D1 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(2))
#define P_LP1_D2 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(2))
#define P_LP1_D3 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(2))
#define P_LP1_D4 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(2))
#define P_LP1_D5 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(2))
#define P_LP1_D6 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(2))
#define P_LP1_D7 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(2))
#define P_LP2_CLK (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(2))
#define P_LP2_ACK (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(2))
#define P_LP2_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
#define P_LP2_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
#define P_LP2_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
#define P_LP2_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
#define P_LP2_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
#define P_LP2_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
#define P_LP2_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
#define P_LP2_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
#define P_LP3_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(2))
#define P_LP3_ACK (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(2))
#define P_LP3_D0 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
#define P_LP3_D1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
#define P_LP3_D2 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
#define P_LP3_D3 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
#define P_LP3_D4 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
#define P_LP3_D5 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
#define P_LP3_D6 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
#define P_LP3_D7 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
/* TWI */
#define P_TWI0_SCL (P_DONTCARE)
#define P_TWI0_SDA (P_DONTCARE)
#define P_TWI1_SCL (P_DONTCARE)
#define P_TWI1_SDA (P_DONTCARE)
/* Rotary Encoder */
#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(3))
#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(3))
#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(3))
#endif /* _MACH_PORTMUX_H_ */