mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
10
arch/c6x/boot/Makefile
Normal file
10
arch/c6x/boot/Makefile
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
#
|
||||
# Makefile for bootable kernel images
|
||||
#
|
||||
|
||||
OBJCOPYFLAGS_vmlinux.bin := -O binary
|
||||
$(obj)/vmlinux.bin: vmlinux FORCE
|
||||
$(call if_changed,objcopy)
|
||||
|
||||
$(obj)/dtbImage.%: vmlinux
|
||||
$(call if_changed,objcopy)
|
||||
20
arch/c6x/boot/dts/Makefile
Normal file
20
arch/c6x/boot/dts/Makefile
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
#
|
||||
# Makefile for device trees
|
||||
#
|
||||
|
||||
DTC_FLAGS ?= -p 1024
|
||||
|
||||
ifneq ($(DTB),)
|
||||
obj-y += linked_dtb.o
|
||||
endif
|
||||
|
||||
quiet_cmd_cp = CP $< $@$2
|
||||
cmd_cp = cat $< >$@$2 || (rm -f $@ && echo false)
|
||||
|
||||
# Generate builtin.dtb from $(DTB).dtb
|
||||
$(obj)/builtin.dtb: $(obj)/$(DTB).dtb
|
||||
$(call if_changed,cp)
|
||||
|
||||
$(obj)/linked_dtb.o: $(obj)/builtin.dtb
|
||||
|
||||
clean-files := *.dtb
|
||||
62
arch/c6x/boot/dts/dsk6455.dts
Normal file
62
arch/c6x/boot/dts/dsk6455.dts
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* arch/c6x/boot/dts/dsk6455.dts
|
||||
*
|
||||
* DSK6455 Evaluation Platform For TMS320C6455
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated
|
||||
*
|
||||
* Author: Mark Salter <msalter@redhat.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "tms320c6455.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Spectrum Digital DSK6455";
|
||||
compatible = "spectrum-digital,dsk6455";
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/nfs ip=dhcp rw";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0xE0000000 0x08000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
megamod_pic: interrupt-controller@1800000 {
|
||||
interrupts = < 12 13 14 15 >;
|
||||
};
|
||||
|
||||
emifa@70000000 {
|
||||
flash@3,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x3 0x0 0x400000>;
|
||||
bank-width = <1>;
|
||||
device-width = <1>;
|
||||
partition@0 {
|
||||
reg = <0x0 0x400000>;
|
||||
label = "NOR";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
timer1: timer@2980000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 69 >;
|
||||
};
|
||||
|
||||
clock-controller@029a0000 {
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
48
arch/c6x/boot/dts/evmc6457.dts
Normal file
48
arch/c6x/boot/dts/evmc6457.dts
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* arch/c6x/boot/dts/evmc6457.dts
|
||||
*
|
||||
* EVMC6457 Evaluation Platform For TMS320C6457
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated
|
||||
*
|
||||
* Author: Mark Salter <msalter@redhat.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "tms320c6457.dtsi"
|
||||
|
||||
/ {
|
||||
model = "eInfochips EVMC6457";
|
||||
compatible = "einfochips,evmc6457";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0xE0000000 0x10000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
megamod_pic: interrupt-controller@1800000 {
|
||||
interrupts = < 12 13 14 15 >;
|
||||
};
|
||||
|
||||
timer0: timer@2940000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 67 >;
|
||||
};
|
||||
|
||||
clock-controller@29a0000 {
|
||||
clock-frequency = <60000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
73
arch/c6x/boot/dts/evmc6472.dts
Normal file
73
arch/c6x/boot/dts/evmc6472.dts
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* arch/c6x/boot/dts/evmc6472.dts
|
||||
*
|
||||
* EVMC6472 Evaluation Platform For TMS320C6472
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated
|
||||
*
|
||||
* Author: Mark Salter <msalter@redhat.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "tms320c6472.dtsi"
|
||||
|
||||
/ {
|
||||
model = "eInfochips EVMC6472";
|
||||
compatible = "einfochips,evmc6472";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0xE0000000 0x10000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
megamod_pic: interrupt-controller@1800000 {
|
||||
interrupts = < 12 13 14 15 >;
|
||||
};
|
||||
|
||||
timer0: timer@25e0000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 16 >;
|
||||
};
|
||||
|
||||
timer1: timer@25f0000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 16 >;
|
||||
};
|
||||
|
||||
timer2: timer@2600000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 16 >;
|
||||
};
|
||||
|
||||
timer3: timer@2610000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 16 >;
|
||||
};
|
||||
|
||||
timer4: timer@2620000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 16 >;
|
||||
};
|
||||
|
||||
timer5: timer@2630000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 16 >;
|
||||
};
|
||||
|
||||
clock-controller@29a0000 {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
58
arch/c6x/boot/dts/evmc6474.dts
Normal file
58
arch/c6x/boot/dts/evmc6474.dts
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* arch/c6x/boot/dts/evmc6474.dts
|
||||
*
|
||||
* EVMC6474 Evaluation Platform For TMS320C6474
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated
|
||||
*
|
||||
* Author: Mark Salter <msalter@redhat.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "tms320c6474.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Spectrum Digital EVMC6474";
|
||||
compatible = "spectrum-digital,evmc6474";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x08000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
megamod_pic: interrupt-controller@1800000 {
|
||||
interrupts = < 12 13 14 15 >;
|
||||
};
|
||||
|
||||
timer3: timer@2940000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 39 >;
|
||||
};
|
||||
|
||||
timer4: timer@2950000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 41 >;
|
||||
};
|
||||
|
||||
timer5: timer@2960000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 43 >;
|
||||
};
|
||||
|
||||
clock-controller@29a0000 {
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
83
arch/c6x/boot/dts/evmc6678.dts
Normal file
83
arch/c6x/boot/dts/evmc6678.dts
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
/*
|
||||
* arch/c6x/boot/dts/evmc6678.dts
|
||||
*
|
||||
* EVMC6678 Evaluation Platform For TMS320C6678
|
||||
*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated
|
||||
*
|
||||
* Author: Ken Cox <jkc@redhat.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "tms320c6678.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Advantech EVMC6678";
|
||||
compatible = "advantech,evmc6678";
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/nfs ip=dhcp rw";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x20000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
megamod_pic: interrupt-controller@1800000 {
|
||||
interrupts = < 12 13 14 15 >;
|
||||
};
|
||||
|
||||
timer8: timer@2280000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 66 >;
|
||||
};
|
||||
|
||||
timer9: timer@2290000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 68 >;
|
||||
};
|
||||
|
||||
timer10: timer@22A0000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 70 >;
|
||||
};
|
||||
|
||||
timer11: timer@22B0000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 72 >;
|
||||
};
|
||||
|
||||
timer12: timer@22C0000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 74 >;
|
||||
};
|
||||
|
||||
timer13: timer@22D0000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 76 >;
|
||||
};
|
||||
|
||||
timer14: timer@22E0000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 78 >;
|
||||
};
|
||||
|
||||
timer15: timer@22F0000 {
|
||||
interrupt-parent = <&megamod_pic>;
|
||||
interrupts = < 80 >;
|
||||
};
|
||||
|
||||
clock-controller@2310000 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
2
arch/c6x/boot/dts/linked_dtb.S
Normal file
2
arch/c6x/boot/dts/linked_dtb.S
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
.section __fdt_blob,"a"
|
||||
.incbin "arch/c6x/boot/dts/builtin.dtb"
|
||||
96
arch/c6x/boot/dts/tms320c6455.dtsi
Normal file
96
arch/c6x/boot/dts/tms320c6455.dtsi
Normal file
|
|
@ -0,0 +1,96 @@
|
|||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "ti,c64x+";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
model = "tms320c6455";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
core_pic: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "ti,c64x+core-pic";
|
||||
};
|
||||
|
||||
/*
|
||||
* Megamodule interrupt controller
|
||||
*/
|
||||
megamod_pic: interrupt-controller@1800000 {
|
||||
compatible = "ti,c64x+megamod-pic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x1800000 0x1000>;
|
||||
interrupt-parent = <&core_pic>;
|
||||
};
|
||||
|
||||
cache-controller@1840000 {
|
||||
compatible = "ti,c64x+cache";
|
||||
reg = <0x01840000 0x8400>;
|
||||
};
|
||||
|
||||
emifa@70000000 {
|
||||
compatible = "ti,c64x+emifa", "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x70000000 0x100>;
|
||||
ranges = <0x2 0x0 0xa0000000 0x00000008
|
||||
0x3 0x0 0xb0000000 0x00400000
|
||||
0x4 0x0 0xc0000000 0x10000000
|
||||
0x5 0x0 0xD0000000 0x10000000>;
|
||||
|
||||
ti,dscr-dev-enable = <13>;
|
||||
ti,emifa-burst-priority = <255>;
|
||||
ti,emifa-ce-config = <0x00240120
|
||||
0x00240120
|
||||
0x00240122
|
||||
0x00240122>;
|
||||
};
|
||||
|
||||
timer1: timer@2980000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
reg = <0x2980000 0x40>;
|
||||
ti,dscr-dev-enable = <4>;
|
||||
};
|
||||
|
||||
clock-controller@029a0000 {
|
||||
compatible = "ti,c6455-pll", "ti,c64x+pll";
|
||||
reg = <0x029a0000 0x200>;
|
||||
ti,c64x+pll-bypass-delay = <1440>;
|
||||
ti,c64x+pll-reset-delay = <15360>;
|
||||
ti,c64x+pll-lock-delay = <24000>;
|
||||
};
|
||||
|
||||
device-state-config-regs@2a80000 {
|
||||
compatible = "ti,c64x+dscr";
|
||||
reg = <0x02a80000 0x41000>;
|
||||
|
||||
ti,dscr-devstat = <0>;
|
||||
ti,dscr-silicon-rev = <8 28 0xf>;
|
||||
ti,dscr-rmii-resets = <0 0x40020 0x00040000>;
|
||||
|
||||
ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
|
||||
ti,dscr-devstate-ctl-regs =
|
||||
<0 12 0x40008 1 0 0 2
|
||||
12 1 0x40008 3 0 30 2
|
||||
13 2 0x4002c 1 0xffffffff 0 1>;
|
||||
ti,dscr-devstate-stat-regs =
|
||||
<0 10 0x40014 1 0 0 3
|
||||
10 2 0x40018 1 0 0 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
68
arch/c6x/boot/dts/tms320c6457.dtsi
Normal file
68
arch/c6x/boot/dts/tms320c6457.dtsi
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "ti,c64x+";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
model = "tms320c6457";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
core_pic: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "ti,c64x+core-pic";
|
||||
};
|
||||
|
||||
megamod_pic: interrupt-controller@1800000 {
|
||||
compatible = "ti,c64x+megamod-pic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&core_pic>;
|
||||
reg = <0x1800000 0x1000>;
|
||||
};
|
||||
|
||||
cache-controller@1840000 {
|
||||
compatible = "ti,c64x+cache";
|
||||
reg = <0x01840000 0x8400>;
|
||||
};
|
||||
|
||||
device-state-controller@2880800 {
|
||||
compatible = "ti,c64x+dscr";
|
||||
reg = <0x02880800 0x400>;
|
||||
|
||||
ti,dscr-devstat = <0x20>;
|
||||
ti,dscr-silicon-rev = <0x18 28 0xf>;
|
||||
ti,dscr-mac-fuse-regs = <0x114 3 4 5 6
|
||||
0x118 0 0 1 2>;
|
||||
ti,dscr-kick-regs = <0x38 0x83E70B13
|
||||
0x3c 0x95A4F1E0>;
|
||||
};
|
||||
|
||||
timer0: timer@2940000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
reg = <0x2940000 0x40>;
|
||||
};
|
||||
|
||||
clock-controller@29a0000 {
|
||||
compatible = "ti,c6457-pll", "ti,c64x+pll";
|
||||
reg = <0x029a0000 0x200>;
|
||||
ti,c64x+pll-bypass-delay = <300>;
|
||||
ti,c64x+pll-reset-delay = <24000>;
|
||||
ti,c64x+pll-lock-delay = <50000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
134
arch/c6x/boot/dts/tms320c6472.dtsi
Normal file
134
arch/c6x/boot/dts/tms320c6472.dtsi
Normal file
|
|
@ -0,0 +1,134 @@
|
|||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
model = "ti,c64x+";
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
model = "ti,c64x+";
|
||||
};
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
model = "ti,c64x+";
|
||||
};
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
model = "ti,c64x+";
|
||||
};
|
||||
cpu@4 {
|
||||
device_type = "cpu";
|
||||
reg = <4>;
|
||||
model = "ti,c64x+";
|
||||
};
|
||||
cpu@5 {
|
||||
device_type = "cpu";
|
||||
reg = <5>;
|
||||
model = "ti,c64x+";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
model = "tms320c6472";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
core_pic: interrupt-controller {
|
||||
compatible = "ti,c64x+core-pic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
megamod_pic: interrupt-controller@1800000 {
|
||||
compatible = "ti,c64x+megamod-pic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x1800000 0x1000>;
|
||||
interrupt-parent = <&core_pic>;
|
||||
};
|
||||
|
||||
cache-controller@1840000 {
|
||||
compatible = "ti,c64x+cache";
|
||||
reg = <0x01840000 0x8400>;
|
||||
};
|
||||
|
||||
timer0: timer@25e0000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
ti,core-mask = < 0x01 >;
|
||||
reg = <0x25e0000 0x40>;
|
||||
};
|
||||
|
||||
timer1: timer@25f0000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
ti,core-mask = < 0x02 >;
|
||||
reg = <0x25f0000 0x40>;
|
||||
};
|
||||
|
||||
timer2: timer@2600000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
ti,core-mask = < 0x04 >;
|
||||
reg = <0x2600000 0x40>;
|
||||
};
|
||||
|
||||
timer3: timer@2610000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
ti,core-mask = < 0x08 >;
|
||||
reg = <0x2610000 0x40>;
|
||||
};
|
||||
|
||||
timer4: timer@2620000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
ti,core-mask = < 0x10 >;
|
||||
reg = <0x2620000 0x40>;
|
||||
};
|
||||
|
||||
timer5: timer@2630000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
ti,core-mask = < 0x20 >;
|
||||
reg = <0x2630000 0x40>;
|
||||
};
|
||||
|
||||
clock-controller@29a0000 {
|
||||
compatible = "ti,c6472-pll", "ti,c64x+pll";
|
||||
reg = <0x029a0000 0x200>;
|
||||
ti,c64x+pll-bypass-delay = <200>;
|
||||
ti,c64x+pll-reset-delay = <12000>;
|
||||
ti,c64x+pll-lock-delay = <80000>;
|
||||
};
|
||||
|
||||
device-state-controller@2a80000 {
|
||||
compatible = "ti,c64x+dscr";
|
||||
reg = <0x02a80000 0x1000>;
|
||||
|
||||
ti,dscr-devstat = <0>;
|
||||
ti,dscr-silicon-rev = <0x70c 16 0xff>;
|
||||
|
||||
ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
|
||||
0x704 5 6 0 0>;
|
||||
|
||||
ti,dscr-rmii-resets = <0x208 1
|
||||
0x20c 1>;
|
||||
|
||||
ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a
|
||||
0x40c 0x420 0xbea7
|
||||
0x41c 0x420 0xbea7>;
|
||||
|
||||
ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
|
||||
|
||||
ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
89
arch/c6x/boot/dts/tms320c6474.dtsi
Normal file
89
arch/c6x/boot/dts/tms320c6474.dtsi
Normal file
|
|
@ -0,0 +1,89 @@
|
|||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
model = "ti,c64x+";
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
model = "ti,c64x+";
|
||||
};
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
model = "ti,c64x+";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
model = "tms320c6474";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
core_pic: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "ti,c64x+core-pic";
|
||||
};
|
||||
|
||||
megamod_pic: interrupt-controller@1800000 {
|
||||
compatible = "ti,c64x+megamod-pic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x1800000 0x1000>;
|
||||
interrupt-parent = <&core_pic>;
|
||||
};
|
||||
|
||||
cache-controller@1840000 {
|
||||
compatible = "ti,c64x+cache";
|
||||
reg = <0x01840000 0x8400>;
|
||||
};
|
||||
|
||||
timer3: timer@2940000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
ti,core-mask = < 0x04 >;
|
||||
reg = <0x2940000 0x40>;
|
||||
};
|
||||
|
||||
timer4: timer@2950000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
ti,core-mask = < 0x02 >;
|
||||
reg = <0x2950000 0x40>;
|
||||
};
|
||||
|
||||
timer5: timer@2960000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
ti,core-mask = < 0x01 >;
|
||||
reg = <0x2960000 0x40>;
|
||||
};
|
||||
|
||||
device-state-controller@2880800 {
|
||||
compatible = "ti,c64x+dscr";
|
||||
reg = <0x02880800 0x400>;
|
||||
|
||||
ti,dscr-devstat = <0x004>;
|
||||
ti,dscr-silicon-rev = <0x014 28 0xf>;
|
||||
ti,dscr-mac-fuse-regs = <0x34 3 4 5 6
|
||||
0x38 0 0 1 2>;
|
||||
};
|
||||
|
||||
clock-controller@29a0000 {
|
||||
compatible = "ti,c6474-pll", "ti,c64x+pll";
|
||||
reg = <0x029a0000 0x200>;
|
||||
ti,c64x+pll-bypass-delay = <120>;
|
||||
ti,c64x+pll-reset-delay = <30000>;
|
||||
ti,c64x+pll-lock-delay = <60000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
146
arch/c6x/boot/dts/tms320c6678.dtsi
Normal file
146
arch/c6x/boot/dts/tms320c6678.dtsi
Normal file
|
|
@ -0,0 +1,146 @@
|
|||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
model = "ti,c66x";
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
model = "ti,c66x";
|
||||
};
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
model = "ti,c66x";
|
||||
};
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
model = "ti,c66x";
|
||||
};
|
||||
cpu@4 {
|
||||
device_type = "cpu";
|
||||
reg = <4>;
|
||||
model = "ti,c66x";
|
||||
};
|
||||
cpu@5 {
|
||||
device_type = "cpu";
|
||||
reg = <5>;
|
||||
model = "ti,c66x";
|
||||
};
|
||||
cpu@6 {
|
||||
device_type = "cpu";
|
||||
reg = <6>;
|
||||
model = "ti,c66x";
|
||||
};
|
||||
cpu@7 {
|
||||
device_type = "cpu";
|
||||
reg = <7>;
|
||||
model = "ti,c66x";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
model = "tms320c6678";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
core_pic: interrupt-controller {
|
||||
compatible = "ti,c64x+core-pic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
megamod_pic: interrupt-controller@1800000 {
|
||||
compatible = "ti,c64x+megamod-pic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x1800000 0x1000>;
|
||||
interrupt-parent = <&core_pic>;
|
||||
};
|
||||
|
||||
cache-controller@1840000 {
|
||||
compatible = "ti,c64x+cache";
|
||||
reg = <0x01840000 0x8400>;
|
||||
};
|
||||
|
||||
timer8: timer@2280000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
ti,core-mask = < 0x01 >;
|
||||
reg = <0x2280000 0x40>;
|
||||
};
|
||||
|
||||
timer9: timer@2290000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
ti,core-mask = < 0x02 >;
|
||||
reg = <0x2290000 0x40>;
|
||||
};
|
||||
|
||||
timer10: timer@22A0000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
ti,core-mask = < 0x04 >;
|
||||
reg = <0x22A0000 0x40>;
|
||||
};
|
||||
|
||||
timer11: timer@22B0000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
ti,core-mask = < 0x08 >;
|
||||
reg = <0x22B0000 0x40>;
|
||||
};
|
||||
|
||||
timer12: timer@22C0000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
ti,core-mask = < 0x10 >;
|
||||
reg = <0x22C0000 0x40>;
|
||||
};
|
||||
|
||||
timer13: timer@22D0000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
ti,core-mask = < 0x20 >;
|
||||
reg = <0x22D0000 0x40>;
|
||||
};
|
||||
|
||||
timer14: timer@22E0000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
ti,core-mask = < 0x40 >;
|
||||
reg = <0x22E0000 0x40>;
|
||||
};
|
||||
|
||||
timer15: timer@22F0000 {
|
||||
compatible = "ti,c64x+timer64";
|
||||
ti,core-mask = < 0x80 >;
|
||||
reg = <0x22F0000 0x40>;
|
||||
};
|
||||
|
||||
clock-controller@2310000 {
|
||||
compatible = "ti,c6678-pll", "ti,c64x+pll";
|
||||
reg = <0x02310000 0x200>;
|
||||
ti,c64x+pll-bypass-delay = <200>;
|
||||
ti,c64x+pll-reset-delay = <12000>;
|
||||
ti,c64x+pll-lock-delay = <80000>;
|
||||
};
|
||||
|
||||
device-state-controller@2620000 {
|
||||
compatible = "ti,c64x+dscr";
|
||||
reg = <0x02620000 0x1000>;
|
||||
|
||||
ti,dscr-devstat = <0x20>;
|
||||
ti,dscr-silicon-rev = <0x18 28 0xf>;
|
||||
|
||||
ti,dscr-mac-fuse-regs = <0x110 1 2 3 4
|
||||
0x114 5 6 0 0>;
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Add table
Add a link
Reference in a new issue