mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-02 17:15:37 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
287
arch/cris/arch-v10/kernel/dma.c
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287
arch/cris/arch-v10/kernel/dma.c
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@ -0,0 +1,287 @@
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/* Wrapper for DMA channel allocator that updates DMA client muxing.
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* Copyright 2004-2007, Axis Communications AB
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <asm/dma.h>
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#include <arch/svinto.h>
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#include <arch/system.h>
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/* Macro to access ETRAX 100 registers */
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#define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \
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IO_STATE_(reg##_, field##_, _##val)
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static char used_dma_channels[MAX_DMA_CHANNELS];
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static const char * used_dma_channels_users[MAX_DMA_CHANNELS];
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int cris_request_dma(unsigned int dmanr, const char * device_id,
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unsigned options, enum dma_owner owner)
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{
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unsigned long flags;
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unsigned long int gens;
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int fail = -EINVAL;
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if (dmanr >= MAX_DMA_CHANNELS) {
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printk(KERN_CRIT "cris_request_dma: invalid DMA channel %u\n", dmanr);
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return -EINVAL;
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}
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local_irq_save(flags);
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if (used_dma_channels[dmanr]) {
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local_irq_restore(flags);
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if (options & DMA_VERBOSE_ON_ERROR) {
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printk(KERN_CRIT "Failed to request DMA %i for %s, already allocated by %s\n", dmanr, device_id, used_dma_channels_users[dmanr]);
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}
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if (options & DMA_PANIC_ON_ERROR) {
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panic("request_dma error!");
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}
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return -EBUSY;
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}
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gens = genconfig_shadow;
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switch(owner)
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{
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case dma_eth:
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if ((dmanr != NETWORK_TX_DMA_NBR) &&
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(dmanr != NETWORK_RX_DMA_NBR)) {
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printk(KERN_CRIT "Invalid DMA channel for eth\n");
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goto bail;
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}
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break;
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case dma_ser0:
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if (dmanr == SER0_TX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma6, serial0);
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} else if (dmanr == SER0_RX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma7, serial0);
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} else {
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printk(KERN_CRIT "Invalid DMA channel for ser0\n");
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goto bail;
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}
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break;
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case dma_ser1:
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if (dmanr == SER1_TX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma8, serial1);
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} else if (dmanr == SER1_RX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma9, serial1);
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} else {
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printk(KERN_CRIT "Invalid DMA channel for ser1\n");
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goto bail;
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}
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break;
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case dma_ser2:
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if (dmanr == SER2_TX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma2, serial2);
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} else if (dmanr == SER2_RX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma3, serial2);
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} else {
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printk(KERN_CRIT "Invalid DMA channel for ser2\n");
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goto bail;
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}
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break;
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case dma_ser3:
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if (dmanr == SER3_TX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma4, serial3);
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} else if (dmanr == SER3_RX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma5, serial3);
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} else {
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printk(KERN_CRIT "Invalid DMA channel for ser3\n");
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goto bail;
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}
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break;
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case dma_ata:
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if (dmanr == ATA_TX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma2, ata);
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} else if (dmanr == ATA_RX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma3, ata);
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} else {
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printk(KERN_CRIT "Invalid DMA channel for ata\n");
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goto bail;
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}
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break;
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case dma_ext0:
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if (dmanr == EXTDMA0_TX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma4, extdma0);
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} else if (dmanr == EXTDMA0_RX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma5, extdma0);
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} else {
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printk(KERN_CRIT "Invalid DMA channel for ext0\n");
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goto bail;
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}
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break;
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case dma_ext1:
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if (dmanr == EXTDMA1_TX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma6, extdma1);
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} else if (dmanr == EXTDMA1_RX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma7, extdma1);
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} else {
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printk(KERN_CRIT "Invalid DMA channel for ext1\n");
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goto bail;
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}
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break;
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case dma_int6:
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if (dmanr == MEM2MEM_RX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma7, intdma6);
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} else {
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printk(KERN_CRIT "Invalid DMA channel for int6\n");
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goto bail;
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}
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break;
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case dma_int7:
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if (dmanr == MEM2MEM_TX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma6, intdma7);
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} else {
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printk(KERN_CRIT "Invalid DMA channel for int7\n");
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goto bail;
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}
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break;
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case dma_usb:
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if (dmanr == USB_TX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma8, usb);
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} else if (dmanr == USB_RX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma9, usb);
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} else {
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printk(KERN_CRIT "Invalid DMA channel for usb\n");
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goto bail;
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}
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break;
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case dma_scsi0:
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if (dmanr == SCSI0_TX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma2, scsi0);
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} else if (dmanr == SCSI0_RX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma3, scsi0);
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} else {
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printk(KERN_CRIT "Invalid DMA channel for scsi0\n");
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goto bail;
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}
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break;
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case dma_scsi1:
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if (dmanr == SCSI1_TX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma4, scsi1);
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} else if (dmanr == SCSI1_RX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma5, scsi1);
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} else {
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printk(KERN_CRIT "Invalid DMA channel for scsi1\n");
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goto bail;
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}
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break;
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case dma_par0:
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if (dmanr == PAR0_TX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma2, par0);
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} else if (dmanr == PAR0_RX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma3, par0);
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} else {
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printk(KERN_CRIT "Invalid DMA channel for par0\n");
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goto bail;
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}
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break;
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case dma_par1:
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if (dmanr == PAR1_TX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma4, par1);
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} else if (dmanr == PAR1_RX_DMA_NBR) {
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SETS(gens, R_GEN_CONFIG, dma5, par1);
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} else {
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printk(KERN_CRIT "Invalid DMA channel for par1\n");
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goto bail;
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}
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break;
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default:
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printk(KERN_CRIT "Invalid DMA owner.\n");
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goto bail;
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}
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used_dma_channels[dmanr] = 1;
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used_dma_channels_users[dmanr] = device_id;
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{
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volatile int i;
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genconfig_shadow = gens;
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*R_GEN_CONFIG = genconfig_shadow;
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/* Wait 12 cycles before doing any DMA command */
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for(i = 6; i > 0; i--)
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nop();
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}
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fail = 0;
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bail:
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local_irq_restore(flags);
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return fail;
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}
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void cris_free_dma(unsigned int dmanr, const char * device_id)
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{
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unsigned long flags;
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if (dmanr >= MAX_DMA_CHANNELS) {
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printk(KERN_CRIT "cris_free_dma: invalid DMA channel %u\n", dmanr);
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return;
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}
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local_irq_save(flags);
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if (!used_dma_channels[dmanr]) {
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printk(KERN_CRIT "cris_free_dma: DMA channel %u not allocated\n", dmanr);
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} else if (device_id != used_dma_channels_users[dmanr]) {
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printk(KERN_CRIT "cris_free_dma: DMA channel %u not allocated by device\n", dmanr);
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} else {
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switch(dmanr)
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{
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case 0:
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*R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, reset);
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while (IO_EXTRACT(R_DMA_CH0_CMD, cmd, *R_DMA_CH0_CMD) ==
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IO_STATE_VALUE(R_DMA_CH0_CMD, cmd, reset));
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break;
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case 1:
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*R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, reset);
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while (IO_EXTRACT(R_DMA_CH1_CMD, cmd, *R_DMA_CH1_CMD) ==
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IO_STATE_VALUE(R_DMA_CH1_CMD, cmd, reset));
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break;
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case 2:
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*R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, reset);
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while (IO_EXTRACT(R_DMA_CH2_CMD, cmd, *R_DMA_CH2_CMD) ==
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IO_STATE_VALUE(R_DMA_CH2_CMD, cmd, reset));
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break;
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case 3:
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*R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, reset);
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while (IO_EXTRACT(R_DMA_CH3_CMD, cmd, *R_DMA_CH3_CMD) ==
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IO_STATE_VALUE(R_DMA_CH3_CMD, cmd, reset));
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break;
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case 4:
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*R_DMA_CH4_CMD = IO_STATE(R_DMA_CH4_CMD, cmd, reset);
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while (IO_EXTRACT(R_DMA_CH4_CMD, cmd, *R_DMA_CH4_CMD) ==
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IO_STATE_VALUE(R_DMA_CH4_CMD, cmd, reset));
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break;
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case 5:
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*R_DMA_CH5_CMD = IO_STATE(R_DMA_CH5_CMD, cmd, reset);
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while (IO_EXTRACT(R_DMA_CH5_CMD, cmd, *R_DMA_CH5_CMD) ==
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IO_STATE_VALUE(R_DMA_CH5_CMD, cmd, reset));
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break;
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case 6:
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*R_DMA_CH6_CMD = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
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while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *R_DMA_CH6_CMD) ==
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IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
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break;
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case 7:
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*R_DMA_CH7_CMD = IO_STATE(R_DMA_CH7_CMD, cmd, reset);
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while (IO_EXTRACT(R_DMA_CH7_CMD, cmd, *R_DMA_CH7_CMD) ==
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IO_STATE_VALUE(R_DMA_CH7_CMD, cmd, reset));
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break;
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case 8:
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*R_DMA_CH8_CMD = IO_STATE(R_DMA_CH8_CMD, cmd, reset);
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while (IO_EXTRACT(R_DMA_CH8_CMD, cmd, *R_DMA_CH8_CMD) ==
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IO_STATE_VALUE(R_DMA_CH8_CMD, cmd, reset));
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break;
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case 9:
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*R_DMA_CH9_CMD = IO_STATE(R_DMA_CH9_CMD, cmd, reset);
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while (IO_EXTRACT(R_DMA_CH9_CMD, cmd, *R_DMA_CH9_CMD) ==
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IO_STATE_VALUE(R_DMA_CH9_CMD, cmd, reset));
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break;
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}
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used_dma_channels[dmanr] = 0;
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}
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL(cris_request_dma);
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EXPORT_SYMBOL(cris_free_dma);
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