mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 01:12:45 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
6
arch/cris/arch-v10/mm/Makefile
Normal file
6
arch/cris/arch-v10/mm/Makefile
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@ -0,0 +1,6 @@
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#
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# Makefile for the linux cris-specific parts of the memory manager.
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#
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obj-y := fault.o init.o tlb.o
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95
arch/cris/arch-v10/mm/fault.c
Normal file
95
arch/cris/arch-v10/mm/fault.c
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@ -0,0 +1,95 @@
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/*
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* linux/arch/cris/mm/fault.c
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*
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* Low level bus fault handler
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*
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*
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* Copyright (C) 2000-2007 Axis Communications AB
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*
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* Authors: Bjorn Wesen
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*
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*/
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#include <linux/mm.h>
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#include <asm/uaccess.h>
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#include <asm/pgtable.h>
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#include <arch/svinto.h>
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#include <asm/mmu_context.h>
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/* debug of low-level TLB reload */
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#undef DEBUG
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#ifdef DEBUG
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#define D(x) x
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#else
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#define D(x)
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#endif
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extern const struct exception_table_entry
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*search_exception_tables(unsigned long addr);
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asmlinkage void do_page_fault(unsigned long address, struct pt_regs *regs,
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int protection, int writeaccess);
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/* fast TLB-fill fault handler
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* this is called from entry.S with interrupts disabled
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*/
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void
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handle_mmu_bus_fault(struct pt_regs *regs)
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{
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int cause;
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int select;
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#ifdef DEBUG
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int index;
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int page_id;
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int acc, inv;
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#endif
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pgd_t* pgd = (pgd_t*)per_cpu(current_pgd, smp_processor_id());
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pmd_t *pmd;
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pte_t pte;
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int miss, we, writeac;
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unsigned long address;
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unsigned long flags;
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cause = *R_MMU_CAUSE;
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address = cause & PAGE_MASK; /* get faulting address */
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select = *R_TLB_SELECT;
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#ifdef DEBUG
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page_id = IO_EXTRACT(R_MMU_CAUSE, page_id, cause);
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acc = IO_EXTRACT(R_MMU_CAUSE, acc_excp, cause);
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inv = IO_EXTRACT(R_MMU_CAUSE, inv_excp, cause);
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index = IO_EXTRACT(R_TLB_SELECT, index, select);
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#endif
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miss = IO_EXTRACT(R_MMU_CAUSE, miss_excp, cause);
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we = IO_EXTRACT(R_MMU_CAUSE, we_excp, cause);
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writeac = IO_EXTRACT(R_MMU_CAUSE, wr_rd, cause);
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D(printk("bus_fault from IRP 0x%lx: addr 0x%lx, miss %d, inv %d, we %d, acc %d, dx %d pid %d\n",
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regs->irp, address, miss, inv, we, acc, index, page_id));
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/* leave it to the MM system fault handler */
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if (miss)
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do_page_fault(address, regs, 0, writeac);
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else
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do_page_fault(address, regs, 1, we);
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/* Reload TLB with new entry to avoid an extra miss exception.
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* do_page_fault may have flushed the TLB so we have to restore
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* the MMU registers.
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*/
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local_irq_save(flags);
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pmd = (pmd_t *)(pgd + pgd_index(address));
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if (pmd_none(*pmd))
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goto exit;
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pte = *pte_offset_kernel(pmd, address);
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if (!pte_present(pte))
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goto exit;
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*R_TLB_SELECT = select;
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*R_TLB_HI = cause;
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*R_TLB_LO = pte_val(pte);
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exit:
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local_irq_restore(flags);
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}
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263
arch/cris/arch-v10/mm/init.c
Normal file
263
arch/cris/arch-v10/mm/init.c
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@ -0,0 +1,263 @@
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/*
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* linux/arch/cris/arch-v10/mm/init.c
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*
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*/
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#include <linux/mmzone.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/mm.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/types.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <asm/mmu_context.h>
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#include <arch/svinto.h>
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extern void tlb_init(void);
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/*
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* The kernel is already mapped with a kernel segment at kseg_c so
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* we don't need to map it with a page table. However head.S also
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* temporarily mapped it at kseg_4 so we should set up the ksegs again,
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* clear the TLB and do some other paging setup stuff.
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*/
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void __init
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paging_init(void)
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{
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int i;
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unsigned long zones_size[MAX_NR_ZONES];
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printk("Setting up paging and the MMU.\n");
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/* clear out the init_mm.pgd that will contain the kernel's mappings */
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for(i = 0; i < PTRS_PER_PGD; i++)
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swapper_pg_dir[i] = __pgd(0);
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/* make sure the current pgd table points to something sane
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* (even if it is most probably not used until the next
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* switch_mm)
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*/
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per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd;
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/* initialise the TLB (tlb.c) */
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tlb_init();
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/* see README.mm for details on the KSEG setup */
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#ifdef CONFIG_CRIS_LOW_MAP
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/* Etrax-100 LX version 1 has a bug so that we cannot map anything
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* across the 0x80000000 boundary, so we need to shrink the user-virtual
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* area to 0x50000000 instead of 0xb0000000 and map things slightly
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* different. The unused areas are marked as paged so that we can catch
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* freak kernel accesses there.
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*
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* The ARTPEC chip is mapped at 0xa so we pass that segment straight
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* through. We cannot vremap it because the vmalloc area is below 0x8
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* and Juliette needs an uncached area above 0x8.
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*
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* Same thing with 0xc and 0x9, which is memory-mapped I/O on some boards.
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* We map them straight over in LOW_MAP, but use vremap in LX version 2.
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*/
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#define CACHED_BOOTROM (KSEG_F | 0x08000000UL)
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*R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* bootrom */
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IO_STATE(R_MMU_KSEG, seg_e, page ) |
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IO_STATE(R_MMU_KSEG, seg_d, page ) |
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IO_STATE(R_MMU_KSEG, seg_c, page ) |
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IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */
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#ifdef CONFIG_JULIETTE
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IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* ARTPEC etc. */
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#else
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IO_STATE(R_MMU_KSEG, seg_a, page ) |
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#endif
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IO_STATE(R_MMU_KSEG, seg_9, seg ) | /* LED's on some boards */
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IO_STATE(R_MMU_KSEG, seg_8, seg ) | /* CSE0/1, flash and I/O */
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IO_STATE(R_MMU_KSEG, seg_7, page ) | /* kernel vmalloc area */
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IO_STATE(R_MMU_KSEG, seg_6, seg ) | /* kernel DRAM area */
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IO_STATE(R_MMU_KSEG, seg_5, seg ) | /* cached flash */
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IO_STATE(R_MMU_KSEG, seg_4, page ) | /* user area */
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IO_STATE(R_MMU_KSEG, seg_3, page ) | /* user area */
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IO_STATE(R_MMU_KSEG, seg_2, page ) | /* user area */
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IO_STATE(R_MMU_KSEG, seg_1, page ) | /* user area */
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IO_STATE(R_MMU_KSEG, seg_0, page ) ); /* user area */
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*R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x3 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_e, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_c, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) |
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#ifdef CONFIG_JULIETTE
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IO_FIELD(R_MMU_KBASE_HI, base_a, 0xa ) |
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#else
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IO_FIELD(R_MMU_KBASE_HI, base_a, 0x0 ) |
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#endif
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IO_FIELD(R_MMU_KBASE_HI, base_9, 0x9 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_8, 0x8 ) );
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*R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_6, 0x4 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_4, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_3, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_2, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_1, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_0, 0x0 ) );
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#else
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/* This code is for the corrected Etrax-100 LX version 2... */
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#define CACHED_BOOTROM (KSEG_A | 0x08000000UL)
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*R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* cached flash */
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IO_STATE(R_MMU_KSEG, seg_e, seg ) | /* uncached flash */
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IO_STATE(R_MMU_KSEG, seg_d, page ) | /* vmalloc area */
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IO_STATE(R_MMU_KSEG, seg_c, seg ) | /* kernel area */
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IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */
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IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* bootrom */
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IO_STATE(R_MMU_KSEG, seg_9, page ) | /* user area */
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IO_STATE(R_MMU_KSEG, seg_8, page ) |
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IO_STATE(R_MMU_KSEG, seg_7, page ) |
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IO_STATE(R_MMU_KSEG, seg_6, page ) |
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IO_STATE(R_MMU_KSEG, seg_5, page ) |
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IO_STATE(R_MMU_KSEG, seg_4, page ) |
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IO_STATE(R_MMU_KSEG, seg_3, page ) |
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IO_STATE(R_MMU_KSEG, seg_2, page ) |
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IO_STATE(R_MMU_KSEG, seg_1, page ) |
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IO_STATE(R_MMU_KSEG, seg_0, page ) );
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*R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_e, 0x8 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_c, 0x4 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) |
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IO_FIELD(R_MMU_KBASE_HI, base_a, 0x3 ) |
|
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IO_FIELD(R_MMU_KBASE_HI, base_9, 0x0 ) |
|
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IO_FIELD(R_MMU_KBASE_HI, base_8, 0x0 ) );
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||||
|
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*R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) |
|
||||
IO_FIELD(R_MMU_KBASE_LO, base_6, 0x0 ) |
|
||||
IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) |
|
||||
IO_FIELD(R_MMU_KBASE_LO, base_4, 0x0 ) |
|
||||
IO_FIELD(R_MMU_KBASE_LO, base_3, 0x0 ) |
|
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IO_FIELD(R_MMU_KBASE_LO, base_2, 0x0 ) |
|
||||
IO_FIELD(R_MMU_KBASE_LO, base_1, 0x0 ) |
|
||||
IO_FIELD(R_MMU_KBASE_LO, base_0, 0x0 ) );
|
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#endif
|
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|
||||
*R_MMU_CONTEXT = ( IO_FIELD(R_MMU_CONTEXT, page_id, 0 ) );
|
||||
|
||||
/* The MMU has been enabled ever since head.S but just to make
|
||||
* it totally obvious we do it here as well.
|
||||
*/
|
||||
|
||||
*R_MMU_CTRL = ( IO_STATE(R_MMU_CTRL, inv_excp, enable ) |
|
||||
IO_STATE(R_MMU_CTRL, acc_excp, enable ) |
|
||||
IO_STATE(R_MMU_CTRL, we_excp, enable ) );
|
||||
|
||||
*R_MMU_ENABLE = IO_STATE(R_MMU_ENABLE, mmu_enable, enable);
|
||||
|
||||
/*
|
||||
* initialize the bad page table and bad page to point
|
||||
* to a couple of allocated pages
|
||||
*/
|
||||
|
||||
empty_zero_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
|
||||
memset((void *)empty_zero_page, 0, PAGE_SIZE);
|
||||
|
||||
/* All pages are DMA'able in Etrax, so put all in the DMA'able zone */
|
||||
|
||||
zones_size[0] = ((unsigned long)high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
|
||||
|
||||
for (i = 1; i < MAX_NR_ZONES; i++)
|
||||
zones_size[i] = 0;
|
||||
|
||||
/* Use free_area_init_node instead of free_area_init, because the former
|
||||
* is designed for systems where the DRAM starts at an address substantially
|
||||
* higher than 0, like us (we start at PAGE_OFFSET). This saves space in the
|
||||
* mem_map page array.
|
||||
*/
|
||||
|
||||
free_area_init_node(0, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0);
|
||||
}
|
||||
|
||||
/* Initialize remaps of some I/O-ports. It is important that this
|
||||
* is called before any driver is initialized.
|
||||
*/
|
||||
|
||||
static int
|
||||
__init init_ioremap(void)
|
||||
{
|
||||
|
||||
/* Give the external I/O-port addresses their values */
|
||||
|
||||
#ifdef CONFIG_CRIS_LOW_MAP
|
||||
/* Simply a linear map (see the KSEG map above in paging_init) */
|
||||
port_cse1_addr = (volatile unsigned long *)(MEM_CSE1_START |
|
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MEM_NON_CACHEABLE);
|
||||
port_csp0_addr = (volatile unsigned long *)(MEM_CSP0_START |
|
||||
MEM_NON_CACHEABLE);
|
||||
port_csp4_addr = (volatile unsigned long *)(MEM_CSP4_START |
|
||||
MEM_NON_CACHEABLE);
|
||||
#else
|
||||
/* Note that nothing blows up just because we do this remapping
|
||||
* it's ok even if the ports are not used or connected
|
||||
* to anything (or connected to a non-I/O thing) */
|
||||
port_cse1_addr = (volatile unsigned long *)
|
||||
ioremap((unsigned long)(MEM_CSE1_START | MEM_NON_CACHEABLE), 16);
|
||||
port_csp0_addr = (volatile unsigned long *)
|
||||
ioremap((unsigned long)(MEM_CSP0_START | MEM_NON_CACHEABLE), 16);
|
||||
port_csp4_addr = (volatile unsigned long *)
|
||||
ioremap((unsigned long)(MEM_CSP4_START | MEM_NON_CACHEABLE), 16);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
__initcall(init_ioremap);
|
||||
|
||||
/* Helper function for the two below */
|
||||
|
||||
static inline void
|
||||
flush_etrax_cacherange(void *startadr, int length)
|
||||
{
|
||||
/* CACHED_BOOTROM is mapped to the boot-rom area (cached) which
|
||||
* we can use to get fast dummy-reads of cachelines
|
||||
*/
|
||||
|
||||
volatile short *flushadr = (volatile short *)(((unsigned long)startadr & ~PAGE_MASK) |
|
||||
CACHED_BOOTROM);
|
||||
|
||||
length = length > 8192 ? 8192 : length; /* No need to flush more than cache size */
|
||||
|
||||
while(length > 0) {
|
||||
*flushadr; /* dummy read to flush */
|
||||
flushadr += (32/sizeof(short)); /* a cacheline is 32 bytes */
|
||||
length -= 32;
|
||||
}
|
||||
}
|
||||
|
||||
/* Due to a bug in Etrax100(LX) all versions, receiving DMA buffers
|
||||
* will occasionally corrupt certain CPU writes if the DMA buffers
|
||||
* happen to be hot in the cache.
|
||||
*
|
||||
* As a workaround, we have to flush the relevant parts of the cache
|
||||
* before (re) inserting any receiving descriptor into the DMA HW.
|
||||
*/
|
||||
|
||||
void
|
||||
prepare_rx_descriptor(struct etrax_dma_descr *desc)
|
||||
{
|
||||
flush_etrax_cacherange((void *)desc->buf, desc->sw_len ? desc->sw_len : 65536);
|
||||
}
|
||||
|
||||
/* Do the same thing but flush the entire cache */
|
||||
|
||||
void
|
||||
flush_etrax_cache(void)
|
||||
{
|
||||
flush_etrax_cacherange(0, 8192);
|
||||
}
|
||||
176
arch/cris/arch-v10/mm/tlb.c
Normal file
176
arch/cris/arch-v10/mm/tlb.c
Normal file
|
|
@ -0,0 +1,176 @@
|
|||
/*
|
||||
* linux/arch/cris/arch-v10/mm/tlb.c
|
||||
*
|
||||
* Low level TLB handling
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2000-2007 Axis Communications AB
|
||||
*
|
||||
* Authors: Bjorn Wesen (bjornw@axis.com)
|
||||
*
|
||||
*/
|
||||
|
||||
#include <asm/tlb.h>
|
||||
#include <asm/mmu_context.h>
|
||||
#include <arch/svinto.h>
|
||||
|
||||
#define D(x)
|
||||
|
||||
/* The TLB can host up to 64 different mm contexts at the same time.
|
||||
* The running context is R_MMU_CONTEXT, and each TLB entry contains a
|
||||
* page_id that has to match to give a hit. In page_id_map, we keep track
|
||||
* of which mm's we have assigned which page_id's, so that we know when
|
||||
* to invalidate TLB entries.
|
||||
*
|
||||
* The last page_id is never running - it is used as an invalid page_id
|
||||
* so we can make TLB entries that will never match.
|
||||
*
|
||||
* Notice that we need to make the flushes atomic, otherwise an interrupt
|
||||
* handler that uses vmalloced memory might cause a TLB load in the middle
|
||||
* of a flush causing.
|
||||
*/
|
||||
|
||||
/* invalidate all TLB entries */
|
||||
|
||||
void
|
||||
flush_tlb_all(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long flags;
|
||||
|
||||
/* the vpn of i & 0xf is so we dont write similar TLB entries
|
||||
* in the same 4-way entry group. details...
|
||||
*/
|
||||
|
||||
local_irq_save(flags);
|
||||
for(i = 0; i < NUM_TLB_ENTRIES; i++) {
|
||||
*R_TLB_SELECT = ( IO_FIELD(R_TLB_SELECT, index, i) );
|
||||
*R_TLB_HI = ( IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) |
|
||||
IO_FIELD(R_TLB_HI, vpn, i & 0xf ) );
|
||||
|
||||
*R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) |
|
||||
IO_STATE(R_TLB_LO, valid, no ) |
|
||||
IO_STATE(R_TLB_LO, kernel,no ) |
|
||||
IO_STATE(R_TLB_LO, we, no ) |
|
||||
IO_FIELD(R_TLB_LO, pfn, 0 ) );
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
D(printk("tlb: flushed all\n"));
|
||||
}
|
||||
|
||||
/* invalidate the selected mm context only */
|
||||
|
||||
void
|
||||
flush_tlb_mm(struct mm_struct *mm)
|
||||
{
|
||||
int i;
|
||||
int page_id = mm->context.page_id;
|
||||
unsigned long flags;
|
||||
|
||||
D(printk("tlb: flush mm context %d (%p)\n", page_id, mm));
|
||||
|
||||
if(page_id == NO_CONTEXT)
|
||||
return;
|
||||
|
||||
/* mark the TLB entries that match the page_id as invalid.
|
||||
* here we could also check the _PAGE_GLOBAL bit and NOT flush
|
||||
* global pages. is it worth the extra I/O ?
|
||||
*/
|
||||
|
||||
local_irq_save(flags);
|
||||
for(i = 0; i < NUM_TLB_ENTRIES; i++) {
|
||||
*R_TLB_SELECT = IO_FIELD(R_TLB_SELECT, index, i);
|
||||
if (IO_EXTRACT(R_TLB_HI, page_id, *R_TLB_HI) == page_id) {
|
||||
*R_TLB_HI = ( IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) |
|
||||
IO_FIELD(R_TLB_HI, vpn, i & 0xf ) );
|
||||
|
||||
*R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) |
|
||||
IO_STATE(R_TLB_LO, valid, no ) |
|
||||
IO_STATE(R_TLB_LO, kernel,no ) |
|
||||
IO_STATE(R_TLB_LO, we, no ) |
|
||||
IO_FIELD(R_TLB_LO, pfn, 0 ) );
|
||||
}
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
/* invalidate a single page */
|
||||
|
||||
void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
|
||||
{
|
||||
struct mm_struct *mm = vma->vm_mm;
|
||||
int page_id = mm->context.page_id;
|
||||
int i;
|
||||
unsigned long flags;
|
||||
|
||||
D(printk("tlb: flush page %p in context %d (%p)\n", addr, page_id, mm));
|
||||
|
||||
if(page_id == NO_CONTEXT)
|
||||
return;
|
||||
|
||||
addr &= PAGE_MASK; /* perhaps not necessary */
|
||||
|
||||
/* invalidate those TLB entries that match both the mm context
|
||||
* and the virtual address requested
|
||||
*/
|
||||
|
||||
local_irq_save(flags);
|
||||
for(i = 0; i < NUM_TLB_ENTRIES; i++) {
|
||||
unsigned long tlb_hi;
|
||||
*R_TLB_SELECT = IO_FIELD(R_TLB_SELECT, index, i);
|
||||
tlb_hi = *R_TLB_HI;
|
||||
if (IO_EXTRACT(R_TLB_HI, page_id, tlb_hi) == page_id &&
|
||||
(tlb_hi & PAGE_MASK) == addr) {
|
||||
*R_TLB_HI = IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) |
|
||||
addr; /* same addr as before works. */
|
||||
|
||||
*R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) |
|
||||
IO_STATE(R_TLB_LO, valid, no ) |
|
||||
IO_STATE(R_TLB_LO, kernel,no ) |
|
||||
IO_STATE(R_TLB_LO, we, no ) |
|
||||
IO_FIELD(R_TLB_LO, pfn, 0 ) );
|
||||
}
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize the context related info for a new mm_struct
|
||||
* instance.
|
||||
*/
|
||||
|
||||
int
|
||||
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
|
||||
{
|
||||
mm->context.page_id = NO_CONTEXT;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* called in schedule() just before actually doing the switch_to */
|
||||
|
||||
void switch_mm(struct mm_struct *prev, struct mm_struct *next,
|
||||
struct task_struct *tsk)
|
||||
{
|
||||
if (prev != next) {
|
||||
/* make sure we have a context */
|
||||
get_mmu_context(next);
|
||||
|
||||
/* remember the pgd for the fault handlers
|
||||
* this is similar to the pgd register in some other CPU's.
|
||||
* we need our own copy of it because current and active_mm
|
||||
* might be invalid at points where we still need to derefer
|
||||
* the pgd.
|
||||
*/
|
||||
|
||||
per_cpu(current_pgd, smp_processor_id()) = next->pgd;
|
||||
|
||||
/* switch context in the MMU */
|
||||
|
||||
D(printk(KERN_DEBUG "switching mmu_context to %d (%p)\n",
|
||||
next->context, next));
|
||||
|
||||
*R_MMU_CONTEXT = IO_FIELD(R_MMU_CONTEXT,
|
||||
page_id, next->context.page_id);
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue