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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 17:32:46 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
191
arch/cris/arch-v32/mach-fs/io.c
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191
arch/cris/arch-v32/mach-fs/io.c
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@ -0,0 +1,191 @@
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/*
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* Helper functions for I/O pins.
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*
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* Copyright (c) 2004-2007 Axis Communications AB.
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*/
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/string.h>
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#include <linux/ctype.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <asm/io.h>
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#include <mach/pinmux.h>
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#include <hwregs/gio_defs.h>
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#ifndef DEBUG
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#define DEBUG(x)
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#endif
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struct crisv32_ioport crisv32_ioports[] = {
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{
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(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_oe),
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(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_dout),
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(unsigned long *)REG_ADDR(gio, regi_gio, r_pa_din),
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8
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},
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{
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(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_oe),
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(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_dout),
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(unsigned long *)REG_ADDR(gio, regi_gio, r_pb_din),
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18
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},
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{
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(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_oe),
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(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_dout),
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(unsigned long *)REG_ADDR(gio, regi_gio, r_pc_din),
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18
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},
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{
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(unsigned long *)REG_ADDR(gio, regi_gio, rw_pd_oe),
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(unsigned long *)REG_ADDR(gio, regi_gio, rw_pd_dout),
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(unsigned long *)REG_ADDR(gio, regi_gio, r_pd_din),
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18
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},
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{
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(unsigned long *)REG_ADDR(gio, regi_gio, rw_pe_oe),
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(unsigned long *)REG_ADDR(gio, regi_gio, rw_pe_dout),
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(unsigned long *)REG_ADDR(gio, regi_gio, r_pe_din),
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18
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}
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};
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#define NBR_OF_PORTS ARRAY_SIZE(crisv32_ioports)
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struct crisv32_iopin crisv32_led_net0_green;
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struct crisv32_iopin crisv32_led_net0_red;
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struct crisv32_iopin crisv32_led_net1_green;
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struct crisv32_iopin crisv32_led_net1_red;
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struct crisv32_iopin crisv32_led2_green;
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struct crisv32_iopin crisv32_led2_red;
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struct crisv32_iopin crisv32_led3_green;
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struct crisv32_iopin crisv32_led3_red;
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/* Dummy port used when green LED and red LED is on the same bit */
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static unsigned long io_dummy;
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static struct crisv32_ioport dummy_port = {
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&io_dummy,
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&io_dummy,
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&io_dummy,
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18
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};
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static struct crisv32_iopin dummy_led = {
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&dummy_port,
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0
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};
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static int __init crisv32_io_init(void)
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{
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int ret = 0;
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u32 i;
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/* Locks *should* be dynamically initialized. */
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for (i = 0; i < ARRAY_SIZE(crisv32_ioports); i++)
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spin_lock_init(&crisv32_ioports[i].lock);
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spin_lock_init(&dummy_port.lock);
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/* Initialize LEDs */
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#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
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ret +=
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crisv32_io_get_name(&crisv32_led_net0_green,
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CONFIG_ETRAX_LED_G_NET0);
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crisv32_io_set_dir(&crisv32_led_net0_green, crisv32_io_dir_out);
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if (strcmp(CONFIG_ETRAX_LED_G_NET0, CONFIG_ETRAX_LED_R_NET0)) {
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ret +=
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crisv32_io_get_name(&crisv32_led_net0_red,
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CONFIG_ETRAX_LED_R_NET0);
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crisv32_io_set_dir(&crisv32_led_net0_red, crisv32_io_dir_out);
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} else
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crisv32_led_net0_red = dummy_led;
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#endif
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#ifdef CONFIG_ETRAX_NBR_LED_GRP_TWO
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ret +=
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crisv32_io_get_name(&crisv32_led_net1_green,
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CONFIG_ETRAX_LED_G_NET1);
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crisv32_io_set_dir(&crisv32_led_net1_green, crisv32_io_dir_out);
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if (strcmp(CONFIG_ETRAX_LED_G_NET1, CONFIG_ETRAX_LED_R_NET1)) {
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crisv32_io_get_name(&crisv32_led_net1_red,
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CONFIG_ETRAX_LED_R_NET1);
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crisv32_io_set_dir(&crisv32_led_net1_red, crisv32_io_dir_out);
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} else
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crisv32_led_net1_red = dummy_led;
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#endif
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ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_V32_LED2G);
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ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_V32_LED2R);
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ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_V32_LED3G);
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ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_V32_LED3R);
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crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out);
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crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out);
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crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out);
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crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out);
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return ret;
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}
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__initcall(crisv32_io_init);
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int crisv32_io_get(struct crisv32_iopin *iopin,
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unsigned int port, unsigned int pin)
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{
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if (port > NBR_OF_PORTS)
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return -EINVAL;
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if (port > crisv32_ioports[port].pin_count)
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return -EINVAL;
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iopin->bit = 1 << pin;
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iopin->port = &crisv32_ioports[port];
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/* Only allocate pinmux gpiopins if port != PORT_A (port 0) */
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/* NOTE! crisv32_pinmux_alloc thinks PORT_B is port 0 */
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if (port != 0 && crisv32_pinmux_alloc(port - 1, pin, pin, pinmux_gpio))
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return -EIO;
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DEBUG(printk(KERN_DEBUG "crisv32_io_get: Allocated pin %d on port %d\n",
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pin, port));
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return 0;
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}
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int crisv32_io_get_name(struct crisv32_iopin *iopin, const char *name)
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{
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int port;
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int pin;
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if (toupper(*name) == 'P')
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name++;
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if (toupper(*name) < 'A' || toupper(*name) > 'E')
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return -EINVAL;
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port = toupper(*name) - 'A';
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name++;
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pin = simple_strtoul(name, NULL, 10);
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if (pin < 0 || pin > crisv32_ioports[port].pin_count)
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return -EINVAL;
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iopin->bit = 1 << pin;
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iopin->port = &crisv32_ioports[port];
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/* Only allocate pinmux gpiopins if port != PORT_A (port 0) */
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/* NOTE! crisv32_pinmux_alloc thinks PORT_B is port 0 */
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if (port != 0 && crisv32_pinmux_alloc(port - 1, pin, pin, pinmux_gpio))
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return -EIO;
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DEBUG(printk(KERN_DEBUG
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"crisv32_io_get_name: Allocated pin %d on port %d\n",
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pin, port));
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return 0;
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}
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#ifdef CONFIG_PCI
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/* PCI I/O access stuff */
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struct cris_io_operations *cris_iops = NULL;
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EXPORT_SYMBOL(cris_iops);
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#endif
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