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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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1
arch/cris/include/arch-v10/arch/Kbuild Normal file
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# CRISv10 arch

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arch/cris/include/arch-v10/arch/atomic.h Normal file
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#ifndef __ASM_CRIS_ARCH_ATOMIC__
#define __ASM_CRIS_ARCH_ATOMIC__
#define cris_atomic_save(addr, flags) local_irq_save(flags);
#define cris_atomic_restore(addr, flags) local_irq_restore(flags);
#endif

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arch/cris/include/arch-v10/arch/bitops.h Normal file
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/* asm/arch/bitops.h for Linux/CRISv10 */
#ifndef _CRIS_ARCH_BITOPS_H
#define _CRIS_ARCH_BITOPS_H
/*
* Helper functions for the core of the ff[sz] functions, wrapping the
* syntactically awkward asms. The asms compute the number of leading
* zeroes of a bits-in-byte and byte-in-word and word-in-dword-swapped
* number. They differ in that the first function also inverts all bits
* in the input.
*/
static inline unsigned long cris_swapnwbrlz(unsigned long w)
{
/* Let's just say we return the result in the same register as the
input. Saying we clobber the input but can return the result
in another register:
! __asm__ ("swapnwbr %2\n\tlz %2,%0"
! : "=r,r" (res), "=r,X" (dummy) : "1,0" (w));
confuses gcc (core.c, gcc from cris-dist-1.14). */
unsigned long res;
__asm__ ("swapnwbr %0 \n\t"
"lz %0,%0"
: "=r" (res) : "0" (w));
return res;
}
static inline unsigned long cris_swapwbrlz(unsigned long w)
{
unsigned res;
__asm__ ("swapwbr %0 \n\t"
"lz %0,%0"
: "=r" (res)
: "0" (w));
return res;
}
/*
* ffz = Find First Zero in word. Undefined if no zero exists,
* so code should check against ~0UL first..
*/
static inline unsigned long ffz(unsigned long w)
{
return cris_swapnwbrlz(w);
}
/**
* __ffs - find first bit in word.
* @word: The word to search
*
* Undefined if no bit exists, so code should check against 0 first.
*/
static inline unsigned long __ffs(unsigned long word)
{
return cris_swapnwbrlz(~word);
}
/**
* ffs - find first bit set
* @x: the word to search
*
* This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
static inline unsigned long kernel_ffs(unsigned long w)
{
return w ? cris_swapwbrlz (w) + 1 : 0;
}
#endif

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arch/cris/include/arch-v10/arch/bug.h Normal file
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#ifndef __ASM_CRISv10_ARCH_BUG_H
#define __ASM_CRISv10_ARCH_BUG_H
#include <linux/stringify.h>
#ifdef CONFIG_BUG
#ifdef CONFIG_DEBUG_BUGVERBOSE
/* The BUG() macro is used for marking obviously incorrect code paths.
* It will cause a message with the file name and line number to be printed,
* and then cause an oops. The message is actually printed by handle_BUG()
* in arch/cris/kernel/traps.c, and the reason we use this method of storing
* the file name and line number is that we do not want to affect the registers
* by calling printk() before causing the oops.
*/
#define BUG_PREFIX 0x0D7F
#define BUG_MAGIC 0x00001234
struct bug_frame {
unsigned short prefix;
unsigned int magic;
unsigned short clear;
unsigned short movu;
unsigned short line;
unsigned short jump;
unsigned char *filename;
};
#if 0
/* Unfortunately this version of the macro does not work due to a problem
* with the compiler (aka a bug) when compiling with -O2, which sometimes
* erroneously causes the second input to be stored in a register...
*/
#define BUG() \
__asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\
"movu.w %0,$r0\n\t" \
"jump %1\n\t" \
: : "i" (__LINE__), "i" (__FILE__))
#else
/* This version will have to do for now, until the compiler is fixed.
* The drawbacks of this version are that the file name will appear multiple
* times in the .rodata section, and that __LINE__ and __FILE__ can probably
* not be used like this with newer versions of gcc.
*/
#define BUG() \
__asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\
"movu.w " __stringify(__LINE__) ",$r0\n\t"\
"jump 0f\n\t" \
".section .rodata\n" \
"0:\t.string \"" __FILE__ "\"\n\t" \
".previous")
#endif
#else
/* This just causes an oops. */
#define BUG() (*(int *)0 = 0)
#endif
#define HAVE_ARCH_BUG
#endif
#include <asm-generic/bug.h>
#endif

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arch/cris/include/arch-v10/arch/cache.h Normal file
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#ifndef _ASM_ARCH_CACHE_H
#define _ASM_ARCH_CACHE_H
/* Etrax 100LX have 32-byte cache-lines. */
#define L1_CACHE_BYTES 32
#define L1_CACHE_SHIFT 5
#endif /* _ASM_ARCH_CACHE_H */

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arch/cris/include/arch-v10/arch/checksum.h Normal file
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#ifndef _CRIS_ARCH_CHECKSUM_H
#define _CRIS_ARCH_CHECKSUM_H
/* Checksum some values used in TCP/UDP headers.
*
* The gain by doing this in asm is that C will not generate carry-additions
* for the 32-bit components of the checksum, so otherwise we would have had
* to split all of those into 16-bit components, then add.
*/
static inline __wsum
csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
unsigned short proto, __wsum sum)
{
__wsum res;
__asm__ ("add.d %2, %0\n\t"
"ax\n\t"
"add.d %3, %0\n\t"
"ax\n\t"
"add.d %4, %0\n\t"
"ax\n\t"
"addq 0, %0\n"
: "=r" (res)
: "0" (sum), "r" (daddr), "r" (saddr), "r" ((len + proto) << 8));
return res;
}
#endif

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arch/cris/include/arch-v10/arch/delay.h Normal file
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#ifndef _CRIS_ARCH_DELAY_H
#define _CRIS_ARCH_DELAY_H
static inline void __delay(int loops)
{
__asm__ __volatile__ (
"move.d %0,$r9\n\t"
"beq 2f\n\t"
"subq 1,$r9\n\t"
"1:\n\t"
"bne 1b\n\t"
"subq 1,$r9\n"
"2:"
: : "g" (loops) : "r9");
}
#endif /* defined(_CRIS_ARCH_DELAY_H) */

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arch/cris/include/arch-v10/arch/dma.h Normal file
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/* Defines for using and allocating dma channels. */
#ifndef _ASM_ARCH_DMA_H
#define _ASM_ARCH_DMA_H
#define MAX_DMA_CHANNELS 10
/* dma0 and dma1 used for network (ethernet) */
#define NETWORK_TX_DMA_NBR 0
#define NETWORK_RX_DMA_NBR 1
/* dma2 and dma3 shared by par0, scsi0, ser2 and ata */
#define PAR0_TX_DMA_NBR 2
#define PAR0_RX_DMA_NBR 3
#define SCSI0_TX_DMA_NBR 2
#define SCSI0_RX_DMA_NBR 3
#define SER2_TX_DMA_NBR 2
#define SER2_RX_DMA_NBR 3
#define ATA_TX_DMA_NBR 2
#define ATA_RX_DMA_NBR 3
/* dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */
#define PAR1_TX_DMA_NBR 4
#define PAR1_RX_DMA_NBR 5
#define SCSI1_TX_DMA_NBR 4
#define SCSI1_RX_DMA_NBR 5
#define SER3_TX_DMA_NBR 4
#define SER3_RX_DMA_NBR 5
#define EXTDMA0_TX_DMA_NBR 4
#define EXTDMA0_RX_DMA_NBR 5
/* dma6 and dma7 shared by ser0, extdma1 and mem2mem */
#define SER0_TX_DMA_NBR 6
#define SER0_RX_DMA_NBR 7
#define EXTDMA1_TX_DMA_NBR 6
#define EXTDMA1_RX_DMA_NBR 7
#define MEM2MEM_TX_DMA_NBR 6
#define MEM2MEM_RX_DMA_NBR 7
/* dma8 and dma9 shared by ser1 and usb */
#define SER1_TX_DMA_NBR 8
#define SER1_RX_DMA_NBR 9
#define USB_TX_DMA_NBR 8
#define USB_RX_DMA_NBR 9
#endif
enum dma_owner
{
dma_eth,
dma_ser0,
dma_ser1, /* Async and sync */
dma_ser2,
dma_ser3, /* Async and sync */
dma_ata,
dma_par0,
dma_par1,
dma_ext0,
dma_ext1,
dma_int6,
dma_int7,
dma_usb,
dma_scsi0,
dma_scsi1
};
/* Masks used by cris_request_dma options: */
#define DMA_VERBOSE_ON_ERROR (1<<0)
#define DMA_PANIC_ON_ERROR ((1<<1)|DMA_VERBOSE_ON_ERROR)
int cris_request_dma(unsigned int dmanr, const char * device_id,
unsigned options, enum dma_owner owner);
void cris_free_dma(unsigned int dmanr, const char * device_id);

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arch/cris/include/arch-v10/arch/elf.h Normal file
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#ifndef __ASMCRIS_ARCH_ELF_H
#define __ASMCRIS_ARCH_ELF_H
#include <arch/system.h>
#define ELF_MACH EF_CRIS_VARIANT_ANY_V0_V10
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch(x) \
((x)->e_machine == EM_CRIS \
&& ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_ANY_V0_V10 \
|| (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32))))
/*
* ELF register definitions..
*/
#include <asm/ptrace.h>
/* SVR4/i386 ABI (pages 3-31, 3-32) says that when the program
starts (a register; assume first param register for CRIS)
contains a pointer to a function which might be
registered using `atexit'. This provides a mean for the
dynamic linker to call DT_FINI functions for shared libraries
that have been loaded before the code runs.
A value of 0 tells we have no such handler. */
/* Explicitly set registers to 0 to increase determinism. */
#define ELF_PLAT_INIT(_r, load_addr) do { \
(_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \
(_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \
(_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \
(_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \
} while (0)
/* The additional layer below is because the stack pointer is missing in
the pt_regs struct, but needed in a core dump. pr_reg is a elf_gregset_t,
and should be filled in according to the layout of the user_regs_struct
struct; regs is a pt_regs struct. We dump all registers, though several are
obviously unnecessary. That way there's less need for intelligence at
the receiving end (i.e. gdb). */
#define ELF_CORE_COPY_REGS(pr_reg, regs) \
pr_reg[0] = regs->r0; \
pr_reg[1] = regs->r1; \
pr_reg[2] = regs->r2; \
pr_reg[3] = regs->r3; \
pr_reg[4] = regs->r4; \
pr_reg[5] = regs->r5; \
pr_reg[6] = regs->r6; \
pr_reg[7] = regs->r7; \
pr_reg[8] = regs->r8; \
pr_reg[9] = regs->r9; \
pr_reg[10] = regs->r10; \
pr_reg[11] = regs->r11; \
pr_reg[12] = regs->r12; \
pr_reg[13] = regs->r13; \
pr_reg[14] = rdusp(); /* sp */ \
pr_reg[15] = regs->irp; /* pc */ \
pr_reg[16] = 0; /* p0 */ \
pr_reg[17] = rdvr(); /* vr */ \
pr_reg[18] = 0; /* p2 */ \
pr_reg[19] = 0; /* p3 */ \
pr_reg[20] = 0; /* p4 */ \
pr_reg[21] = (regs->dccr & 0xffff); /* ccr */ \
pr_reg[22] = 0; /* p6 */ \
pr_reg[23] = regs->mof; /* mof */ \
pr_reg[24] = 0; /* p8 */ \
pr_reg[25] = 0; /* ibr */ \
pr_reg[26] = 0; /* irp */ \
pr_reg[27] = regs->srp; /* srp */ \
pr_reg[28] = 0; /* bar */ \
pr_reg[29] = regs->dccr; /* dccr */ \
pr_reg[30] = 0; /* brp */ \
pr_reg[31] = rdusp(); /* usp */ \
pr_reg[32] = 0; /* csrinstr */ \
pr_reg[33] = 0; /* csraddr */ \
pr_reg[34] = 0; /* csrdata */
#endif

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arch/cris/include/arch-v10/arch/io.h Normal file
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#ifndef _ASM_ARCH_CRIS_IO_H
#define _ASM_ARCH_CRIS_IO_H
/* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */
extern unsigned long gen_config_ii_shadow;
extern unsigned long port_g_data_shadow;
extern unsigned char port_pa_dir_shadow;
extern unsigned char port_pa_data_shadow;
extern unsigned char port_pb_i2c_shadow;
extern unsigned char port_pb_config_shadow;
extern unsigned char port_pb_dir_shadow;
extern unsigned char port_pb_data_shadow;
extern unsigned long r_timer_ctrl_shadow;
extern unsigned long port_cse1_shadow;
extern unsigned long port_csp0_shadow;
extern unsigned long port_csp4_shadow;
extern volatile unsigned long *port_cse1_addr;
extern volatile unsigned long *port_csp0_addr;
extern volatile unsigned long *port_csp4_addr;
/* macro for setting regs through a shadow -
* r = register name (like R_PORT_PA_DATA)
* s = shadow name (like port_pa_data_shadow)
* b = bit number
* v = value (0 or 1)
*/
#define REG_SHADOW_SET(r,s,b,v) *r = s = (s & ~(1 << (b))) | ((v) << (b))
/* The LED's on various Etrax-based products are set differently. */
#if defined(CONFIG_ETRAX_NO_LEDS)
#undef CONFIG_ETRAX_PA_LEDS
#undef CONFIG_ETRAX_PB_LEDS
#undef CONFIG_ETRAX_CSP0_LEDS
#define CRIS_LED_NETWORK_SET_G(x)
#define CRIS_LED_NETWORK_SET_R(x)
#define CRIS_LED_ACTIVE_SET_G(x)
#define CRIS_LED_ACTIVE_SET_R(x)
#define CRIS_LED_DISK_WRITE(x)
#define CRIS_LED_DISK_READ(x)
#endif
#if !defined(CONFIG_ETRAX_CSP0_LEDS)
#define CRIS_LED_BIT_SET(x)
#define CRIS_LED_BIT_CLR(x)
#endif
#define CRIS_LED_OFF 0x00
#define CRIS_LED_GREEN 0x01
#define CRIS_LED_RED 0x02
#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED)
#if defined(CONFIG_ETRAX_NO_LEDS)
#define CRIS_LED_NETWORK_SET(x)
#else
#if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R
#define CRIS_LED_NETWORK_SET(x) \
do { \
CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \
} while (0)
#else
#define CRIS_LED_NETWORK_SET(x) \
do { \
CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \
CRIS_LED_NETWORK_SET_R((x) & CRIS_LED_RED); \
} while (0)
#endif
#if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R
#define CRIS_LED_ACTIVE_SET(x) \
do { \
CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \
} while (0)
#else
#define CRIS_LED_ACTIVE_SET(x) \
do { \
CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \
CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \
} while (0)
#endif
#endif
#ifdef CONFIG_ETRAX_PA_LEDS
#define CRIS_LED_NETWORK_SET_G(x) \
REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1G, !(x))
#define CRIS_LED_NETWORK_SET_R(x) \
REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1R, !(x))
#define CRIS_LED_ACTIVE_SET_G(x) \
REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2G, !(x))
#define CRIS_LED_ACTIVE_SET_R(x) \
REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2R, !(x))
#define CRIS_LED_DISK_WRITE(x) \
do{\
REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x));\
REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3R, !(x));\
}while(0)
#define CRIS_LED_DISK_READ(x) \
REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, \
CONFIG_ETRAX_LED3G, !(x))
#endif
#ifdef CONFIG_ETRAX_PB_LEDS
#define CRIS_LED_NETWORK_SET_G(x) \
REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1G, !(x))
#define CRIS_LED_NETWORK_SET_R(x) \
REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1R, !(x))
#define CRIS_LED_ACTIVE_SET_G(x) \
REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2G, !(x))
#define CRIS_LED_ACTIVE_SET_R(x) \
REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2R, !(x))
#define CRIS_LED_DISK_WRITE(x) \
do{\
REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x));\
REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3R, !(x));\
}while(0)
#define CRIS_LED_DISK_READ(x) \
REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, \
CONFIG_ETRAX_LED3G, !(x))
#endif
#ifdef CONFIG_ETRAX_CSP0_LEDS
#define CONFIGURABLE_LEDS\
((1 << CONFIG_ETRAX_LED1G ) | (1 << CONFIG_ETRAX_LED1R ) |\
(1 << CONFIG_ETRAX_LED2G ) | (1 << CONFIG_ETRAX_LED2R ) |\
(1 << CONFIG_ETRAX_LED3G ) | (1 << CONFIG_ETRAX_LED3R ) |\
(1 << CONFIG_ETRAX_LED4G ) | (1 << CONFIG_ETRAX_LED4R ) |\
(1 << CONFIG_ETRAX_LED5G ) | (1 << CONFIG_ETRAX_LED5R ) |\
(1 << CONFIG_ETRAX_LED6G ) | (1 << CONFIG_ETRAX_LED6R ) |\
(1 << CONFIG_ETRAX_LED7G ) | (1 << CONFIG_ETRAX_LED7R ) |\
(1 << CONFIG_ETRAX_LED8Y ) | (1 << CONFIG_ETRAX_LED9Y ) |\
(1 << CONFIG_ETRAX_LED10Y ) |(1 << CONFIG_ETRAX_LED11Y )|\
(1 << CONFIG_ETRAX_LED12R ))
#define CRIS_LED_NETWORK_SET_G(x) \
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1G, !(x))
#define CRIS_LED_NETWORK_SET_R(x) \
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1R, !(x))
#define CRIS_LED_ACTIVE_SET_G(x) \
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2G, !(x))
#define CRIS_LED_ACTIVE_SET_R(x) \
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2R, !(x))
#define CRIS_LED_DISK_WRITE(x) \
do{\
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x));\
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3R, !(x));\
}while(0)
#define CRIS_LED_DISK_READ(x) \
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x))
#define CRIS_LED_BIT_SET(x)\
do{\
if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 1);\
}while(0)
#define CRIS_LED_BIT_CLR(x)\
do{\
if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 0);\
}while(0)
#endif
#
#ifdef CONFIG_ETRAX_SOFT_SHUTDOWN
#define SOFT_SHUTDOWN() \
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_SHUTDOWN_BIT, 1)
#else
#define SOFT_SHUTDOWN()
#endif
#endif

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arch/cris/include/arch-v10/arch/io_interface_mux.h Normal file
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/* IO interface mux allocator for ETRAX100LX.
* Copyright 2004, Axis Communications AB
* $Id: io_interface_mux.h,v 1.1 2004/12/13 12:21:53 starvik Exp $
*/
#ifndef _IO_INTERFACE_MUX_H
#define _IO_INTERFACE_MUX_H
/* C.f. ETRAX100LX Designer's Reference 20.9 */
/* The order in enum must match the order of interfaces[] in
* io_interface_mux.c */
enum cris_io_interface {
/* Begin Non-multiplexed interfaces */
if_eth = 0,
if_serial_0,
/* End Non-multiplexed interfaces */
if_serial_1,
if_serial_2,
if_serial_3,
if_sync_serial_1,
if_sync_serial_3,
if_shared_ram,
if_shared_ram_w,
if_par_0,
if_par_1,
if_par_w,
if_scsi8_0,
if_scsi8_1,
if_scsi_w,
if_ata,
if_csp,
if_i2c,
if_usb_1,
if_usb_2,
/* GPIO pins */
if_gpio_grp_a,
if_gpio_grp_b,
if_gpio_grp_c,
if_gpio_grp_d,
if_gpio_grp_e,
if_gpio_grp_f,
if_max_interfaces,
if_unclaimed
};
int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id);
void cris_free_io_interface(enum cris_io_interface ioif);
/* port can be 'a', 'b' or 'g' */
int cris_io_interface_allocate_pins(const enum cris_io_interface ioif,
const char port,
const unsigned start_bit,
const unsigned stop_bit);
/* port can be 'a', 'b' or 'g' */
int cris_io_interface_free_pins(const enum cris_io_interface ioif,
const char port,
const unsigned start_bit,
const unsigned stop_bit);
int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available,
const unsigned int gpio_out_available,
const unsigned char pa_available,
const unsigned char pb_available));
void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available,
const unsigned int gpio_out_available,
const unsigned char pa_available,
const unsigned char pb_available));
#endif /* _IO_INTERFACE_MUX_H */

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/*
* Interrupt handling assembler and defines for Linux/CRISv10
*/
#ifndef _ASM_ARCH_IRQ_H
#define _ASM_ARCH_IRQ_H
#include <arch/sv_addr_ag.h>
#define NR_IRQS 32
/* The first vector number used for IRQs in v10 is really 0x20 */
/* but all the code and constants are offseted to make 0 the first */
#define FIRST_IRQ 0
#define SOME_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, some) /* 0 ? */
#define NMI_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, nmi) /* 1 */
#define TIMER0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer0) /* 2 */
#define TIMER1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer1) /* 3 */
/* mio, ata, par0, scsi0 on 4 */
/* par1, scsi1 on 5 */
#define NETWORK_STATUS_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, network) /* 6 */
#define SERIAL_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, serial) /* 8 */
#define PA_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, pa) /* 11 */
/* extdma0 and extdma1 is at irq 12 and 13 and/or same as dma5 and dma6 ? */
#define EXTDMA0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma0)
#define EXTDMA1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma1)
/* dma0-9 is irq 16..25 */
/* 16,17: network */
#define DMA0_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma0)
#define DMA1_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma1)
#define NETWORK_DMA_TX_IRQ_NBR DMA0_TX_IRQ_NBR
#define NETWORK_DMA_RX_IRQ_NBR DMA1_RX_IRQ_NBR
/* 18,19: dma2 and dma3 shared by par0, scsi0, ser2 and ata */
#define DMA2_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma2)
#define DMA3_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma3)
#define SER2_DMA_TX_IRQ_NBR DMA2_TX_IRQ_NBR
#define SER2_DMA_RX_IRQ_NBR DMA3_RX_IRQ_NBR
/* 20,21: dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */
#define DMA4_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma4)
#define DMA5_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma5)
#define SER3_DMA_TX_IRQ_NBR DMA4_TX_IRQ_NBR
#define SER3_DMA_RX_IRQ_NBR DMA5_RX_IRQ_NBR
/* 22,23: dma6 and dma7 shared by ser0, extdma1 and mem2mem */
#define DMA6_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma6)
#define DMA7_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma7)
#define SER0_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR
#define SER0_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR
#define MEM2MEM_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR
#define MEM2MEM_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR
/* 24,25: dma8 and dma9 shared by ser1 and usb */
#define DMA8_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma8)
#define DMA9_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma9)
#define SER1_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR
#define SER1_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR
#define USB_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR
#define USB_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR
/* usb: controller at irq 31 + uses DMA8 and DMA9 */
#define USB_HC_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, usb)
/* our fine, global, etrax irq vector! the pointer lives in the head.S file. */
typedef void (*irqvectptr)(void);
struct etrax_interrupt_vector {
irqvectptr v[256];
};
extern struct etrax_interrupt_vector *etrax_irv;
void set_int_vector(int n, irqvectptr addr);
void set_break_vector(int n, irqvectptr addr);
#define __STR(x) #x
#define STR(x) __STR(x)
/* SAVE_ALL saves registers so they match pt_regs */
#define SAVE_ALL \
"move $irp,[$sp=$sp-16]\n\t" /* push instruction pointer and fake SBFS struct */ \
"push $srp\n\t" /* push subroutine return pointer */ \
"push $dccr\n\t" /* push condition codes */ \
"push $mof\n\t" /* push multiply overflow reg */ \
"di\n\t" /* need to disable irq's at this point */\
"subq 14*4,$sp\n\t" /* make room for r0-r13 */ \
"movem $r13,[$sp]\n\t" /* push the r0-r13 registers */ \
"push $r10\n\t" /* push orig_r10 */ \
"clear.d [$sp=$sp-4]\n\t" /* frametype - this is a normal stackframe */
/* BLOCK_IRQ and UNBLOCK_IRQ do the same as
* crisv10_mask_irq and crisv10_unmask_irq */
#define BLOCK_IRQ(mask,nr) \
"move.d " #mask ",$r0\n\t" \
"move.d $r0,[0xb00000d8]\n\t"
#define UNBLOCK_IRQ(mask) \
"move.d " #mask ",$r0\n\t" \
"move.d $r0,[0xb00000dc]\n\t"
#define IRQ_NAME2(nr) nr##_interrupt(void)
#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
#define sIRQ_NAME(nr) IRQ_NAME2(sIRQ##nr)
#define BAD_IRQ_NAME(nr) IRQ_NAME2(bad_IRQ##nr)
/* the asm IRQ handler makes sure the causing IRQ is blocked, then it calls
* do_IRQ (with irq disabled still). after that it unblocks and jumps to
* ret_from_intr (entry.S)
*
* The reason the IRQ is blocked is to allow an sti() before the handler which
* will acknowledge the interrupt is run.
*/
#define BUILD_IRQ(nr,mask) \
void IRQ_NAME(nr); \
__asm__ ( \
".text\n\t" \
"IRQ" #nr "_interrupt:\n\t" \
SAVE_ALL \
BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \
"moveq "#nr",$r10\n\t" \
"move.d $sp,$r11\n\t" \
"jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
UNBLOCK_IRQ(mask) \
"moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
"jump ret_from_intr\n\t");
/* This is subtle. The timer interrupt is crucial and it should not be disabled for
* too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would
* have been BLOCK'ed, and then softirq's are run before we return here to UNBLOCK.
* If the softirq's take too much time to run, the timer irq won't run and the
* watchdog will kill us.
*
* Furthermore, if a lot of other irq's occur before we return here, the multiple_irq
* handler is run and it prioritizes the timer interrupt. However if we had BLOCK'ed
* it here, we would not get the multiple_irq at all.
*
* The non-blocking here is based on the knowledge that the timer interrupt runs
* with interrupts disabled, and therefore there will not be an sti() before the
* timer irq handler is run to acknowledge the interrupt.
*/
#define BUILD_TIMER_IRQ(nr,mask) \
void IRQ_NAME(nr); \
__asm__ ( \
".text\n\t" \
"IRQ" #nr "_interrupt:\n\t" \
SAVE_ALL \
"moveq "#nr",$r10\n\t" \
"move.d $sp,$r11\n\t" \
"jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
"moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
"jump ret_from_intr\n\t");
#endif

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#ifndef __ASM_CRIS_ARCH_IRQFLAGS_H
#define __ASM_CRIS_ARCH_IRQFLAGS_H
#include <linux/types.h>
static inline unsigned long arch_local_save_flags(void)
{
unsigned long flags;
asm volatile("move $ccr,%0" : "=rm" (flags) : : "memory");
return flags;
}
static inline void arch_local_irq_disable(void)
{
asm volatile("di" : : : "memory");
}
static inline void arch_local_irq_enable(void)
{
asm volatile("ei" : : : "memory");
}
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags = arch_local_save_flags();
arch_local_irq_disable();
return flags;
}
static inline void arch_local_irq_restore(unsigned long flags)
{
asm volatile("move %0,$ccr" : : "rm" (flags) : "memory");
}
static inline bool arch_irqs_disabled_flags(unsigned long flags)
{
return !(flags & (1 << 5));
}
static inline bool arch_irqs_disabled(void)
{
return arch_irqs_disabled_flags(arch_local_save_flags());
}
#endif /* __ASM_CRIS_ARCH_IRQFLAGS_H */

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#ifndef _ASM_ARCH_MEMMAP_H
#define _ASM_ARCH_MEMMAP_H
#define MEM_CSE0_START (0x00000000)
#define MEM_CSE0_SIZE (0x04000000)
#define MEM_CSE1_START (0x04000000)
#define MEM_CSE1_SIZE (0x04000000)
#define MEM_CSR0_START (0x08000000)
#define MEM_CSR1_START (0x0c000000)
#define MEM_CSP0_START (0x10000000)
#define MEM_CSP1_START (0x14000000)
#define MEM_CSP2_START (0x18000000)
#define MEM_CSP3_START (0x1c000000)
#define MEM_CSP4_START (0x20000000)
#define MEM_CSP5_START (0x24000000)
#define MEM_CSP6_START (0x28000000)
#define MEM_CSP7_START (0x2c000000)
#define MEM_DRAM_START (0x40000000)
#define MEM_NON_CACHEABLE (0x80000000)
#endif

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/*
* CRIS MMU constants and PTE layout
*/
#ifndef _CRIS_ARCH_MMU_H
#define _CRIS_ARCH_MMU_H
/* type used in struct mm to couple an MMU context to an active mm */
typedef struct
{
unsigned int page_id;
} mm_context_t;
/* kernel memory segments */
#define KSEG_F 0xf0000000UL
#define KSEG_E 0xe0000000UL
#define KSEG_D 0xd0000000UL
#define KSEG_C 0xc0000000UL
#define KSEG_B 0xb0000000UL
#define KSEG_A 0xa0000000UL
#define KSEG_9 0x90000000UL
#define KSEG_8 0x80000000UL
#define KSEG_7 0x70000000UL
#define KSEG_6 0x60000000UL
#define KSEG_5 0x50000000UL
#define KSEG_4 0x40000000UL
#define KSEG_3 0x30000000UL
#define KSEG_2 0x20000000UL
#define KSEG_1 0x10000000UL
#define KSEG_0 0x00000000UL
/* CRIS PTE bits (see R_TLB_LO in the register description)
*
* Bit: 31 30-13 12-------4 3 2 1 0
* _______________________________________________________
* | cache |pfn | reserved | global | valid | kernel | we |
* |_______|____|__________|________|_______|________|_____|
*
* (pfn = physical frame number)
*/
/* Real HW-based PTE bits. We use some synonym names so that
* things become less confusing in combination with the SW-based
* bits further below.
*
*/
#define _PAGE_WE (1<<0) /* page is write-enabled */
#define _PAGE_SILENT_WRITE (1<<0) /* synonym */
#define _PAGE_KERNEL (1<<1) /* page is kernel only */
#define _PAGE_VALID (1<<2) /* page is valid */
#define _PAGE_SILENT_READ (1<<2) /* synonym */
#define _PAGE_GLOBAL (1<<3) /* global page - context is ignored */
#define _PAGE_NO_CACHE (1<<31) /* part of the uncached memory map */
/* Bits the HW doesn't care about but the kernel uses them in SW */
#define _PAGE_PRESENT (1<<4) /* page present in memory */
#define _PAGE_FILE (1<<5) /* set: pagecache, unset: swap (when !PRESENT) */
#define _PAGE_ACCESSED (1<<5) /* simulated in software using valid bit */
#define _PAGE_MODIFIED (1<<6) /* simulated in software using we bit */
#define _PAGE_READ (1<<7) /* read-enabled */
#define _PAGE_WRITE (1<<8) /* write-enabled */
/* Define some higher level generic page attributes. */
#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE)
#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED)
#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
_PAGE_ACCESSED)
#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) // | _PAGE_COW
#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE)
#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \
_PAGE_PRESENT | __READABLE | __WRITEABLE)
#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL)
/*
* CRIS can't do page protection for execute, and considers read the same.
* Also, write permissions imply read permissions. This is the closest we can
* get..
*/
#define __P000 PAGE_NONE
#define __P001 PAGE_READONLY
#define __P010 PAGE_COPY
#define __P011 PAGE_COPY
#define __P100 PAGE_READONLY
#define __P101 PAGE_READONLY
#define __P110 PAGE_COPY
#define __P111 PAGE_COPY
#define __S000 PAGE_NONE
#define __S001 PAGE_READONLY
#define __S010 PAGE_SHARED
#define __S011 PAGE_SHARED
#define __S100 PAGE_READONLY
#define __S101 PAGE_READONLY
#define __S110 PAGE_SHARED
#define __S111 PAGE_SHARED
#define PTE_FILE_MAX_BITS 26
#endif

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#ifndef __ASM_OFFSETS_H__
#define __ASM_OFFSETS_H__
/*
* DO NOT MODIFY.
*
* This file was generated by arch/cris/Makefile
*
*/
#define PT_orig_r10 4 /* offsetof(struct pt_regs, orig_r10) */
#define PT_r13 8 /* offsetof(struct pt_regs, r13) */
#define PT_r12 12 /* offsetof(struct pt_regs, r12) */
#define PT_r11 16 /* offsetof(struct pt_regs, r11) */
#define PT_r10 20 /* offsetof(struct pt_regs, r10) */
#define PT_r9 24 /* offsetof(struct pt_regs, r9) */
#define PT_mof 64 /* offsetof(struct pt_regs, mof) */
#define PT_dccr 68 /* offsetof(struct pt_regs, dccr) */
#define PT_srp 72 /* offsetof(struct pt_regs, srp) */
#define TI_task 0 /* offsetof(struct thread_info, task) */
#define TI_flags 8 /* offsetof(struct thread_info, flags) */
#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */
#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */
#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */
#define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */
#define TASK_pid 141 /* offsetof(struct task_struct, pid) */
#define LCLONE_VM 256 /* CLONE_VM */
#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */
#endif

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#ifndef _CRIS_ARCH_PAGE_H
#define _CRIS_ARCH_PAGE_H
#ifdef __KERNEL__
/* This handles the memory map.. */
#ifdef CONFIG_CRIS_LOW_MAP
#define PAGE_OFFSET KSEG_6 /* kseg_6 is mapped to physical ram */
#else
#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram */
#endif
/* macros to convert between really physical and virtual addresses
* by stripping a selected bit, we can convert between KSEG_x and
* 0x40000000 where the DRAM really resides
*/
#ifdef CONFIG_CRIS_LOW_MAP
/* we have DRAM virtually at 0x6 */
#define __pa(x) ((unsigned long)(x) & 0xdfffffff)
#define __va(x) ((void *)((unsigned long)(x) | 0x20000000))
#else
/* we have DRAM virtually at 0xc */
#define __pa(x) ((unsigned long)(x) & 0x7fffffff)
#define __va(x) ((void *)((unsigned long)(x) | 0x80000000))
#endif
#endif
#endif

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#ifndef _CRIS_ARCH_PGTABLE_H
#define _CRIS_ARCH_PGTABLE_H
/*
* Kernels own virtual memory area.
*/
#ifdef CONFIG_CRIS_LOW_MAP
#define VMALLOC_START KSEG_7
#define VMALLOC_END KSEG_8
#else
#define VMALLOC_START KSEG_D
#define VMALLOC_END KSEG_E
#endif
#endif

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#ifndef __ASM_CRIS_ARCH_PROCESSOR_H
#define __ASM_CRIS_ARCH_PROCESSOR_H
/*
* Default implementation of macro that returns current
* instruction pointer ("program counter").
*/
#define current_text_addr() ({void *pc; __asm__ ("move.d $pc,%0" : "=rm" (pc)); pc; })
/* CRIS has no problems with write protection */
#define wp_works_ok 1
/* CRIS thread_struct. this really has nothing to do with the processor itself, since
* CRIS does not do any hardware task-switching, but it's here for legacy reasons.
* The thread_struct here is used when task-switching using _resume defined in entry.S.
* The offsets here are hardcoded into _resume - if you change this struct, you need to
* change them as well!!!
*/
struct thread_struct {
unsigned long ksp; /* kernel stack pointer */
unsigned long usp; /* user stack pointer */
unsigned long dccr; /* saved flag register */
};
/*
* User space process size. This is hardcoded into a few places,
* so don't change it unless you know what you are doing.
*/
#ifdef CONFIG_CRIS_LOW_MAP
#define TASK_SIZE (0x50000000UL) /* 1.25 GB */
#else
#define TASK_SIZE (0xA0000000UL) /* 2.56 GB */
#endif
#define INIT_THREAD { \
0, 0, 0x20 } /* ccr = int enable, nothing else */
#define KSTK_EIP(tsk) \
({ \
unsigned long eip = 0; \
unsigned long regs = (unsigned long)task_pt_regs(tsk); \
if (regs > PAGE_SIZE && \
virt_addr_valid(regs)) \
eip = ((struct pt_regs *)regs)->irp; \
eip; \
})
/* give the thread a program location
* set user-mode (The 'U' flag (User mode flag) is CCR/DCCR bit 8)
* switch user-stackpointer
*/
#define start_thread(regs, ip, usp) do { \
regs->irp = ip; \
regs->dccr |= 1 << U_DCCR_BITNR; \
wrusp(usp); \
} while(0)
/* Called when handling a kernel bus fault fixup.
*
* After a fixup we do not want to return by restoring the CPU-state
* anymore, so switch frame-types (see ptrace.h)
*/
#define arch_fixup(regs) \
regs->frametype = CRIS_FRAME_NORMAL;
#endif

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#ifndef _CRIS_ARCH_PTRACE_H
#define _CRIS_ARCH_PTRACE_H
/* Frame types */
#define CRIS_FRAME_NORMAL 0 /* normal frame without SBFS stacking */
#define CRIS_FRAME_BUSFAULT 1 /* frame stacked using SBFS, need RBF return
path */
/* Register numbers in the ptrace system call interface */
#define PT_FRAMETYPE 0
#define PT_ORIG_R10 1
#define PT_R13 2
#define PT_R12 3
#define PT_R11 4
#define PT_R10 5
#define PT_R9 6
#define PT_R8 7
#define PT_R7 8
#define PT_R6 9
#define PT_R5 10
#define PT_R4 11
#define PT_R3 12
#define PT_R2 13
#define PT_R1 14
#define PT_R0 15
#define PT_MOF 16
#define PT_DCCR 17
#define PT_SRP 18
#define PT_IRP 19 /* This is actually the debugged process' PC */
#define PT_CSRINSTR 20 /* CPU Status record remnants -
valid if frametype == busfault */
#define PT_CSRADDR 21
#define PT_CSRDATA 22
#define PT_USP 23 /* special case - USP is not in the pt_regs */
#define PT_MAX 23
/* Condition code bit numbers. The same numbers apply to CCR of course,
but we use DCCR everywhere else, so let's try and be consistent. */
#define C_DCCR_BITNR 0
#define V_DCCR_BITNR 1
#define Z_DCCR_BITNR 2
#define N_DCCR_BITNR 3
#define X_DCCR_BITNR 4
#define I_DCCR_BITNR 5
#define B_DCCR_BITNR 6
#define M_DCCR_BITNR 7
#define U_DCCR_BITNR 8
#define P_DCCR_BITNR 9
#define F_DCCR_BITNR 10
/* pt_regs not only specifices the format in the user-struct during
* ptrace but is also the frame format used in the kernel prologue/epilogues
* themselves
*/
struct pt_regs {
unsigned long frametype; /* type of stackframe */
unsigned long orig_r10;
/* pushed by movem r13, [sp] in SAVE_ALL, movem pushes backwards */
unsigned long r13;
unsigned long r12;
unsigned long r11;
unsigned long r10;
unsigned long r9;
unsigned long r8;
unsigned long r7;
unsigned long r6;
unsigned long r5;
unsigned long r4;
unsigned long r3;
unsigned long r2;
unsigned long r1;
unsigned long r0;
unsigned long mof;
unsigned long dccr;
unsigned long srp;
unsigned long irp; /* This is actually the debugged process' PC */
unsigned long csrinstr;
unsigned long csraddr;
unsigned long csrdata;
};
/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S)
* when doing a context-switch. it is used (apart from in resume) when a new
* thread is made and we need to make _resume (which is starting it for the
* first time) realise what is going on.
*
* Actually, the use is very close to the thread struct (TSS) in that both the
* switch_stack and the TSS are used to keep thread stuff when switching in
* _resume.
*/
struct switch_stack {
unsigned long r9;
unsigned long r8;
unsigned long r7;
unsigned long r6;
unsigned long r5;
unsigned long r4;
unsigned long r3;
unsigned long r2;
unsigned long r1;
unsigned long r0;
unsigned long return_ip; /* ip that _resume will return to */
};
#ifdef __KERNEL__
/* bit 8 is user-mode flag */
#define user_mode(regs) (((regs)->dccr & 0x100) != 0)
#define instruction_pointer(regs) ((regs)->irp)
#define profile_pc(regs) instruction_pointer(regs)
#endif /* __KERNEL__ */
#endif

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#ifndef _CRIS_ARCH_SWAB_H
#define _CRIS_ARCH_SWAB_H
#include <asm/types.h>
#include <linux/compiler.h>
#define __SWAB_64_THRU_32__
/* we just define these two (as we can do the swap in a single
* asm instruction in CRIS) and the arch-independent files will put
* them together into ntohl etc.
*/
static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
{
__asm__ ("swapwb %0" : "=r" (x) : "0" (x));
return(x);
}
#define __arch_swab32 __arch_swab32
static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
{
__asm__ ("swapb %0" : "=r" (x) : "0" (x));
return(x);
}
#define __arch_swab16 __arch_swab16
#endif

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#ifndef __ASM_CRIS_ARCH_SYSTEM_H
#define __ASM_CRIS_ARCH_SYSTEM_H
/* read the CPU version register */
static inline unsigned long rdvr(void) {
unsigned char vr;
__asm__ volatile ("move $vr,%0" : "=rm" (vr));
return vr;
}
#define cris_machine_name "cris"
/* read/write the user-mode stackpointer */
static inline unsigned long rdusp(void) {
unsigned long usp;
__asm__ __volatile__("move $usp,%0" : "=rm" (usp));
return usp;
}
#define wrusp(usp) \
__asm__ __volatile__("move %0,$usp" : /* no outputs */ : "rm" (usp))
/* read the current stackpointer */
static inline unsigned long rdsp(void) {
unsigned long sp;
__asm__ __volatile__("move.d $sp,%0" : "=rm" (sp));
return sp;
}
static inline unsigned long _get_base(char * addr)
{
return 0;
}
#define nop() __asm__ __volatile__ ("nop");
#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
#define tas(ptr) (xchg((ptr),1))
struct __xchg_dummy { unsigned long a[100]; };
#define __xg(x) ((struct __xchg_dummy *)(x))
#endif

12
arch/cris/include/arch-v10/arch/thread_info.h Normal file
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#ifndef _ASM_ARCH_THREAD_INFO_H
#define _ASM_ARCH_THREAD_INFO_H
/* how to get the thread information struct from C */
static inline struct thread_info *current_thread_info(void)
{
struct thread_info *ti;
__asm__("and.d $sp,%0; ":"=r" (ti) : "0" (~8191UL));
return ti;
}
#endif

30
arch/cris/include/arch-v10/arch/timex.h Normal file
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/*
* Use prescale timer at 25000 Hz instead of the baudrate timer at
* 19200 to get rid of the 64ppm to fast timer (and we get better
* resolution within a jiffie as well.
*/
#ifndef _ASM_CRIS_ARCH_TIMEX_H
#define _ASM_CRIS_ARCH_TIMEX_H
/* The prescaler clock runs at 25MHz, we divide it by 1000 in the prescaler */
/* If you change anything here you must check time.c as well... */
#define PRESCALE_FREQ 25000000
#define PRESCALE_VALUE 1000
#define CLOCK_TICK_RATE 25000 /* Underlying frequency of the HZ timer */
/* The timer0 values gives 40us resolution (1/25000) but interrupts at HZ*/
#define TIMER0_FREQ (CLOCK_TICK_RATE)
#define TIMER0_CLKSEL flexible
#define TIMER0_DIV (TIMER0_FREQ/(HZ))
#define GET_JIFFIES_USEC() \
( (TIMER0_DIV - *R_TIMER0_DATA) * (1000000/HZ)/TIMER0_DIV )
unsigned long get_ns_in_jiffie(void);
static inline unsigned long get_us_in_jiffie_highres(void)
{
return get_ns_in_jiffie()/1000;
}
#endif

13
arch/cris/include/arch-v10/arch/tlb.h Normal file
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#ifndef _CRIS_ARCH_TLB_H
#define _CRIS_ARCH_TLB_H
/* The TLB can host up to 64 different mm contexts at the same time.
* The last page_id is never running - it is used as an invalid page_id
* so we can make TLB entries that will never match.
*/
#define NUM_TLB_ENTRIES 64
#define NUM_PAGEID 64
#define INVALID_PAGEID 63
#define NO_CONTEXT -1
#endif

660
arch/cris/include/arch-v10/arch/uaccess.h Normal file
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/*
* Authors: Bjorn Wesen (bjornw@axis.com)
* Hans-Peter Nilsson (hp@axis.com)
*
*/
#ifndef _CRIS_ARCH_UACCESS_H
#define _CRIS_ARCH_UACCESS_H
/*
* We don't tell gcc that we are accessing memory, but this is OK
* because we do not write to any memory gcc knows about, so there
* are no aliasing issues.
*
* Note that PC at a fault is the address *after* the faulting
* instruction.
*/
#define __put_user_asm(x, addr, err, op) \
__asm__ __volatile__( \
" "op" %1,[%2]\n" \
"2:\n" \
" .section .fixup,\"ax\"\n" \
"3: move.d %3,%0\n" \
" jump 2b\n" \
" .previous\n" \
" .section __ex_table,\"a\"\n" \
" .dword 2b,3b\n" \
" .previous\n" \
: "=r" (err) \
: "r" (x), "r" (addr), "g" (-EFAULT), "0" (err))
#define __put_user_asm_64(x, addr, err) \
__asm__ __volatile__( \
" move.d %M1,[%2]\n" \
"2: move.d %H1,[%2+4]\n" \
"4:\n" \
" .section .fixup,\"ax\"\n" \
"3: move.d %3,%0\n" \
" jump 4b\n" \
" .previous\n" \
" .section __ex_table,\"a\"\n" \
" .dword 2b,3b\n" \
" .dword 4b,3b\n" \
" .previous\n" \
: "=r" (err) \
: "r" (x), "r" (addr), "g" (-EFAULT), "0" (err))
/* See comment before __put_user_asm. */
#define __get_user_asm(x, addr, err, op) \
__asm__ __volatile__( \
" "op" [%2],%1\n" \
"2:\n" \
" .section .fixup,\"ax\"\n" \
"3: move.d %3,%0\n" \
" moveq 0,%1\n" \
" jump 2b\n" \
" .previous\n" \
" .section __ex_table,\"a\"\n" \
" .dword 2b,3b\n" \
" .previous\n" \
: "=r" (err), "=r" (x) \
: "r" (addr), "g" (-EFAULT), "0" (err))
#define __get_user_asm_64(x, addr, err) \
__asm__ __volatile__( \
" move.d [%2],%M1\n" \
"2: move.d [%2+4],%H1\n" \
"4:\n" \
" .section .fixup,\"ax\"\n" \
"3: move.d %3,%0\n" \
" moveq 0,%1\n" \
" jump 4b\n" \
" .previous\n" \
" .section __ex_table,\"a\"\n" \
" .dword 2b,3b\n" \
" .dword 4b,3b\n" \
" .previous\n" \
: "=r" (err), "=r" (x) \
: "r" (addr), "g" (-EFAULT), "0" (err))
/*
* Copy a null terminated string from userspace.
*
* Must return:
* -EFAULT for an exception
* count if we hit the buffer limit
* bytes copied if we hit a null byte
* (without the null byte)
*/
static inline long
__do_strncpy_from_user(char *dst, const char *src, long count)
{
long res;
if (count == 0)
return 0;
/*
* Currently, in 2.4.0-test9, most ports use a simple byte-copy loop.
* So do we.
*
* This code is deduced from:
*
* char tmp2;
* long tmp1, tmp3
* tmp1 = count;
* while ((*dst++ = (tmp2 = *src++)) != 0
* && --tmp1)
* ;
*
* res = count - tmp1;
*
* with tweaks.
*/
__asm__ __volatile__ (
" move.d %3,%0\n"
" move.b [%2+],$r9\n"
"1: beq 2f\n"
" move.b $r9,[%1+]\n"
" subq 1,%0\n"
" bne 1b\n"
" move.b [%2+],$r9\n"
"2: sub.d %3,%0\n"
" neg.d %0,%0\n"
"3:\n"
" .section .fixup,\"ax\"\n"
"4: move.d %7,%0\n"
" jump 3b\n"
/* There's one address for a fault at the first move, and
two possible PC values for a fault at the second move,
being a delay-slot filler. However, the branch-target
for the second move is the same as the first address.
Just so you don't get confused... */
" .previous\n"
" .section __ex_table,\"a\"\n"
" .dword 1b,4b\n"
" .dword 2b,4b\n"
" .previous"
: "=r" (res), "=r" (dst), "=r" (src), "=r" (count)
: "3" (count), "1" (dst), "2" (src), "g" (-EFAULT)
: "r9");
return res;
}
/* A few copy asms to build up the more complex ones from.
Note again, a post-increment is performed regardless of whether a bus
fault occurred in that instruction, and PC for a faulted insn is the
address *after* the insn. */
#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm__ __volatile__ ( \
COPY \
"1:\n" \
" .section .fixup,\"ax\"\n" \
FIXUP \
" jump 1b\n" \
" .previous\n" \
" .section __ex_table,\"a\"\n" \
TENTRY \
" .previous\n" \
: "=r" (to), "=r" (from), "=r" (ret) \
: "0" (to), "1" (from), "2" (ret) \
: "r9", "memory")
#define __asm_copy_from_user_1(to, from, ret) \
__asm_copy_user_cont(to, from, ret, \
" move.b [%1+],$r9\n" \
"2: move.b $r9,[%0+]\n", \
"3: addq 1,%2\n" \
" clear.b [%0+]\n", \
" .dword 2b,3b\n")
#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_user_cont(to, from, ret, \
" move.w [%1+],$r9\n" \
"2: move.w $r9,[%0+]\n" COPY, \
"3: addq 2,%2\n" \
" clear.w [%0+]\n" FIXUP, \
" .dword 2b,3b\n" TENTRY)
#define __asm_copy_from_user_2(to, from, ret) \
__asm_copy_from_user_2x_cont(to, from, ret, "", "", "")
#define __asm_copy_from_user_3(to, from, ret) \
__asm_copy_from_user_2x_cont(to, from, ret, \
" move.b [%1+],$r9\n" \
"4: move.b $r9,[%0+]\n", \
"5: addq 1,%2\n" \
" clear.b [%0+]\n", \
" .dword 4b,5b\n")
#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_user_cont(to, from, ret, \
" move.d [%1+],$r9\n" \
"2: move.d $r9,[%0+]\n" COPY, \
"3: addq 4,%2\n" \
" clear.d [%0+]\n" FIXUP, \
" .dword 2b,3b\n" TENTRY)
#define __asm_copy_from_user_4(to, from, ret) \
__asm_copy_from_user_4x_cont(to, from, ret, "", "", "")
#define __asm_copy_from_user_5(to, from, ret) \
__asm_copy_from_user_4x_cont(to, from, ret, \
" move.b [%1+],$r9\n" \
"4: move.b $r9,[%0+]\n", \
"5: addq 1,%2\n" \
" clear.b [%0+]\n", \
" .dword 4b,5b\n")
#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_from_user_4x_cont(to, from, ret, \
" move.w [%1+],$r9\n" \
"4: move.w $r9,[%0+]\n" COPY, \
"5: addq 2,%2\n" \
" clear.w [%0+]\n" FIXUP, \
" .dword 4b,5b\n" TENTRY)
#define __asm_copy_from_user_6(to, from, ret) \
__asm_copy_from_user_6x_cont(to, from, ret, "", "", "")
#define __asm_copy_from_user_7(to, from, ret) \
__asm_copy_from_user_6x_cont(to, from, ret, \
" move.b [%1+],$r9\n" \
"6: move.b $r9,[%0+]\n", \
"7: addq 1,%2\n" \
" clear.b [%0+]\n", \
" .dword 6b,7b\n")
#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_from_user_4x_cont(to, from, ret, \
" move.d [%1+],$r9\n" \
"4: move.d $r9,[%0+]\n" COPY, \
"5: addq 4,%2\n" \
" clear.d [%0+]\n" FIXUP, \
" .dword 4b,5b\n" TENTRY)
#define __asm_copy_from_user_8(to, from, ret) \
__asm_copy_from_user_8x_cont(to, from, ret, "", "", "")
#define __asm_copy_from_user_9(to, from, ret) \
__asm_copy_from_user_8x_cont(to, from, ret, \
" move.b [%1+],$r9\n" \
"6: move.b $r9,[%0+]\n", \
"7: addq 1,%2\n" \
" clear.b [%0+]\n", \
" .dword 6b,7b\n")
#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_from_user_8x_cont(to, from, ret, \
" move.w [%1+],$r9\n" \
"6: move.w $r9,[%0+]\n" COPY, \
"7: addq 2,%2\n" \
" clear.w [%0+]\n" FIXUP, \
" .dword 6b,7b\n" TENTRY)
#define __asm_copy_from_user_10(to, from, ret) \
__asm_copy_from_user_10x_cont(to, from, ret, "", "", "")
#define __asm_copy_from_user_11(to, from, ret) \
__asm_copy_from_user_10x_cont(to, from, ret, \
" move.b [%1+],$r9\n" \
"8: move.b $r9,[%0+]\n", \
"9: addq 1,%2\n" \
" clear.b [%0+]\n", \
" .dword 8b,9b\n")
#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_from_user_8x_cont(to, from, ret, \
" move.d [%1+],$r9\n" \
"6: move.d $r9,[%0+]\n" COPY, \
"7: addq 4,%2\n" \
" clear.d [%0+]\n" FIXUP, \
" .dword 6b,7b\n" TENTRY)
#define __asm_copy_from_user_12(to, from, ret) \
__asm_copy_from_user_12x_cont(to, from, ret, "", "", "")
#define __asm_copy_from_user_13(to, from, ret) \
__asm_copy_from_user_12x_cont(to, from, ret, \
" move.b [%1+],$r9\n" \
"8: move.b $r9,[%0+]\n", \
"9: addq 1,%2\n" \
" clear.b [%0+]\n", \
" .dword 8b,9b\n")
#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_from_user_12x_cont(to, from, ret, \
" move.w [%1+],$r9\n" \
"8: move.w $r9,[%0+]\n" COPY, \
"9: addq 2,%2\n" \
" clear.w [%0+]\n" FIXUP, \
" .dword 8b,9b\n" TENTRY)
#define __asm_copy_from_user_14(to, from, ret) \
__asm_copy_from_user_14x_cont(to, from, ret, "", "", "")
#define __asm_copy_from_user_15(to, from, ret) \
__asm_copy_from_user_14x_cont(to, from, ret, \
" move.b [%1+],$r9\n" \
"10: move.b $r9,[%0+]\n", \
"11: addq 1,%2\n" \
" clear.b [%0+]\n", \
" .dword 10b,11b\n")
#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_from_user_12x_cont(to, from, ret, \
" move.d [%1+],$r9\n" \
"8: move.d $r9,[%0+]\n" COPY, \
"9: addq 4,%2\n" \
" clear.d [%0+]\n" FIXUP, \
" .dword 8b,9b\n" TENTRY)
#define __asm_copy_from_user_16(to, from, ret) \
__asm_copy_from_user_16x_cont(to, from, ret, "", "", "")
#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_from_user_16x_cont(to, from, ret, \
" move.d [%1+],$r9\n" \
"10: move.d $r9,[%0+]\n" COPY, \
"11: addq 4,%2\n" \
" clear.d [%0+]\n" FIXUP, \
" .dword 10b,11b\n" TENTRY)
#define __asm_copy_from_user_20(to, from, ret) \
__asm_copy_from_user_20x_cont(to, from, ret, "", "", "")
#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_from_user_20x_cont(to, from, ret, \
" move.d [%1+],$r9\n" \
"12: move.d $r9,[%0+]\n" COPY, \
"13: addq 4,%2\n" \
" clear.d [%0+]\n" FIXUP, \
" .dword 12b,13b\n" TENTRY)
#define __asm_copy_from_user_24(to, from, ret) \
__asm_copy_from_user_24x_cont(to, from, ret, "", "", "")
/* And now, the to-user ones. */
#define __asm_copy_to_user_1(to, from, ret) \
__asm_copy_user_cont(to, from, ret, \
" move.b [%1+],$r9\n" \
" move.b $r9,[%0+]\n2:\n", \
"3: addq 1,%2\n", \
" .dword 2b,3b\n")
#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_user_cont(to, from, ret, \
" move.w [%1+],$r9\n" \
" move.w $r9,[%0+]\n2:\n" COPY, \
"3: addq 2,%2\n" FIXUP, \
" .dword 2b,3b\n" TENTRY)
#define __asm_copy_to_user_2(to, from, ret) \
__asm_copy_to_user_2x_cont(to, from, ret, "", "", "")
#define __asm_copy_to_user_3(to, from, ret) \
__asm_copy_to_user_2x_cont(to, from, ret, \
" move.b [%1+],$r9\n" \
" move.b $r9,[%0+]\n4:\n", \
"5: addq 1,%2\n", \
" .dword 4b,5b\n")
#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_user_cont(to, from, ret, \
" move.d [%1+],$r9\n" \
" move.d $r9,[%0+]\n2:\n" COPY, \
"3: addq 4,%2\n" FIXUP, \
" .dword 2b,3b\n" TENTRY)
#define __asm_copy_to_user_4(to, from, ret) \
__asm_copy_to_user_4x_cont(to, from, ret, "", "", "")
#define __asm_copy_to_user_5(to, from, ret) \
__asm_copy_to_user_4x_cont(to, from, ret, \
" move.b [%1+],$r9\n" \
" move.b $r9,[%0+]\n4:\n", \
"5: addq 1,%2\n", \
" .dword 4b,5b\n")
#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_to_user_4x_cont(to, from, ret, \
" move.w [%1+],$r9\n" \
" move.w $r9,[%0+]\n4:\n" COPY, \
"5: addq 2,%2\n" FIXUP, \
" .dword 4b,5b\n" TENTRY)
#define __asm_copy_to_user_6(to, from, ret) \
__asm_copy_to_user_6x_cont(to, from, ret, "", "", "")
#define __asm_copy_to_user_7(to, from, ret) \
__asm_copy_to_user_6x_cont(to, from, ret, \
" move.b [%1+],$r9\n" \
" move.b $r9,[%0+]\n6:\n", \
"7: addq 1,%2\n", \
" .dword 6b,7b\n")
#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_to_user_4x_cont(to, from, ret, \
" move.d [%1+],$r9\n" \
" move.d $r9,[%0+]\n4:\n" COPY, \
"5: addq 4,%2\n" FIXUP, \
" .dword 4b,5b\n" TENTRY)
#define __asm_copy_to_user_8(to, from, ret) \
__asm_copy_to_user_8x_cont(to, from, ret, "", "", "")
#define __asm_copy_to_user_9(to, from, ret) \
__asm_copy_to_user_8x_cont(to, from, ret, \
" move.b [%1+],$r9\n" \
" move.b $r9,[%0+]\n6:\n", \
"7: addq 1,%2\n", \
" .dword 6b,7b\n")
#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_to_user_8x_cont(to, from, ret, \
" move.w [%1+],$r9\n" \
" move.w $r9,[%0+]\n6:\n" COPY, \
"7: addq 2,%2\n" FIXUP, \
" .dword 6b,7b\n" TENTRY)
#define __asm_copy_to_user_10(to, from, ret) \
__asm_copy_to_user_10x_cont(to, from, ret, "", "", "")
#define __asm_copy_to_user_11(to, from, ret) \
__asm_copy_to_user_10x_cont(to, from, ret, \
" move.b [%1+],$r9\n" \
" move.b $r9,[%0+]\n8:\n", \
"9: addq 1,%2\n", \
" .dword 8b,9b\n")
#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_to_user_8x_cont(to, from, ret, \
" move.d [%1+],$r9\n" \
" move.d $r9,[%0+]\n6:\n" COPY, \
"7: addq 4,%2\n" FIXUP, \
" .dword 6b,7b\n" TENTRY)
#define __asm_copy_to_user_12(to, from, ret) \
__asm_copy_to_user_12x_cont(to, from, ret, "", "", "")
#define __asm_copy_to_user_13(to, from, ret) \
__asm_copy_to_user_12x_cont(to, from, ret, \
" move.b [%1+],$r9\n" \
" move.b $r9,[%0+]\n8:\n", \
"9: addq 1,%2\n", \
" .dword 8b,9b\n")
#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_to_user_12x_cont(to, from, ret, \
" move.w [%1+],$r9\n" \
" move.w $r9,[%0+]\n8:\n" COPY, \
"9: addq 2,%2\n" FIXUP, \
" .dword 8b,9b\n" TENTRY)
#define __asm_copy_to_user_14(to, from, ret) \
__asm_copy_to_user_14x_cont(to, from, ret, "", "", "")
#define __asm_copy_to_user_15(to, from, ret) \
__asm_copy_to_user_14x_cont(to, from, ret, \
" move.b [%1+],$r9\n" \
" move.b $r9,[%0+]\n10:\n", \
"11: addq 1,%2\n", \
" .dword 10b,11b\n")
#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_to_user_12x_cont(to, from, ret, \
" move.d [%1+],$r9\n" \
" move.d $r9,[%0+]\n8:\n" COPY, \
"9: addq 4,%2\n" FIXUP, \
" .dword 8b,9b\n" TENTRY)
#define __asm_copy_to_user_16(to, from, ret) \
__asm_copy_to_user_16x_cont(to, from, ret, "", "", "")
#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_to_user_16x_cont(to, from, ret, \
" move.d [%1+],$r9\n" \
" move.d $r9,[%0+]\n10:\n" COPY, \
"11: addq 4,%2\n" FIXUP, \
" .dword 10b,11b\n" TENTRY)
#define __asm_copy_to_user_20(to, from, ret) \
__asm_copy_to_user_20x_cont(to, from, ret, "", "", "")
#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
__asm_copy_to_user_20x_cont(to, from, ret, \
" move.d [%1+],$r9\n" \
" move.d $r9,[%0+]\n12:\n" COPY, \
"13: addq 4,%2\n" FIXUP, \
" .dword 12b,13b\n" TENTRY)
#define __asm_copy_to_user_24(to, from, ret) \
__asm_copy_to_user_24x_cont(to, from, ret, "", "", "")
/* Define a few clearing asms with exception handlers. */
/* This frame-asm is like the __asm_copy_user_cont one, but has one less
input. */
#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \
__asm__ __volatile__ ( \
CLEAR \
"1:\n" \
" .section .fixup,\"ax\"\n" \
FIXUP \
" jump 1b\n" \
" .previous\n" \
" .section __ex_table,\"a\"\n" \
TENTRY \
" .previous" \
: "=r" (to), "=r" (ret) \
: "0" (to), "1" (ret) \
: "memory")
#define __asm_clear_1(to, ret) \
__asm_clear(to, ret, \
" clear.b [%0+]\n2:\n", \
"3: addq 1,%1\n", \
" .dword 2b,3b\n")
#define __asm_clear_2(to, ret) \
__asm_clear(to, ret, \
" clear.w [%0+]\n2:\n", \
"3: addq 2,%1\n", \
" .dword 2b,3b\n")
#define __asm_clear_3(to, ret) \
__asm_clear(to, ret, \
" clear.w [%0+]\n" \
"2: clear.b [%0+]\n3:\n", \
"4: addq 2,%1\n" \
"5: addq 1,%1\n", \
" .dword 2b,4b\n" \
" .dword 3b,5b\n")
#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
__asm_clear(to, ret, \
" clear.d [%0+]\n2:\n" CLEAR, \
"3: addq 4,%1\n" FIXUP, \
" .dword 2b,3b\n" TENTRY)
#define __asm_clear_4(to, ret) \
__asm_clear_4x_cont(to, ret, "", "", "")
#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
__asm_clear_4x_cont(to, ret, \
" clear.d [%0+]\n4:\n" CLEAR, \
"5: addq 4,%1\n" FIXUP, \
" .dword 4b,5b\n" TENTRY)
#define __asm_clear_8(to, ret) \
__asm_clear_8x_cont(to, ret, "", "", "")
#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
__asm_clear_8x_cont(to, ret, \
" clear.d [%0+]\n6:\n" CLEAR, \
"7: addq 4,%1\n" FIXUP, \
" .dword 6b,7b\n" TENTRY)
#define __asm_clear_12(to, ret) \
__asm_clear_12x_cont(to, ret, "", "", "")
#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
__asm_clear_12x_cont(to, ret, \
" clear.d [%0+]\n8:\n" CLEAR, \
"9: addq 4,%1\n" FIXUP, \
" .dword 8b,9b\n" TENTRY)
#define __asm_clear_16(to, ret) \
__asm_clear_16x_cont(to, ret, "", "", "")
#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
__asm_clear_16x_cont(to, ret, \
" clear.d [%0+]\n10:\n" CLEAR, \
"11: addq 4,%1\n" FIXUP, \
" .dword 10b,11b\n" TENTRY)
#define __asm_clear_20(to, ret) \
__asm_clear_20x_cont(to, ret, "", "", "")
#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
__asm_clear_20x_cont(to, ret, \
" clear.d [%0+]\n12:\n" CLEAR, \
"13: addq 4,%1\n" FIXUP, \
" .dword 12b,13b\n" TENTRY)
#define __asm_clear_24(to, ret) \
__asm_clear_24x_cont(to, ret, "", "", "")
/*
* Return the size of a string (including the ending 0)
*
* Return length of string in userspace including terminating 0
* or 0 for error. Return a value greater than N if too long.
*/
static inline long
strnlen_user(const char *s, long n)
{
long res, tmp1;
if (!access_ok(VERIFY_READ, s, 0))
return 0;
/*
* This code is deduced from:
*
* tmp1 = n;
* while (tmp1-- > 0 && *s++)
* ;
*
* res = n - tmp1;
*
* (with tweaks).
*/
__asm__ __volatile__ (
" move.d %1,$r9\n"
"0:\n"
" ble 1f\n"
" subq 1,$r9\n"
" test.b [%0+]\n"
" bne 0b\n"
" test.d $r9\n"
"1:\n"
" move.d %1,%0\n"
" sub.d $r9,%0\n"
"2:\n"
" .section .fixup,\"ax\"\n"
"3: clear.d %0\n"
" jump 2b\n"
/* There's one address for a fault at the first move, and
two possible PC values for a fault at the second move,
being a delay-slot filler. However, the branch-target
for the second move is the same as the first address.
Just so you don't get confused... */
" .previous\n"
" .section __ex_table,\"a\"\n"
" .dword 0b,3b\n"
" .dword 1b,3b\n"
" .previous\n"
: "=r" (res), "=r" (tmp1)
: "0" (s), "1" (n)
: "r9");
return res;
}
#endif

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arch/cris/include/arch-v10/arch/unistd.h Normal file
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#ifndef _ASM_CRIS_ARCH_UNISTD_H_
#define _ASM_CRIS_ARCH_UNISTD_H_
/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
/*
* Don't remove the .ifnc tests; they are an insurance against
* any hard-to-spot gcc register allocation bugs.
*/
#define _syscall0(type,name) \
type name(void) \
{ \
register long __a __asm__ ("r10"); \
register long __n_ __asm__ ("r9") = (__NR_##name); \
__asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
".err\n\t" \
".endif\n\t" \
"break 13" \
: "=r" (__a) \
: "r" (__n_)); \
if (__a >= 0) \
return (type) __a; \
errno = -__a; \
return (type) -1; \
}
#define _syscall1(type,name,type1,arg1) \
type name(type1 arg1) \
{ \
register long __a __asm__ ("r10") = (long) arg1; \
register long __n_ __asm__ ("r9") = (__NR_##name); \
__asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
".err\n\t" \
".endif\n\t" \
"break 13" \
: "=r" (__a) \
: "r" (__n_), "0" (__a)); \
if (__a >= 0) \
return (type) __a; \
errno = -__a; \
return (type) -1; \
}
#define _syscall2(type,name,type1,arg1,type2,arg2) \
type name(type1 arg1,type2 arg2) \
{ \
register long __a __asm__ ("r10") = (long) arg1; \
register long __b __asm__ ("r11") = (long) arg2; \
register long __n_ __asm__ ("r9") = (__NR_##name); \
__asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \
".err\n\t" \
".endif\n\t" \
"break 13" \
: "=r" (__a) \
: "r" (__n_), "0" (__a), "r" (__b)); \
if (__a >= 0) \
return (type) __a; \
errno = -__a; \
return (type) -1; \
}
#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
type name(type1 arg1,type2 arg2,type3 arg3) \
{ \
register long __a __asm__ ("r10") = (long) arg1; \
register long __b __asm__ ("r11") = (long) arg2; \
register long __c __asm__ ("r12") = (long) arg3; \
register long __n_ __asm__ ("r9") = (__NR_##name); \
__asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \
".err\n\t" \
".endif\n\t" \
"break 13" \
: "=r" (__a) \
: "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \
if (__a >= 0) \
return (type) __a; \
errno = -__a; \
return (type) -1; \
}
#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
{ \
register long __a __asm__ ("r10") = (long) arg1; \
register long __b __asm__ ("r11") = (long) arg2; \
register long __c __asm__ ("r12") = (long) arg3; \
register long __d __asm__ ("r13") = (long) arg4; \
register long __n_ __asm__ ("r9") = (__NR_##name); \
__asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
".err\n\t" \
".endif\n\t" \
"break 13" \
: "=r" (__a) \
: "r" (__n_), "0" (__a), "r" (__b), \
"r" (__c), "r" (__d)); \
if (__a >= 0) \
return (type) __a; \
errno = -__a; \
return (type) -1; \
}
#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
type5,arg5) \
type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \
{ \
register long __a __asm__ ("r10") = (long) arg1; \
register long __b __asm__ ("r11") = (long) arg2; \
register long __c __asm__ ("r12") = (long) arg3; \
register long __d __asm__ ("r13") = (long) arg4; \
register long __n_ __asm__ ("r9") = (__NR_##name); \
__asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
".err\n\t" \
".endif\n\t" \
"move %6,$mof\n\t" \
"break 13" \
: "=r" (__a) \
: "r" (__n_), "0" (__a), "r" (__b), \
"r" (__c), "r" (__d), "g" (arg5)); \
if (__a >= 0) \
return (type) __a; \
errno = -__a; \
return (type) -1; \
}
#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
type5,arg5,type6,arg6) \
type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \
{ \
register long __a __asm__ ("r10") = (long) arg1; \
register long __b __asm__ ("r11") = (long) arg2; \
register long __c __asm__ ("r12") = (long) arg3; \
register long __d __asm__ ("r13") = (long) arg4; \
register long __n_ __asm__ ("r9") = (__NR_##name); \
__asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
".err\n\t" \
".endif\n\t" \
"move %6,$mof\n\tmove %7,$srp\n\t" \
"break 13" \
: "=r" (__a) \
: "r" (__n_), "0" (__a), "r" (__b), \
"r" (__c), "r" (__d), "g" (arg5), "g" (arg6)\
: "srp"); \
if (__a >= 0) \
return (type) __a; \
errno = -__a; \
return (type) -1; \
}
#endif

1
arch/cris/include/arch-v32/arch/Kbuild Normal file
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# CRISv32 arch

36
arch/cris/include/arch-v32/arch/atomic.h Normal file
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#ifndef __ASM_CRIS_ARCH_ATOMIC__
#define __ASM_CRIS_ARCH_ATOMIC__
#include <linux/spinlock_types.h>
extern void cris_spin_unlock(void *l, int val);
extern void cris_spin_lock(void *l);
extern int cris_spin_trylock(void* l);
#ifndef CONFIG_SMP
#define cris_atomic_save(addr, flags) local_irq_save(flags);
#define cris_atomic_restore(addr, flags) local_irq_restore(flags);
#else
extern spinlock_t cris_atomic_locks[];
#define LOCK_COUNT 128
#define HASH_ADDR(a) (((int)a) & 127)
#define cris_atomic_save(addr, flags) \
local_irq_save(flags); \
cris_spin_lock((void *)&cris_atomic_locks[HASH_ADDR(addr)].raw_lock.slock);
#define cris_atomic_restore(addr, flags) \
{ \
spinlock_t *lock = (void*)&cris_atomic_locks[HASH_ADDR(addr)]; \
__asm__ volatile ("move.d %1,%0" \
: "=m" (lock->raw_lock.slock) \
: "r" (1) \
: "memory"); \
local_irq_restore(flags); \
}
#endif
#endif

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arch/cris/include/arch-v32/arch/bitops.h Normal file
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#ifndef _ASM_CRIS_ARCH_BITOPS_H
#define _ASM_CRIS_ARCH_BITOPS_H
/*
* Helper functions for the core of the ff[sz] functions. They compute the
* number of leading zeroes of a bits-in-byte, byte-in-word and
* word-in-dword-swapped number. They differ in that the first function also
* inverts all bits in the input.
*/
static inline unsigned long
cris_swapnwbrlz(unsigned long w)
{
unsigned long res;
__asm__ __volatile__ ("swapnwbr %0\n\t"
"lz %0,%0"
: "=r" (res) : "0" (w));
return res;
}
static inline unsigned long
cris_swapwbrlz(unsigned long w)
{
unsigned long res;
__asm__ __volatile__ ("swapwbr %0\n\t"
"lz %0,%0"
: "=r" (res) : "0" (w));
return res;
}
/*
* Find First Zero in word. Undefined if no zero exist, so the caller should
* check against ~0 first.
*/
static inline unsigned long
ffz(unsigned long w)
{
return cris_swapnwbrlz(w);
}
/*
* Find First Set bit in word. Undefined if no 1 exist, so the caller
* should check against 0 first.
*/
static inline unsigned long
__ffs(unsigned long w)
{
return cris_swapnwbrlz(~w);
}
/*
* Find First Bit that is set.
*/
static inline unsigned long
kernel_ffs(unsigned long w)
{
return w ? cris_swapwbrlz (w) + 1 : 0;
}
#endif /* _ASM_CRIS_ARCH_BITOPS_H */

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arch/cris/include/arch-v32/arch/bug.h Normal file
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#ifndef __ASM_CRISv32_ARCH_BUG_H
#define __ASM_CRISv32_ARCH_BUG_H
#include <linux/stringify.h>
#ifdef CONFIG_BUG
#ifdef CONFIG_DEBUG_BUGVERBOSE
/*
* The penalty for the in-band code path will be the size of break 14.
* All other stuff is done out-of-band with exception handlers.
*/
#define BUG() \
__asm__ __volatile__ ("0: break 14\n\t" \
".section .fixup,\"ax\"\n" \
"1:\n\t" \
"move.d %0, $r10\n\t" \
"move.d %1, $r11\n\t" \
"jump do_BUG\n\t" \
"nop\n\t" \
".previous\n\t" \
".section __ex_table,\"a\"\n\t" \
".dword 0b, 1b\n\t" \
".previous\n\t" \
: : "ri" (__FILE__), "i" (__LINE__))
#else
#define BUG() __asm__ __volatile__ ("break 14\n\t")
#endif
#define HAVE_ARCH_BUG
#endif
#include <asm-generic/bug.h>
#endif

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arch/cris/include/arch-v32/arch/cache.h Normal file
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#ifndef _ASM_CRIS_ARCH_CACHE_H
#define _ASM_CRIS_ARCH_CACHE_H
#include <arch/hwregs/dma.h>
/* A cache-line is 32 bytes. */
#define L1_CACHE_BYTES 32
#define L1_CACHE_SHIFT 5
#define __read_mostly __attribute__((__section__(".data..read_mostly")))
void flush_dma_list(dma_descr_data *descr);
void flush_dma_descr(dma_descr_data *descr, int flush_buf);
#define flush_dma_context(c) \
flush_dma_list(phys_to_virt((c)->saved_data));
void cris_flush_cache_range(void *buf, unsigned long len);
void cris_flush_cache(void);
#endif /* _ASM_CRIS_ARCH_CACHE_H */

29
arch/cris/include/arch-v32/arch/checksum.h Normal file
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#ifndef _ASM_CRIS_ARCH_CHECKSUM_H
#define _ASM_CRIS_ARCH_CHECKSUM_H
/*
* Check values used in TCP/UDP headers.
*
* The gain of doing this in assembler instead of C, is that C doesn't
* generate carry-additions for the 32-bit components of the
* checksum. Which means it would be necessary to split all those into
* 16-bit components and then add.
*/
static inline __wsum
csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
unsigned short len, unsigned short proto, __wsum sum)
{
__wsum res;
__asm__ __volatile__ ("add.d %2, %0\n\t"
"addc %3, %0\n\t"
"addc %4, %0\n\t"
"addc 0, %0\n\t"
: "=r" (res)
: "0" (sum), "r" (daddr), "r" (saddr), \
"r" ((len + proto) << 8));
return res;
}
#endif /* _ASM_CRIS_ARCH_CHECKSUM_H */

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arch/cris/include/arch-v32/arch/cryptocop.h Normal file
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/*
* The device /dev/cryptocop is accessible using this driver using
* CRYPTOCOP_MAJOR (254) and minor number 0.
*/
#ifndef CRYPTOCOP_H
#define CRYPTOCOP_H
#include <uapi/arch-v32/arch/cryptocop.h>
/********** The API to use from inside the kernel. ************/
#include <arch/hwregs/dma.h>
typedef enum {
cryptocop_alg_csum = 0,
cryptocop_alg_mem2mem,
cryptocop_alg_md5,
cryptocop_alg_sha1,
cryptocop_alg_des,
cryptocop_alg_3des,
cryptocop_alg_aes,
cryptocop_no_alg,
} cryptocop_algorithm;
typedef u8 cryptocop_tfrm_id;
struct cryptocop_operation;
typedef void (cryptocop_callback)(struct cryptocop_operation*, void*);
struct cryptocop_transform_init {
cryptocop_algorithm alg;
/* Keydata for ciphers. */
unsigned char key[CRYPTOCOP_MAX_KEY_LENGTH];
unsigned int keylen;
cryptocop_cipher_mode cipher_mode;
cryptocop_3des_mode tdes_mode;
cryptocop_csum_type csum_mode; /* cryptocop_csum_none is not allowed when alg==cryptocop_alg_csum */
cryptocop_tfrm_id tid; /* Locally unique in session; assigned by user, checked by driver. */
struct cryptocop_transform_init *next;
};
typedef enum {
cryptocop_source_dma = 0,
cryptocop_source_des,
cryptocop_source_3des,
cryptocop_source_aes,
cryptocop_source_md5,
cryptocop_source_sha1,
cryptocop_source_csum,
cryptocop_source_none,
} cryptocop_source;
struct cryptocop_desc_cfg {
cryptocop_tfrm_id tid;
cryptocop_source src;
unsigned int last:1; /* Last use of this transform in the operation. Will push outdata when encountered. */
struct cryptocop_desc_cfg *next;
};
struct cryptocop_desc {
size_t length;
struct cryptocop_desc_cfg *cfg;
struct cryptocop_desc *next;
};
/* Flags for cryptocop_tfrm_cfg */
#define CRYPTOCOP_NO_FLAG (0x00)
#define CRYPTOCOP_ENCRYPT (0x01)
#define CRYPTOCOP_DECRYPT (0x02)
#define CRYPTOCOP_EXPLICIT_IV (0x04)
struct cryptocop_tfrm_cfg {
cryptocop_tfrm_id tid;
unsigned int flags; /* DECRYPT, ENCRYPT, EXPLICIT_IV */
/* CBC initialisation vector for cihers. */
u8 iv[CRYPTOCOP_MAX_IV_LENGTH];
/* The position in output where to write the transform output. The order
in which the driver writes the output is unspecified, hence if several
transforms write on the same positions in the output the result is
unspecified. */
size_t inject_ix;
struct cryptocop_tfrm_cfg *next;
};
struct cryptocop_dma_list_operation{
/* The consumer can provide DMA lists to send to the co-processor. 'use_dmalists' in
struct cryptocop_operation must be set for the driver to use them. outlist,
out_data_buf, inlist and in_data_buf must all be physical addresses since they will
be loaded to DMA . */
dma_descr_data *outlist; /* Out from memory to the co-processor. */
char *out_data_buf;
dma_descr_data *inlist; /* In from the co-processor to memory. */
char *in_data_buf;
cryptocop_3des_mode tdes_mode;
cryptocop_csum_type csum_mode;
};
struct cryptocop_tfrm_operation{
/* Operation configuration, if not 'use_dmalists' is set. */
struct cryptocop_tfrm_cfg *tfrm_cfg;
struct cryptocop_desc *desc;
struct iovec *indata;
size_t incount;
size_t inlen; /* Total inlength. */
struct iovec *outdata;
size_t outcount;
size_t outlen; /* Total outlength. */
};
struct cryptocop_operation {
cryptocop_callback *cb;
void *cb_data;
cryptocop_session_id sid;
/* The status of the operation when returned to consumer. */
int operation_status; /* 0, -EAGAIN */
/* Flags */
unsigned int use_dmalists:1; /* Use outlist and inlist instead of the desc/tfrm_cfg configuration. */
unsigned int in_interrupt:1; /* Set if inserting job from interrupt context. */
unsigned int fast_callback:1; /* Set if fast callback wanted, i.e. from interrupt context. */
union{
struct cryptocop_dma_list_operation list_op;
struct cryptocop_tfrm_operation tfrm_op;
};
};
int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag);
int cryptocop_free_session(cryptocop_session_id sid);
int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation);
int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation);
int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation);
#endif /* CRYPTOCOP_H */

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arch/cris/include/arch-v32/arch/delay.h Normal file
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#ifndef _ASM_CRIS_ARCH_DELAY_H
#define _ASM_CRIS_ARCH_DELAY_H
extern void cris_delay10ns(u32 n10ns);
#define udelay(u) cris_delay10ns((u)*100)
#define ndelay(n) cris_delay10ns(((n)+9)/10)
/*
* Not used anymore for udelay or ndelay. Referenced by
* e.g. init/calibrate.c. All other references are likely bugs;
* should be replaced by mdelay, udelay or ndelay.
*/
static inline void
__delay(int loops)
{
__asm__ __volatile__ (
"move.d %0, $r9\n\t"
"beq 2f\n\t"
"subq 1, $r9\n\t"
"1:\n\t"
"bne 1b\n\t"
"subq 1, $r9\n"
"2:"
: : "g" (loops) : "r9");
}
#endif /* _ASM_CRIS_ARCH_DELAY_H */

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arch/cris/include/arch-v32/arch/dma.h Normal file
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#include <mach/dma.h>

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arch/cris/include/arch-v32/arch/elf.h Normal file
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#ifndef _ASM_CRIS_ELF_H
#define _ASM_CRIS_ELF_H
#include <arch/system.h>
#define ELF_CORE_EFLAGS EF_CRIS_VARIANT_V32
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch(x) \
((x)->e_machine == EM_CRIS \
&& ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_V32 \
|| (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32))))
/* CRISv32 ELF register definitions. */
#include <asm/ptrace.h>
/* Explicitly zero out registers to increase determinism. */
#define ELF_PLAT_INIT(_r, load_addr) do { \
(_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \
(_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \
(_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \
(_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \
(_r)->acr = 0; \
} while (0)
/*
* An executable for which elf_read_implies_exec() returns TRUE will
* have the READ_IMPLIES_EXEC personality flag set automatically.
*/
#define elf_read_implies_exec_binary(ex, have_pt_gnu_stack) (!(have_pt_gnu_stack))
/*
* This is basically a pt_regs with the additional definition
* of the stack pointer since it's needed in a core dump.
* pr_regs is a elf_gregset_t and should be filled according
* to the layout of user_regs_struct.
*/
#define ELF_CORE_COPY_REGS(pr_reg, regs) \
pr_reg[0] = regs->r0; \
pr_reg[1] = regs->r1; \
pr_reg[2] = regs->r2; \
pr_reg[3] = regs->r3; \
pr_reg[4] = regs->r4; \
pr_reg[5] = regs->r5; \
pr_reg[6] = regs->r6; \
pr_reg[7] = regs->r7; \
pr_reg[8] = regs->r8; \
pr_reg[9] = regs->r9; \
pr_reg[10] = regs->r10; \
pr_reg[11] = regs->r11; \
pr_reg[12] = regs->r12; \
pr_reg[13] = regs->r13; \
pr_reg[14] = rdusp(); /* SP */ \
pr_reg[15] = regs->acr; /* ACR */ \
pr_reg[16] = 0; /* BZ */ \
pr_reg[17] = rdvr(); /* VR */ \
pr_reg[18] = 0; /* PID */ \
pr_reg[19] = regs->srs; /* SRS */ \
pr_reg[20] = 0; /* WZ */ \
pr_reg[21] = regs->exs; /* EXS */ \
pr_reg[22] = regs->eda; /* EDA */ \
pr_reg[23] = regs->mof; /* MOF */ \
pr_reg[24] = 0; /* DZ */ \
pr_reg[25] = 0; /* EBP */ \
pr_reg[26] = regs->erp; /* ERP */ \
pr_reg[27] = regs->srp; /* SRP */ \
pr_reg[28] = 0; /* NRP */ \
pr_reg[29] = regs->ccs; /* CCS */ \
pr_reg[30] = rdusp(); /* USP */ \
pr_reg[31] = regs->spc; /* SPC */ \
#endif /* _ASM_CRIS_ELF_H */

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# Makefile to generate or copy the latest register definitions
# and related datastructures and helpermacros.
# The official place for these files is at:
RELEASE ?= r1_alfa5
OFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/
# which is updated on each new release.
INCL_ASMFILES =
INCL_FILES = ata_defs.h
INCL_FILES += bif_core_defs.h
INCL_ASMFILES += bif_core_defs_asm.h
INCL_FILES += bif_slave_defs.h
#INCL_FILES += bif_slave_ext_defs.h
INCL_FILES += config_defs.h
INCL_ASMFILES += config_defs_asm.h
INCL_FILES += cpu_vect.h
#INCL_FILES += cris_defs.h
#INCL_FILES += cris_supp_reg.h # In handcrafted supp_reg.h
INCL_FILES += dma.h
INCL_FILES += dma_defs.h
INCL_FILES += eth_defs.h
INCL_FILES += extmem_defs.h
INCL_FILES += gio_defs.h
INCL_ASMFILES += gio_defs_asm.h
INCL_FILES += intr_vect.h
INCL_FILES += intr_vect_defs.h
INCL_ASMFILES += intr_vect_defs_asm.h
INCL_FILES += marb_bp_defs.h
INCL_FILES += marb_defs.h
INCL_ASMFILES += mmu_defs_asm.h
#INCL_FILES += mmu_supp_reg.h # In handcrafted supp_reg.h
#INCL_FILES += par_defs.h # No useful content
INCL_FILES += pinmux_defs.h
INCL_FILES += reg_map.h
INCL_ASMFILES += reg_map_asm.h
INCL_FILES += reg_rdwr.h
INCL_FILES += ser_defs.h
#INCL_FILES += spec_reg.h # In handcrafted supp_reg.h
INCL_FILES += sser_defs.h
INCL_FILES += strcop_defs.h
#INCL_FILES += strcop.h # Where is this?
INCL_FILES += strmux_defs.h
#INCL_FILES += supp_reg.h # Handcrafted instead
INCL_FILES += timer_defs.h
REGDESC =
REGDESC += $(BASEDIR)/io/ata/rtl/ata_regs.r
REGDESC += $(BASEDIR)/io/bif/rtl/bif_core_regs.r
REGDESC += $(BASEDIR)/io/bif/rtl/bif_slave_regs.r
#REGDESC += $(BASEDIR)/io/bif/sw/bif_slave_ext_regs.r
REGDESC += $(DESIGNDIR)/top/rtl/config_regs.r
REGDESC += $(BASEDIR)/mod/dma_common/rtl/dma_regdes.r
REGDESC += $(BASEDIR)/io/eth/rtl/eth_regs.r
REGDESC += $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r
REGDESC += $(DESIGNDIR)/gio/rtl/gio_regs.r
REGDESC += $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
REGDESC += $(BASEDIR)/core/memarb/rtl/guinness/marb_top.r
REGDESC += $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r
#REGDESC += $(BASEDIR)/io/par_port/rtl/par_regs.r
REGDESC += $(BASEDIR)/io/pinmux/rtl/guinness/pinmux_regs.r
REGDESC += $(BASEDIR)/io/ser/rtl/ser_regs.r
REGDESC += $(BASEDIR)/core/strcop/rtl/strcop_regs.r
REGDESC += $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r
REGDESC += $(BASEDIR)/io/timer/rtl/timer_regs.r
#REGDESC += $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r
BASEDIR = /n/asic/design
DESIGNDIR = /n/asic/projects/guinness/design
RDES2C = /n/asic/bin/rdes2c
RDES2C = /n/asic/design/tools/rdesc/rdes2c
RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr
RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt
## all - Just print help - you probably want to do 'make gen'
all: help
# Disable implicit rule that may generate deleted files from RCS/ directory.
%.r:
%.h:
## help - This help
help:
@grep '^## ' Makefile
## gen - Generate include files
gen: $(INCL_FILES) $(INCL_ASMFILES)
ata_defs.h: $(BASEDIR)/io/ata/rtl/ata_regs.r
$(RDES2C) $<
config_defs.h: $(DESIGNDIR)/top/rtl/config_regs.r
$(RDES2C) $<
config_defs_asm.h: $(DESIGNDIR)/top/rtl/config_regs.r
$(RDES2C) -asm $<
# Can't generate cpu_vect.h yet
#cpu_vect.h: $(DESIGNDIR)/top/rtl/cpu_vect.r # ????
# $(RDES2INTR) $<
cpu_vect.h: $(OFFICIAL_INCDIR)cpu_vect.h
cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
dma_defs.h: $(BASEDIR)/core/dma/rtl/common/dma_regdes.r
$(RDES2C) $<
$(BASEDIR)/core/dma/sw/dma.h:
dma.h: $(BASEDIR)/core/dma/sw/dma.h
cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
eth_defs.h: $(BASEDIR)/io/eth/rtl/eth_regs.r
$(RDES2C) $<
extmem_defs.h: $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r
$(RDES2C) $<
gio_defs.h: $(DESIGNDIR)/gio/rtl/gio_regs.r
$(RDES2C) $<
intr_vect_defs.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
$(RDES2C) $<
intr_vect_defs_asm.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
$(RDES2C) -asm $<
# Can't generate intr_vect.h yet
#intr_vect.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
# $(RDES2INTR) $<
intr_vect.h: $(OFFICIAL_INCDIR)intr_vect.h
cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
mmu_defs_asm.h: $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r
$(RDES2C) -asm $<
par_defs.h: $(BASEDIR)/io/par_port/rtl/par_regs.r
$(RDES2C) $<
# From /n/asic/projects/guinness/design/
reg_map.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap
$(RDES2C) -base 0xb0000000 $^
reg_map_asm.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap
$(RDES2C) -base 0xb0000000 -asm -outfile $@ $^
reg_rdwr.h: $(DESIGNDIR)/top/sw/include/reg_rdwr.h
cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
ser_defs.h: $(BASEDIR)/io/ser/rtl/ser_regs.r
$(RDES2C) $<
strcop_defs.h: $(BASEDIR)/core/strcop/rtl/strcop_regs.r
$(RDES2C) $<
strcop.h: $(BASEDIR)/core/strcop/rtl/strcop.h
cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
strmux_defs.h: $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r
$(RDES2C) $<
timer_defs.h: $(BASEDIR)/io/timer/rtl/timer_regs.r
$(RDES2C) $<
usb_defs.h: $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r
$(RDES2C) $<
## copy - Copy files from official location
copy:
@for HFILE in $(INCL_FILES); do \
echo " $$HFILE"; \
cat $(OFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
done
@for HFILE in $(INCL_ASMFILES); do \
echo " $$HFILE"; \
cat $(OFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
done
## ls_official - List official location
ls_official:
(cd $(OFFICIAL_INCDIR); ls -l *.h )
## diff_official - Diff current directory with official location
diff_official:
diff . $(OFFICIAL_INCDIR)
## doc - Generate .axw files from register description.
doc: $(REGDESC)
for RDES in $^; do \
$(RDES2TXT) $$RDES; \
done
.PHONY: axw
## %.axw - Generate the specified .axw file (doesn't work for all files
## due to inconsistent naming ir .r files.
%.axw: axw
@for RDES in $(REGDESC); do \
if echo "$$RDES" | grep $* ; then \
$(RDES2TXT) $$RDES; \
fi \
done
.PHONY: clean
## clean - Remove .h files and .axw files.
clean:
rm -rf $(INCL_FILES) *.axw

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arch/cris/include/arch-v32/arch/hwregs/asm/ata_defs_asm.h Normal file
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#ifndef __ata_defs_asm_h
#define __ata_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/ata/rtl/ata_regs.r
* id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
* last modfied: Mon Apr 11 16:06:25 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r
* id: $Id: ata_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_ctrl0, scope ata, type rw */
#define reg_ata_rw_ctrl0___pio_hold___lsb 0
#define reg_ata_rw_ctrl0___pio_hold___width 6
#define reg_ata_rw_ctrl0___pio_strb___lsb 6
#define reg_ata_rw_ctrl0___pio_strb___width 6
#define reg_ata_rw_ctrl0___pio_setup___lsb 12
#define reg_ata_rw_ctrl0___pio_setup___width 6
#define reg_ata_rw_ctrl0___dma_hold___lsb 18
#define reg_ata_rw_ctrl0___dma_hold___width 6
#define reg_ata_rw_ctrl0___dma_strb___lsb 24
#define reg_ata_rw_ctrl0___dma_strb___width 6
#define reg_ata_rw_ctrl0___rst___lsb 30
#define reg_ata_rw_ctrl0___rst___width 1
#define reg_ata_rw_ctrl0___rst___bit 30
#define reg_ata_rw_ctrl0___en___lsb 31
#define reg_ata_rw_ctrl0___en___width 1
#define reg_ata_rw_ctrl0___en___bit 31
#define reg_ata_rw_ctrl0_offset 12
/* Register rw_ctrl1, scope ata, type rw */
#define reg_ata_rw_ctrl1___udma_tcyc___lsb 0
#define reg_ata_rw_ctrl1___udma_tcyc___width 4
#define reg_ata_rw_ctrl1___udma_tdvs___lsb 4
#define reg_ata_rw_ctrl1___udma_tdvs___width 4
#define reg_ata_rw_ctrl1_offset 16
/* Register rw_ctrl2, scope ata, type rw */
#define reg_ata_rw_ctrl2___data___lsb 0
#define reg_ata_rw_ctrl2___data___width 16
#define reg_ata_rw_ctrl2___dma_size___lsb 19
#define reg_ata_rw_ctrl2___dma_size___width 1
#define reg_ata_rw_ctrl2___dma_size___bit 19
#define reg_ata_rw_ctrl2___multi___lsb 20
#define reg_ata_rw_ctrl2___multi___width 1
#define reg_ata_rw_ctrl2___multi___bit 20
#define reg_ata_rw_ctrl2___hsh___lsb 21
#define reg_ata_rw_ctrl2___hsh___width 2
#define reg_ata_rw_ctrl2___trf_mode___lsb 23
#define reg_ata_rw_ctrl2___trf_mode___width 1
#define reg_ata_rw_ctrl2___trf_mode___bit 23
#define reg_ata_rw_ctrl2___rw___lsb 24
#define reg_ata_rw_ctrl2___rw___width 1
#define reg_ata_rw_ctrl2___rw___bit 24
#define reg_ata_rw_ctrl2___addr___lsb 25
#define reg_ata_rw_ctrl2___addr___width 3
#define reg_ata_rw_ctrl2___cs0___lsb 28
#define reg_ata_rw_ctrl2___cs0___width 1
#define reg_ata_rw_ctrl2___cs0___bit 28
#define reg_ata_rw_ctrl2___cs1___lsb 29
#define reg_ata_rw_ctrl2___cs1___width 1
#define reg_ata_rw_ctrl2___cs1___bit 29
#define reg_ata_rw_ctrl2___sel___lsb 30
#define reg_ata_rw_ctrl2___sel___width 2
#define reg_ata_rw_ctrl2_offset 0
/* Register rs_stat_data, scope ata, type rs */
#define reg_ata_rs_stat_data___data___lsb 0
#define reg_ata_rs_stat_data___data___width 16
#define reg_ata_rs_stat_data___dav___lsb 16
#define reg_ata_rs_stat_data___dav___width 1
#define reg_ata_rs_stat_data___dav___bit 16
#define reg_ata_rs_stat_data___busy___lsb 17
#define reg_ata_rs_stat_data___busy___width 1
#define reg_ata_rs_stat_data___busy___bit 17
#define reg_ata_rs_stat_data_offset 4
/* Register r_stat_data, scope ata, type r */
#define reg_ata_r_stat_data___data___lsb 0
#define reg_ata_r_stat_data___data___width 16
#define reg_ata_r_stat_data___dav___lsb 16
#define reg_ata_r_stat_data___dav___width 1
#define reg_ata_r_stat_data___dav___bit 16
#define reg_ata_r_stat_data___busy___lsb 17
#define reg_ata_r_stat_data___busy___width 1
#define reg_ata_r_stat_data___busy___bit 17
#define reg_ata_r_stat_data_offset 8
/* Register rw_trf_cnt, scope ata, type rw */
#define reg_ata_rw_trf_cnt___cnt___lsb 0
#define reg_ata_rw_trf_cnt___cnt___width 17
#define reg_ata_rw_trf_cnt_offset 20
/* Register r_stat_misc, scope ata, type r */
#define reg_ata_r_stat_misc___crc___lsb 0
#define reg_ata_r_stat_misc___crc___width 16
#define reg_ata_r_stat_misc_offset 24
/* Register rw_intr_mask, scope ata, type rw */
#define reg_ata_rw_intr_mask___bus0___lsb 0
#define reg_ata_rw_intr_mask___bus0___width 1
#define reg_ata_rw_intr_mask___bus0___bit 0
#define reg_ata_rw_intr_mask___bus1___lsb 1
#define reg_ata_rw_intr_mask___bus1___width 1
#define reg_ata_rw_intr_mask___bus1___bit 1
#define reg_ata_rw_intr_mask___bus2___lsb 2
#define reg_ata_rw_intr_mask___bus2___width 1
#define reg_ata_rw_intr_mask___bus2___bit 2
#define reg_ata_rw_intr_mask___bus3___lsb 3
#define reg_ata_rw_intr_mask___bus3___width 1
#define reg_ata_rw_intr_mask___bus3___bit 3
#define reg_ata_rw_intr_mask_offset 28
/* Register rw_ack_intr, scope ata, type rw */
#define reg_ata_rw_ack_intr___bus0___lsb 0
#define reg_ata_rw_ack_intr___bus0___width 1
#define reg_ata_rw_ack_intr___bus0___bit 0
#define reg_ata_rw_ack_intr___bus1___lsb 1
#define reg_ata_rw_ack_intr___bus1___width 1
#define reg_ata_rw_ack_intr___bus1___bit 1
#define reg_ata_rw_ack_intr___bus2___lsb 2
#define reg_ata_rw_ack_intr___bus2___width 1
#define reg_ata_rw_ack_intr___bus2___bit 2
#define reg_ata_rw_ack_intr___bus3___lsb 3
#define reg_ata_rw_ack_intr___bus3___width 1
#define reg_ata_rw_ack_intr___bus3___bit 3
#define reg_ata_rw_ack_intr_offset 32
/* Register r_intr, scope ata, type r */
#define reg_ata_r_intr___bus0___lsb 0
#define reg_ata_r_intr___bus0___width 1
#define reg_ata_r_intr___bus0___bit 0
#define reg_ata_r_intr___bus1___lsb 1
#define reg_ata_r_intr___bus1___width 1
#define reg_ata_r_intr___bus1___bit 1
#define reg_ata_r_intr___bus2___lsb 2
#define reg_ata_r_intr___bus2___width 1
#define reg_ata_r_intr___bus2___bit 2
#define reg_ata_r_intr___bus3___lsb 3
#define reg_ata_r_intr___bus3___width 1
#define reg_ata_r_intr___bus3___bit 3
#define reg_ata_r_intr_offset 36
/* Register r_masked_intr, scope ata, type r */
#define reg_ata_r_masked_intr___bus0___lsb 0
#define reg_ata_r_masked_intr___bus0___width 1
#define reg_ata_r_masked_intr___bus0___bit 0
#define reg_ata_r_masked_intr___bus1___lsb 1
#define reg_ata_r_masked_intr___bus1___width 1
#define reg_ata_r_masked_intr___bus1___bit 1
#define reg_ata_r_masked_intr___bus2___lsb 2
#define reg_ata_r_masked_intr___bus2___width 1
#define reg_ata_r_masked_intr___bus2___bit 2
#define reg_ata_r_masked_intr___bus3___lsb 3
#define reg_ata_r_masked_intr___bus3___width 1
#define reg_ata_r_masked_intr___bus3___bit 3
#define reg_ata_r_masked_intr_offset 40
/* Constants */
#define regk_ata_active 0x00000001
#define regk_ata_byte 0x00000001
#define regk_ata_data 0x00000001
#define regk_ata_dma 0x00000001
#define regk_ata_inactive 0x00000000
#define regk_ata_no 0x00000000
#define regk_ata_nodata 0x00000000
#define regk_ata_pio 0x00000000
#define regk_ata_rd 0x00000001
#define regk_ata_reg 0x00000000
#define regk_ata_rw_ctrl0_default 0x00000000
#define regk_ata_rw_ctrl2_default 0x00000000
#define regk_ata_rw_intr_mask_default 0x00000000
#define regk_ata_udma 0x00000002
#define regk_ata_word 0x00000000
#define regk_ata_wr 0x00000000
#define regk_ata_yes 0x00000001
#endif /* __ata_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/asm/bif_core_defs_asm.h Normal file
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#ifndef __bif_core_defs_asm_h
#define __bif_core_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/bif/rtl/bif_core_regs.r
* id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
* last modfied: Mon Apr 11 16:06:33 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r
* id: $Id: bif_core_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_grp1_cfg, scope bif_core, type rw */
#define reg_bif_core_rw_grp1_cfg___lw___lsb 0
#define reg_bif_core_rw_grp1_cfg___lw___width 6
#define reg_bif_core_rw_grp1_cfg___ew___lsb 6
#define reg_bif_core_rw_grp1_cfg___ew___width 3
#define reg_bif_core_rw_grp1_cfg___zw___lsb 9
#define reg_bif_core_rw_grp1_cfg___zw___width 3
#define reg_bif_core_rw_grp1_cfg___aw___lsb 12
#define reg_bif_core_rw_grp1_cfg___aw___width 2
#define reg_bif_core_rw_grp1_cfg___dw___lsb 14
#define reg_bif_core_rw_grp1_cfg___dw___width 2
#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16
#define reg_bif_core_rw_grp1_cfg___ewb___width 2
#define reg_bif_core_rw_grp1_cfg___bw___lsb 18
#define reg_bif_core_rw_grp1_cfg___bw___width 1
#define reg_bif_core_rw_grp1_cfg___bw___bit 18
#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19
#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1
#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19
#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20
#define reg_bif_core_rw_grp1_cfg___erc_en___width 1
#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20
#define reg_bif_core_rw_grp1_cfg___mode___lsb 21
#define reg_bif_core_rw_grp1_cfg___mode___width 1
#define reg_bif_core_rw_grp1_cfg___mode___bit 21
#define reg_bif_core_rw_grp1_cfg_offset 0
/* Register rw_grp2_cfg, scope bif_core, type rw */
#define reg_bif_core_rw_grp2_cfg___lw___lsb 0
#define reg_bif_core_rw_grp2_cfg___lw___width 6
#define reg_bif_core_rw_grp2_cfg___ew___lsb 6
#define reg_bif_core_rw_grp2_cfg___ew___width 3
#define reg_bif_core_rw_grp2_cfg___zw___lsb 9
#define reg_bif_core_rw_grp2_cfg___zw___width 3
#define reg_bif_core_rw_grp2_cfg___aw___lsb 12
#define reg_bif_core_rw_grp2_cfg___aw___width 2
#define reg_bif_core_rw_grp2_cfg___dw___lsb 14
#define reg_bif_core_rw_grp2_cfg___dw___width 2
#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16
#define reg_bif_core_rw_grp2_cfg___ewb___width 2
#define reg_bif_core_rw_grp2_cfg___bw___lsb 18
#define reg_bif_core_rw_grp2_cfg___bw___width 1
#define reg_bif_core_rw_grp2_cfg___bw___bit 18
#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19
#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1
#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19
#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20
#define reg_bif_core_rw_grp2_cfg___erc_en___width 1
#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20
#define reg_bif_core_rw_grp2_cfg___mode___lsb 21
#define reg_bif_core_rw_grp2_cfg___mode___width 1
#define reg_bif_core_rw_grp2_cfg___mode___bit 21
#define reg_bif_core_rw_grp2_cfg_offset 4
/* Register rw_grp3_cfg, scope bif_core, type rw */
#define reg_bif_core_rw_grp3_cfg___lw___lsb 0
#define reg_bif_core_rw_grp3_cfg___lw___width 6
#define reg_bif_core_rw_grp3_cfg___ew___lsb 6
#define reg_bif_core_rw_grp3_cfg___ew___width 3
#define reg_bif_core_rw_grp3_cfg___zw___lsb 9
#define reg_bif_core_rw_grp3_cfg___zw___width 3
#define reg_bif_core_rw_grp3_cfg___aw___lsb 12
#define reg_bif_core_rw_grp3_cfg___aw___width 2
#define reg_bif_core_rw_grp3_cfg___dw___lsb 14
#define reg_bif_core_rw_grp3_cfg___dw___width 2
#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16
#define reg_bif_core_rw_grp3_cfg___ewb___width 2
#define reg_bif_core_rw_grp3_cfg___bw___lsb 18
#define reg_bif_core_rw_grp3_cfg___bw___width 1
#define reg_bif_core_rw_grp3_cfg___bw___bit 18
#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19
#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1
#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19
#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20
#define reg_bif_core_rw_grp3_cfg___erc_en___width 1
#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20
#define reg_bif_core_rw_grp3_cfg___mode___lsb 21
#define reg_bif_core_rw_grp3_cfg___mode___width 1
#define reg_bif_core_rw_grp3_cfg___mode___bit 21
#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24
#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2
#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26
#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2
#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28
#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2
#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30
#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2
#define reg_bif_core_rw_grp3_cfg_offset 8
/* Register rw_grp4_cfg, scope bif_core, type rw */
#define reg_bif_core_rw_grp4_cfg___lw___lsb 0
#define reg_bif_core_rw_grp4_cfg___lw___width 6
#define reg_bif_core_rw_grp4_cfg___ew___lsb 6
#define reg_bif_core_rw_grp4_cfg___ew___width 3
#define reg_bif_core_rw_grp4_cfg___zw___lsb 9
#define reg_bif_core_rw_grp4_cfg___zw___width 3
#define reg_bif_core_rw_grp4_cfg___aw___lsb 12
#define reg_bif_core_rw_grp4_cfg___aw___width 2
#define reg_bif_core_rw_grp4_cfg___dw___lsb 14
#define reg_bif_core_rw_grp4_cfg___dw___width 2
#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16
#define reg_bif_core_rw_grp4_cfg___ewb___width 2
#define reg_bif_core_rw_grp4_cfg___bw___lsb 18
#define reg_bif_core_rw_grp4_cfg___bw___width 1
#define reg_bif_core_rw_grp4_cfg___bw___bit 18
#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19
#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1
#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19
#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20
#define reg_bif_core_rw_grp4_cfg___erc_en___width 1
#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20
#define reg_bif_core_rw_grp4_cfg___mode___lsb 21
#define reg_bif_core_rw_grp4_cfg___mode___width 1
#define reg_bif_core_rw_grp4_cfg___mode___bit 21
#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26
#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2
#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28
#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2
#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30
#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2
#define reg_bif_core_rw_grp4_cfg_offset 12
/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0
#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5
#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5
#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3
#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8
#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1
#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8
#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9
#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1
#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9
#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10
#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3
#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13
#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1
#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13
#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14
#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1
#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14
#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15
#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5
#define reg_bif_core_rw_sdram_cfg_grp0_offset 16
/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0
#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5
#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5
#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3
#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8
#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1
#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8
#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9
#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1
#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9
#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10
#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3
#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13
#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1
#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13
#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14
#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1
#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14
#define reg_bif_core_rw_sdram_cfg_grp1_offset 20
/* Register rw_sdram_timing, scope bif_core, type rw */
#define reg_bif_core_rw_sdram_timing___cl___lsb 0
#define reg_bif_core_rw_sdram_timing___cl___width 3
#define reg_bif_core_rw_sdram_timing___rcd___lsb 3
#define reg_bif_core_rw_sdram_timing___rcd___width 3
#define reg_bif_core_rw_sdram_timing___rp___lsb 6
#define reg_bif_core_rw_sdram_timing___rp___width 3
#define reg_bif_core_rw_sdram_timing___rc___lsb 9
#define reg_bif_core_rw_sdram_timing___rc___width 2
#define reg_bif_core_rw_sdram_timing___dpl___lsb 11
#define reg_bif_core_rw_sdram_timing___dpl___width 2
#define reg_bif_core_rw_sdram_timing___pde___lsb 13
#define reg_bif_core_rw_sdram_timing___pde___width 1
#define reg_bif_core_rw_sdram_timing___pde___bit 13
#define reg_bif_core_rw_sdram_timing___ref___lsb 14
#define reg_bif_core_rw_sdram_timing___ref___width 2
#define reg_bif_core_rw_sdram_timing___cpd___lsb 16
#define reg_bif_core_rw_sdram_timing___cpd___width 1
#define reg_bif_core_rw_sdram_timing___cpd___bit 16
#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17
#define reg_bif_core_rw_sdram_timing___sdcke___width 1
#define reg_bif_core_rw_sdram_timing___sdcke___bit 17
#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18
#define reg_bif_core_rw_sdram_timing___sdclk___width 1
#define reg_bif_core_rw_sdram_timing___sdclk___bit 18
#define reg_bif_core_rw_sdram_timing_offset 24
/* Register rw_sdram_cmd, scope bif_core, type rw */
#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0
#define reg_bif_core_rw_sdram_cmd___cmd___width 3
#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3
#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15
#define reg_bif_core_rw_sdram_cmd_offset 28
/* Register rs_sdram_ref_stat, scope bif_core, type rs */
#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0
#define reg_bif_core_rs_sdram_ref_stat___ok___width 1
#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0
#define reg_bif_core_rs_sdram_ref_stat_offset 32
/* Register r_sdram_ref_stat, scope bif_core, type r */
#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0
#define reg_bif_core_r_sdram_ref_stat___ok___width 1
#define reg_bif_core_r_sdram_ref_stat___ok___bit 0
#define reg_bif_core_r_sdram_ref_stat_offset 36
/* Constants */
#define regk_bif_core_bank2 0x00000000
#define regk_bif_core_bank4 0x00000001
#define regk_bif_core_bit10 0x0000000a
#define regk_bif_core_bit11 0x0000000b
#define regk_bif_core_bit12 0x0000000c
#define regk_bif_core_bit13 0x0000000d
#define regk_bif_core_bit14 0x0000000e
#define regk_bif_core_bit15 0x0000000f
#define regk_bif_core_bit16 0x00000010
#define regk_bif_core_bit17 0x00000011
#define regk_bif_core_bit18 0x00000012
#define regk_bif_core_bit19 0x00000013
#define regk_bif_core_bit20 0x00000014
#define regk_bif_core_bit21 0x00000015
#define regk_bif_core_bit22 0x00000016
#define regk_bif_core_bit23 0x00000017
#define regk_bif_core_bit24 0x00000018
#define regk_bif_core_bit25 0x00000019
#define regk_bif_core_bit26 0x0000001a
#define regk_bif_core_bit27 0x0000001b
#define regk_bif_core_bit28 0x0000001c
#define regk_bif_core_bit29 0x0000001d
#define regk_bif_core_bit9 0x00000009
#define regk_bif_core_bw16 0x00000001
#define regk_bif_core_bw32 0x00000000
#define regk_bif_core_bwe 0x00000000
#define regk_bif_core_cwe 0x00000001
#define regk_bif_core_e15us 0x00000001
#define regk_bif_core_e7800ns 0x00000002
#define regk_bif_core_grp0 0x00000000
#define regk_bif_core_grp1 0x00000001
#define regk_bif_core_mrs 0x00000003
#define regk_bif_core_no 0x00000000
#define regk_bif_core_none 0x00000000
#define regk_bif_core_nop 0x00000000
#define regk_bif_core_off 0x00000000
#define regk_bif_core_pre 0x00000002
#define regk_bif_core_r_sdram_ref_stat_default 0x00000001
#define regk_bif_core_rd 0x00000002
#define regk_bif_core_ref 0x00000001
#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001
#define regk_bif_core_rw_grp1_cfg_default 0x000006cf
#define regk_bif_core_rw_grp2_cfg_default 0x000006cf
#define regk_bif_core_rw_grp3_cfg_default 0x000006cf
#define regk_bif_core_rw_grp4_cfg_default 0x000006cf
#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000
#define regk_bif_core_slf 0x00000004
#define regk_bif_core_wr 0x00000001
#define regk_bif_core_yes 0x00000001
#endif /* __bif_core_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/asm/bif_dma_defs_asm.h Normal file
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#ifndef __bif_dma_defs_asm_h
#define __bif_dma_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/bif/rtl/bif_dma_regs.r
* id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
* last modfied: Mon Apr 11 16:06:33 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r
* id: $Id: bif_dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_ch0_ctrl, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch0_ctrl___bw___lsb 0
#define reg_bif_dma_rw_ch0_ctrl___bw___width 2
#define reg_bif_dma_rw_ch0_ctrl___burst_len___lsb 2
#define reg_bif_dma_rw_ch0_ctrl___burst_len___width 1
#define reg_bif_dma_rw_ch0_ctrl___burst_len___bit 2
#define reg_bif_dma_rw_ch0_ctrl___cont___lsb 3
#define reg_bif_dma_rw_ch0_ctrl___cont___width 1
#define reg_bif_dma_rw_ch0_ctrl___cont___bit 3
#define reg_bif_dma_rw_ch0_ctrl___end_pad___lsb 4
#define reg_bif_dma_rw_ch0_ctrl___end_pad___width 1
#define reg_bif_dma_rw_ch0_ctrl___end_pad___bit 4
#define reg_bif_dma_rw_ch0_ctrl___cnt___lsb 5
#define reg_bif_dma_rw_ch0_ctrl___cnt___width 1
#define reg_bif_dma_rw_ch0_ctrl___cnt___bit 5
#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___lsb 6
#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___width 3
#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___lsb 9
#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___width 2
#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___lsb 11
#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___width 3
#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___lsb 14
#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___width 2
#define reg_bif_dma_rw_ch0_ctrl___bus_mode___lsb 16
#define reg_bif_dma_rw_ch0_ctrl___bus_mode___width 2
#define reg_bif_dma_rw_ch0_ctrl___rate_en___lsb 18
#define reg_bif_dma_rw_ch0_ctrl___rate_en___width 1
#define reg_bif_dma_rw_ch0_ctrl___rate_en___bit 18
#define reg_bif_dma_rw_ch0_ctrl___wr_all___lsb 19
#define reg_bif_dma_rw_ch0_ctrl___wr_all___width 1
#define reg_bif_dma_rw_ch0_ctrl___wr_all___bit 19
#define reg_bif_dma_rw_ch0_ctrl_offset 0
/* Register rw_ch0_addr, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch0_addr___addr___lsb 0
#define reg_bif_dma_rw_ch0_addr___addr___width 32
#define reg_bif_dma_rw_ch0_addr_offset 4
/* Register rw_ch0_start, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch0_start___run___lsb 0
#define reg_bif_dma_rw_ch0_start___run___width 1
#define reg_bif_dma_rw_ch0_start___run___bit 0
#define reg_bif_dma_rw_ch0_start_offset 8
/* Register rw_ch0_cnt, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch0_cnt___start_cnt___lsb 0
#define reg_bif_dma_rw_ch0_cnt___start_cnt___width 16
#define reg_bif_dma_rw_ch0_cnt_offset 12
/* Register r_ch0_stat, scope bif_dma, type r */
#define reg_bif_dma_r_ch0_stat___cnt___lsb 0
#define reg_bif_dma_r_ch0_stat___cnt___width 16
#define reg_bif_dma_r_ch0_stat___run___lsb 31
#define reg_bif_dma_r_ch0_stat___run___width 1
#define reg_bif_dma_r_ch0_stat___run___bit 31
#define reg_bif_dma_r_ch0_stat_offset 16
/* Register rw_ch1_ctrl, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch1_ctrl___bw___lsb 0
#define reg_bif_dma_rw_ch1_ctrl___bw___width 2
#define reg_bif_dma_rw_ch1_ctrl___burst_len___lsb 2
#define reg_bif_dma_rw_ch1_ctrl___burst_len___width 1
#define reg_bif_dma_rw_ch1_ctrl___burst_len___bit 2
#define reg_bif_dma_rw_ch1_ctrl___cont___lsb 3
#define reg_bif_dma_rw_ch1_ctrl___cont___width 1
#define reg_bif_dma_rw_ch1_ctrl___cont___bit 3
#define reg_bif_dma_rw_ch1_ctrl___end_discard___lsb 4
#define reg_bif_dma_rw_ch1_ctrl___end_discard___width 1
#define reg_bif_dma_rw_ch1_ctrl___end_discard___bit 4
#define reg_bif_dma_rw_ch1_ctrl___cnt___lsb 5
#define reg_bif_dma_rw_ch1_ctrl___cnt___width 1
#define reg_bif_dma_rw_ch1_ctrl___cnt___bit 5
#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___lsb 6
#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___width 3
#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___lsb 9
#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___width 2
#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___lsb 11
#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___width 3
#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___lsb 14
#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___width 2
#define reg_bif_dma_rw_ch1_ctrl___bus_mode___lsb 16
#define reg_bif_dma_rw_ch1_ctrl___bus_mode___width 2
#define reg_bif_dma_rw_ch1_ctrl___rate_en___lsb 18
#define reg_bif_dma_rw_ch1_ctrl___rate_en___width 1
#define reg_bif_dma_rw_ch1_ctrl___rate_en___bit 18
#define reg_bif_dma_rw_ch1_ctrl_offset 32
/* Register rw_ch1_addr, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch1_addr___addr___lsb 0
#define reg_bif_dma_rw_ch1_addr___addr___width 32
#define reg_bif_dma_rw_ch1_addr_offset 36
/* Register rw_ch1_start, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch1_start___run___lsb 0
#define reg_bif_dma_rw_ch1_start___run___width 1
#define reg_bif_dma_rw_ch1_start___run___bit 0
#define reg_bif_dma_rw_ch1_start_offset 40
/* Register rw_ch1_cnt, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch1_cnt___start_cnt___lsb 0
#define reg_bif_dma_rw_ch1_cnt___start_cnt___width 16
#define reg_bif_dma_rw_ch1_cnt_offset 44
/* Register r_ch1_stat, scope bif_dma, type r */
#define reg_bif_dma_r_ch1_stat___cnt___lsb 0
#define reg_bif_dma_r_ch1_stat___cnt___width 16
#define reg_bif_dma_r_ch1_stat___run___lsb 31
#define reg_bif_dma_r_ch1_stat___run___width 1
#define reg_bif_dma_r_ch1_stat___run___bit 31
#define reg_bif_dma_r_ch1_stat_offset 48
/* Register rw_ch2_ctrl, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch2_ctrl___bw___lsb 0
#define reg_bif_dma_rw_ch2_ctrl___bw___width 2
#define reg_bif_dma_rw_ch2_ctrl___burst_len___lsb 2
#define reg_bif_dma_rw_ch2_ctrl___burst_len___width 1
#define reg_bif_dma_rw_ch2_ctrl___burst_len___bit 2
#define reg_bif_dma_rw_ch2_ctrl___cont___lsb 3
#define reg_bif_dma_rw_ch2_ctrl___cont___width 1
#define reg_bif_dma_rw_ch2_ctrl___cont___bit 3
#define reg_bif_dma_rw_ch2_ctrl___end_pad___lsb 4
#define reg_bif_dma_rw_ch2_ctrl___end_pad___width 1
#define reg_bif_dma_rw_ch2_ctrl___end_pad___bit 4
#define reg_bif_dma_rw_ch2_ctrl___cnt___lsb 5
#define reg_bif_dma_rw_ch2_ctrl___cnt___width 1
#define reg_bif_dma_rw_ch2_ctrl___cnt___bit 5
#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___lsb 6
#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___width 3
#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___lsb 9
#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___width 2
#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___lsb 11
#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___width 3
#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___lsb 14
#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___width 2
#define reg_bif_dma_rw_ch2_ctrl___bus_mode___lsb 16
#define reg_bif_dma_rw_ch2_ctrl___bus_mode___width 2
#define reg_bif_dma_rw_ch2_ctrl___rate_en___lsb 18
#define reg_bif_dma_rw_ch2_ctrl___rate_en___width 1
#define reg_bif_dma_rw_ch2_ctrl___rate_en___bit 18
#define reg_bif_dma_rw_ch2_ctrl___wr_all___lsb 19
#define reg_bif_dma_rw_ch2_ctrl___wr_all___width 1
#define reg_bif_dma_rw_ch2_ctrl___wr_all___bit 19
#define reg_bif_dma_rw_ch2_ctrl_offset 64
/* Register rw_ch2_addr, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch2_addr___addr___lsb 0
#define reg_bif_dma_rw_ch2_addr___addr___width 32
#define reg_bif_dma_rw_ch2_addr_offset 68
/* Register rw_ch2_start, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch2_start___run___lsb 0
#define reg_bif_dma_rw_ch2_start___run___width 1
#define reg_bif_dma_rw_ch2_start___run___bit 0
#define reg_bif_dma_rw_ch2_start_offset 72
/* Register rw_ch2_cnt, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch2_cnt___start_cnt___lsb 0
#define reg_bif_dma_rw_ch2_cnt___start_cnt___width 16
#define reg_bif_dma_rw_ch2_cnt_offset 76
/* Register r_ch2_stat, scope bif_dma, type r */
#define reg_bif_dma_r_ch2_stat___cnt___lsb 0
#define reg_bif_dma_r_ch2_stat___cnt___width 16
#define reg_bif_dma_r_ch2_stat___run___lsb 31
#define reg_bif_dma_r_ch2_stat___run___width 1
#define reg_bif_dma_r_ch2_stat___run___bit 31
#define reg_bif_dma_r_ch2_stat_offset 80
/* Register rw_ch3_ctrl, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch3_ctrl___bw___lsb 0
#define reg_bif_dma_rw_ch3_ctrl___bw___width 2
#define reg_bif_dma_rw_ch3_ctrl___burst_len___lsb 2
#define reg_bif_dma_rw_ch3_ctrl___burst_len___width 1
#define reg_bif_dma_rw_ch3_ctrl___burst_len___bit 2
#define reg_bif_dma_rw_ch3_ctrl___cont___lsb 3
#define reg_bif_dma_rw_ch3_ctrl___cont___width 1
#define reg_bif_dma_rw_ch3_ctrl___cont___bit 3
#define reg_bif_dma_rw_ch3_ctrl___end_discard___lsb 4
#define reg_bif_dma_rw_ch3_ctrl___end_discard___width 1
#define reg_bif_dma_rw_ch3_ctrl___end_discard___bit 4
#define reg_bif_dma_rw_ch3_ctrl___cnt___lsb 5
#define reg_bif_dma_rw_ch3_ctrl___cnt___width 1
#define reg_bif_dma_rw_ch3_ctrl___cnt___bit 5
#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___lsb 6
#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___width 3
#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___lsb 9
#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___width 2
#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___lsb 11
#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___width 3
#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___lsb 14
#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___width 2
#define reg_bif_dma_rw_ch3_ctrl___bus_mode___lsb 16
#define reg_bif_dma_rw_ch3_ctrl___bus_mode___width 2
#define reg_bif_dma_rw_ch3_ctrl___rate_en___lsb 18
#define reg_bif_dma_rw_ch3_ctrl___rate_en___width 1
#define reg_bif_dma_rw_ch3_ctrl___rate_en___bit 18
#define reg_bif_dma_rw_ch3_ctrl_offset 96
/* Register rw_ch3_addr, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch3_addr___addr___lsb 0
#define reg_bif_dma_rw_ch3_addr___addr___width 32
#define reg_bif_dma_rw_ch3_addr_offset 100
/* Register rw_ch3_start, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch3_start___run___lsb 0
#define reg_bif_dma_rw_ch3_start___run___width 1
#define reg_bif_dma_rw_ch3_start___run___bit 0
#define reg_bif_dma_rw_ch3_start_offset 104
/* Register rw_ch3_cnt, scope bif_dma, type rw */
#define reg_bif_dma_rw_ch3_cnt___start_cnt___lsb 0
#define reg_bif_dma_rw_ch3_cnt___start_cnt___width 16
#define reg_bif_dma_rw_ch3_cnt_offset 108
/* Register r_ch3_stat, scope bif_dma, type r */
#define reg_bif_dma_r_ch3_stat___cnt___lsb 0
#define reg_bif_dma_r_ch3_stat___cnt___width 16
#define reg_bif_dma_r_ch3_stat___run___lsb 31
#define reg_bif_dma_r_ch3_stat___run___width 1
#define reg_bif_dma_r_ch3_stat___run___bit 31
#define reg_bif_dma_r_ch3_stat_offset 112
/* Register rw_intr_mask, scope bif_dma, type rw */
#define reg_bif_dma_rw_intr_mask___ext_dma0___lsb 0
#define reg_bif_dma_rw_intr_mask___ext_dma0___width 1
#define reg_bif_dma_rw_intr_mask___ext_dma0___bit 0
#define reg_bif_dma_rw_intr_mask___ext_dma1___lsb 1
#define reg_bif_dma_rw_intr_mask___ext_dma1___width 1
#define reg_bif_dma_rw_intr_mask___ext_dma1___bit 1
#define reg_bif_dma_rw_intr_mask___ext_dma2___lsb 2
#define reg_bif_dma_rw_intr_mask___ext_dma2___width 1
#define reg_bif_dma_rw_intr_mask___ext_dma2___bit 2
#define reg_bif_dma_rw_intr_mask___ext_dma3___lsb 3
#define reg_bif_dma_rw_intr_mask___ext_dma3___width 1
#define reg_bif_dma_rw_intr_mask___ext_dma3___bit 3
#define reg_bif_dma_rw_intr_mask_offset 128
/* Register rw_ack_intr, scope bif_dma, type rw */
#define reg_bif_dma_rw_ack_intr___ext_dma0___lsb 0
#define reg_bif_dma_rw_ack_intr___ext_dma0___width 1
#define reg_bif_dma_rw_ack_intr___ext_dma0___bit 0
#define reg_bif_dma_rw_ack_intr___ext_dma1___lsb 1
#define reg_bif_dma_rw_ack_intr___ext_dma1___width 1
#define reg_bif_dma_rw_ack_intr___ext_dma1___bit 1
#define reg_bif_dma_rw_ack_intr___ext_dma2___lsb 2
#define reg_bif_dma_rw_ack_intr___ext_dma2___width 1
#define reg_bif_dma_rw_ack_intr___ext_dma2___bit 2
#define reg_bif_dma_rw_ack_intr___ext_dma3___lsb 3
#define reg_bif_dma_rw_ack_intr___ext_dma3___width 1
#define reg_bif_dma_rw_ack_intr___ext_dma3___bit 3
#define reg_bif_dma_rw_ack_intr_offset 132
/* Register r_intr, scope bif_dma, type r */
#define reg_bif_dma_r_intr___ext_dma0___lsb 0
#define reg_bif_dma_r_intr___ext_dma0___width 1
#define reg_bif_dma_r_intr___ext_dma0___bit 0
#define reg_bif_dma_r_intr___ext_dma1___lsb 1
#define reg_bif_dma_r_intr___ext_dma1___width 1
#define reg_bif_dma_r_intr___ext_dma1___bit 1
#define reg_bif_dma_r_intr___ext_dma2___lsb 2
#define reg_bif_dma_r_intr___ext_dma2___width 1
#define reg_bif_dma_r_intr___ext_dma2___bit 2
#define reg_bif_dma_r_intr___ext_dma3___lsb 3
#define reg_bif_dma_r_intr___ext_dma3___width 1
#define reg_bif_dma_r_intr___ext_dma3___bit 3
#define reg_bif_dma_r_intr_offset 136
/* Register r_masked_intr, scope bif_dma, type r */
#define reg_bif_dma_r_masked_intr___ext_dma0___lsb 0
#define reg_bif_dma_r_masked_intr___ext_dma0___width 1
#define reg_bif_dma_r_masked_intr___ext_dma0___bit 0
#define reg_bif_dma_r_masked_intr___ext_dma1___lsb 1
#define reg_bif_dma_r_masked_intr___ext_dma1___width 1
#define reg_bif_dma_r_masked_intr___ext_dma1___bit 1
#define reg_bif_dma_r_masked_intr___ext_dma2___lsb 2
#define reg_bif_dma_r_masked_intr___ext_dma2___width 1
#define reg_bif_dma_r_masked_intr___ext_dma2___bit 2
#define reg_bif_dma_r_masked_intr___ext_dma3___lsb 3
#define reg_bif_dma_r_masked_intr___ext_dma3___width 1
#define reg_bif_dma_r_masked_intr___ext_dma3___bit 3
#define reg_bif_dma_r_masked_intr_offset 140
/* Register rw_pin0_cfg, scope bif_dma, type rw */
#define reg_bif_dma_rw_pin0_cfg___master_ch___lsb 0
#define reg_bif_dma_rw_pin0_cfg___master_ch___width 2
#define reg_bif_dma_rw_pin0_cfg___master_mode___lsb 2
#define reg_bif_dma_rw_pin0_cfg___master_mode___width 3
#define reg_bif_dma_rw_pin0_cfg___slave_ch___lsb 5
#define reg_bif_dma_rw_pin0_cfg___slave_ch___width 2
#define reg_bif_dma_rw_pin0_cfg___slave_mode___lsb 7
#define reg_bif_dma_rw_pin0_cfg___slave_mode___width 3
#define reg_bif_dma_rw_pin0_cfg_offset 160
/* Register rw_pin1_cfg, scope bif_dma, type rw */
#define reg_bif_dma_rw_pin1_cfg___master_ch___lsb 0
#define reg_bif_dma_rw_pin1_cfg___master_ch___width 2
#define reg_bif_dma_rw_pin1_cfg___master_mode___lsb 2
#define reg_bif_dma_rw_pin1_cfg___master_mode___width 3
#define reg_bif_dma_rw_pin1_cfg___slave_ch___lsb 5
#define reg_bif_dma_rw_pin1_cfg___slave_ch___width 2
#define reg_bif_dma_rw_pin1_cfg___slave_mode___lsb 7
#define reg_bif_dma_rw_pin1_cfg___slave_mode___width 3
#define reg_bif_dma_rw_pin1_cfg_offset 164
/* Register rw_pin2_cfg, scope bif_dma, type rw */
#define reg_bif_dma_rw_pin2_cfg___master_ch___lsb 0
#define reg_bif_dma_rw_pin2_cfg___master_ch___width 2
#define reg_bif_dma_rw_pin2_cfg___master_mode___lsb 2
#define reg_bif_dma_rw_pin2_cfg___master_mode___width 3
#define reg_bif_dma_rw_pin2_cfg___slave_ch___lsb 5
#define reg_bif_dma_rw_pin2_cfg___slave_ch___width 2
#define reg_bif_dma_rw_pin2_cfg___slave_mode___lsb 7
#define reg_bif_dma_rw_pin2_cfg___slave_mode___width 3
#define reg_bif_dma_rw_pin2_cfg_offset 168
/* Register rw_pin3_cfg, scope bif_dma, type rw */
#define reg_bif_dma_rw_pin3_cfg___master_ch___lsb 0
#define reg_bif_dma_rw_pin3_cfg___master_ch___width 2
#define reg_bif_dma_rw_pin3_cfg___master_mode___lsb 2
#define reg_bif_dma_rw_pin3_cfg___master_mode___width 3
#define reg_bif_dma_rw_pin3_cfg___slave_ch___lsb 5
#define reg_bif_dma_rw_pin3_cfg___slave_ch___width 2
#define reg_bif_dma_rw_pin3_cfg___slave_mode___lsb 7
#define reg_bif_dma_rw_pin3_cfg___slave_mode___width 3
#define reg_bif_dma_rw_pin3_cfg_offset 172
/* Register rw_pin4_cfg, scope bif_dma, type rw */
#define reg_bif_dma_rw_pin4_cfg___master_ch___lsb 0
#define reg_bif_dma_rw_pin4_cfg___master_ch___width 2
#define reg_bif_dma_rw_pin4_cfg___master_mode___lsb 2
#define reg_bif_dma_rw_pin4_cfg___master_mode___width 3
#define reg_bif_dma_rw_pin4_cfg___slave_ch___lsb 5
#define reg_bif_dma_rw_pin4_cfg___slave_ch___width 2
#define reg_bif_dma_rw_pin4_cfg___slave_mode___lsb 7
#define reg_bif_dma_rw_pin4_cfg___slave_mode___width 3
#define reg_bif_dma_rw_pin4_cfg_offset 176
/* Register rw_pin5_cfg, scope bif_dma, type rw */
#define reg_bif_dma_rw_pin5_cfg___master_ch___lsb 0
#define reg_bif_dma_rw_pin5_cfg___master_ch___width 2
#define reg_bif_dma_rw_pin5_cfg___master_mode___lsb 2
#define reg_bif_dma_rw_pin5_cfg___master_mode___width 3
#define reg_bif_dma_rw_pin5_cfg___slave_ch___lsb 5
#define reg_bif_dma_rw_pin5_cfg___slave_ch___width 2
#define reg_bif_dma_rw_pin5_cfg___slave_mode___lsb 7
#define reg_bif_dma_rw_pin5_cfg___slave_mode___width 3
#define reg_bif_dma_rw_pin5_cfg_offset 180
/* Register rw_pin6_cfg, scope bif_dma, type rw */
#define reg_bif_dma_rw_pin6_cfg___master_ch___lsb 0
#define reg_bif_dma_rw_pin6_cfg___master_ch___width 2
#define reg_bif_dma_rw_pin6_cfg___master_mode___lsb 2
#define reg_bif_dma_rw_pin6_cfg___master_mode___width 3
#define reg_bif_dma_rw_pin6_cfg___slave_ch___lsb 5
#define reg_bif_dma_rw_pin6_cfg___slave_ch___width 2
#define reg_bif_dma_rw_pin6_cfg___slave_mode___lsb 7
#define reg_bif_dma_rw_pin6_cfg___slave_mode___width 3
#define reg_bif_dma_rw_pin6_cfg_offset 184
/* Register rw_pin7_cfg, scope bif_dma, type rw */
#define reg_bif_dma_rw_pin7_cfg___master_ch___lsb 0
#define reg_bif_dma_rw_pin7_cfg___master_ch___width 2
#define reg_bif_dma_rw_pin7_cfg___master_mode___lsb 2
#define reg_bif_dma_rw_pin7_cfg___master_mode___width 3
#define reg_bif_dma_rw_pin7_cfg___slave_ch___lsb 5
#define reg_bif_dma_rw_pin7_cfg___slave_ch___width 2
#define reg_bif_dma_rw_pin7_cfg___slave_mode___lsb 7
#define reg_bif_dma_rw_pin7_cfg___slave_mode___width 3
#define reg_bif_dma_rw_pin7_cfg_offset 188
/* Register r_pin_stat, scope bif_dma, type r */
#define reg_bif_dma_r_pin_stat___pin0___lsb 0
#define reg_bif_dma_r_pin_stat___pin0___width 1
#define reg_bif_dma_r_pin_stat___pin0___bit 0
#define reg_bif_dma_r_pin_stat___pin1___lsb 1
#define reg_bif_dma_r_pin_stat___pin1___width 1
#define reg_bif_dma_r_pin_stat___pin1___bit 1
#define reg_bif_dma_r_pin_stat___pin2___lsb 2
#define reg_bif_dma_r_pin_stat___pin2___width 1
#define reg_bif_dma_r_pin_stat___pin2___bit 2
#define reg_bif_dma_r_pin_stat___pin3___lsb 3
#define reg_bif_dma_r_pin_stat___pin3___width 1
#define reg_bif_dma_r_pin_stat___pin3___bit 3
#define reg_bif_dma_r_pin_stat___pin4___lsb 4
#define reg_bif_dma_r_pin_stat___pin4___width 1
#define reg_bif_dma_r_pin_stat___pin4___bit 4
#define reg_bif_dma_r_pin_stat___pin5___lsb 5
#define reg_bif_dma_r_pin_stat___pin5___width 1
#define reg_bif_dma_r_pin_stat___pin5___bit 5
#define reg_bif_dma_r_pin_stat___pin6___lsb 6
#define reg_bif_dma_r_pin_stat___pin6___width 1
#define reg_bif_dma_r_pin_stat___pin6___bit 6
#define reg_bif_dma_r_pin_stat___pin7___lsb 7
#define reg_bif_dma_r_pin_stat___pin7___width 1
#define reg_bif_dma_r_pin_stat___pin7___bit 7
#define reg_bif_dma_r_pin_stat_offset 192
/* Constants */
#define regk_bif_dma_as_master 0x00000001
#define regk_bif_dma_as_slave 0x00000001
#define regk_bif_dma_burst1 0x00000000
#define regk_bif_dma_burst8 0x00000001
#define regk_bif_dma_bw16 0x00000001
#define regk_bif_dma_bw32 0x00000002
#define regk_bif_dma_bw8 0x00000000
#define regk_bif_dma_dack 0x00000006
#define regk_bif_dma_dack_inv 0x00000007
#define regk_bif_dma_force 0x00000001
#define regk_bif_dma_hi 0x00000003
#define regk_bif_dma_inv 0x00000003
#define regk_bif_dma_lo 0x00000002
#define regk_bif_dma_master 0x00000001
#define regk_bif_dma_no 0x00000000
#define regk_bif_dma_norm 0x00000002
#define regk_bif_dma_off 0x00000000
#define regk_bif_dma_rw_ch0_ctrl_default 0x00000000
#define regk_bif_dma_rw_ch0_start_default 0x00000000
#define regk_bif_dma_rw_ch1_ctrl_default 0x00000000
#define regk_bif_dma_rw_ch1_start_default 0x00000000
#define regk_bif_dma_rw_ch2_ctrl_default 0x00000000
#define regk_bif_dma_rw_ch2_start_default 0x00000000
#define regk_bif_dma_rw_ch3_ctrl_default 0x00000000
#define regk_bif_dma_rw_ch3_start_default 0x00000000
#define regk_bif_dma_rw_intr_mask_default 0x00000000
#define regk_bif_dma_rw_pin0_cfg_default 0x00000000
#define regk_bif_dma_rw_pin1_cfg_default 0x00000000
#define regk_bif_dma_rw_pin2_cfg_default 0x00000000
#define regk_bif_dma_rw_pin3_cfg_default 0x00000000
#define regk_bif_dma_rw_pin4_cfg_default 0x00000000
#define regk_bif_dma_rw_pin5_cfg_default 0x00000000
#define regk_bif_dma_rw_pin6_cfg_default 0x00000000
#define regk_bif_dma_rw_pin7_cfg_default 0x00000000
#define regk_bif_dma_slave 0x00000002
#define regk_bif_dma_sreq 0x00000006
#define regk_bif_dma_sreq_inv 0x00000007
#define regk_bif_dma_tc 0x00000004
#define regk_bif_dma_tc_inv 0x00000005
#define regk_bif_dma_yes 0x00000001
#endif /* __bif_dma_defs_asm_h */

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#ifndef __bif_slave_defs_asm_h
#define __bif_slave_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/bif/rtl/bif_slave_regs.r
* id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
* last modfied: Mon Apr 11 16:06:34 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_slave_defs_asm.h ../../inst/bif/rtl/bif_slave_regs.r
* id: $Id: bif_slave_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_slave_cfg, scope bif_slave, type rw */
#define reg_bif_slave_rw_slave_cfg___slave_id___lsb 0
#define reg_bif_slave_rw_slave_cfg___slave_id___width 3
#define reg_bif_slave_rw_slave_cfg___use_slave_id___lsb 3
#define reg_bif_slave_rw_slave_cfg___use_slave_id___width 1
#define reg_bif_slave_rw_slave_cfg___use_slave_id___bit 3
#define reg_bif_slave_rw_slave_cfg___boot_rdy___lsb 4
#define reg_bif_slave_rw_slave_cfg___boot_rdy___width 1
#define reg_bif_slave_rw_slave_cfg___boot_rdy___bit 4
#define reg_bif_slave_rw_slave_cfg___loopback___lsb 5
#define reg_bif_slave_rw_slave_cfg___loopback___width 1
#define reg_bif_slave_rw_slave_cfg___loopback___bit 5
#define reg_bif_slave_rw_slave_cfg___dis___lsb 6
#define reg_bif_slave_rw_slave_cfg___dis___width 1
#define reg_bif_slave_rw_slave_cfg___dis___bit 6
#define reg_bif_slave_rw_slave_cfg_offset 0
/* Register r_slave_mode, scope bif_slave, type r */
#define reg_bif_slave_r_slave_mode___ch0_mode___lsb 0
#define reg_bif_slave_r_slave_mode___ch0_mode___width 1
#define reg_bif_slave_r_slave_mode___ch0_mode___bit 0
#define reg_bif_slave_r_slave_mode___ch1_mode___lsb 1
#define reg_bif_slave_r_slave_mode___ch1_mode___width 1
#define reg_bif_slave_r_slave_mode___ch1_mode___bit 1
#define reg_bif_slave_r_slave_mode___ch2_mode___lsb 2
#define reg_bif_slave_r_slave_mode___ch2_mode___width 1
#define reg_bif_slave_r_slave_mode___ch2_mode___bit 2
#define reg_bif_slave_r_slave_mode___ch3_mode___lsb 3
#define reg_bif_slave_r_slave_mode___ch3_mode___width 1
#define reg_bif_slave_r_slave_mode___ch3_mode___bit 3
#define reg_bif_slave_r_slave_mode_offset 4
/* Register rw_ch0_cfg, scope bif_slave, type rw */
#define reg_bif_slave_rw_ch0_cfg___rd_hold___lsb 0
#define reg_bif_slave_rw_ch0_cfg___rd_hold___width 2
#define reg_bif_slave_rw_ch0_cfg___access_mode___lsb 2
#define reg_bif_slave_rw_ch0_cfg___access_mode___width 1
#define reg_bif_slave_rw_ch0_cfg___access_mode___bit 2
#define reg_bif_slave_rw_ch0_cfg___access_ctrl___lsb 3
#define reg_bif_slave_rw_ch0_cfg___access_ctrl___width 1
#define reg_bif_slave_rw_ch0_cfg___access_ctrl___bit 3
#define reg_bif_slave_rw_ch0_cfg___data_cs___lsb 4
#define reg_bif_slave_rw_ch0_cfg___data_cs___width 2
#define reg_bif_slave_rw_ch0_cfg_offset 16
/* Register rw_ch1_cfg, scope bif_slave, type rw */
#define reg_bif_slave_rw_ch1_cfg___rd_hold___lsb 0
#define reg_bif_slave_rw_ch1_cfg___rd_hold___width 2
#define reg_bif_slave_rw_ch1_cfg___access_mode___lsb 2
#define reg_bif_slave_rw_ch1_cfg___access_mode___width 1
#define reg_bif_slave_rw_ch1_cfg___access_mode___bit 2
#define reg_bif_slave_rw_ch1_cfg___access_ctrl___lsb 3
#define reg_bif_slave_rw_ch1_cfg___access_ctrl___width 1
#define reg_bif_slave_rw_ch1_cfg___access_ctrl___bit 3
#define reg_bif_slave_rw_ch1_cfg___data_cs___lsb 4
#define reg_bif_slave_rw_ch1_cfg___data_cs___width 2
#define reg_bif_slave_rw_ch1_cfg_offset 20
/* Register rw_ch2_cfg, scope bif_slave, type rw */
#define reg_bif_slave_rw_ch2_cfg___rd_hold___lsb 0
#define reg_bif_slave_rw_ch2_cfg___rd_hold___width 2
#define reg_bif_slave_rw_ch2_cfg___access_mode___lsb 2
#define reg_bif_slave_rw_ch2_cfg___access_mode___width 1
#define reg_bif_slave_rw_ch2_cfg___access_mode___bit 2
#define reg_bif_slave_rw_ch2_cfg___access_ctrl___lsb 3
#define reg_bif_slave_rw_ch2_cfg___access_ctrl___width 1
#define reg_bif_slave_rw_ch2_cfg___access_ctrl___bit 3
#define reg_bif_slave_rw_ch2_cfg___data_cs___lsb 4
#define reg_bif_slave_rw_ch2_cfg___data_cs___width 2
#define reg_bif_slave_rw_ch2_cfg_offset 24
/* Register rw_ch3_cfg, scope bif_slave, type rw */
#define reg_bif_slave_rw_ch3_cfg___rd_hold___lsb 0
#define reg_bif_slave_rw_ch3_cfg___rd_hold___width 2
#define reg_bif_slave_rw_ch3_cfg___access_mode___lsb 2
#define reg_bif_slave_rw_ch3_cfg___access_mode___width 1
#define reg_bif_slave_rw_ch3_cfg___access_mode___bit 2
#define reg_bif_slave_rw_ch3_cfg___access_ctrl___lsb 3
#define reg_bif_slave_rw_ch3_cfg___access_ctrl___width 1
#define reg_bif_slave_rw_ch3_cfg___access_ctrl___bit 3
#define reg_bif_slave_rw_ch3_cfg___data_cs___lsb 4
#define reg_bif_slave_rw_ch3_cfg___data_cs___width 2
#define reg_bif_slave_rw_ch3_cfg_offset 28
/* Register rw_arb_cfg, scope bif_slave, type rw */
#define reg_bif_slave_rw_arb_cfg___brin_mode___lsb 0
#define reg_bif_slave_rw_arb_cfg___brin_mode___width 1
#define reg_bif_slave_rw_arb_cfg___brin_mode___bit 0
#define reg_bif_slave_rw_arb_cfg___brout_mode___lsb 1
#define reg_bif_slave_rw_arb_cfg___brout_mode___width 3
#define reg_bif_slave_rw_arb_cfg___bg_mode___lsb 4
#define reg_bif_slave_rw_arb_cfg___bg_mode___width 3
#define reg_bif_slave_rw_arb_cfg___release___lsb 7
#define reg_bif_slave_rw_arb_cfg___release___width 2
#define reg_bif_slave_rw_arb_cfg___acquire___lsb 9
#define reg_bif_slave_rw_arb_cfg___acquire___width 1
#define reg_bif_slave_rw_arb_cfg___acquire___bit 9
#define reg_bif_slave_rw_arb_cfg___settle_time___lsb 10
#define reg_bif_slave_rw_arb_cfg___settle_time___width 2
#define reg_bif_slave_rw_arb_cfg___dram_ctrl___lsb 12
#define reg_bif_slave_rw_arb_cfg___dram_ctrl___width 1
#define reg_bif_slave_rw_arb_cfg___dram_ctrl___bit 12
#define reg_bif_slave_rw_arb_cfg_offset 32
/* Register r_arb_stat, scope bif_slave, type r */
#define reg_bif_slave_r_arb_stat___init_mode___lsb 0
#define reg_bif_slave_r_arb_stat___init_mode___width 1
#define reg_bif_slave_r_arb_stat___init_mode___bit 0
#define reg_bif_slave_r_arb_stat___mode___lsb 1
#define reg_bif_slave_r_arb_stat___mode___width 1
#define reg_bif_slave_r_arb_stat___mode___bit 1
#define reg_bif_slave_r_arb_stat___brin___lsb 2
#define reg_bif_slave_r_arb_stat___brin___width 1
#define reg_bif_slave_r_arb_stat___brin___bit 2
#define reg_bif_slave_r_arb_stat___brout___lsb 3
#define reg_bif_slave_r_arb_stat___brout___width 1
#define reg_bif_slave_r_arb_stat___brout___bit 3
#define reg_bif_slave_r_arb_stat___bg___lsb 4
#define reg_bif_slave_r_arb_stat___bg___width 1
#define reg_bif_slave_r_arb_stat___bg___bit 4
#define reg_bif_slave_r_arb_stat_offset 36
/* Register rw_intr_mask, scope bif_slave, type rw */
#define reg_bif_slave_rw_intr_mask___bus_release___lsb 0
#define reg_bif_slave_rw_intr_mask___bus_release___width 1
#define reg_bif_slave_rw_intr_mask___bus_release___bit 0
#define reg_bif_slave_rw_intr_mask___bus_acquire___lsb 1
#define reg_bif_slave_rw_intr_mask___bus_acquire___width 1
#define reg_bif_slave_rw_intr_mask___bus_acquire___bit 1
#define reg_bif_slave_rw_intr_mask_offset 64
/* Register rw_ack_intr, scope bif_slave, type rw */
#define reg_bif_slave_rw_ack_intr___bus_release___lsb 0
#define reg_bif_slave_rw_ack_intr___bus_release___width 1
#define reg_bif_slave_rw_ack_intr___bus_release___bit 0
#define reg_bif_slave_rw_ack_intr___bus_acquire___lsb 1
#define reg_bif_slave_rw_ack_intr___bus_acquire___width 1
#define reg_bif_slave_rw_ack_intr___bus_acquire___bit 1
#define reg_bif_slave_rw_ack_intr_offset 68
/* Register r_intr, scope bif_slave, type r */
#define reg_bif_slave_r_intr___bus_release___lsb 0
#define reg_bif_slave_r_intr___bus_release___width 1
#define reg_bif_slave_r_intr___bus_release___bit 0
#define reg_bif_slave_r_intr___bus_acquire___lsb 1
#define reg_bif_slave_r_intr___bus_acquire___width 1
#define reg_bif_slave_r_intr___bus_acquire___bit 1
#define reg_bif_slave_r_intr_offset 72
/* Register r_masked_intr, scope bif_slave, type r */
#define reg_bif_slave_r_masked_intr___bus_release___lsb 0
#define reg_bif_slave_r_masked_intr___bus_release___width 1
#define reg_bif_slave_r_masked_intr___bus_release___bit 0
#define reg_bif_slave_r_masked_intr___bus_acquire___lsb 1
#define reg_bif_slave_r_masked_intr___bus_acquire___width 1
#define reg_bif_slave_r_masked_intr___bus_acquire___bit 1
#define reg_bif_slave_r_masked_intr_offset 76
/* Constants */
#define regk_bif_slave_active_hi 0x00000003
#define regk_bif_slave_active_lo 0x00000002
#define regk_bif_slave_addr 0x00000000
#define regk_bif_slave_always 0x00000001
#define regk_bif_slave_at_idle 0x00000002
#define regk_bif_slave_burst_end 0x00000003
#define regk_bif_slave_dma 0x00000001
#define regk_bif_slave_hi 0x00000003
#define regk_bif_slave_inv 0x00000001
#define regk_bif_slave_lo 0x00000002
#define regk_bif_slave_local 0x00000001
#define regk_bif_slave_master 0x00000000
#define regk_bif_slave_mode_reg 0x00000001
#define regk_bif_slave_no 0x00000000
#define regk_bif_slave_norm 0x00000000
#define regk_bif_slave_on_access 0x00000000
#define regk_bif_slave_rw_arb_cfg_default 0x00000000
#define regk_bif_slave_rw_ch0_cfg_default 0x00000000
#define regk_bif_slave_rw_ch1_cfg_default 0x00000000
#define regk_bif_slave_rw_ch2_cfg_default 0x00000000
#define regk_bif_slave_rw_ch3_cfg_default 0x00000000
#define regk_bif_slave_rw_intr_mask_default 0x00000000
#define regk_bif_slave_rw_slave_cfg_default 0x00000000
#define regk_bif_slave_shared 0x00000000
#define regk_bif_slave_slave 0x00000001
#define regk_bif_slave_t0ns 0x00000003
#define regk_bif_slave_t10ns 0x00000002
#define regk_bif_slave_t20ns 0x00000003
#define regk_bif_slave_t30ns 0x00000002
#define regk_bif_slave_t40ns 0x00000001
#define regk_bif_slave_t50ns 0x00000000
#define regk_bif_slave_yes 0x00000001
#define regk_bif_slave_z 0x00000004
#endif /* __bif_slave_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/asm/config_defs_asm.h Normal file
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#ifndef __config_defs_asm_h
#define __config_defs_asm_h
/*
* This file is autogenerated from
* file: ../../rtl/config_regs.r
* id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
* last modfied: Thu Mar 4 12:34:39 2004
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r
* id: $Id: config_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register r_bootsel, scope config, type r */
#define reg_config_r_bootsel___boot_mode___lsb 0
#define reg_config_r_bootsel___boot_mode___width 3
#define reg_config_r_bootsel___full_duplex___lsb 3
#define reg_config_r_bootsel___full_duplex___width 1
#define reg_config_r_bootsel___full_duplex___bit 3
#define reg_config_r_bootsel___user___lsb 4
#define reg_config_r_bootsel___user___width 1
#define reg_config_r_bootsel___user___bit 4
#define reg_config_r_bootsel___pll___lsb 5
#define reg_config_r_bootsel___pll___width 1
#define reg_config_r_bootsel___pll___bit 5
#define reg_config_r_bootsel___flash_bw___lsb 6
#define reg_config_r_bootsel___flash_bw___width 1
#define reg_config_r_bootsel___flash_bw___bit 6
#define reg_config_r_bootsel_offset 0
/* Register rw_clk_ctrl, scope config, type rw */
#define reg_config_rw_clk_ctrl___pll___lsb 0
#define reg_config_rw_clk_ctrl___pll___width 1
#define reg_config_rw_clk_ctrl___pll___bit 0
#define reg_config_rw_clk_ctrl___cpu___lsb 1
#define reg_config_rw_clk_ctrl___cpu___width 1
#define reg_config_rw_clk_ctrl___cpu___bit 1
#define reg_config_rw_clk_ctrl___iop___lsb 2
#define reg_config_rw_clk_ctrl___iop___width 1
#define reg_config_rw_clk_ctrl___iop___bit 2
#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3
#define reg_config_rw_clk_ctrl___dma01_eth0___width 1
#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3
#define reg_config_rw_clk_ctrl___dma23___lsb 4
#define reg_config_rw_clk_ctrl___dma23___width 1
#define reg_config_rw_clk_ctrl___dma23___bit 4
#define reg_config_rw_clk_ctrl___dma45___lsb 5
#define reg_config_rw_clk_ctrl___dma45___width 1
#define reg_config_rw_clk_ctrl___dma45___bit 5
#define reg_config_rw_clk_ctrl___dma67___lsb 6
#define reg_config_rw_clk_ctrl___dma67___width 1
#define reg_config_rw_clk_ctrl___dma67___bit 6
#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7
#define reg_config_rw_clk_ctrl___dma89_strcop___width 1
#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7
#define reg_config_rw_clk_ctrl___bif___lsb 8
#define reg_config_rw_clk_ctrl___bif___width 1
#define reg_config_rw_clk_ctrl___bif___bit 8
#define reg_config_rw_clk_ctrl___fix_io___lsb 9
#define reg_config_rw_clk_ctrl___fix_io___width 1
#define reg_config_rw_clk_ctrl___fix_io___bit 9
#define reg_config_rw_clk_ctrl_offset 4
/* Register rw_pad_ctrl, scope config, type rw */
#define reg_config_rw_pad_ctrl___usb_susp___lsb 0
#define reg_config_rw_pad_ctrl___usb_susp___width 1
#define reg_config_rw_pad_ctrl___usb_susp___bit 0
#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1
#define reg_config_rw_pad_ctrl___phyrst_n___width 1
#define reg_config_rw_pad_ctrl___phyrst_n___bit 1
#define reg_config_rw_pad_ctrl_offset 8
/* Constants */
#define regk_config_bw16 0x00000000
#define regk_config_bw32 0x00000001
#define regk_config_master 0x00000005
#define regk_config_nand 0x00000003
#define regk_config_net_rx 0x00000001
#define regk_config_net_tx_rx 0x00000002
#define regk_config_no 0x00000000
#define regk_config_none 0x00000007
#define regk_config_nor 0x00000000
#define regk_config_rw_clk_ctrl_default 0x00000002
#define regk_config_rw_pad_ctrl_default 0x00000000
#define regk_config_ser 0x00000004
#define regk_config_slave 0x00000006
#define regk_config_yes 0x00000001
#endif /* __config_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/asm/cpu_vect.h Normal file
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/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
from ../../inst/crisp/doc/cpu_vect.r
version . */
#ifndef _______INST_CRISP_DOC_CPU_VECT_R
#define _______INST_CRISP_DOC_CPU_VECT_R
#define NMI_INTR_VECT 0x00
#define RESERVED_1_INTR_VECT 0x01
#define RESERVED_2_INTR_VECT 0x02
#define SINGLE_STEP_INTR_VECT 0x03
#define INSTR_TLB_REFILL_INTR_VECT 0x04
#define INSTR_TLB_INV_INTR_VECT 0x05
#define INSTR_TLB_ACC_INTR_VECT 0x06
#define TLB_EX_INTR_VECT 0x07
#define DATA_TLB_REFILL_INTR_VECT 0x08
#define DATA_TLB_INV_INTR_VECT 0x09
#define DATA_TLB_ACC_INTR_VECT 0x0a
#define DATA_TLB_WE_INTR_VECT 0x0b
#define HW_BP_INTR_VECT 0x0c
#define RESERVED_D_INTR_VECT 0x0d
#define RESERVED_E_INTR_VECT 0x0e
#define RESERVED_F_INTR_VECT 0x0f
#define BREAK_0_INTR_VECT 0x10
#define BREAK_1_INTR_VECT 0x11
#define BREAK_2_INTR_VECT 0x12
#define BREAK_3_INTR_VECT 0x13
#define BREAK_4_INTR_VECT 0x14
#define BREAK_5_INTR_VECT 0x15
#define BREAK_6_INTR_VECT 0x16
#define BREAK_7_INTR_VECT 0x17
#define BREAK_8_INTR_VECT 0x18
#define BREAK_9_INTR_VECT 0x19
#define BREAK_10_INTR_VECT 0x1a
#define BREAK_11_INTR_VECT 0x1b
#define BREAK_12_INTR_VECT 0x1c
#define BREAK_13_INTR_VECT 0x1d
#define BREAK_14_INTR_VECT 0x1e
#define BREAK_15_INTR_VECT 0x1f
#define MULTIPLE_INTR_VECT 0x30
#endif

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arch/cris/include/arch-v32/arch/hwregs/asm/cris_defs_asm.h Normal file
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#ifndef __cris_defs_asm_h
#define __cris_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/crisp/doc/cris.r
* id: cris.r,v 1.6 2004/05/05 07:41:12 perz Exp
* last modfied: Mon Apr 11 16:06:39 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r
* id: $Id: cris_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_gc_cfg, scope cris, type rw */
#define reg_cris_rw_gc_cfg___ic___lsb 0
#define reg_cris_rw_gc_cfg___ic___width 1
#define reg_cris_rw_gc_cfg___ic___bit 0
#define reg_cris_rw_gc_cfg___dc___lsb 1
#define reg_cris_rw_gc_cfg___dc___width 1
#define reg_cris_rw_gc_cfg___dc___bit 1
#define reg_cris_rw_gc_cfg___im___lsb 2
#define reg_cris_rw_gc_cfg___im___width 1
#define reg_cris_rw_gc_cfg___im___bit 2
#define reg_cris_rw_gc_cfg___dm___lsb 3
#define reg_cris_rw_gc_cfg___dm___width 1
#define reg_cris_rw_gc_cfg___dm___bit 3
#define reg_cris_rw_gc_cfg___gb___lsb 4
#define reg_cris_rw_gc_cfg___gb___width 1
#define reg_cris_rw_gc_cfg___gb___bit 4
#define reg_cris_rw_gc_cfg___gk___lsb 5
#define reg_cris_rw_gc_cfg___gk___width 1
#define reg_cris_rw_gc_cfg___gk___bit 5
#define reg_cris_rw_gc_cfg___gp___lsb 6
#define reg_cris_rw_gc_cfg___gp___width 1
#define reg_cris_rw_gc_cfg___gp___bit 6
#define reg_cris_rw_gc_cfg_offset 0
/* Register rw_gc_ccs, scope cris, type rw */
#define reg_cris_rw_gc_ccs_offset 4
/* Register rw_gc_srs, scope cris, type rw */
#define reg_cris_rw_gc_srs___srs___lsb 0
#define reg_cris_rw_gc_srs___srs___width 8
#define reg_cris_rw_gc_srs_offset 8
/* Register rw_gc_nrp, scope cris, type rw */
#define reg_cris_rw_gc_nrp_offset 12
/* Register rw_gc_exs, scope cris, type rw */
#define reg_cris_rw_gc_exs_offset 16
/* Register rw_gc_eda, scope cris, type rw */
#define reg_cris_rw_gc_eda_offset 20
/* Register rw_gc_r0, scope cris, type rw */
#define reg_cris_rw_gc_r0_offset 32
/* Register rw_gc_r1, scope cris, type rw */
#define reg_cris_rw_gc_r1_offset 36
/* Register rw_gc_r2, scope cris, type rw */
#define reg_cris_rw_gc_r2_offset 40
/* Register rw_gc_r3, scope cris, type rw */
#define reg_cris_rw_gc_r3_offset 44
/* Constants */
#define regk_cris_no 0x00000000
#define regk_cris_rw_gc_cfg_default 0x00000000
#define regk_cris_yes 0x00000001
#endif /* __cris_defs_asm_h */

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#define RW_GC_CFG 0
#define RW_GC_CCS 1
#define RW_GC_SRS 2
#define RW_GC_NRP 3
#define RW_GC_EXS 4
#define RW_GC_EDA 5
#define RW_GC_R0 8
#define RW_GC_R1 9
#define RW_GC_R2 10
#define RW_GC_R3 11

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#ifndef __dma_defs_asm_h
#define __dma_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
* id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
* last modfied: Mon Apr 11 16:06:51 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/dma_defs_asm.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
* id: $Id: dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_data, scope dma, type rw */
#define reg_dma_rw_data_offset 0
/* Register rw_data_next, scope dma, type rw */
#define reg_dma_rw_data_next_offset 4
/* Register rw_data_buf, scope dma, type rw */
#define reg_dma_rw_data_buf_offset 8
/* Register rw_data_ctrl, scope dma, type rw */
#define reg_dma_rw_data_ctrl___eol___lsb 0
#define reg_dma_rw_data_ctrl___eol___width 1
#define reg_dma_rw_data_ctrl___eol___bit 0
#define reg_dma_rw_data_ctrl___out_eop___lsb 3
#define reg_dma_rw_data_ctrl___out_eop___width 1
#define reg_dma_rw_data_ctrl___out_eop___bit 3
#define reg_dma_rw_data_ctrl___intr___lsb 4
#define reg_dma_rw_data_ctrl___intr___width 1
#define reg_dma_rw_data_ctrl___intr___bit 4
#define reg_dma_rw_data_ctrl___wait___lsb 5
#define reg_dma_rw_data_ctrl___wait___width 1
#define reg_dma_rw_data_ctrl___wait___bit 5
#define reg_dma_rw_data_ctrl_offset 12
/* Register rw_data_stat, scope dma, type rw */
#define reg_dma_rw_data_stat___in_eop___lsb 3
#define reg_dma_rw_data_stat___in_eop___width 1
#define reg_dma_rw_data_stat___in_eop___bit 3
#define reg_dma_rw_data_stat_offset 16
/* Register rw_data_md, scope dma, type rw */
#define reg_dma_rw_data_md___md___lsb 0
#define reg_dma_rw_data_md___md___width 16
#define reg_dma_rw_data_md_offset 20
/* Register rw_data_md_s, scope dma, type rw */
#define reg_dma_rw_data_md_s___md_s___lsb 0
#define reg_dma_rw_data_md_s___md_s___width 16
#define reg_dma_rw_data_md_s_offset 24
/* Register rw_data_after, scope dma, type rw */
#define reg_dma_rw_data_after_offset 28
/* Register rw_ctxt, scope dma, type rw */
#define reg_dma_rw_ctxt_offset 32
/* Register rw_ctxt_next, scope dma, type rw */
#define reg_dma_rw_ctxt_next_offset 36
/* Register rw_ctxt_ctrl, scope dma, type rw */
#define reg_dma_rw_ctxt_ctrl___eol___lsb 0
#define reg_dma_rw_ctxt_ctrl___eol___width 1
#define reg_dma_rw_ctxt_ctrl___eol___bit 0
#define reg_dma_rw_ctxt_ctrl___intr___lsb 4
#define reg_dma_rw_ctxt_ctrl___intr___width 1
#define reg_dma_rw_ctxt_ctrl___intr___bit 4
#define reg_dma_rw_ctxt_ctrl___store_mode___lsb 6
#define reg_dma_rw_ctxt_ctrl___store_mode___width 1
#define reg_dma_rw_ctxt_ctrl___store_mode___bit 6
#define reg_dma_rw_ctxt_ctrl___en___lsb 7
#define reg_dma_rw_ctxt_ctrl___en___width 1
#define reg_dma_rw_ctxt_ctrl___en___bit 7
#define reg_dma_rw_ctxt_ctrl_offset 40
/* Register rw_ctxt_stat, scope dma, type rw */
#define reg_dma_rw_ctxt_stat___dis___lsb 7
#define reg_dma_rw_ctxt_stat___dis___width 1
#define reg_dma_rw_ctxt_stat___dis___bit 7
#define reg_dma_rw_ctxt_stat_offset 44
/* Register rw_ctxt_md0, scope dma, type rw */
#define reg_dma_rw_ctxt_md0___md0___lsb 0
#define reg_dma_rw_ctxt_md0___md0___width 16
#define reg_dma_rw_ctxt_md0_offset 48
/* Register rw_ctxt_md0_s, scope dma, type rw */
#define reg_dma_rw_ctxt_md0_s___md0_s___lsb 0
#define reg_dma_rw_ctxt_md0_s___md0_s___width 16
#define reg_dma_rw_ctxt_md0_s_offset 52
/* Register rw_ctxt_md1, scope dma, type rw */
#define reg_dma_rw_ctxt_md1_offset 56
/* Register rw_ctxt_md1_s, scope dma, type rw */
#define reg_dma_rw_ctxt_md1_s_offset 60
/* Register rw_ctxt_md2, scope dma, type rw */
#define reg_dma_rw_ctxt_md2_offset 64
/* Register rw_ctxt_md2_s, scope dma, type rw */
#define reg_dma_rw_ctxt_md2_s_offset 68
/* Register rw_ctxt_md3, scope dma, type rw */
#define reg_dma_rw_ctxt_md3_offset 72
/* Register rw_ctxt_md3_s, scope dma, type rw */
#define reg_dma_rw_ctxt_md3_s_offset 76
/* Register rw_ctxt_md4, scope dma, type rw */
#define reg_dma_rw_ctxt_md4_offset 80
/* Register rw_ctxt_md4_s, scope dma, type rw */
#define reg_dma_rw_ctxt_md4_s_offset 84
/* Register rw_saved_data, scope dma, type rw */
#define reg_dma_rw_saved_data_offset 88
/* Register rw_saved_data_buf, scope dma, type rw */
#define reg_dma_rw_saved_data_buf_offset 92
/* Register rw_group, scope dma, type rw */
#define reg_dma_rw_group_offset 96
/* Register rw_group_next, scope dma, type rw */
#define reg_dma_rw_group_next_offset 100
/* Register rw_group_ctrl, scope dma, type rw */
#define reg_dma_rw_group_ctrl___eol___lsb 0
#define reg_dma_rw_group_ctrl___eol___width 1
#define reg_dma_rw_group_ctrl___eol___bit 0
#define reg_dma_rw_group_ctrl___tol___lsb 1
#define reg_dma_rw_group_ctrl___tol___width 1
#define reg_dma_rw_group_ctrl___tol___bit 1
#define reg_dma_rw_group_ctrl___bol___lsb 2
#define reg_dma_rw_group_ctrl___bol___width 1
#define reg_dma_rw_group_ctrl___bol___bit 2
#define reg_dma_rw_group_ctrl___intr___lsb 4
#define reg_dma_rw_group_ctrl___intr___width 1
#define reg_dma_rw_group_ctrl___intr___bit 4
#define reg_dma_rw_group_ctrl___en___lsb 7
#define reg_dma_rw_group_ctrl___en___width 1
#define reg_dma_rw_group_ctrl___en___bit 7
#define reg_dma_rw_group_ctrl_offset 104
/* Register rw_group_stat, scope dma, type rw */
#define reg_dma_rw_group_stat___dis___lsb 7
#define reg_dma_rw_group_stat___dis___width 1
#define reg_dma_rw_group_stat___dis___bit 7
#define reg_dma_rw_group_stat_offset 108
/* Register rw_group_md, scope dma, type rw */
#define reg_dma_rw_group_md___md___lsb 0
#define reg_dma_rw_group_md___md___width 16
#define reg_dma_rw_group_md_offset 112
/* Register rw_group_md_s, scope dma, type rw */
#define reg_dma_rw_group_md_s___md_s___lsb 0
#define reg_dma_rw_group_md_s___md_s___width 16
#define reg_dma_rw_group_md_s_offset 116
/* Register rw_group_up, scope dma, type rw */
#define reg_dma_rw_group_up_offset 120
/* Register rw_group_down, scope dma, type rw */
#define reg_dma_rw_group_down_offset 124
/* Register rw_cmd, scope dma, type rw */
#define reg_dma_rw_cmd___cont_data___lsb 0
#define reg_dma_rw_cmd___cont_data___width 1
#define reg_dma_rw_cmd___cont_data___bit 0
#define reg_dma_rw_cmd_offset 128
/* Register rw_cfg, scope dma, type rw */
#define reg_dma_rw_cfg___en___lsb 0
#define reg_dma_rw_cfg___en___width 1
#define reg_dma_rw_cfg___en___bit 0
#define reg_dma_rw_cfg___stop___lsb 1
#define reg_dma_rw_cfg___stop___width 1
#define reg_dma_rw_cfg___stop___bit 1
#define reg_dma_rw_cfg_offset 132
/* Register rw_stat, scope dma, type rw */
#define reg_dma_rw_stat___mode___lsb 0
#define reg_dma_rw_stat___mode___width 5
#define reg_dma_rw_stat___list_state___lsb 5
#define reg_dma_rw_stat___list_state___width 3
#define reg_dma_rw_stat___stream_cmd_src___lsb 8
#define reg_dma_rw_stat___stream_cmd_src___width 8
#define reg_dma_rw_stat___buf___lsb 24
#define reg_dma_rw_stat___buf___width 8
#define reg_dma_rw_stat_offset 136
/* Register rw_intr_mask, scope dma, type rw */
#define reg_dma_rw_intr_mask___group___lsb 0
#define reg_dma_rw_intr_mask___group___width 1
#define reg_dma_rw_intr_mask___group___bit 0
#define reg_dma_rw_intr_mask___ctxt___lsb 1
#define reg_dma_rw_intr_mask___ctxt___width 1
#define reg_dma_rw_intr_mask___ctxt___bit 1
#define reg_dma_rw_intr_mask___data___lsb 2
#define reg_dma_rw_intr_mask___data___width 1
#define reg_dma_rw_intr_mask___data___bit 2
#define reg_dma_rw_intr_mask___in_eop___lsb 3
#define reg_dma_rw_intr_mask___in_eop___width 1
#define reg_dma_rw_intr_mask___in_eop___bit 3
#define reg_dma_rw_intr_mask___stream_cmd___lsb 4
#define reg_dma_rw_intr_mask___stream_cmd___width 1
#define reg_dma_rw_intr_mask___stream_cmd___bit 4
#define reg_dma_rw_intr_mask_offset 140
/* Register rw_ack_intr, scope dma, type rw */
#define reg_dma_rw_ack_intr___group___lsb 0
#define reg_dma_rw_ack_intr___group___width 1
#define reg_dma_rw_ack_intr___group___bit 0
#define reg_dma_rw_ack_intr___ctxt___lsb 1
#define reg_dma_rw_ack_intr___ctxt___width 1
#define reg_dma_rw_ack_intr___ctxt___bit 1
#define reg_dma_rw_ack_intr___data___lsb 2
#define reg_dma_rw_ack_intr___data___width 1
#define reg_dma_rw_ack_intr___data___bit 2
#define reg_dma_rw_ack_intr___in_eop___lsb 3
#define reg_dma_rw_ack_intr___in_eop___width 1
#define reg_dma_rw_ack_intr___in_eop___bit 3
#define reg_dma_rw_ack_intr___stream_cmd___lsb 4
#define reg_dma_rw_ack_intr___stream_cmd___width 1
#define reg_dma_rw_ack_intr___stream_cmd___bit 4
#define reg_dma_rw_ack_intr_offset 144
/* Register r_intr, scope dma, type r */
#define reg_dma_r_intr___group___lsb 0
#define reg_dma_r_intr___group___width 1
#define reg_dma_r_intr___group___bit 0
#define reg_dma_r_intr___ctxt___lsb 1
#define reg_dma_r_intr___ctxt___width 1
#define reg_dma_r_intr___ctxt___bit 1
#define reg_dma_r_intr___data___lsb 2
#define reg_dma_r_intr___data___width 1
#define reg_dma_r_intr___data___bit 2
#define reg_dma_r_intr___in_eop___lsb 3
#define reg_dma_r_intr___in_eop___width 1
#define reg_dma_r_intr___in_eop___bit 3
#define reg_dma_r_intr___stream_cmd___lsb 4
#define reg_dma_r_intr___stream_cmd___width 1
#define reg_dma_r_intr___stream_cmd___bit 4
#define reg_dma_r_intr_offset 148
/* Register r_masked_intr, scope dma, type r */
#define reg_dma_r_masked_intr___group___lsb 0
#define reg_dma_r_masked_intr___group___width 1
#define reg_dma_r_masked_intr___group___bit 0
#define reg_dma_r_masked_intr___ctxt___lsb 1
#define reg_dma_r_masked_intr___ctxt___width 1
#define reg_dma_r_masked_intr___ctxt___bit 1
#define reg_dma_r_masked_intr___data___lsb 2
#define reg_dma_r_masked_intr___data___width 1
#define reg_dma_r_masked_intr___data___bit 2
#define reg_dma_r_masked_intr___in_eop___lsb 3
#define reg_dma_r_masked_intr___in_eop___width 1
#define reg_dma_r_masked_intr___in_eop___bit 3
#define reg_dma_r_masked_intr___stream_cmd___lsb 4
#define reg_dma_r_masked_intr___stream_cmd___width 1
#define reg_dma_r_masked_intr___stream_cmd___bit 4
#define reg_dma_r_masked_intr_offset 152
/* Register rw_stream_cmd, scope dma, type rw */
#define reg_dma_rw_stream_cmd___cmd___lsb 0
#define reg_dma_rw_stream_cmd___cmd___width 10
#define reg_dma_rw_stream_cmd___n___lsb 16
#define reg_dma_rw_stream_cmd___n___width 8
#define reg_dma_rw_stream_cmd___busy___lsb 31
#define reg_dma_rw_stream_cmd___busy___width 1
#define reg_dma_rw_stream_cmd___busy___bit 31
#define reg_dma_rw_stream_cmd_offset 156
/* Constants */
#define regk_dma_ack_pkt 0x00000100
#define regk_dma_anytime 0x00000001
#define regk_dma_array 0x00000008
#define regk_dma_burst 0x00000020
#define regk_dma_client 0x00000002
#define regk_dma_copy_next 0x00000010
#define regk_dma_copy_up 0x00000020
#define regk_dma_data_at_eol 0x00000001
#define regk_dma_dis_c 0x00000010
#define regk_dma_dis_g 0x00000020
#define regk_dma_idle 0x00000001
#define regk_dma_intern 0x00000004
#define regk_dma_load_c 0x00000200
#define regk_dma_load_c_n 0x00000280
#define regk_dma_load_c_next 0x00000240
#define regk_dma_load_d 0x00000140
#define regk_dma_load_g 0x00000300
#define regk_dma_load_g_down 0x000003c0
#define regk_dma_load_g_next 0x00000340
#define regk_dma_load_g_up 0x00000380
#define regk_dma_next_en 0x00000010
#define regk_dma_next_pkt 0x00000010
#define regk_dma_no 0x00000000
#define regk_dma_only_at_wait 0x00000000
#define regk_dma_restore 0x00000020
#define regk_dma_rst 0x00000001
#define regk_dma_running 0x00000004
#define regk_dma_rw_cfg_default 0x00000000
#define regk_dma_rw_cmd_default 0x00000000
#define regk_dma_rw_intr_mask_default 0x00000000
#define regk_dma_rw_stat_default 0x00000101
#define regk_dma_rw_stream_cmd_default 0x00000000
#define regk_dma_save_down 0x00000020
#define regk_dma_save_up 0x00000020
#define regk_dma_set_reg 0x00000050
#define regk_dma_set_w_size1 0x00000190
#define regk_dma_set_w_size2 0x000001a0
#define regk_dma_set_w_size4 0x000001c0
#define regk_dma_stopped 0x00000002
#define regk_dma_store_c 0x00000002
#define regk_dma_store_descr 0x00000000
#define regk_dma_store_g 0x00000004
#define regk_dma_store_md 0x00000001
#define regk_dma_sw 0x00000008
#define regk_dma_update_down 0x00000020
#define regk_dma_yes 0x00000001
#endif /* __dma_defs_asm_h */

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#ifndef __eth_defs_asm_h
#define __eth_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/eth/rtl/eth_regs.r
* id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp
* last modfied: Mon Apr 11 16:07:03 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r
* id: $Id: eth_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_ma0_lo, scope eth, type rw */
#define reg_eth_rw_ma0_lo___addr___lsb 0
#define reg_eth_rw_ma0_lo___addr___width 32
#define reg_eth_rw_ma0_lo_offset 0
/* Register rw_ma0_hi, scope eth, type rw */
#define reg_eth_rw_ma0_hi___addr___lsb 0
#define reg_eth_rw_ma0_hi___addr___width 16
#define reg_eth_rw_ma0_hi_offset 4
/* Register rw_ma1_lo, scope eth, type rw */
#define reg_eth_rw_ma1_lo___addr___lsb 0
#define reg_eth_rw_ma1_lo___addr___width 32
#define reg_eth_rw_ma1_lo_offset 8
/* Register rw_ma1_hi, scope eth, type rw */
#define reg_eth_rw_ma1_hi___addr___lsb 0
#define reg_eth_rw_ma1_hi___addr___width 16
#define reg_eth_rw_ma1_hi_offset 12
/* Register rw_ga_lo, scope eth, type rw */
#define reg_eth_rw_ga_lo___table___lsb 0
#define reg_eth_rw_ga_lo___table___width 32
#define reg_eth_rw_ga_lo_offset 16
/* Register rw_ga_hi, scope eth, type rw */
#define reg_eth_rw_ga_hi___table___lsb 0
#define reg_eth_rw_ga_hi___table___width 32
#define reg_eth_rw_ga_hi_offset 20
/* Register rw_gen_ctrl, scope eth, type rw */
#define reg_eth_rw_gen_ctrl___en___lsb 0
#define reg_eth_rw_gen_ctrl___en___width 1
#define reg_eth_rw_gen_ctrl___en___bit 0
#define reg_eth_rw_gen_ctrl___phy___lsb 1
#define reg_eth_rw_gen_ctrl___phy___width 2
#define reg_eth_rw_gen_ctrl___protocol___lsb 3
#define reg_eth_rw_gen_ctrl___protocol___width 1
#define reg_eth_rw_gen_ctrl___protocol___bit 3
#define reg_eth_rw_gen_ctrl___loopback___lsb 4
#define reg_eth_rw_gen_ctrl___loopback___width 1
#define reg_eth_rw_gen_ctrl___loopback___bit 4
#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___lsb 5
#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___width 1
#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___bit 5
#define reg_eth_rw_gen_ctrl_offset 24
/* Register rw_rec_ctrl, scope eth, type rw */
#define reg_eth_rw_rec_ctrl___ma0___lsb 0
#define reg_eth_rw_rec_ctrl___ma0___width 1
#define reg_eth_rw_rec_ctrl___ma0___bit 0
#define reg_eth_rw_rec_ctrl___ma1___lsb 1
#define reg_eth_rw_rec_ctrl___ma1___width 1
#define reg_eth_rw_rec_ctrl___ma1___bit 1
#define reg_eth_rw_rec_ctrl___individual___lsb 2
#define reg_eth_rw_rec_ctrl___individual___width 1
#define reg_eth_rw_rec_ctrl___individual___bit 2
#define reg_eth_rw_rec_ctrl___broadcast___lsb 3
#define reg_eth_rw_rec_ctrl___broadcast___width 1
#define reg_eth_rw_rec_ctrl___broadcast___bit 3
#define reg_eth_rw_rec_ctrl___undersize___lsb 4
#define reg_eth_rw_rec_ctrl___undersize___width 1
#define reg_eth_rw_rec_ctrl___undersize___bit 4
#define reg_eth_rw_rec_ctrl___oversize___lsb 5
#define reg_eth_rw_rec_ctrl___oversize___width 1
#define reg_eth_rw_rec_ctrl___oversize___bit 5
#define reg_eth_rw_rec_ctrl___bad_crc___lsb 6
#define reg_eth_rw_rec_ctrl___bad_crc___width 1
#define reg_eth_rw_rec_ctrl___bad_crc___bit 6
#define reg_eth_rw_rec_ctrl___duplex___lsb 7
#define reg_eth_rw_rec_ctrl___duplex___width 1
#define reg_eth_rw_rec_ctrl___duplex___bit 7
#define reg_eth_rw_rec_ctrl___max_size___lsb 8
#define reg_eth_rw_rec_ctrl___max_size___width 1
#define reg_eth_rw_rec_ctrl___max_size___bit 8
#define reg_eth_rw_rec_ctrl_offset 28
/* Register rw_tr_ctrl, scope eth, type rw */
#define reg_eth_rw_tr_ctrl___crc___lsb 0
#define reg_eth_rw_tr_ctrl___crc___width 1
#define reg_eth_rw_tr_ctrl___crc___bit 0
#define reg_eth_rw_tr_ctrl___pad___lsb 1
#define reg_eth_rw_tr_ctrl___pad___width 1
#define reg_eth_rw_tr_ctrl___pad___bit 1
#define reg_eth_rw_tr_ctrl___retry___lsb 2
#define reg_eth_rw_tr_ctrl___retry___width 1
#define reg_eth_rw_tr_ctrl___retry___bit 2
#define reg_eth_rw_tr_ctrl___ignore_col___lsb 3
#define reg_eth_rw_tr_ctrl___ignore_col___width 1
#define reg_eth_rw_tr_ctrl___ignore_col___bit 3
#define reg_eth_rw_tr_ctrl___cancel___lsb 4
#define reg_eth_rw_tr_ctrl___cancel___width 1
#define reg_eth_rw_tr_ctrl___cancel___bit 4
#define reg_eth_rw_tr_ctrl___hsh_delay___lsb 5
#define reg_eth_rw_tr_ctrl___hsh_delay___width 1
#define reg_eth_rw_tr_ctrl___hsh_delay___bit 5
#define reg_eth_rw_tr_ctrl___ignore_crs___lsb 6
#define reg_eth_rw_tr_ctrl___ignore_crs___width 1
#define reg_eth_rw_tr_ctrl___ignore_crs___bit 6
#define reg_eth_rw_tr_ctrl_offset 32
/* Register rw_clr_err, scope eth, type rw */
#define reg_eth_rw_clr_err___clr___lsb 0
#define reg_eth_rw_clr_err___clr___width 1
#define reg_eth_rw_clr_err___clr___bit 0
#define reg_eth_rw_clr_err_offset 36
/* Register rw_mgm_ctrl, scope eth, type rw */
#define reg_eth_rw_mgm_ctrl___mdio___lsb 0
#define reg_eth_rw_mgm_ctrl___mdio___width 1
#define reg_eth_rw_mgm_ctrl___mdio___bit 0
#define reg_eth_rw_mgm_ctrl___mdoe___lsb 1
#define reg_eth_rw_mgm_ctrl___mdoe___width 1
#define reg_eth_rw_mgm_ctrl___mdoe___bit 1
#define reg_eth_rw_mgm_ctrl___mdc___lsb 2
#define reg_eth_rw_mgm_ctrl___mdc___width 1
#define reg_eth_rw_mgm_ctrl___mdc___bit 2
#define reg_eth_rw_mgm_ctrl___phyclk___lsb 3
#define reg_eth_rw_mgm_ctrl___phyclk___width 1
#define reg_eth_rw_mgm_ctrl___phyclk___bit 3
#define reg_eth_rw_mgm_ctrl___txdata___lsb 4
#define reg_eth_rw_mgm_ctrl___txdata___width 4
#define reg_eth_rw_mgm_ctrl___txen___lsb 8
#define reg_eth_rw_mgm_ctrl___txen___width 1
#define reg_eth_rw_mgm_ctrl___txen___bit 8
#define reg_eth_rw_mgm_ctrl_offset 40
/* Register r_stat, scope eth, type r */
#define reg_eth_r_stat___mdio___lsb 0
#define reg_eth_r_stat___mdio___width 1
#define reg_eth_r_stat___mdio___bit 0
#define reg_eth_r_stat___exc_col___lsb 1
#define reg_eth_r_stat___exc_col___width 1
#define reg_eth_r_stat___exc_col___bit 1
#define reg_eth_r_stat___urun___lsb 2
#define reg_eth_r_stat___urun___width 1
#define reg_eth_r_stat___urun___bit 2
#define reg_eth_r_stat___phyclk___lsb 3
#define reg_eth_r_stat___phyclk___width 1
#define reg_eth_r_stat___phyclk___bit 3
#define reg_eth_r_stat___txdata___lsb 4
#define reg_eth_r_stat___txdata___width 4
#define reg_eth_r_stat___txen___lsb 8
#define reg_eth_r_stat___txen___width 1
#define reg_eth_r_stat___txen___bit 8
#define reg_eth_r_stat___col___lsb 9
#define reg_eth_r_stat___col___width 1
#define reg_eth_r_stat___col___bit 9
#define reg_eth_r_stat___crs___lsb 10
#define reg_eth_r_stat___crs___width 1
#define reg_eth_r_stat___crs___bit 10
#define reg_eth_r_stat___txclk___lsb 11
#define reg_eth_r_stat___txclk___width 1
#define reg_eth_r_stat___txclk___bit 11
#define reg_eth_r_stat___rxdata___lsb 12
#define reg_eth_r_stat___rxdata___width 4
#define reg_eth_r_stat___rxer___lsb 16
#define reg_eth_r_stat___rxer___width 1
#define reg_eth_r_stat___rxer___bit 16
#define reg_eth_r_stat___rxdv___lsb 17
#define reg_eth_r_stat___rxdv___width 1
#define reg_eth_r_stat___rxdv___bit 17
#define reg_eth_r_stat___rxclk___lsb 18
#define reg_eth_r_stat___rxclk___width 1
#define reg_eth_r_stat___rxclk___bit 18
#define reg_eth_r_stat_offset 44
/* Register rs_rec_cnt, scope eth, type rs */
#define reg_eth_rs_rec_cnt___crc_err___lsb 0
#define reg_eth_rs_rec_cnt___crc_err___width 8
#define reg_eth_rs_rec_cnt___align_err___lsb 8
#define reg_eth_rs_rec_cnt___align_err___width 8
#define reg_eth_rs_rec_cnt___oversize___lsb 16
#define reg_eth_rs_rec_cnt___oversize___width 8
#define reg_eth_rs_rec_cnt___congestion___lsb 24
#define reg_eth_rs_rec_cnt___congestion___width 8
#define reg_eth_rs_rec_cnt_offset 48
/* Register r_rec_cnt, scope eth, type r */
#define reg_eth_r_rec_cnt___crc_err___lsb 0
#define reg_eth_r_rec_cnt___crc_err___width 8
#define reg_eth_r_rec_cnt___align_err___lsb 8
#define reg_eth_r_rec_cnt___align_err___width 8
#define reg_eth_r_rec_cnt___oversize___lsb 16
#define reg_eth_r_rec_cnt___oversize___width 8
#define reg_eth_r_rec_cnt___congestion___lsb 24
#define reg_eth_r_rec_cnt___congestion___width 8
#define reg_eth_r_rec_cnt_offset 52
/* Register rs_tr_cnt, scope eth, type rs */
#define reg_eth_rs_tr_cnt___single_col___lsb 0
#define reg_eth_rs_tr_cnt___single_col___width 8
#define reg_eth_rs_tr_cnt___mult_col___lsb 8
#define reg_eth_rs_tr_cnt___mult_col___width 8
#define reg_eth_rs_tr_cnt___late_col___lsb 16
#define reg_eth_rs_tr_cnt___late_col___width 8
#define reg_eth_rs_tr_cnt___deferred___lsb 24
#define reg_eth_rs_tr_cnt___deferred___width 8
#define reg_eth_rs_tr_cnt_offset 56
/* Register r_tr_cnt, scope eth, type r */
#define reg_eth_r_tr_cnt___single_col___lsb 0
#define reg_eth_r_tr_cnt___single_col___width 8
#define reg_eth_r_tr_cnt___mult_col___lsb 8
#define reg_eth_r_tr_cnt___mult_col___width 8
#define reg_eth_r_tr_cnt___late_col___lsb 16
#define reg_eth_r_tr_cnt___late_col___width 8
#define reg_eth_r_tr_cnt___deferred___lsb 24
#define reg_eth_r_tr_cnt___deferred___width 8
#define reg_eth_r_tr_cnt_offset 60
/* Register rs_phy_cnt, scope eth, type rs */
#define reg_eth_rs_phy_cnt___carrier_loss___lsb 0
#define reg_eth_rs_phy_cnt___carrier_loss___width 8
#define reg_eth_rs_phy_cnt___sqe_err___lsb 8
#define reg_eth_rs_phy_cnt___sqe_err___width 8
#define reg_eth_rs_phy_cnt_offset 64
/* Register r_phy_cnt, scope eth, type r */
#define reg_eth_r_phy_cnt___carrier_loss___lsb 0
#define reg_eth_r_phy_cnt___carrier_loss___width 8
#define reg_eth_r_phy_cnt___sqe_err___lsb 8
#define reg_eth_r_phy_cnt___sqe_err___width 8
#define reg_eth_r_phy_cnt_offset 68
/* Register rw_test_ctrl, scope eth, type rw */
#define reg_eth_rw_test_ctrl___snmp_inc___lsb 0
#define reg_eth_rw_test_ctrl___snmp_inc___width 1
#define reg_eth_rw_test_ctrl___snmp_inc___bit 0
#define reg_eth_rw_test_ctrl___snmp___lsb 1
#define reg_eth_rw_test_ctrl___snmp___width 1
#define reg_eth_rw_test_ctrl___snmp___bit 1
#define reg_eth_rw_test_ctrl___backoff___lsb 2
#define reg_eth_rw_test_ctrl___backoff___width 1
#define reg_eth_rw_test_ctrl___backoff___bit 2
#define reg_eth_rw_test_ctrl_offset 72
/* Register rw_intr_mask, scope eth, type rw */
#define reg_eth_rw_intr_mask___crc___lsb 0
#define reg_eth_rw_intr_mask___crc___width 1
#define reg_eth_rw_intr_mask___crc___bit 0
#define reg_eth_rw_intr_mask___align___lsb 1
#define reg_eth_rw_intr_mask___align___width 1
#define reg_eth_rw_intr_mask___align___bit 1
#define reg_eth_rw_intr_mask___oversize___lsb 2
#define reg_eth_rw_intr_mask___oversize___width 1
#define reg_eth_rw_intr_mask___oversize___bit 2
#define reg_eth_rw_intr_mask___congestion___lsb 3
#define reg_eth_rw_intr_mask___congestion___width 1
#define reg_eth_rw_intr_mask___congestion___bit 3
#define reg_eth_rw_intr_mask___single_col___lsb 4
#define reg_eth_rw_intr_mask___single_col___width 1
#define reg_eth_rw_intr_mask___single_col___bit 4
#define reg_eth_rw_intr_mask___mult_col___lsb 5
#define reg_eth_rw_intr_mask___mult_col___width 1
#define reg_eth_rw_intr_mask___mult_col___bit 5
#define reg_eth_rw_intr_mask___late_col___lsb 6
#define reg_eth_rw_intr_mask___late_col___width 1
#define reg_eth_rw_intr_mask___late_col___bit 6
#define reg_eth_rw_intr_mask___deferred___lsb 7
#define reg_eth_rw_intr_mask___deferred___width 1
#define reg_eth_rw_intr_mask___deferred___bit 7
#define reg_eth_rw_intr_mask___carrier_loss___lsb 8
#define reg_eth_rw_intr_mask___carrier_loss___width 1
#define reg_eth_rw_intr_mask___carrier_loss___bit 8
#define reg_eth_rw_intr_mask___sqe_test_err___lsb 9
#define reg_eth_rw_intr_mask___sqe_test_err___width 1
#define reg_eth_rw_intr_mask___sqe_test_err___bit 9
#define reg_eth_rw_intr_mask___orun___lsb 10
#define reg_eth_rw_intr_mask___orun___width 1
#define reg_eth_rw_intr_mask___orun___bit 10
#define reg_eth_rw_intr_mask___urun___lsb 11
#define reg_eth_rw_intr_mask___urun___width 1
#define reg_eth_rw_intr_mask___urun___bit 11
#define reg_eth_rw_intr_mask___excessive_col___lsb 12
#define reg_eth_rw_intr_mask___excessive_col___width 1
#define reg_eth_rw_intr_mask___excessive_col___bit 12
#define reg_eth_rw_intr_mask___mdio___lsb 13
#define reg_eth_rw_intr_mask___mdio___width 1
#define reg_eth_rw_intr_mask___mdio___bit 13
#define reg_eth_rw_intr_mask_offset 76
/* Register rw_ack_intr, scope eth, type rw */
#define reg_eth_rw_ack_intr___crc___lsb 0
#define reg_eth_rw_ack_intr___crc___width 1
#define reg_eth_rw_ack_intr___crc___bit 0
#define reg_eth_rw_ack_intr___align___lsb 1
#define reg_eth_rw_ack_intr___align___width 1
#define reg_eth_rw_ack_intr___align___bit 1
#define reg_eth_rw_ack_intr___oversize___lsb 2
#define reg_eth_rw_ack_intr___oversize___width 1
#define reg_eth_rw_ack_intr___oversize___bit 2
#define reg_eth_rw_ack_intr___congestion___lsb 3
#define reg_eth_rw_ack_intr___congestion___width 1
#define reg_eth_rw_ack_intr___congestion___bit 3
#define reg_eth_rw_ack_intr___single_col___lsb 4
#define reg_eth_rw_ack_intr___single_col___width 1
#define reg_eth_rw_ack_intr___single_col___bit 4
#define reg_eth_rw_ack_intr___mult_col___lsb 5
#define reg_eth_rw_ack_intr___mult_col___width 1
#define reg_eth_rw_ack_intr___mult_col___bit 5
#define reg_eth_rw_ack_intr___late_col___lsb 6
#define reg_eth_rw_ack_intr___late_col___width 1
#define reg_eth_rw_ack_intr___late_col___bit 6
#define reg_eth_rw_ack_intr___deferred___lsb 7
#define reg_eth_rw_ack_intr___deferred___width 1
#define reg_eth_rw_ack_intr___deferred___bit 7
#define reg_eth_rw_ack_intr___carrier_loss___lsb 8
#define reg_eth_rw_ack_intr___carrier_loss___width 1
#define reg_eth_rw_ack_intr___carrier_loss___bit 8
#define reg_eth_rw_ack_intr___sqe_test_err___lsb 9
#define reg_eth_rw_ack_intr___sqe_test_err___width 1
#define reg_eth_rw_ack_intr___sqe_test_err___bit 9
#define reg_eth_rw_ack_intr___orun___lsb 10
#define reg_eth_rw_ack_intr___orun___width 1
#define reg_eth_rw_ack_intr___orun___bit 10
#define reg_eth_rw_ack_intr___urun___lsb 11
#define reg_eth_rw_ack_intr___urun___width 1
#define reg_eth_rw_ack_intr___urun___bit 11
#define reg_eth_rw_ack_intr___excessive_col___lsb 12
#define reg_eth_rw_ack_intr___excessive_col___width 1
#define reg_eth_rw_ack_intr___excessive_col___bit 12
#define reg_eth_rw_ack_intr___mdio___lsb 13
#define reg_eth_rw_ack_intr___mdio___width 1
#define reg_eth_rw_ack_intr___mdio___bit 13
#define reg_eth_rw_ack_intr_offset 80
/* Register r_intr, scope eth, type r */
#define reg_eth_r_intr___crc___lsb 0
#define reg_eth_r_intr___crc___width 1
#define reg_eth_r_intr___crc___bit 0
#define reg_eth_r_intr___align___lsb 1
#define reg_eth_r_intr___align___width 1
#define reg_eth_r_intr___align___bit 1
#define reg_eth_r_intr___oversize___lsb 2
#define reg_eth_r_intr___oversize___width 1
#define reg_eth_r_intr___oversize___bit 2
#define reg_eth_r_intr___congestion___lsb 3
#define reg_eth_r_intr___congestion___width 1
#define reg_eth_r_intr___congestion___bit 3
#define reg_eth_r_intr___single_col___lsb 4
#define reg_eth_r_intr___single_col___width 1
#define reg_eth_r_intr___single_col___bit 4
#define reg_eth_r_intr___mult_col___lsb 5
#define reg_eth_r_intr___mult_col___width 1
#define reg_eth_r_intr___mult_col___bit 5
#define reg_eth_r_intr___late_col___lsb 6
#define reg_eth_r_intr___late_col___width 1
#define reg_eth_r_intr___late_col___bit 6
#define reg_eth_r_intr___deferred___lsb 7
#define reg_eth_r_intr___deferred___width 1
#define reg_eth_r_intr___deferred___bit 7
#define reg_eth_r_intr___carrier_loss___lsb 8
#define reg_eth_r_intr___carrier_loss___width 1
#define reg_eth_r_intr___carrier_loss___bit 8
#define reg_eth_r_intr___sqe_test_err___lsb 9
#define reg_eth_r_intr___sqe_test_err___width 1
#define reg_eth_r_intr___sqe_test_err___bit 9
#define reg_eth_r_intr___orun___lsb 10
#define reg_eth_r_intr___orun___width 1
#define reg_eth_r_intr___orun___bit 10
#define reg_eth_r_intr___urun___lsb 11
#define reg_eth_r_intr___urun___width 1
#define reg_eth_r_intr___urun___bit 11
#define reg_eth_r_intr___excessive_col___lsb 12
#define reg_eth_r_intr___excessive_col___width 1
#define reg_eth_r_intr___excessive_col___bit 12
#define reg_eth_r_intr___mdio___lsb 13
#define reg_eth_r_intr___mdio___width 1
#define reg_eth_r_intr___mdio___bit 13
#define reg_eth_r_intr_offset 84
/* Register r_masked_intr, scope eth, type r */
#define reg_eth_r_masked_intr___crc___lsb 0
#define reg_eth_r_masked_intr___crc___width 1
#define reg_eth_r_masked_intr___crc___bit 0
#define reg_eth_r_masked_intr___align___lsb 1
#define reg_eth_r_masked_intr___align___width 1
#define reg_eth_r_masked_intr___align___bit 1
#define reg_eth_r_masked_intr___oversize___lsb 2
#define reg_eth_r_masked_intr___oversize___width 1
#define reg_eth_r_masked_intr___oversize___bit 2
#define reg_eth_r_masked_intr___congestion___lsb 3
#define reg_eth_r_masked_intr___congestion___width 1
#define reg_eth_r_masked_intr___congestion___bit 3
#define reg_eth_r_masked_intr___single_col___lsb 4
#define reg_eth_r_masked_intr___single_col___width 1
#define reg_eth_r_masked_intr___single_col___bit 4
#define reg_eth_r_masked_intr___mult_col___lsb 5
#define reg_eth_r_masked_intr___mult_col___width 1
#define reg_eth_r_masked_intr___mult_col___bit 5
#define reg_eth_r_masked_intr___late_col___lsb 6
#define reg_eth_r_masked_intr___late_col___width 1
#define reg_eth_r_masked_intr___late_col___bit 6
#define reg_eth_r_masked_intr___deferred___lsb 7
#define reg_eth_r_masked_intr___deferred___width 1
#define reg_eth_r_masked_intr___deferred___bit 7
#define reg_eth_r_masked_intr___carrier_loss___lsb 8
#define reg_eth_r_masked_intr___carrier_loss___width 1
#define reg_eth_r_masked_intr___carrier_loss___bit 8
#define reg_eth_r_masked_intr___sqe_test_err___lsb 9
#define reg_eth_r_masked_intr___sqe_test_err___width 1
#define reg_eth_r_masked_intr___sqe_test_err___bit 9
#define reg_eth_r_masked_intr___orun___lsb 10
#define reg_eth_r_masked_intr___orun___width 1
#define reg_eth_r_masked_intr___orun___bit 10
#define reg_eth_r_masked_intr___urun___lsb 11
#define reg_eth_r_masked_intr___urun___width 1
#define reg_eth_r_masked_intr___urun___bit 11
#define reg_eth_r_masked_intr___excessive_col___lsb 12
#define reg_eth_r_masked_intr___excessive_col___width 1
#define reg_eth_r_masked_intr___excessive_col___bit 12
#define reg_eth_r_masked_intr___mdio___lsb 13
#define reg_eth_r_masked_intr___mdio___width 1
#define reg_eth_r_masked_intr___mdio___bit 13
#define reg_eth_r_masked_intr_offset 88
/* Constants */
#define regk_eth_discard 0x00000000
#define regk_eth_ether 0x00000000
#define regk_eth_full 0x00000001
#define regk_eth_half 0x00000000
#define regk_eth_hsh 0x00000001
#define regk_eth_mii 0x00000001
#define regk_eth_mii_clk 0x00000000
#define regk_eth_mii_rec 0x00000002
#define regk_eth_no 0x00000000
#define regk_eth_rec 0x00000001
#define regk_eth_rw_ga_hi_default 0x00000000
#define regk_eth_rw_ga_lo_default 0x00000000
#define regk_eth_rw_gen_ctrl_default 0x00000000
#define regk_eth_rw_intr_mask_default 0x00000000
#define regk_eth_rw_ma0_hi_default 0x00000000
#define regk_eth_rw_ma0_lo_default 0x00000000
#define regk_eth_rw_ma1_hi_default 0x00000000
#define regk_eth_rw_ma1_lo_default 0x00000000
#define regk_eth_rw_mgm_ctrl_default 0x00000000
#define regk_eth_rw_test_ctrl_default 0x00000000
#define regk_eth_size1518 0x00000000
#define regk_eth_size1522 0x00000001
#define regk_eth_yes 0x00000001
#endif /* __eth_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/asm/gio_defs_asm.h Normal file
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#ifndef __gio_defs_asm_h
#define __gio_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/gio/rtl/gio_regs.r
* id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
* last modfied: Mon Apr 11 16:07:47 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r
* id: $Id: gio_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_pa_dout, scope gio, type rw */
#define reg_gio_rw_pa_dout___data___lsb 0
#define reg_gio_rw_pa_dout___data___width 8
#define reg_gio_rw_pa_dout_offset 0
/* Register r_pa_din, scope gio, type r */
#define reg_gio_r_pa_din___data___lsb 0
#define reg_gio_r_pa_din___data___width 8
#define reg_gio_r_pa_din_offset 4
/* Register rw_pa_oe, scope gio, type rw */
#define reg_gio_rw_pa_oe___oe___lsb 0
#define reg_gio_rw_pa_oe___oe___width 8
#define reg_gio_rw_pa_oe_offset 8
/* Register rw_intr_cfg, scope gio, type rw */
#define reg_gio_rw_intr_cfg___pa0___lsb 0
#define reg_gio_rw_intr_cfg___pa0___width 3
#define reg_gio_rw_intr_cfg___pa1___lsb 3
#define reg_gio_rw_intr_cfg___pa1___width 3
#define reg_gio_rw_intr_cfg___pa2___lsb 6
#define reg_gio_rw_intr_cfg___pa2___width 3
#define reg_gio_rw_intr_cfg___pa3___lsb 9
#define reg_gio_rw_intr_cfg___pa3___width 3
#define reg_gio_rw_intr_cfg___pa4___lsb 12
#define reg_gio_rw_intr_cfg___pa4___width 3
#define reg_gio_rw_intr_cfg___pa5___lsb 15
#define reg_gio_rw_intr_cfg___pa5___width 3
#define reg_gio_rw_intr_cfg___pa6___lsb 18
#define reg_gio_rw_intr_cfg___pa6___width 3
#define reg_gio_rw_intr_cfg___pa7___lsb 21
#define reg_gio_rw_intr_cfg___pa7___width 3
#define reg_gio_rw_intr_cfg_offset 12
/* Register rw_intr_mask, scope gio, type rw */
#define reg_gio_rw_intr_mask___pa0___lsb 0
#define reg_gio_rw_intr_mask___pa0___width 1
#define reg_gio_rw_intr_mask___pa0___bit 0
#define reg_gio_rw_intr_mask___pa1___lsb 1
#define reg_gio_rw_intr_mask___pa1___width 1
#define reg_gio_rw_intr_mask___pa1___bit 1
#define reg_gio_rw_intr_mask___pa2___lsb 2
#define reg_gio_rw_intr_mask___pa2___width 1
#define reg_gio_rw_intr_mask___pa2___bit 2
#define reg_gio_rw_intr_mask___pa3___lsb 3
#define reg_gio_rw_intr_mask___pa3___width 1
#define reg_gio_rw_intr_mask___pa3___bit 3
#define reg_gio_rw_intr_mask___pa4___lsb 4
#define reg_gio_rw_intr_mask___pa4___width 1
#define reg_gio_rw_intr_mask___pa4___bit 4
#define reg_gio_rw_intr_mask___pa5___lsb 5
#define reg_gio_rw_intr_mask___pa5___width 1
#define reg_gio_rw_intr_mask___pa5___bit 5
#define reg_gio_rw_intr_mask___pa6___lsb 6
#define reg_gio_rw_intr_mask___pa6___width 1
#define reg_gio_rw_intr_mask___pa6___bit 6
#define reg_gio_rw_intr_mask___pa7___lsb 7
#define reg_gio_rw_intr_mask___pa7___width 1
#define reg_gio_rw_intr_mask___pa7___bit 7
#define reg_gio_rw_intr_mask_offset 16
/* Register rw_ack_intr, scope gio, type rw */
#define reg_gio_rw_ack_intr___pa0___lsb 0
#define reg_gio_rw_ack_intr___pa0___width 1
#define reg_gio_rw_ack_intr___pa0___bit 0
#define reg_gio_rw_ack_intr___pa1___lsb 1
#define reg_gio_rw_ack_intr___pa1___width 1
#define reg_gio_rw_ack_intr___pa1___bit 1
#define reg_gio_rw_ack_intr___pa2___lsb 2
#define reg_gio_rw_ack_intr___pa2___width 1
#define reg_gio_rw_ack_intr___pa2___bit 2
#define reg_gio_rw_ack_intr___pa3___lsb 3
#define reg_gio_rw_ack_intr___pa3___width 1
#define reg_gio_rw_ack_intr___pa3___bit 3
#define reg_gio_rw_ack_intr___pa4___lsb 4
#define reg_gio_rw_ack_intr___pa4___width 1
#define reg_gio_rw_ack_intr___pa4___bit 4
#define reg_gio_rw_ack_intr___pa5___lsb 5
#define reg_gio_rw_ack_intr___pa5___width 1
#define reg_gio_rw_ack_intr___pa5___bit 5
#define reg_gio_rw_ack_intr___pa6___lsb 6
#define reg_gio_rw_ack_intr___pa6___width 1
#define reg_gio_rw_ack_intr___pa6___bit 6
#define reg_gio_rw_ack_intr___pa7___lsb 7
#define reg_gio_rw_ack_intr___pa7___width 1
#define reg_gio_rw_ack_intr___pa7___bit 7
#define reg_gio_rw_ack_intr_offset 20
/* Register r_intr, scope gio, type r */
#define reg_gio_r_intr___pa0___lsb 0
#define reg_gio_r_intr___pa0___width 1
#define reg_gio_r_intr___pa0___bit 0
#define reg_gio_r_intr___pa1___lsb 1
#define reg_gio_r_intr___pa1___width 1
#define reg_gio_r_intr___pa1___bit 1
#define reg_gio_r_intr___pa2___lsb 2
#define reg_gio_r_intr___pa2___width 1
#define reg_gio_r_intr___pa2___bit 2
#define reg_gio_r_intr___pa3___lsb 3
#define reg_gio_r_intr___pa3___width 1
#define reg_gio_r_intr___pa3___bit 3
#define reg_gio_r_intr___pa4___lsb 4
#define reg_gio_r_intr___pa4___width 1
#define reg_gio_r_intr___pa4___bit 4
#define reg_gio_r_intr___pa5___lsb 5
#define reg_gio_r_intr___pa5___width 1
#define reg_gio_r_intr___pa5___bit 5
#define reg_gio_r_intr___pa6___lsb 6
#define reg_gio_r_intr___pa6___width 1
#define reg_gio_r_intr___pa6___bit 6
#define reg_gio_r_intr___pa7___lsb 7
#define reg_gio_r_intr___pa7___width 1
#define reg_gio_r_intr___pa7___bit 7
#define reg_gio_r_intr_offset 24
/* Register r_masked_intr, scope gio, type r */
#define reg_gio_r_masked_intr___pa0___lsb 0
#define reg_gio_r_masked_intr___pa0___width 1
#define reg_gio_r_masked_intr___pa0___bit 0
#define reg_gio_r_masked_intr___pa1___lsb 1
#define reg_gio_r_masked_intr___pa1___width 1
#define reg_gio_r_masked_intr___pa1___bit 1
#define reg_gio_r_masked_intr___pa2___lsb 2
#define reg_gio_r_masked_intr___pa2___width 1
#define reg_gio_r_masked_intr___pa2___bit 2
#define reg_gio_r_masked_intr___pa3___lsb 3
#define reg_gio_r_masked_intr___pa3___width 1
#define reg_gio_r_masked_intr___pa3___bit 3
#define reg_gio_r_masked_intr___pa4___lsb 4
#define reg_gio_r_masked_intr___pa4___width 1
#define reg_gio_r_masked_intr___pa4___bit 4
#define reg_gio_r_masked_intr___pa5___lsb 5
#define reg_gio_r_masked_intr___pa5___width 1
#define reg_gio_r_masked_intr___pa5___bit 5
#define reg_gio_r_masked_intr___pa6___lsb 6
#define reg_gio_r_masked_intr___pa6___width 1
#define reg_gio_r_masked_intr___pa6___bit 6
#define reg_gio_r_masked_intr___pa7___lsb 7
#define reg_gio_r_masked_intr___pa7___width 1
#define reg_gio_r_masked_intr___pa7___bit 7
#define reg_gio_r_masked_intr_offset 28
/* Register rw_pb_dout, scope gio, type rw */
#define reg_gio_rw_pb_dout___data___lsb 0
#define reg_gio_rw_pb_dout___data___width 18
#define reg_gio_rw_pb_dout_offset 32
/* Register r_pb_din, scope gio, type r */
#define reg_gio_r_pb_din___data___lsb 0
#define reg_gio_r_pb_din___data___width 18
#define reg_gio_r_pb_din_offset 36
/* Register rw_pb_oe, scope gio, type rw */
#define reg_gio_rw_pb_oe___oe___lsb 0
#define reg_gio_rw_pb_oe___oe___width 18
#define reg_gio_rw_pb_oe_offset 40
/* Register rw_pc_dout, scope gio, type rw */
#define reg_gio_rw_pc_dout___data___lsb 0
#define reg_gio_rw_pc_dout___data___width 18
#define reg_gio_rw_pc_dout_offset 48
/* Register r_pc_din, scope gio, type r */
#define reg_gio_r_pc_din___data___lsb 0
#define reg_gio_r_pc_din___data___width 18
#define reg_gio_r_pc_din_offset 52
/* Register rw_pc_oe, scope gio, type rw */
#define reg_gio_rw_pc_oe___oe___lsb 0
#define reg_gio_rw_pc_oe___oe___width 18
#define reg_gio_rw_pc_oe_offset 56
/* Register rw_pd_dout, scope gio, type rw */
#define reg_gio_rw_pd_dout___data___lsb 0
#define reg_gio_rw_pd_dout___data___width 18
#define reg_gio_rw_pd_dout_offset 64
/* Register r_pd_din, scope gio, type r */
#define reg_gio_r_pd_din___data___lsb 0
#define reg_gio_r_pd_din___data___width 18
#define reg_gio_r_pd_din_offset 68
/* Register rw_pd_oe, scope gio, type rw */
#define reg_gio_rw_pd_oe___oe___lsb 0
#define reg_gio_rw_pd_oe___oe___width 18
#define reg_gio_rw_pd_oe_offset 72
/* Register rw_pe_dout, scope gio, type rw */
#define reg_gio_rw_pe_dout___data___lsb 0
#define reg_gio_rw_pe_dout___data___width 18
#define reg_gio_rw_pe_dout_offset 80
/* Register r_pe_din, scope gio, type r */
#define reg_gio_r_pe_din___data___lsb 0
#define reg_gio_r_pe_din___data___width 18
#define reg_gio_r_pe_din_offset 84
/* Register rw_pe_oe, scope gio, type rw */
#define reg_gio_rw_pe_oe___oe___lsb 0
#define reg_gio_rw_pe_oe___oe___width 18
#define reg_gio_rw_pe_oe_offset 88
/* Constants */
#define regk_gio_anyedge 0x00000007
#define regk_gio_hi 0x00000001
#define regk_gio_lo 0x00000002
#define regk_gio_negedge 0x00000006
#define regk_gio_no 0x00000000
#define regk_gio_off 0x00000000
#define regk_gio_posedge 0x00000005
#define regk_gio_rw_intr_cfg_default 0x00000000
#define regk_gio_rw_intr_mask_default 0x00000000
#define regk_gio_rw_pa_oe_default 0x00000000
#define regk_gio_rw_pb_oe_default 0x00000000
#define regk_gio_rw_pc_oe_default 0x00000000
#define regk_gio_rw_pd_oe_default 0x00000000
#define regk_gio_rw_pe_oe_default 0x00000000
#define regk_gio_set 0x00000003
#define regk_gio_yes 0x00000001
#endif /* __gio_defs_asm_h */

38
arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect.h Normal file
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/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
version . */
#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
#define MEMARB_INTR_VECT 0x31
#define GEN_IO_INTR_VECT 0x32
#define IOP0_INTR_VECT 0x33
#define IOP1_INTR_VECT 0x34
#define IOP2_INTR_VECT 0x35
#define IOP3_INTR_VECT 0x36
#define DMA0_INTR_VECT 0x37
#define DMA1_INTR_VECT 0x38
#define DMA2_INTR_VECT 0x39
#define DMA3_INTR_VECT 0x3a
#define DMA4_INTR_VECT 0x3b
#define DMA5_INTR_VECT 0x3c
#define DMA6_INTR_VECT 0x3d
#define DMA7_INTR_VECT 0x3e
#define DMA8_INTR_VECT 0x3f
#define DMA9_INTR_VECT 0x40
#define ATA_INTR_VECT 0x41
#define SSER0_INTR_VECT 0x42
#define SSER1_INTR_VECT 0x43
#define SER0_INTR_VECT 0x44
#define SER1_INTR_VECT 0x45
#define SER2_INTR_VECT 0x46
#define SER3_INTR_VECT 0x47
#define P21_INTR_VECT 0x48
#define ETH0_INTR_VECT 0x49
#define ETH1_INTR_VECT 0x4a
#define TIMER_INTR_VECT 0x4b
#define BIF_ARB_INTR_VECT 0x4c
#define BIF_DMA_INTR_VECT 0x4d
#define EXT_INTR_VECT 0x4e
#endif

355
arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect_defs_asm.h Normal file
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#ifndef __intr_vect_defs_asm_h
#define __intr_vect_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r
* id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
* last modfied: Mon Apr 11 16:08:03 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
* id: $Id: intr_vect_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_mask, scope intr_vect, type rw */
#define reg_intr_vect_rw_mask___memarb___lsb 0
#define reg_intr_vect_rw_mask___memarb___width 1
#define reg_intr_vect_rw_mask___memarb___bit 0
#define reg_intr_vect_rw_mask___gen_io___lsb 1
#define reg_intr_vect_rw_mask___gen_io___width 1
#define reg_intr_vect_rw_mask___gen_io___bit 1
#define reg_intr_vect_rw_mask___iop0___lsb 2
#define reg_intr_vect_rw_mask___iop0___width 1
#define reg_intr_vect_rw_mask___iop0___bit 2
#define reg_intr_vect_rw_mask___iop1___lsb 3
#define reg_intr_vect_rw_mask___iop1___width 1
#define reg_intr_vect_rw_mask___iop1___bit 3
#define reg_intr_vect_rw_mask___iop2___lsb 4
#define reg_intr_vect_rw_mask___iop2___width 1
#define reg_intr_vect_rw_mask___iop2___bit 4
#define reg_intr_vect_rw_mask___iop3___lsb 5
#define reg_intr_vect_rw_mask___iop3___width 1
#define reg_intr_vect_rw_mask___iop3___bit 5
#define reg_intr_vect_rw_mask___dma0___lsb 6
#define reg_intr_vect_rw_mask___dma0___width 1
#define reg_intr_vect_rw_mask___dma0___bit 6
#define reg_intr_vect_rw_mask___dma1___lsb 7
#define reg_intr_vect_rw_mask___dma1___width 1
#define reg_intr_vect_rw_mask___dma1___bit 7
#define reg_intr_vect_rw_mask___dma2___lsb 8
#define reg_intr_vect_rw_mask___dma2___width 1
#define reg_intr_vect_rw_mask___dma2___bit 8
#define reg_intr_vect_rw_mask___dma3___lsb 9
#define reg_intr_vect_rw_mask___dma3___width 1
#define reg_intr_vect_rw_mask___dma3___bit 9
#define reg_intr_vect_rw_mask___dma4___lsb 10
#define reg_intr_vect_rw_mask___dma4___width 1
#define reg_intr_vect_rw_mask___dma4___bit 10
#define reg_intr_vect_rw_mask___dma5___lsb 11
#define reg_intr_vect_rw_mask___dma5___width 1
#define reg_intr_vect_rw_mask___dma5___bit 11
#define reg_intr_vect_rw_mask___dma6___lsb 12
#define reg_intr_vect_rw_mask___dma6___width 1
#define reg_intr_vect_rw_mask___dma6___bit 12
#define reg_intr_vect_rw_mask___dma7___lsb 13
#define reg_intr_vect_rw_mask___dma7___width 1
#define reg_intr_vect_rw_mask___dma7___bit 13
#define reg_intr_vect_rw_mask___dma8___lsb 14
#define reg_intr_vect_rw_mask___dma8___width 1
#define reg_intr_vect_rw_mask___dma8___bit 14
#define reg_intr_vect_rw_mask___dma9___lsb 15
#define reg_intr_vect_rw_mask___dma9___width 1
#define reg_intr_vect_rw_mask___dma9___bit 15
#define reg_intr_vect_rw_mask___ata___lsb 16
#define reg_intr_vect_rw_mask___ata___width 1
#define reg_intr_vect_rw_mask___ata___bit 16
#define reg_intr_vect_rw_mask___sser0___lsb 17
#define reg_intr_vect_rw_mask___sser0___width 1
#define reg_intr_vect_rw_mask___sser0___bit 17
#define reg_intr_vect_rw_mask___sser1___lsb 18
#define reg_intr_vect_rw_mask___sser1___width 1
#define reg_intr_vect_rw_mask___sser1___bit 18
#define reg_intr_vect_rw_mask___ser0___lsb 19
#define reg_intr_vect_rw_mask___ser0___width 1
#define reg_intr_vect_rw_mask___ser0___bit 19
#define reg_intr_vect_rw_mask___ser1___lsb 20
#define reg_intr_vect_rw_mask___ser1___width 1
#define reg_intr_vect_rw_mask___ser1___bit 20
#define reg_intr_vect_rw_mask___ser2___lsb 21
#define reg_intr_vect_rw_mask___ser2___width 1
#define reg_intr_vect_rw_mask___ser2___bit 21
#define reg_intr_vect_rw_mask___ser3___lsb 22
#define reg_intr_vect_rw_mask___ser3___width 1
#define reg_intr_vect_rw_mask___ser3___bit 22
#define reg_intr_vect_rw_mask___p21___lsb 23
#define reg_intr_vect_rw_mask___p21___width 1
#define reg_intr_vect_rw_mask___p21___bit 23
#define reg_intr_vect_rw_mask___eth0___lsb 24
#define reg_intr_vect_rw_mask___eth0___width 1
#define reg_intr_vect_rw_mask___eth0___bit 24
#define reg_intr_vect_rw_mask___eth1___lsb 25
#define reg_intr_vect_rw_mask___eth1___width 1
#define reg_intr_vect_rw_mask___eth1___bit 25
#define reg_intr_vect_rw_mask___timer___lsb 26
#define reg_intr_vect_rw_mask___timer___width 1
#define reg_intr_vect_rw_mask___timer___bit 26
#define reg_intr_vect_rw_mask___bif_arb___lsb 27
#define reg_intr_vect_rw_mask___bif_arb___width 1
#define reg_intr_vect_rw_mask___bif_arb___bit 27
#define reg_intr_vect_rw_mask___bif_dma___lsb 28
#define reg_intr_vect_rw_mask___bif_dma___width 1
#define reg_intr_vect_rw_mask___bif_dma___bit 28
#define reg_intr_vect_rw_mask___ext___lsb 29
#define reg_intr_vect_rw_mask___ext___width 1
#define reg_intr_vect_rw_mask___ext___bit 29
#define reg_intr_vect_rw_mask_offset 0
/* Register r_vect, scope intr_vect, type r */
#define reg_intr_vect_r_vect___memarb___lsb 0
#define reg_intr_vect_r_vect___memarb___width 1
#define reg_intr_vect_r_vect___memarb___bit 0
#define reg_intr_vect_r_vect___gen_io___lsb 1
#define reg_intr_vect_r_vect___gen_io___width 1
#define reg_intr_vect_r_vect___gen_io___bit 1
#define reg_intr_vect_r_vect___iop0___lsb 2
#define reg_intr_vect_r_vect___iop0___width 1
#define reg_intr_vect_r_vect___iop0___bit 2
#define reg_intr_vect_r_vect___iop1___lsb 3
#define reg_intr_vect_r_vect___iop1___width 1
#define reg_intr_vect_r_vect___iop1___bit 3
#define reg_intr_vect_r_vect___iop2___lsb 4
#define reg_intr_vect_r_vect___iop2___width 1
#define reg_intr_vect_r_vect___iop2___bit 4
#define reg_intr_vect_r_vect___iop3___lsb 5
#define reg_intr_vect_r_vect___iop3___width 1
#define reg_intr_vect_r_vect___iop3___bit 5
#define reg_intr_vect_r_vect___dma0___lsb 6
#define reg_intr_vect_r_vect___dma0___width 1
#define reg_intr_vect_r_vect___dma0___bit 6
#define reg_intr_vect_r_vect___dma1___lsb 7
#define reg_intr_vect_r_vect___dma1___width 1
#define reg_intr_vect_r_vect___dma1___bit 7
#define reg_intr_vect_r_vect___dma2___lsb 8
#define reg_intr_vect_r_vect___dma2___width 1
#define reg_intr_vect_r_vect___dma2___bit 8
#define reg_intr_vect_r_vect___dma3___lsb 9
#define reg_intr_vect_r_vect___dma3___width 1
#define reg_intr_vect_r_vect___dma3___bit 9
#define reg_intr_vect_r_vect___dma4___lsb 10
#define reg_intr_vect_r_vect___dma4___width 1
#define reg_intr_vect_r_vect___dma4___bit 10
#define reg_intr_vect_r_vect___dma5___lsb 11
#define reg_intr_vect_r_vect___dma5___width 1
#define reg_intr_vect_r_vect___dma5___bit 11
#define reg_intr_vect_r_vect___dma6___lsb 12
#define reg_intr_vect_r_vect___dma6___width 1
#define reg_intr_vect_r_vect___dma6___bit 12
#define reg_intr_vect_r_vect___dma7___lsb 13
#define reg_intr_vect_r_vect___dma7___width 1
#define reg_intr_vect_r_vect___dma7___bit 13
#define reg_intr_vect_r_vect___dma8___lsb 14
#define reg_intr_vect_r_vect___dma8___width 1
#define reg_intr_vect_r_vect___dma8___bit 14
#define reg_intr_vect_r_vect___dma9___lsb 15
#define reg_intr_vect_r_vect___dma9___width 1
#define reg_intr_vect_r_vect___dma9___bit 15
#define reg_intr_vect_r_vect___ata___lsb 16
#define reg_intr_vect_r_vect___ata___width 1
#define reg_intr_vect_r_vect___ata___bit 16
#define reg_intr_vect_r_vect___sser0___lsb 17
#define reg_intr_vect_r_vect___sser0___width 1
#define reg_intr_vect_r_vect___sser0___bit 17
#define reg_intr_vect_r_vect___sser1___lsb 18
#define reg_intr_vect_r_vect___sser1___width 1
#define reg_intr_vect_r_vect___sser1___bit 18
#define reg_intr_vect_r_vect___ser0___lsb 19
#define reg_intr_vect_r_vect___ser0___width 1
#define reg_intr_vect_r_vect___ser0___bit 19
#define reg_intr_vect_r_vect___ser1___lsb 20
#define reg_intr_vect_r_vect___ser1___width 1
#define reg_intr_vect_r_vect___ser1___bit 20
#define reg_intr_vect_r_vect___ser2___lsb 21
#define reg_intr_vect_r_vect___ser2___width 1
#define reg_intr_vect_r_vect___ser2___bit 21
#define reg_intr_vect_r_vect___ser3___lsb 22
#define reg_intr_vect_r_vect___ser3___width 1
#define reg_intr_vect_r_vect___ser3___bit 22
#define reg_intr_vect_r_vect___p21___lsb 23
#define reg_intr_vect_r_vect___p21___width 1
#define reg_intr_vect_r_vect___p21___bit 23
#define reg_intr_vect_r_vect___eth0___lsb 24
#define reg_intr_vect_r_vect___eth0___width 1
#define reg_intr_vect_r_vect___eth0___bit 24
#define reg_intr_vect_r_vect___eth1___lsb 25
#define reg_intr_vect_r_vect___eth1___width 1
#define reg_intr_vect_r_vect___eth1___bit 25
#define reg_intr_vect_r_vect___timer___lsb 26
#define reg_intr_vect_r_vect___timer___width 1
#define reg_intr_vect_r_vect___timer___bit 26
#define reg_intr_vect_r_vect___bif_arb___lsb 27
#define reg_intr_vect_r_vect___bif_arb___width 1
#define reg_intr_vect_r_vect___bif_arb___bit 27
#define reg_intr_vect_r_vect___bif_dma___lsb 28
#define reg_intr_vect_r_vect___bif_dma___width 1
#define reg_intr_vect_r_vect___bif_dma___bit 28
#define reg_intr_vect_r_vect___ext___lsb 29
#define reg_intr_vect_r_vect___ext___width 1
#define reg_intr_vect_r_vect___ext___bit 29
#define reg_intr_vect_r_vect_offset 4
/* Register r_masked_vect, scope intr_vect, type r */
#define reg_intr_vect_r_masked_vect___memarb___lsb 0
#define reg_intr_vect_r_masked_vect___memarb___width 1
#define reg_intr_vect_r_masked_vect___memarb___bit 0
#define reg_intr_vect_r_masked_vect___gen_io___lsb 1
#define reg_intr_vect_r_masked_vect___gen_io___width 1
#define reg_intr_vect_r_masked_vect___gen_io___bit 1
#define reg_intr_vect_r_masked_vect___iop0___lsb 2
#define reg_intr_vect_r_masked_vect___iop0___width 1
#define reg_intr_vect_r_masked_vect___iop0___bit 2
#define reg_intr_vect_r_masked_vect___iop1___lsb 3
#define reg_intr_vect_r_masked_vect___iop1___width 1
#define reg_intr_vect_r_masked_vect___iop1___bit 3
#define reg_intr_vect_r_masked_vect___iop2___lsb 4
#define reg_intr_vect_r_masked_vect___iop2___width 1
#define reg_intr_vect_r_masked_vect___iop2___bit 4
#define reg_intr_vect_r_masked_vect___iop3___lsb 5
#define reg_intr_vect_r_masked_vect___iop3___width 1
#define reg_intr_vect_r_masked_vect___iop3___bit 5
#define reg_intr_vect_r_masked_vect___dma0___lsb 6
#define reg_intr_vect_r_masked_vect___dma0___width 1
#define reg_intr_vect_r_masked_vect___dma0___bit 6
#define reg_intr_vect_r_masked_vect___dma1___lsb 7
#define reg_intr_vect_r_masked_vect___dma1___width 1
#define reg_intr_vect_r_masked_vect___dma1___bit 7
#define reg_intr_vect_r_masked_vect___dma2___lsb 8
#define reg_intr_vect_r_masked_vect___dma2___width 1
#define reg_intr_vect_r_masked_vect___dma2___bit 8
#define reg_intr_vect_r_masked_vect___dma3___lsb 9
#define reg_intr_vect_r_masked_vect___dma3___width 1
#define reg_intr_vect_r_masked_vect___dma3___bit 9
#define reg_intr_vect_r_masked_vect___dma4___lsb 10
#define reg_intr_vect_r_masked_vect___dma4___width 1
#define reg_intr_vect_r_masked_vect___dma4___bit 10
#define reg_intr_vect_r_masked_vect___dma5___lsb 11
#define reg_intr_vect_r_masked_vect___dma5___width 1
#define reg_intr_vect_r_masked_vect___dma5___bit 11
#define reg_intr_vect_r_masked_vect___dma6___lsb 12
#define reg_intr_vect_r_masked_vect___dma6___width 1
#define reg_intr_vect_r_masked_vect___dma6___bit 12
#define reg_intr_vect_r_masked_vect___dma7___lsb 13
#define reg_intr_vect_r_masked_vect___dma7___width 1
#define reg_intr_vect_r_masked_vect___dma7___bit 13
#define reg_intr_vect_r_masked_vect___dma8___lsb 14
#define reg_intr_vect_r_masked_vect___dma8___width 1
#define reg_intr_vect_r_masked_vect___dma8___bit 14
#define reg_intr_vect_r_masked_vect___dma9___lsb 15
#define reg_intr_vect_r_masked_vect___dma9___width 1
#define reg_intr_vect_r_masked_vect___dma9___bit 15
#define reg_intr_vect_r_masked_vect___ata___lsb 16
#define reg_intr_vect_r_masked_vect___ata___width 1
#define reg_intr_vect_r_masked_vect___ata___bit 16
#define reg_intr_vect_r_masked_vect___sser0___lsb 17
#define reg_intr_vect_r_masked_vect___sser0___width 1
#define reg_intr_vect_r_masked_vect___sser0___bit 17
#define reg_intr_vect_r_masked_vect___sser1___lsb 18
#define reg_intr_vect_r_masked_vect___sser1___width 1
#define reg_intr_vect_r_masked_vect___sser1___bit 18
#define reg_intr_vect_r_masked_vect___ser0___lsb 19
#define reg_intr_vect_r_masked_vect___ser0___width 1
#define reg_intr_vect_r_masked_vect___ser0___bit 19
#define reg_intr_vect_r_masked_vect___ser1___lsb 20
#define reg_intr_vect_r_masked_vect___ser1___width 1
#define reg_intr_vect_r_masked_vect___ser1___bit 20
#define reg_intr_vect_r_masked_vect___ser2___lsb 21
#define reg_intr_vect_r_masked_vect___ser2___width 1
#define reg_intr_vect_r_masked_vect___ser2___bit 21
#define reg_intr_vect_r_masked_vect___ser3___lsb 22
#define reg_intr_vect_r_masked_vect___ser3___width 1
#define reg_intr_vect_r_masked_vect___ser3___bit 22
#define reg_intr_vect_r_masked_vect___p21___lsb 23
#define reg_intr_vect_r_masked_vect___p21___width 1
#define reg_intr_vect_r_masked_vect___p21___bit 23
#define reg_intr_vect_r_masked_vect___eth0___lsb 24
#define reg_intr_vect_r_masked_vect___eth0___width 1
#define reg_intr_vect_r_masked_vect___eth0___bit 24
#define reg_intr_vect_r_masked_vect___eth1___lsb 25
#define reg_intr_vect_r_masked_vect___eth1___width 1
#define reg_intr_vect_r_masked_vect___eth1___bit 25
#define reg_intr_vect_r_masked_vect___timer___lsb 26
#define reg_intr_vect_r_masked_vect___timer___width 1
#define reg_intr_vect_r_masked_vect___timer___bit 26
#define reg_intr_vect_r_masked_vect___bif_arb___lsb 27
#define reg_intr_vect_r_masked_vect___bif_arb___width 1
#define reg_intr_vect_r_masked_vect___bif_arb___bit 27
#define reg_intr_vect_r_masked_vect___bif_dma___lsb 28
#define reg_intr_vect_r_masked_vect___bif_dma___width 1
#define reg_intr_vect_r_masked_vect___bif_dma___bit 28
#define reg_intr_vect_r_masked_vect___ext___lsb 29
#define reg_intr_vect_r_masked_vect___ext___width 1
#define reg_intr_vect_r_masked_vect___ext___bit 29
#define reg_intr_vect_r_masked_vect_offset 8
/* Register r_nmi, scope intr_vect, type r */
#define reg_intr_vect_r_nmi___ext___lsb 0
#define reg_intr_vect_r_nmi___ext___width 1
#define reg_intr_vect_r_nmi___ext___bit 0
#define reg_intr_vect_r_nmi___watchdog___lsb 1
#define reg_intr_vect_r_nmi___watchdog___width 1
#define reg_intr_vect_r_nmi___watchdog___bit 1
#define reg_intr_vect_r_nmi_offset 12
/* Register r_guru, scope intr_vect, type r */
#define reg_intr_vect_r_guru___jtag___lsb 0
#define reg_intr_vect_r_guru___jtag___width 1
#define reg_intr_vect_r_guru___jtag___bit 0
#define reg_intr_vect_r_guru_offset 16
/* Constants */
#define regk_intr_vect_off 0x00000000
#define regk_intr_vect_on 0x00000001
#define regk_intr_vect_rw_mask_default 0x00000000
#endif /* __intr_vect_defs_asm_h */

69
arch/cris/include/arch-v32/arch/hwregs/asm/irq_nmi_defs_asm.h Normal file
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#ifndef __irq_nmi_defs_asm_h
#define __irq_nmi_defs_asm_h
/*
* This file is autogenerated from
* file: ../../mod/irq_nmi.r
* id: <not found>
* last modfied: Thu Jan 22 09:22:43 2004
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/irq_nmi_defs_asm.h ../../mod/irq_nmi.r
* id: $Id: irq_nmi_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_cmd, scope irq_nmi, type rw */
#define reg_irq_nmi_rw_cmd___delay___lsb 0
#define reg_irq_nmi_rw_cmd___delay___width 16
#define reg_irq_nmi_rw_cmd___op___lsb 16
#define reg_irq_nmi_rw_cmd___op___width 2
#define reg_irq_nmi_rw_cmd_offset 0
/* Constants */
#define regk_irq_nmi_ack_irq 0x00000002
#define regk_irq_nmi_ack_nmi 0x00000003
#define regk_irq_nmi_irq 0x00000000
#define regk_irq_nmi_nmi 0x00000001
#endif /* __irq_nmi_defs_asm_h */

579
arch/cris/include/arch-v32/arch/hwregs/asm/marb_defs_asm.h Normal file
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#ifndef __marb_defs_asm_h
#define __marb_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/memarb/rtl/guinness/marb_top.r
* id: <not found>
* last modfied: Mon Apr 11 16:12:16 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
* id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
#define STRIDE_marb_rw_int_slots 4
/* Register rw_int_slots, scope marb, type rw */
#define reg_marb_rw_int_slots___owner___lsb 0
#define reg_marb_rw_int_slots___owner___width 4
#define reg_marb_rw_int_slots_offset 0
#define STRIDE_marb_rw_ext_slots 4
/* Register rw_ext_slots, scope marb, type rw */
#define reg_marb_rw_ext_slots___owner___lsb 0
#define reg_marb_rw_ext_slots___owner___width 4
#define reg_marb_rw_ext_slots_offset 256
#define STRIDE_marb_rw_regs_slots 4
/* Register rw_regs_slots, scope marb, type rw */
#define reg_marb_rw_regs_slots___owner___lsb 0
#define reg_marb_rw_regs_slots___owner___width 4
#define reg_marb_rw_regs_slots_offset 512
/* Register rw_intr_mask, scope marb, type rw */
#define reg_marb_rw_intr_mask___bp0___lsb 0
#define reg_marb_rw_intr_mask___bp0___width 1
#define reg_marb_rw_intr_mask___bp0___bit 0
#define reg_marb_rw_intr_mask___bp1___lsb 1
#define reg_marb_rw_intr_mask___bp1___width 1
#define reg_marb_rw_intr_mask___bp1___bit 1
#define reg_marb_rw_intr_mask___bp2___lsb 2
#define reg_marb_rw_intr_mask___bp2___width 1
#define reg_marb_rw_intr_mask___bp2___bit 2
#define reg_marb_rw_intr_mask___bp3___lsb 3
#define reg_marb_rw_intr_mask___bp3___width 1
#define reg_marb_rw_intr_mask___bp3___bit 3
#define reg_marb_rw_intr_mask_offset 528
/* Register rw_ack_intr, scope marb, type rw */
#define reg_marb_rw_ack_intr___bp0___lsb 0
#define reg_marb_rw_ack_intr___bp0___width 1
#define reg_marb_rw_ack_intr___bp0___bit 0
#define reg_marb_rw_ack_intr___bp1___lsb 1
#define reg_marb_rw_ack_intr___bp1___width 1
#define reg_marb_rw_ack_intr___bp1___bit 1
#define reg_marb_rw_ack_intr___bp2___lsb 2
#define reg_marb_rw_ack_intr___bp2___width 1
#define reg_marb_rw_ack_intr___bp2___bit 2
#define reg_marb_rw_ack_intr___bp3___lsb 3
#define reg_marb_rw_ack_intr___bp3___width 1
#define reg_marb_rw_ack_intr___bp3___bit 3
#define reg_marb_rw_ack_intr_offset 532
/* Register r_intr, scope marb, type r */
#define reg_marb_r_intr___bp0___lsb 0
#define reg_marb_r_intr___bp0___width 1
#define reg_marb_r_intr___bp0___bit 0
#define reg_marb_r_intr___bp1___lsb 1
#define reg_marb_r_intr___bp1___width 1
#define reg_marb_r_intr___bp1___bit 1
#define reg_marb_r_intr___bp2___lsb 2
#define reg_marb_r_intr___bp2___width 1
#define reg_marb_r_intr___bp2___bit 2
#define reg_marb_r_intr___bp3___lsb 3
#define reg_marb_r_intr___bp3___width 1
#define reg_marb_r_intr___bp3___bit 3
#define reg_marb_r_intr_offset 536
/* Register r_masked_intr, scope marb, type r */
#define reg_marb_r_masked_intr___bp0___lsb 0
#define reg_marb_r_masked_intr___bp0___width 1
#define reg_marb_r_masked_intr___bp0___bit 0
#define reg_marb_r_masked_intr___bp1___lsb 1
#define reg_marb_r_masked_intr___bp1___width 1
#define reg_marb_r_masked_intr___bp1___bit 1
#define reg_marb_r_masked_intr___bp2___lsb 2
#define reg_marb_r_masked_intr___bp2___width 1
#define reg_marb_r_masked_intr___bp2___bit 2
#define reg_marb_r_masked_intr___bp3___lsb 3
#define reg_marb_r_masked_intr___bp3___width 1
#define reg_marb_r_masked_intr___bp3___bit 3
#define reg_marb_r_masked_intr_offset 540
/* Register rw_stop_mask, scope marb, type rw */
#define reg_marb_rw_stop_mask___dma0___lsb 0
#define reg_marb_rw_stop_mask___dma0___width 1
#define reg_marb_rw_stop_mask___dma0___bit 0
#define reg_marb_rw_stop_mask___dma1___lsb 1
#define reg_marb_rw_stop_mask___dma1___width 1
#define reg_marb_rw_stop_mask___dma1___bit 1
#define reg_marb_rw_stop_mask___dma2___lsb 2
#define reg_marb_rw_stop_mask___dma2___width 1
#define reg_marb_rw_stop_mask___dma2___bit 2
#define reg_marb_rw_stop_mask___dma3___lsb 3
#define reg_marb_rw_stop_mask___dma3___width 1
#define reg_marb_rw_stop_mask___dma3___bit 3
#define reg_marb_rw_stop_mask___dma4___lsb 4
#define reg_marb_rw_stop_mask___dma4___width 1
#define reg_marb_rw_stop_mask___dma4___bit 4
#define reg_marb_rw_stop_mask___dma5___lsb 5
#define reg_marb_rw_stop_mask___dma5___width 1
#define reg_marb_rw_stop_mask___dma5___bit 5
#define reg_marb_rw_stop_mask___dma6___lsb 6
#define reg_marb_rw_stop_mask___dma6___width 1
#define reg_marb_rw_stop_mask___dma6___bit 6
#define reg_marb_rw_stop_mask___dma7___lsb 7
#define reg_marb_rw_stop_mask___dma7___width 1
#define reg_marb_rw_stop_mask___dma7___bit 7
#define reg_marb_rw_stop_mask___dma8___lsb 8
#define reg_marb_rw_stop_mask___dma8___width 1
#define reg_marb_rw_stop_mask___dma8___bit 8
#define reg_marb_rw_stop_mask___dma9___lsb 9
#define reg_marb_rw_stop_mask___dma9___width 1
#define reg_marb_rw_stop_mask___dma9___bit 9
#define reg_marb_rw_stop_mask___cpui___lsb 10
#define reg_marb_rw_stop_mask___cpui___width 1
#define reg_marb_rw_stop_mask___cpui___bit 10
#define reg_marb_rw_stop_mask___cpud___lsb 11
#define reg_marb_rw_stop_mask___cpud___width 1
#define reg_marb_rw_stop_mask___cpud___bit 11
#define reg_marb_rw_stop_mask___iop___lsb 12
#define reg_marb_rw_stop_mask___iop___width 1
#define reg_marb_rw_stop_mask___iop___bit 12
#define reg_marb_rw_stop_mask___slave___lsb 13
#define reg_marb_rw_stop_mask___slave___width 1
#define reg_marb_rw_stop_mask___slave___bit 13
#define reg_marb_rw_stop_mask_offset 544
/* Register r_stopped, scope marb, type r */
#define reg_marb_r_stopped___dma0___lsb 0
#define reg_marb_r_stopped___dma0___width 1
#define reg_marb_r_stopped___dma0___bit 0
#define reg_marb_r_stopped___dma1___lsb 1
#define reg_marb_r_stopped___dma1___width 1
#define reg_marb_r_stopped___dma1___bit 1
#define reg_marb_r_stopped___dma2___lsb 2
#define reg_marb_r_stopped___dma2___width 1
#define reg_marb_r_stopped___dma2___bit 2
#define reg_marb_r_stopped___dma3___lsb 3
#define reg_marb_r_stopped___dma3___width 1
#define reg_marb_r_stopped___dma3___bit 3
#define reg_marb_r_stopped___dma4___lsb 4
#define reg_marb_r_stopped___dma4___width 1
#define reg_marb_r_stopped___dma4___bit 4
#define reg_marb_r_stopped___dma5___lsb 5
#define reg_marb_r_stopped___dma5___width 1
#define reg_marb_r_stopped___dma5___bit 5
#define reg_marb_r_stopped___dma6___lsb 6
#define reg_marb_r_stopped___dma6___width 1
#define reg_marb_r_stopped___dma6___bit 6
#define reg_marb_r_stopped___dma7___lsb 7
#define reg_marb_r_stopped___dma7___width 1
#define reg_marb_r_stopped___dma7___bit 7
#define reg_marb_r_stopped___dma8___lsb 8
#define reg_marb_r_stopped___dma8___width 1
#define reg_marb_r_stopped___dma8___bit 8
#define reg_marb_r_stopped___dma9___lsb 9
#define reg_marb_r_stopped___dma9___width 1
#define reg_marb_r_stopped___dma9___bit 9
#define reg_marb_r_stopped___cpui___lsb 10
#define reg_marb_r_stopped___cpui___width 1
#define reg_marb_r_stopped___cpui___bit 10
#define reg_marb_r_stopped___cpud___lsb 11
#define reg_marb_r_stopped___cpud___width 1
#define reg_marb_r_stopped___cpud___bit 11
#define reg_marb_r_stopped___iop___lsb 12
#define reg_marb_r_stopped___iop___width 1
#define reg_marb_r_stopped___iop___bit 12
#define reg_marb_r_stopped___slave___lsb 13
#define reg_marb_r_stopped___slave___width 1
#define reg_marb_r_stopped___slave___bit 13
#define reg_marb_r_stopped_offset 548
/* Register rw_no_snoop, scope marb, type rw */
#define reg_marb_rw_no_snoop___dma0___lsb 0
#define reg_marb_rw_no_snoop___dma0___width 1
#define reg_marb_rw_no_snoop___dma0___bit 0
#define reg_marb_rw_no_snoop___dma1___lsb 1
#define reg_marb_rw_no_snoop___dma1___width 1
#define reg_marb_rw_no_snoop___dma1___bit 1
#define reg_marb_rw_no_snoop___dma2___lsb 2
#define reg_marb_rw_no_snoop___dma2___width 1
#define reg_marb_rw_no_snoop___dma2___bit 2
#define reg_marb_rw_no_snoop___dma3___lsb 3
#define reg_marb_rw_no_snoop___dma3___width 1
#define reg_marb_rw_no_snoop___dma3___bit 3
#define reg_marb_rw_no_snoop___dma4___lsb 4
#define reg_marb_rw_no_snoop___dma4___width 1
#define reg_marb_rw_no_snoop___dma4___bit 4
#define reg_marb_rw_no_snoop___dma5___lsb 5
#define reg_marb_rw_no_snoop___dma5___width 1
#define reg_marb_rw_no_snoop___dma5___bit 5
#define reg_marb_rw_no_snoop___dma6___lsb 6
#define reg_marb_rw_no_snoop___dma6___width 1
#define reg_marb_rw_no_snoop___dma6___bit 6
#define reg_marb_rw_no_snoop___dma7___lsb 7
#define reg_marb_rw_no_snoop___dma7___width 1
#define reg_marb_rw_no_snoop___dma7___bit 7
#define reg_marb_rw_no_snoop___dma8___lsb 8
#define reg_marb_rw_no_snoop___dma8___width 1
#define reg_marb_rw_no_snoop___dma8___bit 8
#define reg_marb_rw_no_snoop___dma9___lsb 9
#define reg_marb_rw_no_snoop___dma9___width 1
#define reg_marb_rw_no_snoop___dma9___bit 9
#define reg_marb_rw_no_snoop___cpui___lsb 10
#define reg_marb_rw_no_snoop___cpui___width 1
#define reg_marb_rw_no_snoop___cpui___bit 10
#define reg_marb_rw_no_snoop___cpud___lsb 11
#define reg_marb_rw_no_snoop___cpud___width 1
#define reg_marb_rw_no_snoop___cpud___bit 11
#define reg_marb_rw_no_snoop___iop___lsb 12
#define reg_marb_rw_no_snoop___iop___width 1
#define reg_marb_rw_no_snoop___iop___bit 12
#define reg_marb_rw_no_snoop___slave___lsb 13
#define reg_marb_rw_no_snoop___slave___width 1
#define reg_marb_rw_no_snoop___slave___bit 13
#define reg_marb_rw_no_snoop_offset 832
/* Register rw_no_snoop_rq, scope marb, type rw */
#define reg_marb_rw_no_snoop_rq___cpui___lsb 10
#define reg_marb_rw_no_snoop_rq___cpui___width 1
#define reg_marb_rw_no_snoop_rq___cpui___bit 10
#define reg_marb_rw_no_snoop_rq___cpud___lsb 11
#define reg_marb_rw_no_snoop_rq___cpud___width 1
#define reg_marb_rw_no_snoop_rq___cpud___bit 11
#define reg_marb_rw_no_snoop_rq_offset 836
/* Constants */
#define regk_marb_cpud 0x0000000b
#define regk_marb_cpui 0x0000000a
#define regk_marb_dma0 0x00000000
#define regk_marb_dma1 0x00000001
#define regk_marb_dma2 0x00000002
#define regk_marb_dma3 0x00000003
#define regk_marb_dma4 0x00000004
#define regk_marb_dma5 0x00000005
#define regk_marb_dma6 0x00000006
#define regk_marb_dma7 0x00000007
#define regk_marb_dma8 0x00000008
#define regk_marb_dma9 0x00000009
#define regk_marb_iop 0x0000000c
#define regk_marb_no 0x00000000
#define regk_marb_r_stopped_default 0x00000000
#define regk_marb_rw_ext_slots_default 0x00000000
#define regk_marb_rw_ext_slots_size 0x00000040
#define regk_marb_rw_int_slots_default 0x00000000
#define regk_marb_rw_int_slots_size 0x00000040
#define regk_marb_rw_intr_mask_default 0x00000000
#define regk_marb_rw_no_snoop_default 0x00000000
#define regk_marb_rw_no_snoop_rq_default 0x00000000
#define regk_marb_rw_regs_slots_default 0x00000000
#define regk_marb_rw_regs_slots_size 0x00000004
#define regk_marb_rw_stop_mask_default 0x00000000
#define regk_marb_slave 0x0000000d
#define regk_marb_yes 0x00000001
#endif /* __marb_defs_asm_h */
#ifndef __marb_bp_defs_asm_h
#define __marb_bp_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/memarb/rtl/guinness/marb_top.r
* id: <not found>
* last modfied: Mon Apr 11 16:12:16 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
* id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_first_addr, scope marb_bp, type rw */
#define reg_marb_bp_rw_first_addr_offset 0
/* Register rw_last_addr, scope marb_bp, type rw */
#define reg_marb_bp_rw_last_addr_offset 4
/* Register rw_op, scope marb_bp, type rw */
#define reg_marb_bp_rw_op___rd___lsb 0
#define reg_marb_bp_rw_op___rd___width 1
#define reg_marb_bp_rw_op___rd___bit 0
#define reg_marb_bp_rw_op___wr___lsb 1
#define reg_marb_bp_rw_op___wr___width 1
#define reg_marb_bp_rw_op___wr___bit 1
#define reg_marb_bp_rw_op___rd_excl___lsb 2
#define reg_marb_bp_rw_op___rd_excl___width 1
#define reg_marb_bp_rw_op___rd_excl___bit 2
#define reg_marb_bp_rw_op___pri_wr___lsb 3
#define reg_marb_bp_rw_op___pri_wr___width 1
#define reg_marb_bp_rw_op___pri_wr___bit 3
#define reg_marb_bp_rw_op___us_rd___lsb 4
#define reg_marb_bp_rw_op___us_rd___width 1
#define reg_marb_bp_rw_op___us_rd___bit 4
#define reg_marb_bp_rw_op___us_wr___lsb 5
#define reg_marb_bp_rw_op___us_wr___width 1
#define reg_marb_bp_rw_op___us_wr___bit 5
#define reg_marb_bp_rw_op___us_rd_excl___lsb 6
#define reg_marb_bp_rw_op___us_rd_excl___width 1
#define reg_marb_bp_rw_op___us_rd_excl___bit 6
#define reg_marb_bp_rw_op___us_pri_wr___lsb 7
#define reg_marb_bp_rw_op___us_pri_wr___width 1
#define reg_marb_bp_rw_op___us_pri_wr___bit 7
#define reg_marb_bp_rw_op_offset 8
/* Register rw_clients, scope marb_bp, type rw */
#define reg_marb_bp_rw_clients___dma0___lsb 0
#define reg_marb_bp_rw_clients___dma0___width 1
#define reg_marb_bp_rw_clients___dma0___bit 0
#define reg_marb_bp_rw_clients___dma1___lsb 1
#define reg_marb_bp_rw_clients___dma1___width 1
#define reg_marb_bp_rw_clients___dma1___bit 1
#define reg_marb_bp_rw_clients___dma2___lsb 2
#define reg_marb_bp_rw_clients___dma2___width 1
#define reg_marb_bp_rw_clients___dma2___bit 2
#define reg_marb_bp_rw_clients___dma3___lsb 3
#define reg_marb_bp_rw_clients___dma3___width 1
#define reg_marb_bp_rw_clients___dma3___bit 3
#define reg_marb_bp_rw_clients___dma4___lsb 4
#define reg_marb_bp_rw_clients___dma4___width 1
#define reg_marb_bp_rw_clients___dma4___bit 4
#define reg_marb_bp_rw_clients___dma5___lsb 5
#define reg_marb_bp_rw_clients___dma5___width 1
#define reg_marb_bp_rw_clients___dma5___bit 5
#define reg_marb_bp_rw_clients___dma6___lsb 6
#define reg_marb_bp_rw_clients___dma6___width 1
#define reg_marb_bp_rw_clients___dma6___bit 6
#define reg_marb_bp_rw_clients___dma7___lsb 7
#define reg_marb_bp_rw_clients___dma7___width 1
#define reg_marb_bp_rw_clients___dma7___bit 7
#define reg_marb_bp_rw_clients___dma8___lsb 8
#define reg_marb_bp_rw_clients___dma8___width 1
#define reg_marb_bp_rw_clients___dma8___bit 8
#define reg_marb_bp_rw_clients___dma9___lsb 9
#define reg_marb_bp_rw_clients___dma9___width 1
#define reg_marb_bp_rw_clients___dma9___bit 9
#define reg_marb_bp_rw_clients___cpui___lsb 10
#define reg_marb_bp_rw_clients___cpui___width 1
#define reg_marb_bp_rw_clients___cpui___bit 10
#define reg_marb_bp_rw_clients___cpud___lsb 11
#define reg_marb_bp_rw_clients___cpud___width 1
#define reg_marb_bp_rw_clients___cpud___bit 11
#define reg_marb_bp_rw_clients___iop___lsb 12
#define reg_marb_bp_rw_clients___iop___width 1
#define reg_marb_bp_rw_clients___iop___bit 12
#define reg_marb_bp_rw_clients___slave___lsb 13
#define reg_marb_bp_rw_clients___slave___width 1
#define reg_marb_bp_rw_clients___slave___bit 13
#define reg_marb_bp_rw_clients_offset 12
/* Register rw_options, scope marb_bp, type rw */
#define reg_marb_bp_rw_options___wrap___lsb 0
#define reg_marb_bp_rw_options___wrap___width 1
#define reg_marb_bp_rw_options___wrap___bit 0
#define reg_marb_bp_rw_options_offset 16
/* Register r_brk_addr, scope marb_bp, type r */
#define reg_marb_bp_r_brk_addr_offset 20
/* Register r_brk_op, scope marb_bp, type r */
#define reg_marb_bp_r_brk_op___rd___lsb 0
#define reg_marb_bp_r_brk_op___rd___width 1
#define reg_marb_bp_r_brk_op___rd___bit 0
#define reg_marb_bp_r_brk_op___wr___lsb 1
#define reg_marb_bp_r_brk_op___wr___width 1
#define reg_marb_bp_r_brk_op___wr___bit 1
#define reg_marb_bp_r_brk_op___rd_excl___lsb 2
#define reg_marb_bp_r_brk_op___rd_excl___width 1
#define reg_marb_bp_r_brk_op___rd_excl___bit 2
#define reg_marb_bp_r_brk_op___pri_wr___lsb 3
#define reg_marb_bp_r_brk_op___pri_wr___width 1
#define reg_marb_bp_r_brk_op___pri_wr___bit 3
#define reg_marb_bp_r_brk_op___us_rd___lsb 4
#define reg_marb_bp_r_brk_op___us_rd___width 1
#define reg_marb_bp_r_brk_op___us_rd___bit 4
#define reg_marb_bp_r_brk_op___us_wr___lsb 5
#define reg_marb_bp_r_brk_op___us_wr___width 1
#define reg_marb_bp_r_brk_op___us_wr___bit 5
#define reg_marb_bp_r_brk_op___us_rd_excl___lsb 6
#define reg_marb_bp_r_brk_op___us_rd_excl___width 1
#define reg_marb_bp_r_brk_op___us_rd_excl___bit 6
#define reg_marb_bp_r_brk_op___us_pri_wr___lsb 7
#define reg_marb_bp_r_brk_op___us_pri_wr___width 1
#define reg_marb_bp_r_brk_op___us_pri_wr___bit 7
#define reg_marb_bp_r_brk_op_offset 24
/* Register r_brk_clients, scope marb_bp, type r */
#define reg_marb_bp_r_brk_clients___dma0___lsb 0
#define reg_marb_bp_r_brk_clients___dma0___width 1
#define reg_marb_bp_r_brk_clients___dma0___bit 0
#define reg_marb_bp_r_brk_clients___dma1___lsb 1
#define reg_marb_bp_r_brk_clients___dma1___width 1
#define reg_marb_bp_r_brk_clients___dma1___bit 1
#define reg_marb_bp_r_brk_clients___dma2___lsb 2
#define reg_marb_bp_r_brk_clients___dma2___width 1
#define reg_marb_bp_r_brk_clients___dma2___bit 2
#define reg_marb_bp_r_brk_clients___dma3___lsb 3
#define reg_marb_bp_r_brk_clients___dma3___width 1
#define reg_marb_bp_r_brk_clients___dma3___bit 3
#define reg_marb_bp_r_brk_clients___dma4___lsb 4
#define reg_marb_bp_r_brk_clients___dma4___width 1
#define reg_marb_bp_r_brk_clients___dma4___bit 4
#define reg_marb_bp_r_brk_clients___dma5___lsb 5
#define reg_marb_bp_r_brk_clients___dma5___width 1
#define reg_marb_bp_r_brk_clients___dma5___bit 5
#define reg_marb_bp_r_brk_clients___dma6___lsb 6
#define reg_marb_bp_r_brk_clients___dma6___width 1
#define reg_marb_bp_r_brk_clients___dma6___bit 6
#define reg_marb_bp_r_brk_clients___dma7___lsb 7
#define reg_marb_bp_r_brk_clients___dma7___width 1
#define reg_marb_bp_r_brk_clients___dma7___bit 7
#define reg_marb_bp_r_brk_clients___dma8___lsb 8
#define reg_marb_bp_r_brk_clients___dma8___width 1
#define reg_marb_bp_r_brk_clients___dma8___bit 8
#define reg_marb_bp_r_brk_clients___dma9___lsb 9
#define reg_marb_bp_r_brk_clients___dma9___width 1
#define reg_marb_bp_r_brk_clients___dma9___bit 9
#define reg_marb_bp_r_brk_clients___cpui___lsb 10
#define reg_marb_bp_r_brk_clients___cpui___width 1
#define reg_marb_bp_r_brk_clients___cpui___bit 10
#define reg_marb_bp_r_brk_clients___cpud___lsb 11
#define reg_marb_bp_r_brk_clients___cpud___width 1
#define reg_marb_bp_r_brk_clients___cpud___bit 11
#define reg_marb_bp_r_brk_clients___iop___lsb 12
#define reg_marb_bp_r_brk_clients___iop___width 1
#define reg_marb_bp_r_brk_clients___iop___bit 12
#define reg_marb_bp_r_brk_clients___slave___lsb 13
#define reg_marb_bp_r_brk_clients___slave___width 1
#define reg_marb_bp_r_brk_clients___slave___bit 13
#define reg_marb_bp_r_brk_clients_offset 28
/* Register r_brk_first_client, scope marb_bp, type r */
#define reg_marb_bp_r_brk_first_client___dma0___lsb 0
#define reg_marb_bp_r_brk_first_client___dma0___width 1
#define reg_marb_bp_r_brk_first_client___dma0___bit 0
#define reg_marb_bp_r_brk_first_client___dma1___lsb 1
#define reg_marb_bp_r_brk_first_client___dma1___width 1
#define reg_marb_bp_r_brk_first_client___dma1___bit 1
#define reg_marb_bp_r_brk_first_client___dma2___lsb 2
#define reg_marb_bp_r_brk_first_client___dma2___width 1
#define reg_marb_bp_r_brk_first_client___dma2___bit 2
#define reg_marb_bp_r_brk_first_client___dma3___lsb 3
#define reg_marb_bp_r_brk_first_client___dma3___width 1
#define reg_marb_bp_r_brk_first_client___dma3___bit 3
#define reg_marb_bp_r_brk_first_client___dma4___lsb 4
#define reg_marb_bp_r_brk_first_client___dma4___width 1
#define reg_marb_bp_r_brk_first_client___dma4___bit 4
#define reg_marb_bp_r_brk_first_client___dma5___lsb 5
#define reg_marb_bp_r_brk_first_client___dma5___width 1
#define reg_marb_bp_r_brk_first_client___dma5___bit 5
#define reg_marb_bp_r_brk_first_client___dma6___lsb 6
#define reg_marb_bp_r_brk_first_client___dma6___width 1
#define reg_marb_bp_r_brk_first_client___dma6___bit 6
#define reg_marb_bp_r_brk_first_client___dma7___lsb 7
#define reg_marb_bp_r_brk_first_client___dma7___width 1
#define reg_marb_bp_r_brk_first_client___dma7___bit 7
#define reg_marb_bp_r_brk_first_client___dma8___lsb 8
#define reg_marb_bp_r_brk_first_client___dma8___width 1
#define reg_marb_bp_r_brk_first_client___dma8___bit 8
#define reg_marb_bp_r_brk_first_client___dma9___lsb 9
#define reg_marb_bp_r_brk_first_client___dma9___width 1
#define reg_marb_bp_r_brk_first_client___dma9___bit 9
#define reg_marb_bp_r_brk_first_client___cpui___lsb 10
#define reg_marb_bp_r_brk_first_client___cpui___width 1
#define reg_marb_bp_r_brk_first_client___cpui___bit 10
#define reg_marb_bp_r_brk_first_client___cpud___lsb 11
#define reg_marb_bp_r_brk_first_client___cpud___width 1
#define reg_marb_bp_r_brk_first_client___cpud___bit 11
#define reg_marb_bp_r_brk_first_client___iop___lsb 12
#define reg_marb_bp_r_brk_first_client___iop___width 1
#define reg_marb_bp_r_brk_first_client___iop___bit 12
#define reg_marb_bp_r_brk_first_client___slave___lsb 13
#define reg_marb_bp_r_brk_first_client___slave___width 1
#define reg_marb_bp_r_brk_first_client___slave___bit 13
#define reg_marb_bp_r_brk_first_client_offset 32
/* Register r_brk_size, scope marb_bp, type r */
#define reg_marb_bp_r_brk_size_offset 36
/* Register rw_ack, scope marb_bp, type rw */
#define reg_marb_bp_rw_ack_offset 40
/* Constants */
#define regk_marb_bp_no 0x00000000
#define regk_marb_bp_rw_op_default 0x00000000
#define regk_marb_bp_rw_options_default 0x00000000
#define regk_marb_bp_yes 0x00000001
#endif /* __marb_bp_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/asm/mmu_defs_asm.h Normal file
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#ifndef __mmu_defs_asm_h
#define __mmu_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/mmu/doc/mmu_regs.r
* id: mmu_regs.r,v 1.12 2004/05/06 13:48:45 mikaeln Exp
* last modfied: Mon Apr 11 17:03:20 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r
* id: $Id: mmu_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_mm_cfg, scope mmu, type rw */
#define reg_mmu_rw_mm_cfg___seg_0___lsb 0
#define reg_mmu_rw_mm_cfg___seg_0___width 1
#define reg_mmu_rw_mm_cfg___seg_0___bit 0
#define reg_mmu_rw_mm_cfg___seg_1___lsb 1
#define reg_mmu_rw_mm_cfg___seg_1___width 1
#define reg_mmu_rw_mm_cfg___seg_1___bit 1
#define reg_mmu_rw_mm_cfg___seg_2___lsb 2
#define reg_mmu_rw_mm_cfg___seg_2___width 1
#define reg_mmu_rw_mm_cfg___seg_2___bit 2
#define reg_mmu_rw_mm_cfg___seg_3___lsb 3
#define reg_mmu_rw_mm_cfg___seg_3___width 1
#define reg_mmu_rw_mm_cfg___seg_3___bit 3
#define reg_mmu_rw_mm_cfg___seg_4___lsb 4
#define reg_mmu_rw_mm_cfg___seg_4___width 1
#define reg_mmu_rw_mm_cfg___seg_4___bit 4
#define reg_mmu_rw_mm_cfg___seg_5___lsb 5
#define reg_mmu_rw_mm_cfg___seg_5___width 1
#define reg_mmu_rw_mm_cfg___seg_5___bit 5
#define reg_mmu_rw_mm_cfg___seg_6___lsb 6
#define reg_mmu_rw_mm_cfg___seg_6___width 1
#define reg_mmu_rw_mm_cfg___seg_6___bit 6
#define reg_mmu_rw_mm_cfg___seg_7___lsb 7
#define reg_mmu_rw_mm_cfg___seg_7___width 1
#define reg_mmu_rw_mm_cfg___seg_7___bit 7
#define reg_mmu_rw_mm_cfg___seg_8___lsb 8
#define reg_mmu_rw_mm_cfg___seg_8___width 1
#define reg_mmu_rw_mm_cfg___seg_8___bit 8
#define reg_mmu_rw_mm_cfg___seg_9___lsb 9
#define reg_mmu_rw_mm_cfg___seg_9___width 1
#define reg_mmu_rw_mm_cfg___seg_9___bit 9
#define reg_mmu_rw_mm_cfg___seg_a___lsb 10
#define reg_mmu_rw_mm_cfg___seg_a___width 1
#define reg_mmu_rw_mm_cfg___seg_a___bit 10
#define reg_mmu_rw_mm_cfg___seg_b___lsb 11
#define reg_mmu_rw_mm_cfg___seg_b___width 1
#define reg_mmu_rw_mm_cfg___seg_b___bit 11
#define reg_mmu_rw_mm_cfg___seg_c___lsb 12
#define reg_mmu_rw_mm_cfg___seg_c___width 1
#define reg_mmu_rw_mm_cfg___seg_c___bit 12
#define reg_mmu_rw_mm_cfg___seg_d___lsb 13
#define reg_mmu_rw_mm_cfg___seg_d___width 1
#define reg_mmu_rw_mm_cfg___seg_d___bit 13
#define reg_mmu_rw_mm_cfg___seg_e___lsb 14
#define reg_mmu_rw_mm_cfg___seg_e___width 1
#define reg_mmu_rw_mm_cfg___seg_e___bit 14
#define reg_mmu_rw_mm_cfg___seg_f___lsb 15
#define reg_mmu_rw_mm_cfg___seg_f___width 1
#define reg_mmu_rw_mm_cfg___seg_f___bit 15
#define reg_mmu_rw_mm_cfg___inv___lsb 16
#define reg_mmu_rw_mm_cfg___inv___width 1
#define reg_mmu_rw_mm_cfg___inv___bit 16
#define reg_mmu_rw_mm_cfg___ex___lsb 17
#define reg_mmu_rw_mm_cfg___ex___width 1
#define reg_mmu_rw_mm_cfg___ex___bit 17
#define reg_mmu_rw_mm_cfg___acc___lsb 18
#define reg_mmu_rw_mm_cfg___acc___width 1
#define reg_mmu_rw_mm_cfg___acc___bit 18
#define reg_mmu_rw_mm_cfg___we___lsb 19
#define reg_mmu_rw_mm_cfg___we___width 1
#define reg_mmu_rw_mm_cfg___we___bit 19
#define reg_mmu_rw_mm_cfg_offset 0
/* Register rw_mm_kbase_lo, scope mmu, type rw */
#define reg_mmu_rw_mm_kbase_lo___base_0___lsb 0
#define reg_mmu_rw_mm_kbase_lo___base_0___width 4
#define reg_mmu_rw_mm_kbase_lo___base_1___lsb 4
#define reg_mmu_rw_mm_kbase_lo___base_1___width 4
#define reg_mmu_rw_mm_kbase_lo___base_2___lsb 8
#define reg_mmu_rw_mm_kbase_lo___base_2___width 4
#define reg_mmu_rw_mm_kbase_lo___base_3___lsb 12
#define reg_mmu_rw_mm_kbase_lo___base_3___width 4
#define reg_mmu_rw_mm_kbase_lo___base_4___lsb 16
#define reg_mmu_rw_mm_kbase_lo___base_4___width 4
#define reg_mmu_rw_mm_kbase_lo___base_5___lsb 20
#define reg_mmu_rw_mm_kbase_lo___base_5___width 4
#define reg_mmu_rw_mm_kbase_lo___base_6___lsb 24
#define reg_mmu_rw_mm_kbase_lo___base_6___width 4
#define reg_mmu_rw_mm_kbase_lo___base_7___lsb 28
#define reg_mmu_rw_mm_kbase_lo___base_7___width 4
#define reg_mmu_rw_mm_kbase_lo_offset 4
/* Register rw_mm_kbase_hi, scope mmu, type rw */
#define reg_mmu_rw_mm_kbase_hi___base_8___lsb 0
#define reg_mmu_rw_mm_kbase_hi___base_8___width 4
#define reg_mmu_rw_mm_kbase_hi___base_9___lsb 4
#define reg_mmu_rw_mm_kbase_hi___base_9___width 4
#define reg_mmu_rw_mm_kbase_hi___base_a___lsb 8
#define reg_mmu_rw_mm_kbase_hi___base_a___width 4
#define reg_mmu_rw_mm_kbase_hi___base_b___lsb 12
#define reg_mmu_rw_mm_kbase_hi___base_b___width 4
#define reg_mmu_rw_mm_kbase_hi___base_c___lsb 16
#define reg_mmu_rw_mm_kbase_hi___base_c___width 4
#define reg_mmu_rw_mm_kbase_hi___base_d___lsb 20
#define reg_mmu_rw_mm_kbase_hi___base_d___width 4
#define reg_mmu_rw_mm_kbase_hi___base_e___lsb 24
#define reg_mmu_rw_mm_kbase_hi___base_e___width 4
#define reg_mmu_rw_mm_kbase_hi___base_f___lsb 28
#define reg_mmu_rw_mm_kbase_hi___base_f___width 4
#define reg_mmu_rw_mm_kbase_hi_offset 8
/* Register r_mm_cause, scope mmu, type r */
#define reg_mmu_r_mm_cause___pid___lsb 0
#define reg_mmu_r_mm_cause___pid___width 8
#define reg_mmu_r_mm_cause___op___lsb 8
#define reg_mmu_r_mm_cause___op___width 2
#define reg_mmu_r_mm_cause___vpn___lsb 13
#define reg_mmu_r_mm_cause___vpn___width 19
#define reg_mmu_r_mm_cause_offset 12
/* Register rw_mm_tlb_sel, scope mmu, type rw */
#define reg_mmu_rw_mm_tlb_sel___idx___lsb 0
#define reg_mmu_rw_mm_tlb_sel___idx___width 4
#define reg_mmu_rw_mm_tlb_sel___set___lsb 4
#define reg_mmu_rw_mm_tlb_sel___set___width 2
#define reg_mmu_rw_mm_tlb_sel_offset 16
/* Register rw_mm_tlb_lo, scope mmu, type rw */
#define reg_mmu_rw_mm_tlb_lo___x___lsb 0
#define reg_mmu_rw_mm_tlb_lo___x___width 1
#define reg_mmu_rw_mm_tlb_lo___x___bit 0
#define reg_mmu_rw_mm_tlb_lo___w___lsb 1
#define reg_mmu_rw_mm_tlb_lo___w___width 1
#define reg_mmu_rw_mm_tlb_lo___w___bit 1
#define reg_mmu_rw_mm_tlb_lo___k___lsb 2
#define reg_mmu_rw_mm_tlb_lo___k___width 1
#define reg_mmu_rw_mm_tlb_lo___k___bit 2
#define reg_mmu_rw_mm_tlb_lo___v___lsb 3
#define reg_mmu_rw_mm_tlb_lo___v___width 1
#define reg_mmu_rw_mm_tlb_lo___v___bit 3
#define reg_mmu_rw_mm_tlb_lo___g___lsb 4
#define reg_mmu_rw_mm_tlb_lo___g___width 1
#define reg_mmu_rw_mm_tlb_lo___g___bit 4
#define reg_mmu_rw_mm_tlb_lo___pfn___lsb 13
#define reg_mmu_rw_mm_tlb_lo___pfn___width 19
#define reg_mmu_rw_mm_tlb_lo_offset 20
/* Register rw_mm_tlb_hi, scope mmu, type rw */
#define reg_mmu_rw_mm_tlb_hi___pid___lsb 0
#define reg_mmu_rw_mm_tlb_hi___pid___width 8
#define reg_mmu_rw_mm_tlb_hi___vpn___lsb 13
#define reg_mmu_rw_mm_tlb_hi___vpn___width 19
#define reg_mmu_rw_mm_tlb_hi_offset 24
/* Constants */
#define regk_mmu_execute 0x00000000
#define regk_mmu_flush 0x00000003
#define regk_mmu_linear 0x00000001
#define regk_mmu_no 0x00000000
#define regk_mmu_off 0x00000000
#define regk_mmu_on 0x00000001
#define regk_mmu_page 0x00000000
#define regk_mmu_read 0x00000001
#define regk_mmu_write 0x00000002
#define regk_mmu_yes 0x00000001
#endif /* __mmu_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/asm/mmu_supp_reg.h Normal file
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#define RW_MM_CFG 0
#define RW_MM_KBASE_LO 1
#define RW_MM_KBASE_HI 2
#define R_MM_CAUSE 3
#define RW_MM_TLB_SEL 4
#define RW_MM_TLB_LO 5
#define RW_MM_TLB_HI 6

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arch/cris/include/arch-v32/arch/hwregs/asm/rt_trace_defs_asm.h Normal file
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#ifndef __rt_trace_defs_asm_h
#define __rt_trace_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/rt_trace/rtl/rt_regs.r
* id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp
* last modfied: Mon Apr 11 16:09:14 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/rt_trace_defs_asm.h ../../inst/rt_trace/rtl/rt_regs.r
* id: $Id: rt_trace_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_cfg, scope rt_trace, type rw */
#define reg_rt_trace_rw_cfg___en___lsb 0
#define reg_rt_trace_rw_cfg___en___width 1
#define reg_rt_trace_rw_cfg___en___bit 0
#define reg_rt_trace_rw_cfg___mode___lsb 1
#define reg_rt_trace_rw_cfg___mode___width 1
#define reg_rt_trace_rw_cfg___mode___bit 1
#define reg_rt_trace_rw_cfg___owner___lsb 2
#define reg_rt_trace_rw_cfg___owner___width 1
#define reg_rt_trace_rw_cfg___owner___bit 2
#define reg_rt_trace_rw_cfg___wp___lsb 3
#define reg_rt_trace_rw_cfg___wp___width 1
#define reg_rt_trace_rw_cfg___wp___bit 3
#define reg_rt_trace_rw_cfg___stall___lsb 4
#define reg_rt_trace_rw_cfg___stall___width 1
#define reg_rt_trace_rw_cfg___stall___bit 4
#define reg_rt_trace_rw_cfg___wp_start___lsb 8
#define reg_rt_trace_rw_cfg___wp_start___width 7
#define reg_rt_trace_rw_cfg___wp_stop___lsb 16
#define reg_rt_trace_rw_cfg___wp_stop___width 7
#define reg_rt_trace_rw_cfg_offset 0
/* Register rw_tap_ctrl, scope rt_trace, type rw */
#define reg_rt_trace_rw_tap_ctrl___ack_data___lsb 0
#define reg_rt_trace_rw_tap_ctrl___ack_data___width 1
#define reg_rt_trace_rw_tap_ctrl___ack_data___bit 0
#define reg_rt_trace_rw_tap_ctrl___ack_guru___lsb 1
#define reg_rt_trace_rw_tap_ctrl___ack_guru___width 1
#define reg_rt_trace_rw_tap_ctrl___ack_guru___bit 1
#define reg_rt_trace_rw_tap_ctrl_offset 4
/* Register r_tap_stat, scope rt_trace, type r */
#define reg_rt_trace_r_tap_stat___dav___lsb 0
#define reg_rt_trace_r_tap_stat___dav___width 1
#define reg_rt_trace_r_tap_stat___dav___bit 0
#define reg_rt_trace_r_tap_stat___empty___lsb 1
#define reg_rt_trace_r_tap_stat___empty___width 1
#define reg_rt_trace_r_tap_stat___empty___bit 1
#define reg_rt_trace_r_tap_stat_offset 8
/* Register rw_tap_data, scope rt_trace, type rw */
#define reg_rt_trace_rw_tap_data_offset 12
/* Register rw_tap_hdata, scope rt_trace, type rw */
#define reg_rt_trace_rw_tap_hdata___op___lsb 0
#define reg_rt_trace_rw_tap_hdata___op___width 4
#define reg_rt_trace_rw_tap_hdata___sub_op___lsb 4
#define reg_rt_trace_rw_tap_hdata___sub_op___width 4
#define reg_rt_trace_rw_tap_hdata_offset 16
/* Register r_redir, scope rt_trace, type r */
#define reg_rt_trace_r_redir_offset 20
/* Constants */
#define regk_rt_trace_brk 0x0000000c
#define regk_rt_trace_dbg 0x00000003
#define regk_rt_trace_dbgdi 0x00000004
#define regk_rt_trace_dbgdo 0x00000005
#define regk_rt_trace_gmode 0x00000000
#define regk_rt_trace_no 0x00000000
#define regk_rt_trace_nop 0x00000000
#define regk_rt_trace_normal 0x00000000
#define regk_rt_trace_rdmem 0x00000007
#define regk_rt_trace_rdmemb 0x00000009
#define regk_rt_trace_rdpreg 0x00000002
#define regk_rt_trace_rdreg 0x00000001
#define regk_rt_trace_rdsreg 0x00000003
#define regk_rt_trace_redir 0x00000006
#define regk_rt_trace_ret 0x0000000b
#define regk_rt_trace_rw_cfg_default 0x00000000
#define regk_rt_trace_trcfg 0x00000001
#define regk_rt_trace_wp 0x00000001
#define regk_rt_trace_wp0 0x00000001
#define regk_rt_trace_wp1 0x00000002
#define regk_rt_trace_wp2 0x00000004
#define regk_rt_trace_wp3 0x00000008
#define regk_rt_trace_wp4 0x00000010
#define regk_rt_trace_wp5 0x00000020
#define regk_rt_trace_wp6 0x00000040
#define regk_rt_trace_wrmem 0x00000008
#define regk_rt_trace_wrmemb 0x0000000a
#define regk_rt_trace_wrpreg 0x00000005
#define regk_rt_trace_wrreg 0x00000004
#define regk_rt_trace_wrsreg 0x00000006
#define regk_rt_trace_yes 0x00000001
#endif /* __rt_trace_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/asm/ser_defs_asm.h Normal file
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#ifndef __ser_defs_asm_h
#define __ser_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/ser/rtl/ser_regs.r
* id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp
* last modfied: Mon Apr 11 16:09:21 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ser_defs_asm.h ../../inst/ser/rtl/ser_regs.r
* id: $Id: ser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_tr_ctrl, scope ser, type rw */
#define reg_ser_rw_tr_ctrl___base_freq___lsb 0
#define reg_ser_rw_tr_ctrl___base_freq___width 3
#define reg_ser_rw_tr_ctrl___en___lsb 3
#define reg_ser_rw_tr_ctrl___en___width 1
#define reg_ser_rw_tr_ctrl___en___bit 3
#define reg_ser_rw_tr_ctrl___par___lsb 4
#define reg_ser_rw_tr_ctrl___par___width 2
#define reg_ser_rw_tr_ctrl___par_en___lsb 6
#define reg_ser_rw_tr_ctrl___par_en___width 1
#define reg_ser_rw_tr_ctrl___par_en___bit 6
#define reg_ser_rw_tr_ctrl___data_bits___lsb 7
#define reg_ser_rw_tr_ctrl___data_bits___width 1
#define reg_ser_rw_tr_ctrl___data_bits___bit 7
#define reg_ser_rw_tr_ctrl___stop_bits___lsb 8
#define reg_ser_rw_tr_ctrl___stop_bits___width 1
#define reg_ser_rw_tr_ctrl___stop_bits___bit 8
#define reg_ser_rw_tr_ctrl___stop___lsb 9
#define reg_ser_rw_tr_ctrl___stop___width 1
#define reg_ser_rw_tr_ctrl___stop___bit 9
#define reg_ser_rw_tr_ctrl___rts_delay___lsb 10
#define reg_ser_rw_tr_ctrl___rts_delay___width 3
#define reg_ser_rw_tr_ctrl___rts_setup___lsb 13
#define reg_ser_rw_tr_ctrl___rts_setup___width 1
#define reg_ser_rw_tr_ctrl___rts_setup___bit 13
#define reg_ser_rw_tr_ctrl___auto_rts___lsb 14
#define reg_ser_rw_tr_ctrl___auto_rts___width 1
#define reg_ser_rw_tr_ctrl___auto_rts___bit 14
#define reg_ser_rw_tr_ctrl___txd___lsb 15
#define reg_ser_rw_tr_ctrl___txd___width 1
#define reg_ser_rw_tr_ctrl___txd___bit 15
#define reg_ser_rw_tr_ctrl___auto_cts___lsb 16
#define reg_ser_rw_tr_ctrl___auto_cts___width 1
#define reg_ser_rw_tr_ctrl___auto_cts___bit 16
#define reg_ser_rw_tr_ctrl_offset 0
/* Register rw_tr_dma_en, scope ser, type rw */
#define reg_ser_rw_tr_dma_en___en___lsb 0
#define reg_ser_rw_tr_dma_en___en___width 1
#define reg_ser_rw_tr_dma_en___en___bit 0
#define reg_ser_rw_tr_dma_en_offset 4
/* Register rw_rec_ctrl, scope ser, type rw */
#define reg_ser_rw_rec_ctrl___base_freq___lsb 0
#define reg_ser_rw_rec_ctrl___base_freq___width 3
#define reg_ser_rw_rec_ctrl___en___lsb 3
#define reg_ser_rw_rec_ctrl___en___width 1
#define reg_ser_rw_rec_ctrl___en___bit 3
#define reg_ser_rw_rec_ctrl___par___lsb 4
#define reg_ser_rw_rec_ctrl___par___width 2
#define reg_ser_rw_rec_ctrl___par_en___lsb 6
#define reg_ser_rw_rec_ctrl___par_en___width 1
#define reg_ser_rw_rec_ctrl___par_en___bit 6
#define reg_ser_rw_rec_ctrl___data_bits___lsb 7
#define reg_ser_rw_rec_ctrl___data_bits___width 1
#define reg_ser_rw_rec_ctrl___data_bits___bit 7
#define reg_ser_rw_rec_ctrl___dma_mode___lsb 8
#define reg_ser_rw_rec_ctrl___dma_mode___width 1
#define reg_ser_rw_rec_ctrl___dma_mode___bit 8
#define reg_ser_rw_rec_ctrl___dma_err___lsb 9
#define reg_ser_rw_rec_ctrl___dma_err___width 1
#define reg_ser_rw_rec_ctrl___dma_err___bit 9
#define reg_ser_rw_rec_ctrl___sampling___lsb 10
#define reg_ser_rw_rec_ctrl___sampling___width 1
#define reg_ser_rw_rec_ctrl___sampling___bit 10
#define reg_ser_rw_rec_ctrl___timeout___lsb 11
#define reg_ser_rw_rec_ctrl___timeout___width 3
#define reg_ser_rw_rec_ctrl___auto_eop___lsb 14
#define reg_ser_rw_rec_ctrl___auto_eop___width 1
#define reg_ser_rw_rec_ctrl___auto_eop___bit 14
#define reg_ser_rw_rec_ctrl___half_duplex___lsb 15
#define reg_ser_rw_rec_ctrl___half_duplex___width 1
#define reg_ser_rw_rec_ctrl___half_duplex___bit 15
#define reg_ser_rw_rec_ctrl___rts_n___lsb 16
#define reg_ser_rw_rec_ctrl___rts_n___width 1
#define reg_ser_rw_rec_ctrl___rts_n___bit 16
#define reg_ser_rw_rec_ctrl___loopback___lsb 17
#define reg_ser_rw_rec_ctrl___loopback___width 1
#define reg_ser_rw_rec_ctrl___loopback___bit 17
#define reg_ser_rw_rec_ctrl_offset 8
/* Register rw_tr_baud_div, scope ser, type rw */
#define reg_ser_rw_tr_baud_div___div___lsb 0
#define reg_ser_rw_tr_baud_div___div___width 16
#define reg_ser_rw_tr_baud_div_offset 12
/* Register rw_rec_baud_div, scope ser, type rw */
#define reg_ser_rw_rec_baud_div___div___lsb 0
#define reg_ser_rw_rec_baud_div___div___width 16
#define reg_ser_rw_rec_baud_div_offset 16
/* Register rw_xoff, scope ser, type rw */
#define reg_ser_rw_xoff___chr___lsb 0
#define reg_ser_rw_xoff___chr___width 8
#define reg_ser_rw_xoff___automatic___lsb 8
#define reg_ser_rw_xoff___automatic___width 1
#define reg_ser_rw_xoff___automatic___bit 8
#define reg_ser_rw_xoff_offset 20
/* Register rw_xoff_clr, scope ser, type rw */
#define reg_ser_rw_xoff_clr___clr___lsb 0
#define reg_ser_rw_xoff_clr___clr___width 1
#define reg_ser_rw_xoff_clr___clr___bit 0
#define reg_ser_rw_xoff_clr_offset 24
/* Register rw_dout, scope ser, type rw */
#define reg_ser_rw_dout___data___lsb 0
#define reg_ser_rw_dout___data___width 8
#define reg_ser_rw_dout_offset 28
/* Register rs_stat_din, scope ser, type rs */
#define reg_ser_rs_stat_din___data___lsb 0
#define reg_ser_rs_stat_din___data___width 8
#define reg_ser_rs_stat_din___dav___lsb 16
#define reg_ser_rs_stat_din___dav___width 1
#define reg_ser_rs_stat_din___dav___bit 16
#define reg_ser_rs_stat_din___framing_err___lsb 17
#define reg_ser_rs_stat_din___framing_err___width 1
#define reg_ser_rs_stat_din___framing_err___bit 17
#define reg_ser_rs_stat_din___par_err___lsb 18
#define reg_ser_rs_stat_din___par_err___width 1
#define reg_ser_rs_stat_din___par_err___bit 18
#define reg_ser_rs_stat_din___orun___lsb 19
#define reg_ser_rs_stat_din___orun___width 1
#define reg_ser_rs_stat_din___orun___bit 19
#define reg_ser_rs_stat_din___rec_err___lsb 20
#define reg_ser_rs_stat_din___rec_err___width 1
#define reg_ser_rs_stat_din___rec_err___bit 20
#define reg_ser_rs_stat_din___rxd___lsb 21
#define reg_ser_rs_stat_din___rxd___width 1
#define reg_ser_rs_stat_din___rxd___bit 21
#define reg_ser_rs_stat_din___tr_idle___lsb 22
#define reg_ser_rs_stat_din___tr_idle___width 1
#define reg_ser_rs_stat_din___tr_idle___bit 22
#define reg_ser_rs_stat_din___tr_empty___lsb 23
#define reg_ser_rs_stat_din___tr_empty___width 1
#define reg_ser_rs_stat_din___tr_empty___bit 23
#define reg_ser_rs_stat_din___tr_rdy___lsb 24
#define reg_ser_rs_stat_din___tr_rdy___width 1
#define reg_ser_rs_stat_din___tr_rdy___bit 24
#define reg_ser_rs_stat_din___cts_n___lsb 25
#define reg_ser_rs_stat_din___cts_n___width 1
#define reg_ser_rs_stat_din___cts_n___bit 25
#define reg_ser_rs_stat_din___xoff_detect___lsb 26
#define reg_ser_rs_stat_din___xoff_detect___width 1
#define reg_ser_rs_stat_din___xoff_detect___bit 26
#define reg_ser_rs_stat_din___rts_n___lsb 27
#define reg_ser_rs_stat_din___rts_n___width 1
#define reg_ser_rs_stat_din___rts_n___bit 27
#define reg_ser_rs_stat_din___txd___lsb 28
#define reg_ser_rs_stat_din___txd___width 1
#define reg_ser_rs_stat_din___txd___bit 28
#define reg_ser_rs_stat_din_offset 32
/* Register r_stat_din, scope ser, type r */
#define reg_ser_r_stat_din___data___lsb 0
#define reg_ser_r_stat_din___data___width 8
#define reg_ser_r_stat_din___dav___lsb 16
#define reg_ser_r_stat_din___dav___width 1
#define reg_ser_r_stat_din___dav___bit 16
#define reg_ser_r_stat_din___framing_err___lsb 17
#define reg_ser_r_stat_din___framing_err___width 1
#define reg_ser_r_stat_din___framing_err___bit 17
#define reg_ser_r_stat_din___par_err___lsb 18
#define reg_ser_r_stat_din___par_err___width 1
#define reg_ser_r_stat_din___par_err___bit 18
#define reg_ser_r_stat_din___orun___lsb 19
#define reg_ser_r_stat_din___orun___width 1
#define reg_ser_r_stat_din___orun___bit 19
#define reg_ser_r_stat_din___rec_err___lsb 20
#define reg_ser_r_stat_din___rec_err___width 1
#define reg_ser_r_stat_din___rec_err___bit 20
#define reg_ser_r_stat_din___rxd___lsb 21
#define reg_ser_r_stat_din___rxd___width 1
#define reg_ser_r_stat_din___rxd___bit 21
#define reg_ser_r_stat_din___tr_idle___lsb 22
#define reg_ser_r_stat_din___tr_idle___width 1
#define reg_ser_r_stat_din___tr_idle___bit 22
#define reg_ser_r_stat_din___tr_empty___lsb 23
#define reg_ser_r_stat_din___tr_empty___width 1
#define reg_ser_r_stat_din___tr_empty___bit 23
#define reg_ser_r_stat_din___tr_rdy___lsb 24
#define reg_ser_r_stat_din___tr_rdy___width 1
#define reg_ser_r_stat_din___tr_rdy___bit 24
#define reg_ser_r_stat_din___cts_n___lsb 25
#define reg_ser_r_stat_din___cts_n___width 1
#define reg_ser_r_stat_din___cts_n___bit 25
#define reg_ser_r_stat_din___xoff_detect___lsb 26
#define reg_ser_r_stat_din___xoff_detect___width 1
#define reg_ser_r_stat_din___xoff_detect___bit 26
#define reg_ser_r_stat_din___rts_n___lsb 27
#define reg_ser_r_stat_din___rts_n___width 1
#define reg_ser_r_stat_din___rts_n___bit 27
#define reg_ser_r_stat_din___txd___lsb 28
#define reg_ser_r_stat_din___txd___width 1
#define reg_ser_r_stat_din___txd___bit 28
#define reg_ser_r_stat_din_offset 36
/* Register rw_rec_eop, scope ser, type rw */
#define reg_ser_rw_rec_eop___set___lsb 0
#define reg_ser_rw_rec_eop___set___width 1
#define reg_ser_rw_rec_eop___set___bit 0
#define reg_ser_rw_rec_eop_offset 40
/* Register rw_intr_mask, scope ser, type rw */
#define reg_ser_rw_intr_mask___tr_rdy___lsb 0
#define reg_ser_rw_intr_mask___tr_rdy___width 1
#define reg_ser_rw_intr_mask___tr_rdy___bit 0
#define reg_ser_rw_intr_mask___tr_empty___lsb 1
#define reg_ser_rw_intr_mask___tr_empty___width 1
#define reg_ser_rw_intr_mask___tr_empty___bit 1
#define reg_ser_rw_intr_mask___tr_idle___lsb 2
#define reg_ser_rw_intr_mask___tr_idle___width 1
#define reg_ser_rw_intr_mask___tr_idle___bit 2
#define reg_ser_rw_intr_mask___dav___lsb 3
#define reg_ser_rw_intr_mask___dav___width 1
#define reg_ser_rw_intr_mask___dav___bit 3
#define reg_ser_rw_intr_mask_offset 44
/* Register rw_ack_intr, scope ser, type rw */
#define reg_ser_rw_ack_intr___tr_rdy___lsb 0
#define reg_ser_rw_ack_intr___tr_rdy___width 1
#define reg_ser_rw_ack_intr___tr_rdy___bit 0
#define reg_ser_rw_ack_intr___tr_empty___lsb 1
#define reg_ser_rw_ack_intr___tr_empty___width 1
#define reg_ser_rw_ack_intr___tr_empty___bit 1
#define reg_ser_rw_ack_intr___tr_idle___lsb 2
#define reg_ser_rw_ack_intr___tr_idle___width 1
#define reg_ser_rw_ack_intr___tr_idle___bit 2
#define reg_ser_rw_ack_intr___dav___lsb 3
#define reg_ser_rw_ack_intr___dav___width 1
#define reg_ser_rw_ack_intr___dav___bit 3
#define reg_ser_rw_ack_intr_offset 48
/* Register r_intr, scope ser, type r */
#define reg_ser_r_intr___tr_rdy___lsb 0
#define reg_ser_r_intr___tr_rdy___width 1
#define reg_ser_r_intr___tr_rdy___bit 0
#define reg_ser_r_intr___tr_empty___lsb 1
#define reg_ser_r_intr___tr_empty___width 1
#define reg_ser_r_intr___tr_empty___bit 1
#define reg_ser_r_intr___tr_idle___lsb 2
#define reg_ser_r_intr___tr_idle___width 1
#define reg_ser_r_intr___tr_idle___bit 2
#define reg_ser_r_intr___dav___lsb 3
#define reg_ser_r_intr___dav___width 1
#define reg_ser_r_intr___dav___bit 3
#define reg_ser_r_intr_offset 52
/* Register r_masked_intr, scope ser, type r */
#define reg_ser_r_masked_intr___tr_rdy___lsb 0
#define reg_ser_r_masked_intr___tr_rdy___width 1
#define reg_ser_r_masked_intr___tr_rdy___bit 0
#define reg_ser_r_masked_intr___tr_empty___lsb 1
#define reg_ser_r_masked_intr___tr_empty___width 1
#define reg_ser_r_masked_intr___tr_empty___bit 1
#define reg_ser_r_masked_intr___tr_idle___lsb 2
#define reg_ser_r_masked_intr___tr_idle___width 1
#define reg_ser_r_masked_intr___tr_idle___bit 2
#define reg_ser_r_masked_intr___dav___lsb 3
#define reg_ser_r_masked_intr___dav___width 1
#define reg_ser_r_masked_intr___dav___bit 3
#define reg_ser_r_masked_intr_offset 56
/* Constants */
#define regk_ser_active 0x00000000
#define regk_ser_bits1 0x00000000
#define regk_ser_bits2 0x00000001
#define regk_ser_bits7 0x00000001
#define regk_ser_bits8 0x00000000
#define regk_ser_del0_5 0x00000000
#define regk_ser_del1 0x00000001
#define regk_ser_del1_5 0x00000002
#define regk_ser_del2 0x00000003
#define regk_ser_del2_5 0x00000004
#define regk_ser_del3 0x00000005
#define regk_ser_del3_5 0x00000006
#define regk_ser_del4 0x00000007
#define regk_ser_even 0x00000000
#define regk_ser_ext 0x00000001
#define regk_ser_f100 0x00000007
#define regk_ser_f29_493 0x00000004
#define regk_ser_f32 0x00000005
#define regk_ser_f32_768 0x00000006
#define regk_ser_ignore 0x00000001
#define regk_ser_inactive 0x00000001
#define regk_ser_majority 0x00000001
#define regk_ser_mark 0x00000002
#define regk_ser_middle 0x00000000
#define regk_ser_no 0x00000000
#define regk_ser_odd 0x00000001
#define regk_ser_off 0x00000000
#define regk_ser_rw_intr_mask_default 0x00000000
#define regk_ser_rw_rec_baud_div_default 0x00000000
#define regk_ser_rw_rec_ctrl_default 0x00010000
#define regk_ser_rw_tr_baud_div_default 0x00000000
#define regk_ser_rw_tr_ctrl_default 0x00008000
#define regk_ser_rw_tr_dma_en_default 0x00000000
#define regk_ser_rw_xoff_default 0x00000000
#define regk_ser_space 0x00000003
#define regk_ser_stop 0x00000000
#define regk_ser_yes 0x00000001
#endif /* __ser_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/asm/sser_defs_asm.h Normal file
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#ifndef __sser_defs_asm_h
#define __sser_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/syncser/rtl/sser_regs.r
* id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp
* last modfied: Mon Apr 11 16:09:48 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r
* id: $Id: sser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_cfg, scope sser, type rw */
#define reg_sser_rw_cfg___clk_div___lsb 0
#define reg_sser_rw_cfg___clk_div___width 16
#define reg_sser_rw_cfg___base_freq___lsb 16
#define reg_sser_rw_cfg___base_freq___width 3
#define reg_sser_rw_cfg___gate_clk___lsb 19
#define reg_sser_rw_cfg___gate_clk___width 1
#define reg_sser_rw_cfg___gate_clk___bit 19
#define reg_sser_rw_cfg___clkgate_ctrl___lsb 20
#define reg_sser_rw_cfg___clkgate_ctrl___width 1
#define reg_sser_rw_cfg___clkgate_ctrl___bit 20
#define reg_sser_rw_cfg___clkgate_in___lsb 21
#define reg_sser_rw_cfg___clkgate_in___width 1
#define reg_sser_rw_cfg___clkgate_in___bit 21
#define reg_sser_rw_cfg___clk_dir___lsb 22
#define reg_sser_rw_cfg___clk_dir___width 1
#define reg_sser_rw_cfg___clk_dir___bit 22
#define reg_sser_rw_cfg___clk_od_mode___lsb 23
#define reg_sser_rw_cfg___clk_od_mode___width 1
#define reg_sser_rw_cfg___clk_od_mode___bit 23
#define reg_sser_rw_cfg___out_clk_pol___lsb 24
#define reg_sser_rw_cfg___out_clk_pol___width 1
#define reg_sser_rw_cfg___out_clk_pol___bit 24
#define reg_sser_rw_cfg___out_clk_src___lsb 25
#define reg_sser_rw_cfg___out_clk_src___width 2
#define reg_sser_rw_cfg___clk_in_sel___lsb 27
#define reg_sser_rw_cfg___clk_in_sel___width 1
#define reg_sser_rw_cfg___clk_in_sel___bit 27
#define reg_sser_rw_cfg___hold_pol___lsb 28
#define reg_sser_rw_cfg___hold_pol___width 1
#define reg_sser_rw_cfg___hold_pol___bit 28
#define reg_sser_rw_cfg___prepare___lsb 29
#define reg_sser_rw_cfg___prepare___width 1
#define reg_sser_rw_cfg___prepare___bit 29
#define reg_sser_rw_cfg___en___lsb 30
#define reg_sser_rw_cfg___en___width 1
#define reg_sser_rw_cfg___en___bit 30
#define reg_sser_rw_cfg_offset 0
/* Register rw_frm_cfg, scope sser, type rw */
#define reg_sser_rw_frm_cfg___wordrate___lsb 0
#define reg_sser_rw_frm_cfg___wordrate___width 10
#define reg_sser_rw_frm_cfg___rec_delay___lsb 10
#define reg_sser_rw_frm_cfg___rec_delay___width 3
#define reg_sser_rw_frm_cfg___tr_delay___lsb 13
#define reg_sser_rw_frm_cfg___tr_delay___width 3
#define reg_sser_rw_frm_cfg___early_wend___lsb 16
#define reg_sser_rw_frm_cfg___early_wend___width 1
#define reg_sser_rw_frm_cfg___early_wend___bit 16
#define reg_sser_rw_frm_cfg___level___lsb 17
#define reg_sser_rw_frm_cfg___level___width 2
#define reg_sser_rw_frm_cfg___type___lsb 19
#define reg_sser_rw_frm_cfg___type___width 1
#define reg_sser_rw_frm_cfg___type___bit 19
#define reg_sser_rw_frm_cfg___clk_pol___lsb 20
#define reg_sser_rw_frm_cfg___clk_pol___width 1
#define reg_sser_rw_frm_cfg___clk_pol___bit 20
#define reg_sser_rw_frm_cfg___fr_in_rxclk___lsb 21
#define reg_sser_rw_frm_cfg___fr_in_rxclk___width 1
#define reg_sser_rw_frm_cfg___fr_in_rxclk___bit 21
#define reg_sser_rw_frm_cfg___clk_src___lsb 22
#define reg_sser_rw_frm_cfg___clk_src___width 1
#define reg_sser_rw_frm_cfg___clk_src___bit 22
#define reg_sser_rw_frm_cfg___out_off___lsb 23
#define reg_sser_rw_frm_cfg___out_off___width 1
#define reg_sser_rw_frm_cfg___out_off___bit 23
#define reg_sser_rw_frm_cfg___out_on___lsb 24
#define reg_sser_rw_frm_cfg___out_on___width 1
#define reg_sser_rw_frm_cfg___out_on___bit 24
#define reg_sser_rw_frm_cfg___frame_pin_dir___lsb 25
#define reg_sser_rw_frm_cfg___frame_pin_dir___width 1
#define reg_sser_rw_frm_cfg___frame_pin_dir___bit 25
#define reg_sser_rw_frm_cfg___frame_pin_use___lsb 26
#define reg_sser_rw_frm_cfg___frame_pin_use___width 2
#define reg_sser_rw_frm_cfg___status_pin_dir___lsb 28
#define reg_sser_rw_frm_cfg___status_pin_dir___width 1
#define reg_sser_rw_frm_cfg___status_pin_dir___bit 28
#define reg_sser_rw_frm_cfg___status_pin_use___lsb 29
#define reg_sser_rw_frm_cfg___status_pin_use___width 2
#define reg_sser_rw_frm_cfg_offset 4
/* Register rw_tr_cfg, scope sser, type rw */
#define reg_sser_rw_tr_cfg___tr_en___lsb 0
#define reg_sser_rw_tr_cfg___tr_en___width 1
#define reg_sser_rw_tr_cfg___tr_en___bit 0
#define reg_sser_rw_tr_cfg___stop___lsb 1
#define reg_sser_rw_tr_cfg___stop___width 1
#define reg_sser_rw_tr_cfg___stop___bit 1
#define reg_sser_rw_tr_cfg___urun_stop___lsb 2
#define reg_sser_rw_tr_cfg___urun_stop___width 1
#define reg_sser_rw_tr_cfg___urun_stop___bit 2
#define reg_sser_rw_tr_cfg___eop_stop___lsb 3
#define reg_sser_rw_tr_cfg___eop_stop___width 1
#define reg_sser_rw_tr_cfg___eop_stop___bit 3
#define reg_sser_rw_tr_cfg___sample_size___lsb 4
#define reg_sser_rw_tr_cfg___sample_size___width 6
#define reg_sser_rw_tr_cfg___sh_dir___lsb 10
#define reg_sser_rw_tr_cfg___sh_dir___width 1
#define reg_sser_rw_tr_cfg___sh_dir___bit 10
#define reg_sser_rw_tr_cfg___clk_pol___lsb 11
#define reg_sser_rw_tr_cfg___clk_pol___width 1
#define reg_sser_rw_tr_cfg___clk_pol___bit 11
#define reg_sser_rw_tr_cfg___clk_src___lsb 12
#define reg_sser_rw_tr_cfg___clk_src___width 1
#define reg_sser_rw_tr_cfg___clk_src___bit 12
#define reg_sser_rw_tr_cfg___use_dma___lsb 13
#define reg_sser_rw_tr_cfg___use_dma___width 1
#define reg_sser_rw_tr_cfg___use_dma___bit 13
#define reg_sser_rw_tr_cfg___mode___lsb 14
#define reg_sser_rw_tr_cfg___mode___width 2
#define reg_sser_rw_tr_cfg___frm_src___lsb 16
#define reg_sser_rw_tr_cfg___frm_src___width 1
#define reg_sser_rw_tr_cfg___frm_src___bit 16
#define reg_sser_rw_tr_cfg___use60958___lsb 17
#define reg_sser_rw_tr_cfg___use60958___width 1
#define reg_sser_rw_tr_cfg___use60958___bit 17
#define reg_sser_rw_tr_cfg___iec60958_ckdiv___lsb 18
#define reg_sser_rw_tr_cfg___iec60958_ckdiv___width 2
#define reg_sser_rw_tr_cfg___rate_ctrl___lsb 20
#define reg_sser_rw_tr_cfg___rate_ctrl___width 1
#define reg_sser_rw_tr_cfg___rate_ctrl___bit 20
#define reg_sser_rw_tr_cfg___use_md___lsb 21
#define reg_sser_rw_tr_cfg___use_md___width 1
#define reg_sser_rw_tr_cfg___use_md___bit 21
#define reg_sser_rw_tr_cfg___dual_i2s___lsb 22
#define reg_sser_rw_tr_cfg___dual_i2s___width 1
#define reg_sser_rw_tr_cfg___dual_i2s___bit 22
#define reg_sser_rw_tr_cfg___data_pin_use___lsb 23
#define reg_sser_rw_tr_cfg___data_pin_use___width 2
#define reg_sser_rw_tr_cfg___od_mode___lsb 25
#define reg_sser_rw_tr_cfg___od_mode___width 1
#define reg_sser_rw_tr_cfg___od_mode___bit 25
#define reg_sser_rw_tr_cfg___bulk_wspace___lsb 26
#define reg_sser_rw_tr_cfg___bulk_wspace___width 2
#define reg_sser_rw_tr_cfg_offset 8
/* Register rw_rec_cfg, scope sser, type rw */
#define reg_sser_rw_rec_cfg___rec_en___lsb 0
#define reg_sser_rw_rec_cfg___rec_en___width 1
#define reg_sser_rw_rec_cfg___rec_en___bit 0
#define reg_sser_rw_rec_cfg___force_eop___lsb 1
#define reg_sser_rw_rec_cfg___force_eop___width 1
#define reg_sser_rw_rec_cfg___force_eop___bit 1
#define reg_sser_rw_rec_cfg___stop___lsb 2
#define reg_sser_rw_rec_cfg___stop___width 1
#define reg_sser_rw_rec_cfg___stop___bit 2
#define reg_sser_rw_rec_cfg___orun_stop___lsb 3
#define reg_sser_rw_rec_cfg___orun_stop___width 1
#define reg_sser_rw_rec_cfg___orun_stop___bit 3
#define reg_sser_rw_rec_cfg___eop_stop___lsb 4
#define reg_sser_rw_rec_cfg___eop_stop___width 1
#define reg_sser_rw_rec_cfg___eop_stop___bit 4
#define reg_sser_rw_rec_cfg___sample_size___lsb 5
#define reg_sser_rw_rec_cfg___sample_size___width 6
#define reg_sser_rw_rec_cfg___sh_dir___lsb 11
#define reg_sser_rw_rec_cfg___sh_dir___width 1
#define reg_sser_rw_rec_cfg___sh_dir___bit 11
#define reg_sser_rw_rec_cfg___clk_pol___lsb 12
#define reg_sser_rw_rec_cfg___clk_pol___width 1
#define reg_sser_rw_rec_cfg___clk_pol___bit 12
#define reg_sser_rw_rec_cfg___clk_src___lsb 13
#define reg_sser_rw_rec_cfg___clk_src___width 1
#define reg_sser_rw_rec_cfg___clk_src___bit 13
#define reg_sser_rw_rec_cfg___use_dma___lsb 14
#define reg_sser_rw_rec_cfg___use_dma___width 1
#define reg_sser_rw_rec_cfg___use_dma___bit 14
#define reg_sser_rw_rec_cfg___mode___lsb 15
#define reg_sser_rw_rec_cfg___mode___width 2
#define reg_sser_rw_rec_cfg___frm_src___lsb 17
#define reg_sser_rw_rec_cfg___frm_src___width 2
#define reg_sser_rw_rec_cfg___use60958___lsb 19
#define reg_sser_rw_rec_cfg___use60958___width 1
#define reg_sser_rw_rec_cfg___use60958___bit 19
#define reg_sser_rw_rec_cfg___iec60958_ui_len___lsb 20
#define reg_sser_rw_rec_cfg___iec60958_ui_len___width 5
#define reg_sser_rw_rec_cfg___slave2_en___lsb 25
#define reg_sser_rw_rec_cfg___slave2_en___width 1
#define reg_sser_rw_rec_cfg___slave2_en___bit 25
#define reg_sser_rw_rec_cfg___slave3_en___lsb 26
#define reg_sser_rw_rec_cfg___slave3_en___width 1
#define reg_sser_rw_rec_cfg___slave3_en___bit 26
#define reg_sser_rw_rec_cfg___fifo_thr___lsb 27
#define reg_sser_rw_rec_cfg___fifo_thr___width 2
#define reg_sser_rw_rec_cfg_offset 12
/* Register rw_tr_data, scope sser, type rw */
#define reg_sser_rw_tr_data___data___lsb 0
#define reg_sser_rw_tr_data___data___width 16
#define reg_sser_rw_tr_data___md___lsb 16
#define reg_sser_rw_tr_data___md___width 1
#define reg_sser_rw_tr_data___md___bit 16
#define reg_sser_rw_tr_data_offset 16
/* Register r_rec_data, scope sser, type r */
#define reg_sser_r_rec_data___data___lsb 0
#define reg_sser_r_rec_data___data___width 16
#define reg_sser_r_rec_data___md___lsb 16
#define reg_sser_r_rec_data___md___width 1
#define reg_sser_r_rec_data___md___bit 16
#define reg_sser_r_rec_data___ext_clk___lsb 17
#define reg_sser_r_rec_data___ext_clk___width 1
#define reg_sser_r_rec_data___ext_clk___bit 17
#define reg_sser_r_rec_data___status_in___lsb 18
#define reg_sser_r_rec_data___status_in___width 1
#define reg_sser_r_rec_data___status_in___bit 18
#define reg_sser_r_rec_data___frame_in___lsb 19
#define reg_sser_r_rec_data___frame_in___width 1
#define reg_sser_r_rec_data___frame_in___bit 19
#define reg_sser_r_rec_data___din___lsb 20
#define reg_sser_r_rec_data___din___width 1
#define reg_sser_r_rec_data___din___bit 20
#define reg_sser_r_rec_data___data_in___lsb 21
#define reg_sser_r_rec_data___data_in___width 1
#define reg_sser_r_rec_data___data_in___bit 21
#define reg_sser_r_rec_data___clk_in___lsb 22
#define reg_sser_r_rec_data___clk_in___width 1
#define reg_sser_r_rec_data___clk_in___bit 22
#define reg_sser_r_rec_data_offset 20
/* Register rw_extra, scope sser, type rw */
#define reg_sser_rw_extra___clkoff_cycles___lsb 0
#define reg_sser_rw_extra___clkoff_cycles___width 20
#define reg_sser_rw_extra___clkoff_en___lsb 20
#define reg_sser_rw_extra___clkoff_en___width 1
#define reg_sser_rw_extra___clkoff_en___bit 20
#define reg_sser_rw_extra___clkon_en___lsb 21
#define reg_sser_rw_extra___clkon_en___width 1
#define reg_sser_rw_extra___clkon_en___bit 21
#define reg_sser_rw_extra___dout_delay___lsb 22
#define reg_sser_rw_extra___dout_delay___width 5
#define reg_sser_rw_extra_offset 24
/* Register rw_intr_mask, scope sser, type rw */
#define reg_sser_rw_intr_mask___trdy___lsb 0
#define reg_sser_rw_intr_mask___trdy___width 1
#define reg_sser_rw_intr_mask___trdy___bit 0
#define reg_sser_rw_intr_mask___rdav___lsb 1
#define reg_sser_rw_intr_mask___rdav___width 1
#define reg_sser_rw_intr_mask___rdav___bit 1
#define reg_sser_rw_intr_mask___tidle___lsb 2
#define reg_sser_rw_intr_mask___tidle___width 1
#define reg_sser_rw_intr_mask___tidle___bit 2
#define reg_sser_rw_intr_mask___rstop___lsb 3
#define reg_sser_rw_intr_mask___rstop___width 1
#define reg_sser_rw_intr_mask___rstop___bit 3
#define reg_sser_rw_intr_mask___urun___lsb 4
#define reg_sser_rw_intr_mask___urun___width 1
#define reg_sser_rw_intr_mask___urun___bit 4
#define reg_sser_rw_intr_mask___orun___lsb 5
#define reg_sser_rw_intr_mask___orun___width 1
#define reg_sser_rw_intr_mask___orun___bit 5
#define reg_sser_rw_intr_mask___md_rec___lsb 6
#define reg_sser_rw_intr_mask___md_rec___width 1
#define reg_sser_rw_intr_mask___md_rec___bit 6
#define reg_sser_rw_intr_mask___md_sent___lsb 7
#define reg_sser_rw_intr_mask___md_sent___width 1
#define reg_sser_rw_intr_mask___md_sent___bit 7
#define reg_sser_rw_intr_mask___r958err___lsb 8
#define reg_sser_rw_intr_mask___r958err___width 1
#define reg_sser_rw_intr_mask___r958err___bit 8
#define reg_sser_rw_intr_mask_offset 28
/* Register rw_ack_intr, scope sser, type rw */
#define reg_sser_rw_ack_intr___trdy___lsb 0
#define reg_sser_rw_ack_intr___trdy___width 1
#define reg_sser_rw_ack_intr___trdy___bit 0
#define reg_sser_rw_ack_intr___rdav___lsb 1
#define reg_sser_rw_ack_intr___rdav___width 1
#define reg_sser_rw_ack_intr___rdav___bit 1
#define reg_sser_rw_ack_intr___tidle___lsb 2
#define reg_sser_rw_ack_intr___tidle___width 1
#define reg_sser_rw_ack_intr___tidle___bit 2
#define reg_sser_rw_ack_intr___rstop___lsb 3
#define reg_sser_rw_ack_intr___rstop___width 1
#define reg_sser_rw_ack_intr___rstop___bit 3
#define reg_sser_rw_ack_intr___urun___lsb 4
#define reg_sser_rw_ack_intr___urun___width 1
#define reg_sser_rw_ack_intr___urun___bit 4
#define reg_sser_rw_ack_intr___orun___lsb 5
#define reg_sser_rw_ack_intr___orun___width 1
#define reg_sser_rw_ack_intr___orun___bit 5
#define reg_sser_rw_ack_intr___md_rec___lsb 6
#define reg_sser_rw_ack_intr___md_rec___width 1
#define reg_sser_rw_ack_intr___md_rec___bit 6
#define reg_sser_rw_ack_intr___md_sent___lsb 7
#define reg_sser_rw_ack_intr___md_sent___width 1
#define reg_sser_rw_ack_intr___md_sent___bit 7
#define reg_sser_rw_ack_intr___r958err___lsb 8
#define reg_sser_rw_ack_intr___r958err___width 1
#define reg_sser_rw_ack_intr___r958err___bit 8
#define reg_sser_rw_ack_intr_offset 32
/* Register r_intr, scope sser, type r */
#define reg_sser_r_intr___trdy___lsb 0
#define reg_sser_r_intr___trdy___width 1
#define reg_sser_r_intr___trdy___bit 0
#define reg_sser_r_intr___rdav___lsb 1
#define reg_sser_r_intr___rdav___width 1
#define reg_sser_r_intr___rdav___bit 1
#define reg_sser_r_intr___tidle___lsb 2
#define reg_sser_r_intr___tidle___width 1
#define reg_sser_r_intr___tidle___bit 2
#define reg_sser_r_intr___rstop___lsb 3
#define reg_sser_r_intr___rstop___width 1
#define reg_sser_r_intr___rstop___bit 3
#define reg_sser_r_intr___urun___lsb 4
#define reg_sser_r_intr___urun___width 1
#define reg_sser_r_intr___urun___bit 4
#define reg_sser_r_intr___orun___lsb 5
#define reg_sser_r_intr___orun___width 1
#define reg_sser_r_intr___orun___bit 5
#define reg_sser_r_intr___md_rec___lsb 6
#define reg_sser_r_intr___md_rec___width 1
#define reg_sser_r_intr___md_rec___bit 6
#define reg_sser_r_intr___md_sent___lsb 7
#define reg_sser_r_intr___md_sent___width 1
#define reg_sser_r_intr___md_sent___bit 7
#define reg_sser_r_intr___r958err___lsb 8
#define reg_sser_r_intr___r958err___width 1
#define reg_sser_r_intr___r958err___bit 8
#define reg_sser_r_intr_offset 36
/* Register r_masked_intr, scope sser, type r */
#define reg_sser_r_masked_intr___trdy___lsb 0
#define reg_sser_r_masked_intr___trdy___width 1
#define reg_sser_r_masked_intr___trdy___bit 0
#define reg_sser_r_masked_intr___rdav___lsb 1
#define reg_sser_r_masked_intr___rdav___width 1
#define reg_sser_r_masked_intr___rdav___bit 1
#define reg_sser_r_masked_intr___tidle___lsb 2
#define reg_sser_r_masked_intr___tidle___width 1
#define reg_sser_r_masked_intr___tidle___bit 2
#define reg_sser_r_masked_intr___rstop___lsb 3
#define reg_sser_r_masked_intr___rstop___width 1
#define reg_sser_r_masked_intr___rstop___bit 3
#define reg_sser_r_masked_intr___urun___lsb 4
#define reg_sser_r_masked_intr___urun___width 1
#define reg_sser_r_masked_intr___urun___bit 4
#define reg_sser_r_masked_intr___orun___lsb 5
#define reg_sser_r_masked_intr___orun___width 1
#define reg_sser_r_masked_intr___orun___bit 5
#define reg_sser_r_masked_intr___md_rec___lsb 6
#define reg_sser_r_masked_intr___md_rec___width 1
#define reg_sser_r_masked_intr___md_rec___bit 6
#define reg_sser_r_masked_intr___md_sent___lsb 7
#define reg_sser_r_masked_intr___md_sent___width 1
#define reg_sser_r_masked_intr___md_sent___bit 7
#define reg_sser_r_masked_intr___r958err___lsb 8
#define reg_sser_r_masked_intr___r958err___width 1
#define reg_sser_r_masked_intr___r958err___bit 8
#define reg_sser_r_masked_intr_offset 40
/* Constants */
#define regk_sser_both 0x00000002
#define regk_sser_bulk 0x00000001
#define regk_sser_clk100 0x00000000
#define regk_sser_clk_in 0x00000000
#define regk_sser_const0 0x00000003
#define regk_sser_dout 0x00000002
#define regk_sser_edge 0x00000000
#define regk_sser_ext 0x00000001
#define regk_sser_ext_clk 0x00000001
#define regk_sser_f100 0x00000000
#define regk_sser_f29_493 0x00000004
#define regk_sser_f32 0x00000005
#define regk_sser_f32_768 0x00000006
#define regk_sser_frm 0x00000003
#define regk_sser_gio0 0x00000000
#define regk_sser_gio1 0x00000001
#define regk_sser_hispeed 0x00000001
#define regk_sser_hold 0x00000002
#define regk_sser_in 0x00000000
#define regk_sser_inf 0x00000003
#define regk_sser_intern 0x00000000
#define regk_sser_intern_clk 0x00000001
#define regk_sser_intern_tb 0x00000000
#define regk_sser_iso 0x00000000
#define regk_sser_level 0x00000001
#define regk_sser_lospeed 0x00000000
#define regk_sser_lsbfirst 0x00000000
#define regk_sser_msbfirst 0x00000001
#define regk_sser_neg 0x00000001
#define regk_sser_neg_lo 0x00000000
#define regk_sser_no 0x00000000
#define regk_sser_no_clk 0x00000007
#define regk_sser_nojitter 0x00000002
#define regk_sser_out 0x00000001
#define regk_sser_pos 0x00000000
#define regk_sser_pos_hi 0x00000001
#define regk_sser_rec 0x00000000
#define regk_sser_rw_cfg_default 0x00000000
#define regk_sser_rw_extra_default 0x00000000
#define regk_sser_rw_frm_cfg_default 0x00000000
#define regk_sser_rw_intr_mask_default 0x00000000
#define regk_sser_rw_rec_cfg_default 0x00000000
#define regk_sser_rw_tr_cfg_default 0x01800000
#define regk_sser_rw_tr_data_default 0x00000000
#define regk_sser_thr16 0x00000001
#define regk_sser_thr32 0x00000002
#define regk_sser_thr8 0x00000000
#define regk_sser_tr 0x00000001
#define regk_sser_ts_out 0x00000003
#define regk_sser_tx_bulk 0x00000002
#define regk_sser_wiresave 0x00000002
#define regk_sser_yes 0x00000001
#endif /* __sser_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/asm/strcop_defs_asm.h Normal file
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#ifndef __strcop_defs_asm_h
#define __strcop_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/strcop/rtl/strcop_regs.r
* id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp
* last modfied: Mon Apr 11 16:09:38 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strcop_defs_asm.h ../../inst/strcop/rtl/strcop_regs.r
* id: $Id: strcop_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_cfg, scope strcop, type rw */
#define reg_strcop_rw_cfg___td3___lsb 0
#define reg_strcop_rw_cfg___td3___width 1
#define reg_strcop_rw_cfg___td3___bit 0
#define reg_strcop_rw_cfg___td2___lsb 1
#define reg_strcop_rw_cfg___td2___width 1
#define reg_strcop_rw_cfg___td2___bit 1
#define reg_strcop_rw_cfg___td1___lsb 2
#define reg_strcop_rw_cfg___td1___width 1
#define reg_strcop_rw_cfg___td1___bit 2
#define reg_strcop_rw_cfg___ipend___lsb 3
#define reg_strcop_rw_cfg___ipend___width 1
#define reg_strcop_rw_cfg___ipend___bit 3
#define reg_strcop_rw_cfg___ignore_sync___lsb 4
#define reg_strcop_rw_cfg___ignore_sync___width 1
#define reg_strcop_rw_cfg___ignore_sync___bit 4
#define reg_strcop_rw_cfg___en___lsb 5
#define reg_strcop_rw_cfg___en___width 1
#define reg_strcop_rw_cfg___en___bit 5
#define reg_strcop_rw_cfg_offset 0
/* Constants */
#define regk_strcop_big 0x00000001
#define regk_strcop_d 0x00000001
#define regk_strcop_e 0x00000000
#define regk_strcop_little 0x00000000
#define regk_strcop_rw_cfg_default 0x00000002
#endif /* __strcop_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/asm/strmux_defs_asm.h Normal file
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#ifndef __strmux_defs_asm_h
#define __strmux_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/strmux/rtl/guinness/strmux_regs.r
* id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp
* last modfied: Mon Apr 11 16:09:43 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strmux_defs_asm.h ../../inst/strmux/rtl/guinness/strmux_regs.r
* id: $Id: strmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_cfg, scope strmux, type rw */
#define reg_strmux_rw_cfg___dma0___lsb 0
#define reg_strmux_rw_cfg___dma0___width 3
#define reg_strmux_rw_cfg___dma1___lsb 3
#define reg_strmux_rw_cfg___dma1___width 3
#define reg_strmux_rw_cfg___dma2___lsb 6
#define reg_strmux_rw_cfg___dma2___width 3
#define reg_strmux_rw_cfg___dma3___lsb 9
#define reg_strmux_rw_cfg___dma3___width 3
#define reg_strmux_rw_cfg___dma4___lsb 12
#define reg_strmux_rw_cfg___dma4___width 3
#define reg_strmux_rw_cfg___dma5___lsb 15
#define reg_strmux_rw_cfg___dma5___width 3
#define reg_strmux_rw_cfg___dma6___lsb 18
#define reg_strmux_rw_cfg___dma6___width 3
#define reg_strmux_rw_cfg___dma7___lsb 21
#define reg_strmux_rw_cfg___dma7___width 3
#define reg_strmux_rw_cfg___dma8___lsb 24
#define reg_strmux_rw_cfg___dma8___width 3
#define reg_strmux_rw_cfg___dma9___lsb 27
#define reg_strmux_rw_cfg___dma9___width 3
#define reg_strmux_rw_cfg_offset 0
/* Constants */
#define regk_strmux_ata 0x00000003
#define regk_strmux_eth0 0x00000001
#define regk_strmux_eth1 0x00000004
#define regk_strmux_ext0 0x00000001
#define regk_strmux_ext1 0x00000001
#define regk_strmux_ext2 0x00000001
#define regk_strmux_ext3 0x00000001
#define regk_strmux_iop0 0x00000002
#define regk_strmux_iop1 0x00000001
#define regk_strmux_off 0x00000000
#define regk_strmux_p21 0x00000004
#define regk_strmux_rw_cfg_default 0x00000000
#define regk_strmux_ser0 0x00000002
#define regk_strmux_ser1 0x00000002
#define regk_strmux_ser2 0x00000004
#define regk_strmux_ser3 0x00000003
#define regk_strmux_sser0 0x00000003
#define regk_strmux_sser1 0x00000003
#define regk_strmux_strcop 0x00000002
#endif /* __strmux_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/asm/timer_defs_asm.h Normal file
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#ifndef __timer_defs_asm_h
#define __timer_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/timer/rtl/timer_regs.r
* id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
* last modfied: Mon Apr 11 16:09:53 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r
* id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_tmr0_div, scope timer, type rw */
#define reg_timer_rw_tmr0_div_offset 0
/* Register r_tmr0_data, scope timer, type r */
#define reg_timer_r_tmr0_data_offset 4
/* Register rw_tmr0_ctrl, scope timer, type rw */
#define reg_timer_rw_tmr0_ctrl___op___lsb 0
#define reg_timer_rw_tmr0_ctrl___op___width 2
#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
#define reg_timer_rw_tmr0_ctrl___freq___width 3
#define reg_timer_rw_tmr0_ctrl_offset 8
/* Register rw_tmr1_div, scope timer, type rw */
#define reg_timer_rw_tmr1_div_offset 16
/* Register r_tmr1_data, scope timer, type r */
#define reg_timer_r_tmr1_data_offset 20
/* Register rw_tmr1_ctrl, scope timer, type rw */
#define reg_timer_rw_tmr1_ctrl___op___lsb 0
#define reg_timer_rw_tmr1_ctrl___op___width 2
#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
#define reg_timer_rw_tmr1_ctrl___freq___width 3
#define reg_timer_rw_tmr1_ctrl_offset 24
/* Register rs_cnt_data, scope timer, type rs */
#define reg_timer_rs_cnt_data___tmr___lsb 0
#define reg_timer_rs_cnt_data___tmr___width 24
#define reg_timer_rs_cnt_data___cnt___lsb 24
#define reg_timer_rs_cnt_data___cnt___width 8
#define reg_timer_rs_cnt_data_offset 32
/* Register r_cnt_data, scope timer, type r */
#define reg_timer_r_cnt_data___tmr___lsb 0
#define reg_timer_r_cnt_data___tmr___width 24
#define reg_timer_r_cnt_data___cnt___lsb 24
#define reg_timer_r_cnt_data___cnt___width 8
#define reg_timer_r_cnt_data_offset 36
/* Register rw_cnt_cfg, scope timer, type rw */
#define reg_timer_rw_cnt_cfg___clk___lsb 0
#define reg_timer_rw_cnt_cfg___clk___width 2
#define reg_timer_rw_cnt_cfg_offset 40
/* Register rw_trig, scope timer, type rw */
#define reg_timer_rw_trig_offset 48
/* Register rw_trig_cfg, scope timer, type rw */
#define reg_timer_rw_trig_cfg___tmr___lsb 0
#define reg_timer_rw_trig_cfg___tmr___width 2
#define reg_timer_rw_trig_cfg_offset 52
/* Register r_time, scope timer, type r */
#define reg_timer_r_time_offset 56
/* Register rw_out, scope timer, type rw */
#define reg_timer_rw_out___tmr___lsb 0
#define reg_timer_rw_out___tmr___width 2
#define reg_timer_rw_out_offset 60
/* Register rw_wd_ctrl, scope timer, type rw */
#define reg_timer_rw_wd_ctrl___cnt___lsb 0
#define reg_timer_rw_wd_ctrl___cnt___width 8
#define reg_timer_rw_wd_ctrl___cmd___lsb 8
#define reg_timer_rw_wd_ctrl___cmd___width 1
#define reg_timer_rw_wd_ctrl___cmd___bit 8
#define reg_timer_rw_wd_ctrl___key___lsb 9
#define reg_timer_rw_wd_ctrl___key___width 7
#define reg_timer_rw_wd_ctrl_offset 64
/* Register r_wd_stat, scope timer, type r */
#define reg_timer_r_wd_stat___cnt___lsb 0
#define reg_timer_r_wd_stat___cnt___width 8
#define reg_timer_r_wd_stat___cmd___lsb 8
#define reg_timer_r_wd_stat___cmd___width 1
#define reg_timer_r_wd_stat___cmd___bit 8
#define reg_timer_r_wd_stat_offset 68
/* Register rw_intr_mask, scope timer, type rw */
#define reg_timer_rw_intr_mask___tmr0___lsb 0
#define reg_timer_rw_intr_mask___tmr0___width 1
#define reg_timer_rw_intr_mask___tmr0___bit 0
#define reg_timer_rw_intr_mask___tmr1___lsb 1
#define reg_timer_rw_intr_mask___tmr1___width 1
#define reg_timer_rw_intr_mask___tmr1___bit 1
#define reg_timer_rw_intr_mask___cnt___lsb 2
#define reg_timer_rw_intr_mask___cnt___width 1
#define reg_timer_rw_intr_mask___cnt___bit 2
#define reg_timer_rw_intr_mask___trig___lsb 3
#define reg_timer_rw_intr_mask___trig___width 1
#define reg_timer_rw_intr_mask___trig___bit 3
#define reg_timer_rw_intr_mask_offset 72
/* Register rw_ack_intr, scope timer, type rw */
#define reg_timer_rw_ack_intr___tmr0___lsb 0
#define reg_timer_rw_ack_intr___tmr0___width 1
#define reg_timer_rw_ack_intr___tmr0___bit 0
#define reg_timer_rw_ack_intr___tmr1___lsb 1
#define reg_timer_rw_ack_intr___tmr1___width 1
#define reg_timer_rw_ack_intr___tmr1___bit 1
#define reg_timer_rw_ack_intr___cnt___lsb 2
#define reg_timer_rw_ack_intr___cnt___width 1
#define reg_timer_rw_ack_intr___cnt___bit 2
#define reg_timer_rw_ack_intr___trig___lsb 3
#define reg_timer_rw_ack_intr___trig___width 1
#define reg_timer_rw_ack_intr___trig___bit 3
#define reg_timer_rw_ack_intr_offset 76
/* Register r_intr, scope timer, type r */
#define reg_timer_r_intr___tmr0___lsb 0
#define reg_timer_r_intr___tmr0___width 1
#define reg_timer_r_intr___tmr0___bit 0
#define reg_timer_r_intr___tmr1___lsb 1
#define reg_timer_r_intr___tmr1___width 1
#define reg_timer_r_intr___tmr1___bit 1
#define reg_timer_r_intr___cnt___lsb 2
#define reg_timer_r_intr___cnt___width 1
#define reg_timer_r_intr___cnt___bit 2
#define reg_timer_r_intr___trig___lsb 3
#define reg_timer_r_intr___trig___width 1
#define reg_timer_r_intr___trig___bit 3
#define reg_timer_r_intr_offset 80
/* Register r_masked_intr, scope timer, type r */
#define reg_timer_r_masked_intr___tmr0___lsb 0
#define reg_timer_r_masked_intr___tmr0___width 1
#define reg_timer_r_masked_intr___tmr0___bit 0
#define reg_timer_r_masked_intr___tmr1___lsb 1
#define reg_timer_r_masked_intr___tmr1___width 1
#define reg_timer_r_masked_intr___tmr1___bit 1
#define reg_timer_r_masked_intr___cnt___lsb 2
#define reg_timer_r_masked_intr___cnt___width 1
#define reg_timer_r_masked_intr___cnt___bit 2
#define reg_timer_r_masked_intr___trig___lsb 3
#define reg_timer_r_masked_intr___trig___width 1
#define reg_timer_r_masked_intr___trig___bit 3
#define reg_timer_r_masked_intr_offset 84
/* Register rw_test, scope timer, type rw */
#define reg_timer_rw_test___dis___lsb 0
#define reg_timer_rw_test___dis___width 1
#define reg_timer_rw_test___dis___bit 0
#define reg_timer_rw_test___en___lsb 1
#define reg_timer_rw_test___en___width 1
#define reg_timer_rw_test___en___bit 1
#define reg_timer_rw_test_offset 88
/* Constants */
#define regk_timer_ext 0x00000001
#define regk_timer_f100 0x00000007
#define regk_timer_f29_493 0x00000004
#define regk_timer_f32 0x00000005
#define regk_timer_f32_768 0x00000006
#define regk_timer_hold 0x00000001
#define regk_timer_ld 0x00000000
#define regk_timer_no 0x00000000
#define regk_timer_off 0x00000000
#define regk_timer_run 0x00000002
#define regk_timer_rw_cnt_cfg_default 0x00000000
#define regk_timer_rw_intr_mask_default 0x00000000
#define regk_timer_rw_out_default 0x00000000
#define regk_timer_rw_test_default 0x00000000
#define regk_timer_rw_tmr0_ctrl_default 0x00000000
#define regk_timer_rw_tmr1_ctrl_default 0x00000000
#define regk_timer_rw_trig_cfg_default 0x00000000
#define regk_timer_start 0x00000001
#define regk_timer_stop 0x00000000
#define regk_timer_time 0x00000001
#define regk_timer_tmr0 0x00000002
#define regk_timer_tmr1 0x00000003
#define regk_timer_yes 0x00000001
#endif /* __timer_defs_asm_h */

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#ifndef __ata_defs_h
#define __ata_defs_h
/*
* This file is autogenerated from
* file: ../../inst/ata/rtl/ata_regs.r
* id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
* last modfied: Mon Apr 11 16:06:25 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r
* id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope ata */
/* Register rw_ctrl0, scope ata, type rw */
typedef struct {
unsigned int pio_hold : 6;
unsigned int pio_strb : 6;
unsigned int pio_setup : 6;
unsigned int dma_hold : 6;
unsigned int dma_strb : 6;
unsigned int rst : 1;
unsigned int en : 1;
} reg_ata_rw_ctrl0;
#define REG_RD_ADDR_ata_rw_ctrl0 12
#define REG_WR_ADDR_ata_rw_ctrl0 12
/* Register rw_ctrl1, scope ata, type rw */
typedef struct {
unsigned int udma_tcyc : 4;
unsigned int udma_tdvs : 4;
unsigned int dummy1 : 24;
} reg_ata_rw_ctrl1;
#define REG_RD_ADDR_ata_rw_ctrl1 16
#define REG_WR_ADDR_ata_rw_ctrl1 16
/* Register rw_ctrl2, scope ata, type rw */
typedef struct {
unsigned int data : 16;
unsigned int dummy1 : 3;
unsigned int dma_size : 1;
unsigned int multi : 1;
unsigned int hsh : 2;
unsigned int trf_mode : 1;
unsigned int rw : 1;
unsigned int addr : 3;
unsigned int cs0 : 1;
unsigned int cs1 : 1;
unsigned int sel : 2;
} reg_ata_rw_ctrl2;
#define REG_RD_ADDR_ata_rw_ctrl2 0
#define REG_WR_ADDR_ata_rw_ctrl2 0
/* Register rs_stat_data, scope ata, type rs */
typedef struct {
unsigned int data : 16;
unsigned int dav : 1;
unsigned int busy : 1;
unsigned int dummy1 : 14;
} reg_ata_rs_stat_data;
#define REG_RD_ADDR_ata_rs_stat_data 4
/* Register r_stat_data, scope ata, type r */
typedef struct {
unsigned int data : 16;
unsigned int dav : 1;
unsigned int busy : 1;
unsigned int dummy1 : 14;
} reg_ata_r_stat_data;
#define REG_RD_ADDR_ata_r_stat_data 8
/* Register rw_trf_cnt, scope ata, type rw */
typedef struct {
unsigned int cnt : 17;
unsigned int dummy1 : 15;
} reg_ata_rw_trf_cnt;
#define REG_RD_ADDR_ata_rw_trf_cnt 20
#define REG_WR_ADDR_ata_rw_trf_cnt 20
/* Register r_stat_misc, scope ata, type r */
typedef struct {
unsigned int crc : 16;
unsigned int dummy1 : 16;
} reg_ata_r_stat_misc;
#define REG_RD_ADDR_ata_r_stat_misc 24
/* Register rw_intr_mask, scope ata, type rw */
typedef struct {
unsigned int bus0 : 1;
unsigned int bus1 : 1;
unsigned int bus2 : 1;
unsigned int bus3 : 1;
unsigned int dummy1 : 28;
} reg_ata_rw_intr_mask;
#define REG_RD_ADDR_ata_rw_intr_mask 28
#define REG_WR_ADDR_ata_rw_intr_mask 28
/* Register rw_ack_intr, scope ata, type rw */
typedef struct {
unsigned int bus0 : 1;
unsigned int bus1 : 1;
unsigned int bus2 : 1;
unsigned int bus3 : 1;
unsigned int dummy1 : 28;
} reg_ata_rw_ack_intr;
#define REG_RD_ADDR_ata_rw_ack_intr 32
#define REG_WR_ADDR_ata_rw_ack_intr 32
/* Register r_intr, scope ata, type r */
typedef struct {
unsigned int bus0 : 1;
unsigned int bus1 : 1;
unsigned int bus2 : 1;
unsigned int bus3 : 1;
unsigned int dummy1 : 28;
} reg_ata_r_intr;
#define REG_RD_ADDR_ata_r_intr 36
/* Register r_masked_intr, scope ata, type r */
typedef struct {
unsigned int bus0 : 1;
unsigned int bus1 : 1;
unsigned int bus2 : 1;
unsigned int bus3 : 1;
unsigned int dummy1 : 28;
} reg_ata_r_masked_intr;
#define REG_RD_ADDR_ata_r_masked_intr 40
/* Constants */
enum {
regk_ata_active = 0x00000001,
regk_ata_byte = 0x00000001,
regk_ata_data = 0x00000001,
regk_ata_dma = 0x00000001,
regk_ata_inactive = 0x00000000,
regk_ata_no = 0x00000000,
regk_ata_nodata = 0x00000000,
regk_ata_pio = 0x00000000,
regk_ata_rd = 0x00000001,
regk_ata_reg = 0x00000000,
regk_ata_rw_ctrl0_default = 0x00000000,
regk_ata_rw_ctrl2_default = 0x00000000,
regk_ata_rw_intr_mask_default = 0x00000000,
regk_ata_udma = 0x00000002,
regk_ata_word = 0x00000000,
regk_ata_wr = 0x00000000,
regk_ata_yes = 0x00000001
};
#endif /* __ata_defs_h */

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#ifndef __bif_core_defs_h
#define __bif_core_defs_h
/*
* This file is autogenerated from
* file: ../../inst/bif/rtl/bif_core_regs.r
* id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
* last modfied: Mon Apr 11 16:06:33 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
* id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope bif_core */
/* Register rw_grp1_cfg, scope bif_core, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int wr_extend : 1;
unsigned int erc_en : 1;
unsigned int mode : 1;
unsigned int dummy1 : 10;
} reg_bif_core_rw_grp1_cfg;
#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0
#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0
/* Register rw_grp2_cfg, scope bif_core, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int wr_extend : 1;
unsigned int erc_en : 1;
unsigned int mode : 1;
unsigned int dummy1 : 10;
} reg_bif_core_rw_grp2_cfg;
#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4
#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4
/* Register rw_grp3_cfg, scope bif_core, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int wr_extend : 1;
unsigned int erc_en : 1;
unsigned int mode : 1;
unsigned int dummy1 : 2;
unsigned int gated_csp0 : 2;
unsigned int gated_csp1 : 2;
unsigned int gated_csp2 : 2;
unsigned int gated_csp3 : 2;
} reg_bif_core_rw_grp3_cfg;
#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8
#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8
/* Register rw_grp4_cfg, scope bif_core, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int wr_extend : 1;
unsigned int erc_en : 1;
unsigned int mode : 1;
unsigned int dummy1 : 4;
unsigned int gated_csp4 : 2;
unsigned int gated_csp5 : 2;
unsigned int gated_csp6 : 2;
} reg_bif_core_rw_grp4_cfg;
#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12
#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12
/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
typedef struct {
unsigned int bank_sel : 5;
unsigned int ca : 3;
unsigned int type : 1;
unsigned int bw : 1;
unsigned int sh : 3;
unsigned int wmm : 1;
unsigned int sh16 : 1;
unsigned int grp_sel : 5;
unsigned int dummy1 : 12;
} reg_bif_core_rw_sdram_cfg_grp0;
#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16
#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16
/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
typedef struct {
unsigned int bank_sel : 5;
unsigned int ca : 3;
unsigned int type : 1;
unsigned int bw : 1;
unsigned int sh : 3;
unsigned int wmm : 1;
unsigned int sh16 : 1;
unsigned int dummy1 : 17;
} reg_bif_core_rw_sdram_cfg_grp1;
#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20
#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20
/* Register rw_sdram_timing, scope bif_core, type rw */
typedef struct {
unsigned int cl : 3;
unsigned int rcd : 3;
unsigned int rp : 3;
unsigned int rc : 2;
unsigned int dpl : 2;
unsigned int pde : 1;
unsigned int ref : 2;
unsigned int cpd : 1;
unsigned int sdcke : 1;
unsigned int sdclk : 1;
unsigned int dummy1 : 13;
} reg_bif_core_rw_sdram_timing;
#define REG_RD_ADDR_bif_core_rw_sdram_timing 24
#define REG_WR_ADDR_bif_core_rw_sdram_timing 24
/* Register rw_sdram_cmd, scope bif_core, type rw */
typedef struct {
unsigned int cmd : 3;
unsigned int mrs_data : 15;
unsigned int dummy1 : 14;
} reg_bif_core_rw_sdram_cmd;
#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28
#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28
/* Register rs_sdram_ref_stat, scope bif_core, type rs */
typedef struct {
unsigned int ok : 1;
unsigned int dummy1 : 31;
} reg_bif_core_rs_sdram_ref_stat;
#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32
/* Register r_sdram_ref_stat, scope bif_core, type r */
typedef struct {
unsigned int ok : 1;
unsigned int dummy1 : 31;
} reg_bif_core_r_sdram_ref_stat;
#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36
/* Constants */
enum {
regk_bif_core_bank2 = 0x00000000,
regk_bif_core_bank4 = 0x00000001,
regk_bif_core_bit10 = 0x0000000a,
regk_bif_core_bit11 = 0x0000000b,
regk_bif_core_bit12 = 0x0000000c,
regk_bif_core_bit13 = 0x0000000d,
regk_bif_core_bit14 = 0x0000000e,
regk_bif_core_bit15 = 0x0000000f,
regk_bif_core_bit16 = 0x00000010,
regk_bif_core_bit17 = 0x00000011,
regk_bif_core_bit18 = 0x00000012,
regk_bif_core_bit19 = 0x00000013,
regk_bif_core_bit20 = 0x00000014,
regk_bif_core_bit21 = 0x00000015,
regk_bif_core_bit22 = 0x00000016,
regk_bif_core_bit23 = 0x00000017,
regk_bif_core_bit24 = 0x00000018,
regk_bif_core_bit25 = 0x00000019,
regk_bif_core_bit26 = 0x0000001a,
regk_bif_core_bit27 = 0x0000001b,
regk_bif_core_bit28 = 0x0000001c,
regk_bif_core_bit29 = 0x0000001d,
regk_bif_core_bit9 = 0x00000009,
regk_bif_core_bw16 = 0x00000001,
regk_bif_core_bw32 = 0x00000000,
regk_bif_core_bwe = 0x00000000,
regk_bif_core_cwe = 0x00000001,
regk_bif_core_e15us = 0x00000001,
regk_bif_core_e7800ns = 0x00000002,
regk_bif_core_grp0 = 0x00000000,
regk_bif_core_grp1 = 0x00000001,
regk_bif_core_mrs = 0x00000003,
regk_bif_core_no = 0x00000000,
regk_bif_core_none = 0x00000000,
regk_bif_core_nop = 0x00000000,
regk_bif_core_off = 0x00000000,
regk_bif_core_pre = 0x00000002,
regk_bif_core_r_sdram_ref_stat_default = 0x00000001,
regk_bif_core_rd = 0x00000002,
regk_bif_core_ref = 0x00000001,
regk_bif_core_rs_sdram_ref_stat_default = 0x00000001,
regk_bif_core_rw_grp1_cfg_default = 0x000006cf,
regk_bif_core_rw_grp2_cfg_default = 0x000006cf,
regk_bif_core_rw_grp3_cfg_default = 0x000006cf,
regk_bif_core_rw_grp4_cfg_default = 0x000006cf,
regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000,
regk_bif_core_slf = 0x00000004,
regk_bif_core_wr = 0x00000001,
regk_bif_core_yes = 0x00000001
};
#endif /* __bif_core_defs_h */

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#ifndef __bif_dma_defs_h
#define __bif_dma_defs_h
/*
* This file is autogenerated from
* file: ../../inst/bif/rtl/bif_dma_regs.r
* id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
* last modfied: Mon Apr 11 16:06:33 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r
* id: $Id: bif_dma_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope bif_dma */
/* Register rw_ch0_ctrl, scope bif_dma, type rw */
typedef struct {
unsigned int bw : 2;
unsigned int burst_len : 1;
unsigned int cont : 1;
unsigned int end_pad : 1;
unsigned int cnt : 1;
unsigned int dreq_pin : 3;
unsigned int dreq_mode : 2;
unsigned int tc_in_pin : 3;
unsigned int tc_in_mode : 2;
unsigned int bus_mode : 2;
unsigned int rate_en : 1;
unsigned int wr_all : 1;
unsigned int dummy1 : 12;
} reg_bif_dma_rw_ch0_ctrl;
#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0
#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0
/* Register rw_ch0_addr, scope bif_dma, type rw */
typedef struct {
unsigned int addr : 32;
} reg_bif_dma_rw_ch0_addr;
#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4
#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4
/* Register rw_ch0_start, scope bif_dma, type rw */
typedef struct {
unsigned int run : 1;
unsigned int dummy1 : 31;
} reg_bif_dma_rw_ch0_start;
#define REG_RD_ADDR_bif_dma_rw_ch0_start 8
#define REG_WR_ADDR_bif_dma_rw_ch0_start 8
/* Register rw_ch0_cnt, scope bif_dma, type rw */
typedef struct {
unsigned int start_cnt : 16;
unsigned int dummy1 : 16;
} reg_bif_dma_rw_ch0_cnt;
#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12
#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12
/* Register r_ch0_stat, scope bif_dma, type r */
typedef struct {
unsigned int cnt : 16;
unsigned int dummy1 : 15;
unsigned int run : 1;
} reg_bif_dma_r_ch0_stat;
#define REG_RD_ADDR_bif_dma_r_ch0_stat 16
/* Register rw_ch1_ctrl, scope bif_dma, type rw */
typedef struct {
unsigned int bw : 2;
unsigned int burst_len : 1;
unsigned int cont : 1;
unsigned int end_discard : 1;
unsigned int cnt : 1;
unsigned int dreq_pin : 3;
unsigned int dreq_mode : 2;
unsigned int tc_in_pin : 3;
unsigned int tc_in_mode : 2;
unsigned int bus_mode : 2;
unsigned int rate_en : 1;
unsigned int dummy1 : 13;
} reg_bif_dma_rw_ch1_ctrl;
#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32
#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32
/* Register rw_ch1_addr, scope bif_dma, type rw */
typedef struct {
unsigned int addr : 32;
} reg_bif_dma_rw_ch1_addr;
#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36
#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36
/* Register rw_ch1_start, scope bif_dma, type rw */
typedef struct {
unsigned int run : 1;
unsigned int dummy1 : 31;
} reg_bif_dma_rw_ch1_start;
#define REG_RD_ADDR_bif_dma_rw_ch1_start 40
#define REG_WR_ADDR_bif_dma_rw_ch1_start 40
/* Register rw_ch1_cnt, scope bif_dma, type rw */
typedef struct {
unsigned int start_cnt : 16;
unsigned int dummy1 : 16;
} reg_bif_dma_rw_ch1_cnt;
#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44
#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44
/* Register r_ch1_stat, scope bif_dma, type r */
typedef struct {
unsigned int cnt : 16;
unsigned int dummy1 : 15;
unsigned int run : 1;
} reg_bif_dma_r_ch1_stat;
#define REG_RD_ADDR_bif_dma_r_ch1_stat 48
/* Register rw_ch2_ctrl, scope bif_dma, type rw */
typedef struct {
unsigned int bw : 2;
unsigned int burst_len : 1;
unsigned int cont : 1;
unsigned int end_pad : 1;
unsigned int cnt : 1;
unsigned int dreq_pin : 3;
unsigned int dreq_mode : 2;
unsigned int tc_in_pin : 3;
unsigned int tc_in_mode : 2;
unsigned int bus_mode : 2;
unsigned int rate_en : 1;
unsigned int wr_all : 1;
unsigned int dummy1 : 12;
} reg_bif_dma_rw_ch2_ctrl;
#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64
#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64
/* Register rw_ch2_addr, scope bif_dma, type rw */
typedef struct {
unsigned int addr : 32;
} reg_bif_dma_rw_ch2_addr;
#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68
#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68
/* Register rw_ch2_start, scope bif_dma, type rw */
typedef struct {
unsigned int run : 1;
unsigned int dummy1 : 31;
} reg_bif_dma_rw_ch2_start;
#define REG_RD_ADDR_bif_dma_rw_ch2_start 72
#define REG_WR_ADDR_bif_dma_rw_ch2_start 72
/* Register rw_ch2_cnt, scope bif_dma, type rw */
typedef struct {
unsigned int start_cnt : 16;
unsigned int dummy1 : 16;
} reg_bif_dma_rw_ch2_cnt;
#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76
#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76
/* Register r_ch2_stat, scope bif_dma, type r */
typedef struct {
unsigned int cnt : 16;
unsigned int dummy1 : 15;
unsigned int run : 1;
} reg_bif_dma_r_ch2_stat;
#define REG_RD_ADDR_bif_dma_r_ch2_stat 80
/* Register rw_ch3_ctrl, scope bif_dma, type rw */
typedef struct {
unsigned int bw : 2;
unsigned int burst_len : 1;
unsigned int cont : 1;
unsigned int end_discard : 1;
unsigned int cnt : 1;
unsigned int dreq_pin : 3;
unsigned int dreq_mode : 2;
unsigned int tc_in_pin : 3;
unsigned int tc_in_mode : 2;
unsigned int bus_mode : 2;
unsigned int rate_en : 1;
unsigned int dummy1 : 13;
} reg_bif_dma_rw_ch3_ctrl;
#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96
#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96
/* Register rw_ch3_addr, scope bif_dma, type rw */
typedef struct {
unsigned int addr : 32;
} reg_bif_dma_rw_ch3_addr;
#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100
#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100
/* Register rw_ch3_start, scope bif_dma, type rw */
typedef struct {
unsigned int run : 1;
unsigned int dummy1 : 31;
} reg_bif_dma_rw_ch3_start;
#define REG_RD_ADDR_bif_dma_rw_ch3_start 104
#define REG_WR_ADDR_bif_dma_rw_ch3_start 104
/* Register rw_ch3_cnt, scope bif_dma, type rw */
typedef struct {
unsigned int start_cnt : 16;
unsigned int dummy1 : 16;
} reg_bif_dma_rw_ch3_cnt;
#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108
#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108
/* Register r_ch3_stat, scope bif_dma, type r */
typedef struct {
unsigned int cnt : 16;
unsigned int dummy1 : 15;
unsigned int run : 1;
} reg_bif_dma_r_ch3_stat;
#define REG_RD_ADDR_bif_dma_r_ch3_stat 112
/* Register rw_intr_mask, scope bif_dma, type rw */
typedef struct {
unsigned int ext_dma0 : 1;
unsigned int ext_dma1 : 1;
unsigned int ext_dma2 : 1;
unsigned int ext_dma3 : 1;
unsigned int dummy1 : 28;
} reg_bif_dma_rw_intr_mask;
#define REG_RD_ADDR_bif_dma_rw_intr_mask 128
#define REG_WR_ADDR_bif_dma_rw_intr_mask 128
/* Register rw_ack_intr, scope bif_dma, type rw */
typedef struct {
unsigned int ext_dma0 : 1;
unsigned int ext_dma1 : 1;
unsigned int ext_dma2 : 1;
unsigned int ext_dma3 : 1;
unsigned int dummy1 : 28;
} reg_bif_dma_rw_ack_intr;
#define REG_RD_ADDR_bif_dma_rw_ack_intr 132
#define REG_WR_ADDR_bif_dma_rw_ack_intr 132
/* Register r_intr, scope bif_dma, type r */
typedef struct {
unsigned int ext_dma0 : 1;
unsigned int ext_dma1 : 1;
unsigned int ext_dma2 : 1;
unsigned int ext_dma3 : 1;
unsigned int dummy1 : 28;
} reg_bif_dma_r_intr;
#define REG_RD_ADDR_bif_dma_r_intr 136
/* Register r_masked_intr, scope bif_dma, type r */
typedef struct {
unsigned int ext_dma0 : 1;
unsigned int ext_dma1 : 1;
unsigned int ext_dma2 : 1;
unsigned int ext_dma3 : 1;
unsigned int dummy1 : 28;
} reg_bif_dma_r_masked_intr;
#define REG_RD_ADDR_bif_dma_r_masked_intr 140
/* Register rw_pin0_cfg, scope bif_dma, type rw */
typedef struct {
unsigned int master_ch : 2;
unsigned int master_mode : 3;
unsigned int slave_ch : 2;
unsigned int slave_mode : 3;
unsigned int dummy1 : 22;
} reg_bif_dma_rw_pin0_cfg;
#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160
#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160
/* Register rw_pin1_cfg, scope bif_dma, type rw */
typedef struct {
unsigned int master_ch : 2;
unsigned int master_mode : 3;
unsigned int slave_ch : 2;
unsigned int slave_mode : 3;
unsigned int dummy1 : 22;
} reg_bif_dma_rw_pin1_cfg;
#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164
#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164
/* Register rw_pin2_cfg, scope bif_dma, type rw */
typedef struct {
unsigned int master_ch : 2;
unsigned int master_mode : 3;
unsigned int slave_ch : 2;
unsigned int slave_mode : 3;
unsigned int dummy1 : 22;
} reg_bif_dma_rw_pin2_cfg;
#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168
#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168
/* Register rw_pin3_cfg, scope bif_dma, type rw */
typedef struct {
unsigned int master_ch : 2;
unsigned int master_mode : 3;
unsigned int slave_ch : 2;
unsigned int slave_mode : 3;
unsigned int dummy1 : 22;
} reg_bif_dma_rw_pin3_cfg;
#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172
#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172
/* Register rw_pin4_cfg, scope bif_dma, type rw */
typedef struct {
unsigned int master_ch : 2;
unsigned int master_mode : 3;
unsigned int slave_ch : 2;
unsigned int slave_mode : 3;
unsigned int dummy1 : 22;
} reg_bif_dma_rw_pin4_cfg;
#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176
#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176
/* Register rw_pin5_cfg, scope bif_dma, type rw */
typedef struct {
unsigned int master_ch : 2;
unsigned int master_mode : 3;
unsigned int slave_ch : 2;
unsigned int slave_mode : 3;
unsigned int dummy1 : 22;
} reg_bif_dma_rw_pin5_cfg;
#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180
#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180
/* Register rw_pin6_cfg, scope bif_dma, type rw */
typedef struct {
unsigned int master_ch : 2;
unsigned int master_mode : 3;
unsigned int slave_ch : 2;
unsigned int slave_mode : 3;
unsigned int dummy1 : 22;
} reg_bif_dma_rw_pin6_cfg;
#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184
#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184
/* Register rw_pin7_cfg, scope bif_dma, type rw */
typedef struct {
unsigned int master_ch : 2;
unsigned int master_mode : 3;
unsigned int slave_ch : 2;
unsigned int slave_mode : 3;
unsigned int dummy1 : 22;
} reg_bif_dma_rw_pin7_cfg;
#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188
#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188
/* Register r_pin_stat, scope bif_dma, type r */
typedef struct {
unsigned int pin0 : 1;
unsigned int pin1 : 1;
unsigned int pin2 : 1;
unsigned int pin3 : 1;
unsigned int pin4 : 1;
unsigned int pin5 : 1;
unsigned int pin6 : 1;
unsigned int pin7 : 1;
unsigned int dummy1 : 24;
} reg_bif_dma_r_pin_stat;
#define REG_RD_ADDR_bif_dma_r_pin_stat 192
/* Constants */
enum {
regk_bif_dma_as_master = 0x00000001,
regk_bif_dma_as_slave = 0x00000001,
regk_bif_dma_burst1 = 0x00000000,
regk_bif_dma_burst8 = 0x00000001,
regk_bif_dma_bw16 = 0x00000001,
regk_bif_dma_bw32 = 0x00000002,
regk_bif_dma_bw8 = 0x00000000,
regk_bif_dma_dack = 0x00000006,
regk_bif_dma_dack_inv = 0x00000007,
regk_bif_dma_force = 0x00000001,
regk_bif_dma_hi = 0x00000003,
regk_bif_dma_inv = 0x00000003,
regk_bif_dma_lo = 0x00000002,
regk_bif_dma_master = 0x00000001,
regk_bif_dma_no = 0x00000000,
regk_bif_dma_norm = 0x00000002,
regk_bif_dma_off = 0x00000000,
regk_bif_dma_rw_ch0_ctrl_default = 0x00000000,
regk_bif_dma_rw_ch0_start_default = 0x00000000,
regk_bif_dma_rw_ch1_ctrl_default = 0x00000000,
regk_bif_dma_rw_ch1_start_default = 0x00000000,
regk_bif_dma_rw_ch2_ctrl_default = 0x00000000,
regk_bif_dma_rw_ch2_start_default = 0x00000000,
regk_bif_dma_rw_ch3_ctrl_default = 0x00000000,
regk_bif_dma_rw_ch3_start_default = 0x00000000,
regk_bif_dma_rw_intr_mask_default = 0x00000000,
regk_bif_dma_rw_pin0_cfg_default = 0x00000000,
regk_bif_dma_rw_pin1_cfg_default = 0x00000000,
regk_bif_dma_rw_pin2_cfg_default = 0x00000000,
regk_bif_dma_rw_pin3_cfg_default = 0x00000000,
regk_bif_dma_rw_pin4_cfg_default = 0x00000000,
regk_bif_dma_rw_pin5_cfg_default = 0x00000000,
regk_bif_dma_rw_pin6_cfg_default = 0x00000000,
regk_bif_dma_rw_pin7_cfg_default = 0x00000000,
regk_bif_dma_slave = 0x00000002,
regk_bif_dma_sreq = 0x00000006,
regk_bif_dma_sreq_inv = 0x00000007,
regk_bif_dma_tc = 0x00000004,
regk_bif_dma_tc_inv = 0x00000005,
regk_bif_dma_yes = 0x00000001
};
#endif /* __bif_dma_defs_h */

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#ifndef __bif_slave_defs_h
#define __bif_slave_defs_h
/*
* This file is autogenerated from
* file: ../../inst/bif/rtl/bif_slave_regs.r
* id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
* last modfied: Mon Apr 11 16:06:34 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r
* id: $Id: bif_slave_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope bif_slave */
/* Register rw_slave_cfg, scope bif_slave, type rw */
typedef struct {
unsigned int slave_id : 3;
unsigned int use_slave_id : 1;
unsigned int boot_rdy : 1;
unsigned int loopback : 1;
unsigned int dis : 1;
unsigned int dummy1 : 25;
} reg_bif_slave_rw_slave_cfg;
#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0
#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0
/* Register r_slave_mode, scope bif_slave, type r */
typedef struct {
unsigned int ch0_mode : 1;
unsigned int ch1_mode : 1;
unsigned int ch2_mode : 1;
unsigned int ch3_mode : 1;
unsigned int dummy1 : 28;
} reg_bif_slave_r_slave_mode;
#define REG_RD_ADDR_bif_slave_r_slave_mode 4
/* Register rw_ch0_cfg, scope bif_slave, type rw */
typedef struct {
unsigned int rd_hold : 2;
unsigned int access_mode : 1;
unsigned int access_ctrl : 1;
unsigned int data_cs : 2;
unsigned int dummy1 : 26;
} reg_bif_slave_rw_ch0_cfg;
#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16
#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16
/* Register rw_ch1_cfg, scope bif_slave, type rw */
typedef struct {
unsigned int rd_hold : 2;
unsigned int access_mode : 1;
unsigned int access_ctrl : 1;
unsigned int data_cs : 2;
unsigned int dummy1 : 26;
} reg_bif_slave_rw_ch1_cfg;
#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20
#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20
/* Register rw_ch2_cfg, scope bif_slave, type rw */
typedef struct {
unsigned int rd_hold : 2;
unsigned int access_mode : 1;
unsigned int access_ctrl : 1;
unsigned int data_cs : 2;
unsigned int dummy1 : 26;
} reg_bif_slave_rw_ch2_cfg;
#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24
#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24
/* Register rw_ch3_cfg, scope bif_slave, type rw */
typedef struct {
unsigned int rd_hold : 2;
unsigned int access_mode : 1;
unsigned int access_ctrl : 1;
unsigned int data_cs : 2;
unsigned int dummy1 : 26;
} reg_bif_slave_rw_ch3_cfg;
#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28
#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28
/* Register rw_arb_cfg, scope bif_slave, type rw */
typedef struct {
unsigned int brin_mode : 1;
unsigned int brout_mode : 3;
unsigned int bg_mode : 3;
unsigned int release : 2;
unsigned int acquire : 1;
unsigned int settle_time : 2;
unsigned int dram_ctrl : 1;
unsigned int dummy1 : 19;
} reg_bif_slave_rw_arb_cfg;
#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32
#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32
/* Register r_arb_stat, scope bif_slave, type r */
typedef struct {
unsigned int init_mode : 1;
unsigned int mode : 1;
unsigned int brin : 1;
unsigned int brout : 1;
unsigned int bg : 1;
unsigned int dummy1 : 27;
} reg_bif_slave_r_arb_stat;
#define REG_RD_ADDR_bif_slave_r_arb_stat 36
/* Register rw_intr_mask, scope bif_slave, type rw */
typedef struct {
unsigned int bus_release : 1;
unsigned int bus_acquire : 1;
unsigned int dummy1 : 30;
} reg_bif_slave_rw_intr_mask;
#define REG_RD_ADDR_bif_slave_rw_intr_mask 64
#define REG_WR_ADDR_bif_slave_rw_intr_mask 64
/* Register rw_ack_intr, scope bif_slave, type rw */
typedef struct {
unsigned int bus_release : 1;
unsigned int bus_acquire : 1;
unsigned int dummy1 : 30;
} reg_bif_slave_rw_ack_intr;
#define REG_RD_ADDR_bif_slave_rw_ack_intr 68
#define REG_WR_ADDR_bif_slave_rw_ack_intr 68
/* Register r_intr, scope bif_slave, type r */
typedef struct {
unsigned int bus_release : 1;
unsigned int bus_acquire : 1;
unsigned int dummy1 : 30;
} reg_bif_slave_r_intr;
#define REG_RD_ADDR_bif_slave_r_intr 72
/* Register r_masked_intr, scope bif_slave, type r */
typedef struct {
unsigned int bus_release : 1;
unsigned int bus_acquire : 1;
unsigned int dummy1 : 30;
} reg_bif_slave_r_masked_intr;
#define REG_RD_ADDR_bif_slave_r_masked_intr 76
/* Constants */
enum {
regk_bif_slave_active_hi = 0x00000003,
regk_bif_slave_active_lo = 0x00000002,
regk_bif_slave_addr = 0x00000000,
regk_bif_slave_always = 0x00000001,
regk_bif_slave_at_idle = 0x00000002,
regk_bif_slave_burst_end = 0x00000003,
regk_bif_slave_dma = 0x00000001,
regk_bif_slave_hi = 0x00000003,
regk_bif_slave_inv = 0x00000001,
regk_bif_slave_lo = 0x00000002,
regk_bif_slave_local = 0x00000001,
regk_bif_slave_master = 0x00000000,
regk_bif_slave_mode_reg = 0x00000001,
regk_bif_slave_no = 0x00000000,
regk_bif_slave_norm = 0x00000000,
regk_bif_slave_on_access = 0x00000000,
regk_bif_slave_rw_arb_cfg_default = 0x00000000,
regk_bif_slave_rw_ch0_cfg_default = 0x00000000,
regk_bif_slave_rw_ch1_cfg_default = 0x00000000,
regk_bif_slave_rw_ch2_cfg_default = 0x00000000,
regk_bif_slave_rw_ch3_cfg_default = 0x00000000,
regk_bif_slave_rw_intr_mask_default = 0x00000000,
regk_bif_slave_rw_slave_cfg_default = 0x00000000,
regk_bif_slave_shared = 0x00000000,
regk_bif_slave_slave = 0x00000001,
regk_bif_slave_t0ns = 0x00000003,
regk_bif_slave_t10ns = 0x00000002,
regk_bif_slave_t20ns = 0x00000003,
regk_bif_slave_t30ns = 0x00000002,
regk_bif_slave_t40ns = 0x00000001,
regk_bif_slave_t50ns = 0x00000000,
regk_bif_slave_yes = 0x00000001,
regk_bif_slave_z = 0x00000004
};
#endif /* __bif_slave_defs_h */

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#ifndef __config_defs_h
#define __config_defs_h
/*
* This file is autogenerated from
* file: ../../rtl/config_regs.r
* id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
* last modfied: Thu Mar 4 12:34:39 2004
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r
* id: $Id: config_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope config */
/* Register r_bootsel, scope config, type r */
typedef struct {
unsigned int boot_mode : 3;
unsigned int full_duplex : 1;
unsigned int user : 1;
unsigned int pll : 1;
unsigned int flash_bw : 1;
unsigned int dummy1 : 25;
} reg_config_r_bootsel;
#define REG_RD_ADDR_config_r_bootsel 0
/* Register rw_clk_ctrl, scope config, type rw */
typedef struct {
unsigned int pll : 1;
unsigned int cpu : 1;
unsigned int iop : 1;
unsigned int dma01_eth0 : 1;
unsigned int dma23 : 1;
unsigned int dma45 : 1;
unsigned int dma67 : 1;
unsigned int dma89_strcop : 1;
unsigned int bif : 1;
unsigned int fix_io : 1;
unsigned int dummy1 : 22;
} reg_config_rw_clk_ctrl;
#define REG_RD_ADDR_config_rw_clk_ctrl 4
#define REG_WR_ADDR_config_rw_clk_ctrl 4
/* Register rw_pad_ctrl, scope config, type rw */
typedef struct {
unsigned int usb_susp : 1;
unsigned int phyrst_n : 1;
unsigned int dummy1 : 30;
} reg_config_rw_pad_ctrl;
#define REG_RD_ADDR_config_rw_pad_ctrl 8
#define REG_WR_ADDR_config_rw_pad_ctrl 8
/* Constants */
enum {
regk_config_bw16 = 0x00000000,
regk_config_bw32 = 0x00000001,
regk_config_master = 0x00000005,
regk_config_nand = 0x00000003,
regk_config_net_rx = 0x00000001,
regk_config_net_tx_rx = 0x00000002,
regk_config_no = 0x00000000,
regk_config_none = 0x00000007,
regk_config_nor = 0x00000000,
regk_config_rw_clk_ctrl_default = 0x00000002,
regk_config_rw_pad_ctrl_default = 0x00000000,
regk_config_ser = 0x00000004,
regk_config_slave = 0x00000006,
regk_config_yes = 0x00000001
};
#endif /* __config_defs_h */

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/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
from ../../inst/crisp/doc/cpu_vect.r
version . */
#ifndef _______INST_CRISP_DOC_CPU_VECT_R
#define _______INST_CRISP_DOC_CPU_VECT_R
#define NMI_INTR_VECT 0x00
#define RESERVED_1_INTR_VECT 0x01
#define RESERVED_2_INTR_VECT 0x02
#define SINGLE_STEP_INTR_VECT 0x03
#define INSTR_TLB_REFILL_INTR_VECT 0x04
#define INSTR_TLB_INV_INTR_VECT 0x05
#define INSTR_TLB_ACC_INTR_VECT 0x06
#define TLB_EX_INTR_VECT 0x07
#define DATA_TLB_REFILL_INTR_VECT 0x08
#define DATA_TLB_INV_INTR_VECT 0x09
#define DATA_TLB_ACC_INTR_VECT 0x0a
#define DATA_TLB_WE_INTR_VECT 0x0b
#define HW_BP_INTR_VECT 0x0c
#define RESERVED_D_INTR_VECT 0x0d
#define RESERVED_E_INTR_VECT 0x0e
#define RESERVED_F_INTR_VECT 0x0f
#define BREAK_0_INTR_VECT 0x10
#define BREAK_1_INTR_VECT 0x11
#define BREAK_2_INTR_VECT 0x12
#define BREAK_3_INTR_VECT 0x13
#define BREAK_4_INTR_VECT 0x14
#define BREAK_5_INTR_VECT 0x15
#define BREAK_6_INTR_VECT 0x16
#define BREAK_7_INTR_VECT 0x17
#define BREAK_8_INTR_VECT 0x18
#define BREAK_9_INTR_VECT 0x19
#define BREAK_10_INTR_VECT 0x1a
#define BREAK_11_INTR_VECT 0x1b
#define BREAK_12_INTR_VECT 0x1c
#define BREAK_13_INTR_VECT 0x1d
#define BREAK_14_INTR_VECT 0x1e
#define BREAK_15_INTR_VECT 0x1f
#define MULTIPLE_INTR_VECT 0x30
#endif

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/*
* DMA C definitions and help macros
*
*/
#ifndef dma_h
#define dma_h
/* registers */ /* Really needed, since both are listed in sw.list? */
#include <arch/hwregs/dma_defs.h>
/* descriptors */
// ------------------------------------------------------------ dma_descr_group
typedef struct dma_descr_group {
struct dma_descr_group *next;
unsigned eol : 1;
unsigned tol : 1;
unsigned bol : 1;
unsigned : 1;
unsigned intr : 1;
unsigned : 2;
unsigned en : 1;
unsigned : 7;
unsigned dis : 1;
unsigned md : 16;
struct dma_descr_group *up;
union {
struct dma_descr_context *context;
struct dma_descr_group *group;
} down;
} dma_descr_group;
// ---------------------------------------------------------- dma_descr_context
typedef struct dma_descr_context {
struct dma_descr_context *next;
unsigned eol : 1;
unsigned : 3;
unsigned intr : 1;
unsigned : 1;
unsigned store_mode : 1;
unsigned en : 1;
unsigned : 7;
unsigned dis : 1;
unsigned md0 : 16;
unsigned md1;
unsigned md2;
unsigned md3;
unsigned md4;
struct dma_descr_data *saved_data;
char *saved_data_buf;
} dma_descr_context;
// ------------------------------------------------------------- dma_descr_data
typedef struct dma_descr_data {
struct dma_descr_data *next;
char *buf;
unsigned eol : 1;
unsigned : 2;
unsigned out_eop : 1;
unsigned intr : 1;
unsigned wait : 1;
unsigned : 2;
unsigned : 3;
unsigned in_eop : 1;
unsigned : 4;
unsigned md : 16;
char *after;
} dma_descr_data;
// --------------------------------------------------------------------- macros
// enable DMA channel
#define DMA_ENABLE( inst ) \
do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\
e.en = regk_dma_yes; \
REG_WR( dma, inst, rw_cfg, e); } while( 0 )
// reset DMA channel
#define DMA_RESET( inst ) \
do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\
r.en = regk_dma_no; \
REG_WR( dma, inst, rw_cfg, r); } while( 0 )
// stop DMA channel
#define DMA_STOP( inst ) \
do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\
s.stop = regk_dma_yes; \
REG_WR( dma, inst, rw_cfg, s); } while( 0 )
// continue DMA channel operation
#define DMA_CONTINUE( inst ) \
do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\
c.stop = regk_dma_no; \
REG_WR( dma, inst, rw_cfg, c); } while( 0 )
// give stream command
#define DMA_WR_CMD( inst, cmd_par ) \
do { reg_dma_rw_stream_cmd __x = {0}; \
do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \
__x.cmd = (cmd_par); \
REG_WR(dma, inst, rw_stream_cmd, __x); \
} while (0)
// load: g,c,d:burst
#define DMA_START_GROUP( inst, group_descr ) \
do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \
DMA_WR_CMD( inst, regk_dma_load_g ); \
DMA_WR_CMD( inst, regk_dma_load_c ); \
DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
} while( 0 )
// load: c,d:burst
#define DMA_START_CONTEXT( inst, ctx_descr ) \
do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \
DMA_WR_CMD( inst, regk_dma_load_c ); \
DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
} while( 0 )
// if the DMA is at the end of the data list, the last data descr is reloaded
#define DMA_CONTINUE_DATA( inst ) \
do { reg_dma_rw_cmd c = {0}; \
c.cont_data = regk_dma_yes;\
REG_WR( dma, inst, rw_cmd, c ); } while( 0 )
#endif

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#ifndef __dma_defs_h
#define __dma_defs_h
/*
* This file is autogenerated from
* file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
* id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
* last modfied: Mon Apr 11 16:06:51 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
* id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope dma */
/* Register rw_data, scope dma, type rw */
typedef unsigned int reg_dma_rw_data;
#define REG_RD_ADDR_dma_rw_data 0
#define REG_WR_ADDR_dma_rw_data 0
/* Register rw_data_next, scope dma, type rw */
typedef unsigned int reg_dma_rw_data_next;
#define REG_RD_ADDR_dma_rw_data_next 4
#define REG_WR_ADDR_dma_rw_data_next 4
/* Register rw_data_buf, scope dma, type rw */
typedef unsigned int reg_dma_rw_data_buf;
#define REG_RD_ADDR_dma_rw_data_buf 8
#define REG_WR_ADDR_dma_rw_data_buf 8
/* Register rw_data_ctrl, scope dma, type rw */
typedef struct {
unsigned int eol : 1;
unsigned int dummy1 : 2;
unsigned int out_eop : 1;
unsigned int intr : 1;
unsigned int wait : 1;
unsigned int dummy2 : 26;
} reg_dma_rw_data_ctrl;
#define REG_RD_ADDR_dma_rw_data_ctrl 12
#define REG_WR_ADDR_dma_rw_data_ctrl 12
/* Register rw_data_stat, scope dma, type rw */
typedef struct {
unsigned int dummy1 : 3;
unsigned int in_eop : 1;
unsigned int dummy2 : 28;
} reg_dma_rw_data_stat;
#define REG_RD_ADDR_dma_rw_data_stat 16
#define REG_WR_ADDR_dma_rw_data_stat 16
/* Register rw_data_md, scope dma, type rw */
typedef struct {
unsigned int md : 16;
unsigned int dummy1 : 16;
} reg_dma_rw_data_md;
#define REG_RD_ADDR_dma_rw_data_md 20
#define REG_WR_ADDR_dma_rw_data_md 20
/* Register rw_data_md_s, scope dma, type rw */
typedef struct {
unsigned int md_s : 16;
unsigned int dummy1 : 16;
} reg_dma_rw_data_md_s;
#define REG_RD_ADDR_dma_rw_data_md_s 24
#define REG_WR_ADDR_dma_rw_data_md_s 24
/* Register rw_data_after, scope dma, type rw */
typedef unsigned int reg_dma_rw_data_after;
#define REG_RD_ADDR_dma_rw_data_after 28
#define REG_WR_ADDR_dma_rw_data_after 28
/* Register rw_ctxt, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt;
#define REG_RD_ADDR_dma_rw_ctxt 32
#define REG_WR_ADDR_dma_rw_ctxt 32
/* Register rw_ctxt_next, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_next;
#define REG_RD_ADDR_dma_rw_ctxt_next 36
#define REG_WR_ADDR_dma_rw_ctxt_next 36
/* Register rw_ctxt_ctrl, scope dma, type rw */
typedef struct {
unsigned int eol : 1;
unsigned int dummy1 : 3;
unsigned int intr : 1;
unsigned int dummy2 : 1;
unsigned int store_mode : 1;
unsigned int en : 1;
unsigned int dummy3 : 24;
} reg_dma_rw_ctxt_ctrl;
#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40
#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40
/* Register rw_ctxt_stat, scope dma, type rw */
typedef struct {
unsigned int dummy1 : 7;
unsigned int dis : 1;
unsigned int dummy2 : 24;
} reg_dma_rw_ctxt_stat;
#define REG_RD_ADDR_dma_rw_ctxt_stat 44
#define REG_WR_ADDR_dma_rw_ctxt_stat 44
/* Register rw_ctxt_md0, scope dma, type rw */
typedef struct {
unsigned int md0 : 16;
unsigned int dummy1 : 16;
} reg_dma_rw_ctxt_md0;
#define REG_RD_ADDR_dma_rw_ctxt_md0 48
#define REG_WR_ADDR_dma_rw_ctxt_md0 48
/* Register rw_ctxt_md0_s, scope dma, type rw */
typedef struct {
unsigned int md0_s : 16;
unsigned int dummy1 : 16;
} reg_dma_rw_ctxt_md0_s;
#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52
#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52
/* Register rw_ctxt_md1, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md1;
#define REG_RD_ADDR_dma_rw_ctxt_md1 56
#define REG_WR_ADDR_dma_rw_ctxt_md1 56
/* Register rw_ctxt_md1_s, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md1_s;
#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60
#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60
/* Register rw_ctxt_md2, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md2;
#define REG_RD_ADDR_dma_rw_ctxt_md2 64
#define REG_WR_ADDR_dma_rw_ctxt_md2 64
/* Register rw_ctxt_md2_s, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md2_s;
#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68
#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68
/* Register rw_ctxt_md3, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md3;
#define REG_RD_ADDR_dma_rw_ctxt_md3 72
#define REG_WR_ADDR_dma_rw_ctxt_md3 72
/* Register rw_ctxt_md3_s, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md3_s;
#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76
#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76
/* Register rw_ctxt_md4, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md4;
#define REG_RD_ADDR_dma_rw_ctxt_md4 80
#define REG_WR_ADDR_dma_rw_ctxt_md4 80
/* Register rw_ctxt_md4_s, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md4_s;
#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84
#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84
/* Register rw_saved_data, scope dma, type rw */
typedef unsigned int reg_dma_rw_saved_data;
#define REG_RD_ADDR_dma_rw_saved_data 88
#define REG_WR_ADDR_dma_rw_saved_data 88
/* Register rw_saved_data_buf, scope dma, type rw */
typedef unsigned int reg_dma_rw_saved_data_buf;
#define REG_RD_ADDR_dma_rw_saved_data_buf 92
#define REG_WR_ADDR_dma_rw_saved_data_buf 92
/* Register rw_group, scope dma, type rw */
typedef unsigned int reg_dma_rw_group;
#define REG_RD_ADDR_dma_rw_group 96
#define REG_WR_ADDR_dma_rw_group 96
/* Register rw_group_next, scope dma, type rw */
typedef unsigned int reg_dma_rw_group_next;
#define REG_RD_ADDR_dma_rw_group_next 100
#define REG_WR_ADDR_dma_rw_group_next 100
/* Register rw_group_ctrl, scope dma, type rw */
typedef struct {
unsigned int eol : 1;
unsigned int tol : 1;
unsigned int bol : 1;
unsigned int dummy1 : 1;
unsigned int intr : 1;
unsigned int dummy2 : 2;
unsigned int en : 1;
unsigned int dummy3 : 24;
} reg_dma_rw_group_ctrl;
#define REG_RD_ADDR_dma_rw_group_ctrl 104
#define REG_WR_ADDR_dma_rw_group_ctrl 104
/* Register rw_group_stat, scope dma, type rw */
typedef struct {
unsigned int dummy1 : 7;
unsigned int dis : 1;
unsigned int dummy2 : 24;
} reg_dma_rw_group_stat;
#define REG_RD_ADDR_dma_rw_group_stat 108
#define REG_WR_ADDR_dma_rw_group_stat 108
/* Register rw_group_md, scope dma, type rw */
typedef struct {
unsigned int md : 16;
unsigned int dummy1 : 16;
} reg_dma_rw_group_md;
#define REG_RD_ADDR_dma_rw_group_md 112
#define REG_WR_ADDR_dma_rw_group_md 112
/* Register rw_group_md_s, scope dma, type rw */
typedef struct {
unsigned int md_s : 16;
unsigned int dummy1 : 16;
} reg_dma_rw_group_md_s;
#define REG_RD_ADDR_dma_rw_group_md_s 116
#define REG_WR_ADDR_dma_rw_group_md_s 116
/* Register rw_group_up, scope dma, type rw */
typedef unsigned int reg_dma_rw_group_up;
#define REG_RD_ADDR_dma_rw_group_up 120
#define REG_WR_ADDR_dma_rw_group_up 120
/* Register rw_group_down, scope dma, type rw */
typedef unsigned int reg_dma_rw_group_down;
#define REG_RD_ADDR_dma_rw_group_down 124
#define REG_WR_ADDR_dma_rw_group_down 124
/* Register rw_cmd, scope dma, type rw */
typedef struct {
unsigned int cont_data : 1;
unsigned int dummy1 : 31;
} reg_dma_rw_cmd;
#define REG_RD_ADDR_dma_rw_cmd 128
#define REG_WR_ADDR_dma_rw_cmd 128
/* Register rw_cfg, scope dma, type rw */
typedef struct {
unsigned int en : 1;
unsigned int stop : 1;
unsigned int dummy1 : 30;
} reg_dma_rw_cfg;
#define REG_RD_ADDR_dma_rw_cfg 132
#define REG_WR_ADDR_dma_rw_cfg 132
/* Register rw_stat, scope dma, type rw */
typedef struct {
unsigned int mode : 5;
unsigned int list_state : 3;
unsigned int stream_cmd_src : 8;
unsigned int dummy1 : 8;
unsigned int buf : 8;
} reg_dma_rw_stat;
#define REG_RD_ADDR_dma_rw_stat 136
#define REG_WR_ADDR_dma_rw_stat 136
/* Register rw_intr_mask, scope dma, type rw */
typedef struct {
unsigned int group : 1;
unsigned int ctxt : 1;
unsigned int data : 1;
unsigned int in_eop : 1;
unsigned int stream_cmd : 1;
unsigned int dummy1 : 27;
} reg_dma_rw_intr_mask;
#define REG_RD_ADDR_dma_rw_intr_mask 140
#define REG_WR_ADDR_dma_rw_intr_mask 140
/* Register rw_ack_intr, scope dma, type rw */
typedef struct {
unsigned int group : 1;
unsigned int ctxt : 1;
unsigned int data : 1;
unsigned int in_eop : 1;
unsigned int stream_cmd : 1;
unsigned int dummy1 : 27;
} reg_dma_rw_ack_intr;
#define REG_RD_ADDR_dma_rw_ack_intr 144
#define REG_WR_ADDR_dma_rw_ack_intr 144
/* Register r_intr, scope dma, type r */
typedef struct {
unsigned int group : 1;
unsigned int ctxt : 1;
unsigned int data : 1;
unsigned int in_eop : 1;
unsigned int stream_cmd : 1;
unsigned int dummy1 : 27;
} reg_dma_r_intr;
#define REG_RD_ADDR_dma_r_intr 148
/* Register r_masked_intr, scope dma, type r */
typedef struct {
unsigned int group : 1;
unsigned int ctxt : 1;
unsigned int data : 1;
unsigned int in_eop : 1;
unsigned int stream_cmd : 1;
unsigned int dummy1 : 27;
} reg_dma_r_masked_intr;
#define REG_RD_ADDR_dma_r_masked_intr 152
/* Register rw_stream_cmd, scope dma, type rw */
typedef struct {
unsigned int cmd : 10;
unsigned int dummy1 : 6;
unsigned int n : 8;
unsigned int dummy2 : 7;
unsigned int busy : 1;
} reg_dma_rw_stream_cmd;
#define REG_RD_ADDR_dma_rw_stream_cmd 156
#define REG_WR_ADDR_dma_rw_stream_cmd 156
/* Constants */
enum {
regk_dma_ack_pkt = 0x00000100,
regk_dma_anytime = 0x00000001,
regk_dma_array = 0x00000008,
regk_dma_burst = 0x00000020,
regk_dma_client = 0x00000002,
regk_dma_copy_next = 0x00000010,
regk_dma_copy_up = 0x00000020,
regk_dma_data_at_eol = 0x00000001,
regk_dma_dis_c = 0x00000010,
regk_dma_dis_g = 0x00000020,
regk_dma_idle = 0x00000001,
regk_dma_intern = 0x00000004,
regk_dma_load_c = 0x00000200,
regk_dma_load_c_n = 0x00000280,
regk_dma_load_c_next = 0x00000240,
regk_dma_load_d = 0x00000140,
regk_dma_load_g = 0x00000300,
regk_dma_load_g_down = 0x000003c0,
regk_dma_load_g_next = 0x00000340,
regk_dma_load_g_up = 0x00000380,
regk_dma_next_en = 0x00000010,
regk_dma_next_pkt = 0x00000010,
regk_dma_no = 0x00000000,
regk_dma_only_at_wait = 0x00000000,
regk_dma_restore = 0x00000020,
regk_dma_rst = 0x00000001,
regk_dma_running = 0x00000004,
regk_dma_rw_cfg_default = 0x00000000,
regk_dma_rw_cmd_default = 0x00000000,
regk_dma_rw_intr_mask_default = 0x00000000,
regk_dma_rw_stat_default = 0x00000101,
regk_dma_rw_stream_cmd_default = 0x00000000,
regk_dma_save_down = 0x00000020,
regk_dma_save_up = 0x00000020,
regk_dma_set_reg = 0x00000050,
regk_dma_set_w_size1 = 0x00000190,
regk_dma_set_w_size2 = 0x000001a0,
regk_dma_set_w_size4 = 0x000001c0,
regk_dma_stopped = 0x00000002,
regk_dma_store_c = 0x00000002,
regk_dma_store_descr = 0x00000000,
regk_dma_store_g = 0x00000004,
regk_dma_store_md = 0x00000001,
regk_dma_sw = 0x00000008,
regk_dma_update_down = 0x00000020,
regk_dma_yes = 0x00000001
};
#endif /* __dma_defs_h */

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#ifndef __eth_defs_h
#define __eth_defs_h
/*
* This file is autogenerated from
* file: eth.r
* id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp
* last modfied: Mon Jan 9 06:06:41 2006
*
* by /n/asic/design/tools/rdesc/rdes2c eth.r
* id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope eth */
/* Register rw_ma0_lo, scope eth, type rw */
typedef struct {
unsigned int addr : 32;
} reg_eth_rw_ma0_lo;
#define REG_RD_ADDR_eth_rw_ma0_lo 0
#define REG_WR_ADDR_eth_rw_ma0_lo 0
/* Register rw_ma0_hi, scope eth, type rw */
typedef struct {
unsigned int addr : 16;
unsigned int dummy1 : 16;
} reg_eth_rw_ma0_hi;
#define REG_RD_ADDR_eth_rw_ma0_hi 4
#define REG_WR_ADDR_eth_rw_ma0_hi 4
/* Register rw_ma1_lo, scope eth, type rw */
typedef struct {
unsigned int addr : 32;
} reg_eth_rw_ma1_lo;
#define REG_RD_ADDR_eth_rw_ma1_lo 8
#define REG_WR_ADDR_eth_rw_ma1_lo 8
/* Register rw_ma1_hi, scope eth, type rw */
typedef struct {
unsigned int addr : 16;
unsigned int dummy1 : 16;
} reg_eth_rw_ma1_hi;
#define REG_RD_ADDR_eth_rw_ma1_hi 12
#define REG_WR_ADDR_eth_rw_ma1_hi 12
/* Register rw_ga_lo, scope eth, type rw */
typedef struct {
unsigned int tbl : 32;
} reg_eth_rw_ga_lo;
#define REG_RD_ADDR_eth_rw_ga_lo 16
#define REG_WR_ADDR_eth_rw_ga_lo 16
/* Register rw_ga_hi, scope eth, type rw */
typedef struct {
unsigned int tbl : 32;
} reg_eth_rw_ga_hi;
#define REG_RD_ADDR_eth_rw_ga_hi 20
#define REG_WR_ADDR_eth_rw_ga_hi 20
/* Register rw_gen_ctrl, scope eth, type rw */
typedef struct {
unsigned int en : 1;
unsigned int phy : 2;
unsigned int protocol : 1;
unsigned int loopback : 1;
unsigned int flow_ctrl : 1;
unsigned int gtxclk_out : 1;
unsigned int phyrst_n : 1;
unsigned int dummy1 : 24;
} reg_eth_rw_gen_ctrl;
#define REG_RD_ADDR_eth_rw_gen_ctrl 24
#define REG_WR_ADDR_eth_rw_gen_ctrl 24
/* Register rw_rec_ctrl, scope eth, type rw */
typedef struct {
unsigned int ma0 : 1;
unsigned int ma1 : 1;
unsigned int individual : 1;
unsigned int broadcast : 1;
unsigned int undersize : 1;
unsigned int oversize : 1;
unsigned int bad_crc : 1;
unsigned int duplex : 1;
unsigned int max_size : 16;
unsigned int dummy1 : 8;
} reg_eth_rw_rec_ctrl;
#define REG_RD_ADDR_eth_rw_rec_ctrl 28
#define REG_WR_ADDR_eth_rw_rec_ctrl 28
/* Register rw_tr_ctrl, scope eth, type rw */
typedef struct {
unsigned int crc : 1;
unsigned int pad : 1;
unsigned int retry : 1;
unsigned int ignore_col : 1;
unsigned int cancel : 1;
unsigned int hsh_delay : 1;
unsigned int ignore_crs : 1;
unsigned int carrier_ext : 1;
unsigned int dummy1 : 24;
} reg_eth_rw_tr_ctrl;
#define REG_RD_ADDR_eth_rw_tr_ctrl 32
#define REG_WR_ADDR_eth_rw_tr_ctrl 32
/* Register rw_clr_err, scope eth, type rw */
typedef struct {
unsigned int clr : 1;
unsigned int dummy1 : 31;
} reg_eth_rw_clr_err;
#define REG_RD_ADDR_eth_rw_clr_err 36
#define REG_WR_ADDR_eth_rw_clr_err 36
/* Register rw_mgm_ctrl, scope eth, type rw */
typedef struct {
unsigned int mdio : 1;
unsigned int mdoe : 1;
unsigned int mdc : 1;
unsigned int dummy1 : 29;
} reg_eth_rw_mgm_ctrl;
#define REG_RD_ADDR_eth_rw_mgm_ctrl 40
#define REG_WR_ADDR_eth_rw_mgm_ctrl 40
/* Register r_stat, scope eth, type r */
typedef struct {
unsigned int mdio : 1;
unsigned int exc_col : 1;
unsigned int urun : 1;
unsigned int clk_125 : 1;
unsigned int dummy1 : 28;
} reg_eth_r_stat;
#define REG_RD_ADDR_eth_r_stat 44
/* Register rs_rec_cnt, scope eth, type rs */
typedef struct {
unsigned int crc_err : 8;
unsigned int align_err : 8;
unsigned int oversize : 8;
unsigned int congestion : 8;
} reg_eth_rs_rec_cnt;
#define REG_RD_ADDR_eth_rs_rec_cnt 48
/* Register r_rec_cnt, scope eth, type r */
typedef struct {
unsigned int crc_err : 8;
unsigned int align_err : 8;
unsigned int oversize : 8;
unsigned int congestion : 8;
} reg_eth_r_rec_cnt;
#define REG_RD_ADDR_eth_r_rec_cnt 52
/* Register rs_tr_cnt, scope eth, type rs */
typedef struct {
unsigned int single_col : 8;
unsigned int mult_col : 8;
unsigned int late_col : 8;
unsigned int deferred : 8;
} reg_eth_rs_tr_cnt;
#define REG_RD_ADDR_eth_rs_tr_cnt 56
/* Register r_tr_cnt, scope eth, type r */
typedef struct {
unsigned int single_col : 8;
unsigned int mult_col : 8;
unsigned int late_col : 8;
unsigned int deferred : 8;
} reg_eth_r_tr_cnt;
#define REG_RD_ADDR_eth_r_tr_cnt 60
/* Register rs_phy_cnt, scope eth, type rs */
typedef struct {
unsigned int carrier_loss : 8;
unsigned int sqe_err : 8;
unsigned int dummy1 : 16;
} reg_eth_rs_phy_cnt;
#define REG_RD_ADDR_eth_rs_phy_cnt 64
/* Register r_phy_cnt, scope eth, type r */
typedef struct {
unsigned int carrier_loss : 8;
unsigned int sqe_err : 8;
unsigned int dummy1 : 16;
} reg_eth_r_phy_cnt;
#define REG_RD_ADDR_eth_r_phy_cnt 68
/* Register rw_test_ctrl, scope eth, type rw */
typedef struct {
unsigned int snmp_inc : 1;
unsigned int snmp : 1;
unsigned int backoff : 1;
unsigned int dummy1 : 29;
} reg_eth_rw_test_ctrl;
#define REG_RD_ADDR_eth_rw_test_ctrl 72
#define REG_WR_ADDR_eth_rw_test_ctrl 72
/* Register rw_intr_mask, scope eth, type rw */
typedef struct {
unsigned int crc : 1;
unsigned int align : 1;
unsigned int oversize : 1;
unsigned int congestion : 1;
unsigned int single_col : 1;
unsigned int mult_col : 1;
unsigned int late_col : 1;
unsigned int deferred : 1;
unsigned int carrier_loss : 1;
unsigned int sqe_test_err : 1;
unsigned int orun : 1;
unsigned int urun : 1;
unsigned int exc_col : 1;
unsigned int mdio : 1;
unsigned int dummy1 : 18;
} reg_eth_rw_intr_mask;
#define REG_RD_ADDR_eth_rw_intr_mask 76
#define REG_WR_ADDR_eth_rw_intr_mask 76
/* Register rw_ack_intr, scope eth, type rw */
typedef struct {
unsigned int crc : 1;
unsigned int align : 1;
unsigned int oversize : 1;
unsigned int congestion : 1;
unsigned int single_col : 1;
unsigned int mult_col : 1;
unsigned int late_col : 1;
unsigned int deferred : 1;
unsigned int carrier_loss : 1;
unsigned int sqe_test_err : 1;
unsigned int orun : 1;
unsigned int urun : 1;
unsigned int exc_col : 1;
unsigned int mdio : 1;
unsigned int dummy1 : 18;
} reg_eth_rw_ack_intr;
#define REG_RD_ADDR_eth_rw_ack_intr 80
#define REG_WR_ADDR_eth_rw_ack_intr 80
/* Register r_intr, scope eth, type r */
typedef struct {
unsigned int crc : 1;
unsigned int align : 1;
unsigned int oversize : 1;
unsigned int congestion : 1;
unsigned int single_col : 1;
unsigned int mult_col : 1;
unsigned int late_col : 1;
unsigned int deferred : 1;
unsigned int carrier_loss : 1;
unsigned int sqe_test_err : 1;
unsigned int orun : 1;
unsigned int urun : 1;
unsigned int exc_col : 1;
unsigned int mdio : 1;
unsigned int dummy1 : 18;
} reg_eth_r_intr;
#define REG_RD_ADDR_eth_r_intr 84
/* Register r_masked_intr, scope eth, type r */
typedef struct {
unsigned int crc : 1;
unsigned int align : 1;
unsigned int oversize : 1;
unsigned int congestion : 1;
unsigned int single_col : 1;
unsigned int mult_col : 1;
unsigned int late_col : 1;
unsigned int deferred : 1;
unsigned int carrier_loss : 1;
unsigned int sqe_test_err : 1;
unsigned int orun : 1;
unsigned int urun : 1;
unsigned int exc_col : 1;
unsigned int mdio : 1;
unsigned int dummy1 : 18;
} reg_eth_r_masked_intr;
#define REG_RD_ADDR_eth_r_masked_intr 88
/* Constants */
enum {
regk_eth_discard = 0x00000000,
regk_eth_ether = 0x00000000,
regk_eth_full = 0x00000001,
regk_eth_gmii = 0x00000003,
regk_eth_gtxclk = 0x00000001,
regk_eth_half = 0x00000000,
regk_eth_hsh = 0x00000001,
regk_eth_mii = 0x00000001,
regk_eth_mii_arec = 0x00000002,
regk_eth_mii_clk = 0x00000000,
regk_eth_no = 0x00000000,
regk_eth_phyrst = 0x00000000,
regk_eth_rec = 0x00000001,
regk_eth_rw_ga_hi_default = 0x00000000,
regk_eth_rw_ga_lo_default = 0x00000000,
regk_eth_rw_gen_ctrl_default = 0x00000000,
regk_eth_rw_intr_mask_default = 0x00000000,
regk_eth_rw_ma0_hi_default = 0x00000000,
regk_eth_rw_ma0_lo_default = 0x00000000,
regk_eth_rw_ma1_hi_default = 0x00000000,
regk_eth_rw_ma1_lo_default = 0x00000000,
regk_eth_rw_mgm_ctrl_default = 0x00000000,
regk_eth_rw_test_ctrl_default = 0x00000000,
regk_eth_size1518 = 0x000005ee,
regk_eth_size1522 = 0x000005f2,
regk_eth_yes = 0x00000001
};
#endif /* __eth_defs_h */

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#ifndef __extmem_defs_h
#define __extmem_defs_h
/*
* This file is autogenerated from
* file: ../../inst/ext_mem/mod/extmem_regs.r
* id: extmem_regs.r,v 1.1 2004/02/16 13:29:30 np Exp
* last modfied: Tue Mar 30 22:26:21 2004
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r
* id: $Id: extmem_defs.h,v 1.5 2004/06/04 07:15:33 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope extmem */
/* Register rw_cse0_cfg, scope extmem, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int mode : 1;
unsigned int erc_en : 1;
unsigned int dummy1 : 6;
unsigned int size : 3;
unsigned int log : 1;
unsigned int en : 1;
} reg_extmem_rw_cse0_cfg;
#define REG_RD_ADDR_extmem_rw_cse0_cfg 0
#define REG_WR_ADDR_extmem_rw_cse0_cfg 0
/* Register rw_cse1_cfg, scope extmem, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int mode : 1;
unsigned int erc_en : 1;
unsigned int dummy1 : 6;
unsigned int size : 3;
unsigned int log : 1;
unsigned int en : 1;
} reg_extmem_rw_cse1_cfg;
#define REG_RD_ADDR_extmem_rw_cse1_cfg 4
#define REG_WR_ADDR_extmem_rw_cse1_cfg 4
/* Register rw_csr0_cfg, scope extmem, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int mode : 1;
unsigned int erc_en : 1;
unsigned int dummy1 : 6;
unsigned int size : 3;
unsigned int log : 1;
unsigned int en : 1;
} reg_extmem_rw_csr0_cfg;
#define REG_RD_ADDR_extmem_rw_csr0_cfg 8
#define REG_WR_ADDR_extmem_rw_csr0_cfg 8
/* Register rw_csr1_cfg, scope extmem, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int mode : 1;
unsigned int erc_en : 1;
unsigned int dummy1 : 6;
unsigned int size : 3;
unsigned int log : 1;
unsigned int en : 1;
} reg_extmem_rw_csr1_cfg;
#define REG_RD_ADDR_extmem_rw_csr1_cfg 12
#define REG_WR_ADDR_extmem_rw_csr1_cfg 12
/* Register rw_csp0_cfg, scope extmem, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int mode : 1;
unsigned int erc_en : 1;
unsigned int dummy1 : 6;
unsigned int size : 3;
unsigned int log : 1;
unsigned int en : 1;
} reg_extmem_rw_csp0_cfg;
#define REG_RD_ADDR_extmem_rw_csp0_cfg 16
#define REG_WR_ADDR_extmem_rw_csp0_cfg 16
/* Register rw_csp1_cfg, scope extmem, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int mode : 1;
unsigned int erc_en : 1;
unsigned int dummy1 : 6;
unsigned int size : 3;
unsigned int log : 1;
unsigned int en : 1;
} reg_extmem_rw_csp1_cfg;
#define REG_RD_ADDR_extmem_rw_csp1_cfg 20
#define REG_WR_ADDR_extmem_rw_csp1_cfg 20
/* Register rw_csp2_cfg, scope extmem, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int mode : 1;
unsigned int erc_en : 1;
unsigned int dummy1 : 6;
unsigned int size : 3;
unsigned int log : 1;
unsigned int en : 1;
} reg_extmem_rw_csp2_cfg;
#define REG_RD_ADDR_extmem_rw_csp2_cfg 24
#define REG_WR_ADDR_extmem_rw_csp2_cfg 24
/* Register rw_csp3_cfg, scope extmem, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int mode : 1;
unsigned int erc_en : 1;
unsigned int dummy1 : 6;
unsigned int size : 3;
unsigned int log : 1;
unsigned int en : 1;
} reg_extmem_rw_csp3_cfg;
#define REG_RD_ADDR_extmem_rw_csp3_cfg 28
#define REG_WR_ADDR_extmem_rw_csp3_cfg 28
/* Register rw_csp4_cfg, scope extmem, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int mode : 1;
unsigned int erc_en : 1;
unsigned int dummy1 : 6;
unsigned int size : 3;
unsigned int log : 1;
unsigned int en : 1;
} reg_extmem_rw_csp4_cfg;
#define REG_RD_ADDR_extmem_rw_csp4_cfg 32
#define REG_WR_ADDR_extmem_rw_csp4_cfg 32
/* Register rw_csp5_cfg, scope extmem, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int mode : 1;
unsigned int erc_en : 1;
unsigned int dummy1 : 6;
unsigned int size : 3;
unsigned int log : 1;
unsigned int en : 1;
} reg_extmem_rw_csp5_cfg;
#define REG_RD_ADDR_extmem_rw_csp5_cfg 36
#define REG_WR_ADDR_extmem_rw_csp5_cfg 36
/* Register rw_csp6_cfg, scope extmem, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int mode : 1;
unsigned int erc_en : 1;
unsigned int dummy1 : 6;
unsigned int size : 3;
unsigned int log : 1;
unsigned int en : 1;
} reg_extmem_rw_csp6_cfg;
#define REG_RD_ADDR_extmem_rw_csp6_cfg 40
#define REG_WR_ADDR_extmem_rw_csp6_cfg 40
/* Register rw_css_cfg, scope extmem, type rw */
typedef struct {
unsigned int lw : 6;
unsigned int ew : 3;
unsigned int zw : 3;
unsigned int aw : 2;
unsigned int dw : 2;
unsigned int ewb : 2;
unsigned int bw : 1;
unsigned int mode : 1;
unsigned int erc_en : 1;
unsigned int dummy1 : 6;
unsigned int size : 3;
unsigned int log : 1;
unsigned int en : 1;
} reg_extmem_rw_css_cfg;
#define REG_RD_ADDR_extmem_rw_css_cfg 44
#define REG_WR_ADDR_extmem_rw_css_cfg 44
/* Register rw_status_handle, scope extmem, type rw */
typedef struct {
unsigned int h : 32;
} reg_extmem_rw_status_handle;
#define REG_RD_ADDR_extmem_rw_status_handle 48
#define REG_WR_ADDR_extmem_rw_status_handle 48
/* Register rw_wait_pin, scope extmem, type rw */
typedef struct {
unsigned int val : 16;
unsigned int dummy1 : 15;
unsigned int start : 1;
} reg_extmem_rw_wait_pin;
#define REG_RD_ADDR_extmem_rw_wait_pin 52
#define REG_WR_ADDR_extmem_rw_wait_pin 52
/* Register rw_gated_csp, scope extmem, type rw */
typedef struct {
unsigned int dummy1 : 31;
unsigned int en : 1;
} reg_extmem_rw_gated_csp;
#define REG_RD_ADDR_extmem_rw_gated_csp 56
#define REG_WR_ADDR_extmem_rw_gated_csp 56
/* Constants */
enum {
regk_extmem_b16 = 0x00000001,
regk_extmem_b32 = 0x00000000,
regk_extmem_bwe = 0x00000000,
regk_extmem_cwe = 0x00000001,
regk_extmem_no = 0x00000000,
regk_extmem_rw_cse0_cfg_default = 0x000006cf,
regk_extmem_rw_cse1_cfg_default = 0x000006cf,
regk_extmem_rw_csp0_cfg_default = 0x000006cf,
regk_extmem_rw_csp1_cfg_default = 0x000006cf,
regk_extmem_rw_csp2_cfg_default = 0x000006cf,
regk_extmem_rw_csp3_cfg_default = 0x000006cf,
regk_extmem_rw_csp4_cfg_default = 0x000006cf,
regk_extmem_rw_csp5_cfg_default = 0x000006cf,
regk_extmem_rw_csp6_cfg_default = 0x000006cf,
regk_extmem_rw_csr0_cfg_default = 0x000006cf,
regk_extmem_rw_csr1_cfg_default = 0x000006cf,
regk_extmem_rw_css_cfg_default = 0x000006cf,
regk_extmem_s128KB = 0x00000000,
regk_extmem_s16MB = 0x00000005,
regk_extmem_s1MB = 0x00000001,
regk_extmem_s2MB = 0x00000002,
regk_extmem_s32MB = 0x00000006,
regk_extmem_s4MB = 0x00000003,
regk_extmem_s64MB = 0x00000007,
regk_extmem_s8MB = 0x00000004,
regk_extmem_yes = 0x00000001
};
#endif /* __extmem_defs_h */

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# $Id: Makefile,v 1.3 2004/01/07 20:34:55 johana Exp $
# Makefile to generate or copy the latest register definitions
# and related datastructures and helpermacros.
# The official place for these files is probably at:
RELEASE ?= r1_alfa5
IOPOFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/
IOPROCDIR = /n/asic/design/io/io_proc/rtl
IOPROCINCL_FILES =
IOPROCINCL_FILES2=
IOPROCINCL_FILES += iop_crc_par_defs.h
IOPROCINCL_FILES += iop_dmc_in_defs.h
IOPROCINCL_FILES += iop_dmc_out_defs.h
IOPROCINCL_FILES += iop_fifo_in_defs.h
IOPROCINCL_FILES += iop_fifo_in_xtra_defs.h
IOPROCINCL_FILES += iop_fifo_out_defs.h
IOPROCINCL_FILES += iop_fifo_out_xtra_defs.h
IOPROCINCL_FILES += iop_mpu_defs.h
IOPROCINCL_FILES2+= iop_mpu_macros.h
IOPROCINCL_FILES2+= iop_reg_space.h
IOPROCINCL_FILES += iop_sap_in_defs.h
IOPROCINCL_FILES += iop_sap_out_defs.h
IOPROCINCL_FILES += iop_scrc_in_defs.h
IOPROCINCL_FILES += iop_scrc_out_defs.h
IOPROCINCL_FILES += iop_spu_defs.h
# in guiness/
IOPROCINCL_FILES += iop_sw_cfg_defs.h
IOPROCINCL_FILES += iop_sw_cpu_defs.h
IOPROCINCL_FILES += iop_sw_mpu_defs.h
IOPROCINCL_FILES += iop_sw_spu_defs.h
#
IOPROCINCL_FILES += iop_timer_grp_defs.h
IOPROCINCL_FILES += iop_trigger_grp_defs.h
# in guiness/
IOPROCINCL_FILES += iop_version_defs.h
IOPROCASMINCL_FILES = $(patsubst %_defs.h,%_defs_asm.h,$(IOPROCINCL_FILES))
IOPROCASMINCL_FILES+= iop_reg_space_asm.h
IOPROCREGDESC =
IOPROCREGDESC += $(IOPROCDIR)/iop_crc_par.r
#IOPROCREGDESC += $(IOPROCDIR)/iop_crc_ser.r
IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_in.r
IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_out.r
IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in.r
IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in_xtra.r
IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out.r
IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out_xtra.r
IOPROCREGDESC += $(IOPROCDIR)/iop_mpu.r
IOPROCREGDESC += $(IOPROCDIR)/iop_sap_in.r
IOPROCREGDESC += $(IOPROCDIR)/iop_sap_out.r
IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_in.r
IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_out.r
IOPROCREGDESC += $(IOPROCDIR)/iop_spu.r
IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cfg.r
IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cpu.r
IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_mpu.r
IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_spu.r
IOPROCREGDESC += $(IOPROCDIR)/iop_timer_grp.r
IOPROCREGDESC += $(IOPROCDIR)/iop_trigger_grp.r
IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_version.r
RDES2C = /n/asic/bin/rdes2c
RDES2C = /n/asic/design/tools/rdesc/rdes2c
RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr
RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt
## all - Just print help - you probably want to do 'make gen'
all: help
## help - This help
help:
@grep '^## ' Makefile
## gen - Generate include files
gen: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES)
echo "INCL: $(IOPROCINCL_FILES)"
echo "INCL2: $(IOPROCINCL_FILES2)"
echo "ASMINCL: $(IOPROCASMINCL_FILES)"
# From the official location...
iop_reg_space.h: $(IOPOFFICIAL_INCDIR)/iop_reg_space.h
cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
iop_mpu_macros.h: $(IOPOFFICIAL_INCDIR)/iop_mpu_macros.h
cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
## copy - Copy files from official location
copy:
@echo "## Copying and fixing iop files ##"
@for HFILE in $(IOPROCINCL_FILES); do \
echo " $$HFILE"; \
cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
done
@for HFILE in $(IOPROCINCL_FILES2); do \
echo " $$HFILE"; \
cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
done
@echo "## Copying and fixing iop asm files ##"
@for HFILE in $(IOPROCASMINCL_FILES); do \
echo " $$HFILE"; \
cat $(IOPOFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > asm/$$HFILE; \
done
# I/O processor files:
## iop - Generate I/O processor include files
iop: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES)
iop_sw_%_defs.h: $(IOPROCDIR)/guinness/iop_sw_%.r
$(RDES2C) $<
iop_version_defs.h: $(IOPROCDIR)/guinness/iop_version.r
$(RDES2C) $<
%_defs.h: $(IOPROCDIR)/%.r
$(RDES2C) $<
%_defs_asm.h: $(IOPROCDIR)/%.r
$(RDES2C) -asm $<
iop_version_defs_asm.h: $(IOPROCDIR)/guinness/iop_version.r
$(RDES2C) -asm $<
## doc - Generate .axw files from register description.
doc: $(IOPROCREGDESC)
for RDES in $^; do \
$(RDES2TXT) $$RDES; \
done
.PHONY: axw
## %.axw - Generate the specified .axw file (doesn't work for all files
## due to inconsistent naming of .r files.
%.axw: axw
@for RDES in $(IOPROCREGDESC); do \
if echo "$$RDES" | grep $* ; then \
$(RDES2TXT) $$RDES; \
fi \
done
.PHONY: clean
## clean - Remove .h files and .axw files.
clean:
rm -rf $(IOPROCINCL_FILES) *.axw
.PHONY: cleandoc
## cleandoc - Remove .axw files.
cleandoc:
rm -rf *.axw

171
arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h Normal file
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#ifndef __iop_crc_par_defs_asm_h
#define __iop_crc_par_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_crc_par.r
* id: <not found>
* last modfied: Mon Apr 11 16:08:45 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r
* id: $Id: iop_crc_par_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_cfg, scope iop_crc_par, type rw */
#define reg_iop_crc_par_rw_cfg___mode___lsb 0
#define reg_iop_crc_par_rw_cfg___mode___width 1
#define reg_iop_crc_par_rw_cfg___mode___bit 0
#define reg_iop_crc_par_rw_cfg___crc_out___lsb 1
#define reg_iop_crc_par_rw_cfg___crc_out___width 1
#define reg_iop_crc_par_rw_cfg___crc_out___bit 1
#define reg_iop_crc_par_rw_cfg___rev_out___lsb 2
#define reg_iop_crc_par_rw_cfg___rev_out___width 1
#define reg_iop_crc_par_rw_cfg___rev_out___bit 2
#define reg_iop_crc_par_rw_cfg___inv_out___lsb 3
#define reg_iop_crc_par_rw_cfg___inv_out___width 1
#define reg_iop_crc_par_rw_cfg___inv_out___bit 3
#define reg_iop_crc_par_rw_cfg___trig___lsb 4
#define reg_iop_crc_par_rw_cfg___trig___width 2
#define reg_iop_crc_par_rw_cfg___poly___lsb 6
#define reg_iop_crc_par_rw_cfg___poly___width 3
#define reg_iop_crc_par_rw_cfg_offset 0
/* Register rw_init_crc, scope iop_crc_par, type rw */
#define reg_iop_crc_par_rw_init_crc_offset 4
/* Register rw_correct_crc, scope iop_crc_par, type rw */
#define reg_iop_crc_par_rw_correct_crc_offset 8
/* Register rw_ctrl, scope iop_crc_par, type rw */
#define reg_iop_crc_par_rw_ctrl___en___lsb 0
#define reg_iop_crc_par_rw_ctrl___en___width 1
#define reg_iop_crc_par_rw_ctrl___en___bit 0
#define reg_iop_crc_par_rw_ctrl_offset 12
/* Register rw_set_last, scope iop_crc_par, type rw */
#define reg_iop_crc_par_rw_set_last___tr_dif___lsb 0
#define reg_iop_crc_par_rw_set_last___tr_dif___width 1
#define reg_iop_crc_par_rw_set_last___tr_dif___bit 0
#define reg_iop_crc_par_rw_set_last_offset 16
/* Register rw_wr1byte, scope iop_crc_par, type rw */
#define reg_iop_crc_par_rw_wr1byte___data___lsb 0
#define reg_iop_crc_par_rw_wr1byte___data___width 8
#define reg_iop_crc_par_rw_wr1byte_offset 20
/* Register rw_wr2byte, scope iop_crc_par, type rw */
#define reg_iop_crc_par_rw_wr2byte___data___lsb 0
#define reg_iop_crc_par_rw_wr2byte___data___width 16
#define reg_iop_crc_par_rw_wr2byte_offset 24
/* Register rw_wr3byte, scope iop_crc_par, type rw */
#define reg_iop_crc_par_rw_wr3byte___data___lsb 0
#define reg_iop_crc_par_rw_wr3byte___data___width 24
#define reg_iop_crc_par_rw_wr3byte_offset 28
/* Register rw_wr4byte, scope iop_crc_par, type rw */
#define reg_iop_crc_par_rw_wr4byte___data___lsb 0
#define reg_iop_crc_par_rw_wr4byte___data___width 32
#define reg_iop_crc_par_rw_wr4byte_offset 32
/* Register rw_wr1byte_last, scope iop_crc_par, type rw */
#define reg_iop_crc_par_rw_wr1byte_last___data___lsb 0
#define reg_iop_crc_par_rw_wr1byte_last___data___width 8
#define reg_iop_crc_par_rw_wr1byte_last_offset 36
/* Register rw_wr2byte_last, scope iop_crc_par, type rw */
#define reg_iop_crc_par_rw_wr2byte_last___data___lsb 0
#define reg_iop_crc_par_rw_wr2byte_last___data___width 16
#define reg_iop_crc_par_rw_wr2byte_last_offset 40
/* Register rw_wr3byte_last, scope iop_crc_par, type rw */
#define reg_iop_crc_par_rw_wr3byte_last___data___lsb 0
#define reg_iop_crc_par_rw_wr3byte_last___data___width 24
#define reg_iop_crc_par_rw_wr3byte_last_offset 44
/* Register rw_wr4byte_last, scope iop_crc_par, type rw */
#define reg_iop_crc_par_rw_wr4byte_last___data___lsb 0
#define reg_iop_crc_par_rw_wr4byte_last___data___width 32
#define reg_iop_crc_par_rw_wr4byte_last_offset 48
/* Register r_stat, scope iop_crc_par, type r */
#define reg_iop_crc_par_r_stat___err___lsb 0
#define reg_iop_crc_par_r_stat___err___width 1
#define reg_iop_crc_par_r_stat___err___bit 0
#define reg_iop_crc_par_r_stat___busy___lsb 1
#define reg_iop_crc_par_r_stat___busy___width 1
#define reg_iop_crc_par_r_stat___busy___bit 1
#define reg_iop_crc_par_r_stat_offset 52
/* Register r_sh_reg, scope iop_crc_par, type r */
#define reg_iop_crc_par_r_sh_reg_offset 56
/* Register r_crc, scope iop_crc_par, type r */
#define reg_iop_crc_par_r_crc_offset 60
/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
#define reg_iop_crc_par_rw_strb_rec_dif_in___last___lsb 0
#define reg_iop_crc_par_rw_strb_rec_dif_in___last___width 2
#define reg_iop_crc_par_rw_strb_rec_dif_in_offset 64
/* Constants */
#define regk_iop_crc_par_calc 0x00000001
#define regk_iop_crc_par_ccitt 0x00000002
#define regk_iop_crc_par_check 0x00000000
#define regk_iop_crc_par_crc16 0x00000001
#define regk_iop_crc_par_crc32 0x00000000
#define regk_iop_crc_par_crc5 0x00000003
#define regk_iop_crc_par_crc5_11 0x00000004
#define regk_iop_crc_par_dif_in 0x00000002
#define regk_iop_crc_par_hi 0x00000000
#define regk_iop_crc_par_neg 0x00000002
#define regk_iop_crc_par_no 0x00000000
#define regk_iop_crc_par_pos 0x00000001
#define regk_iop_crc_par_pos_neg 0x00000003
#define regk_iop_crc_par_rw_cfg_default 0x00000000
#define regk_iop_crc_par_rw_ctrl_default 0x00000000
#define regk_iop_crc_par_yes 0x00000001
#endif /* __iop_crc_par_defs_asm_h */

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#ifndef __iop_dmc_in_defs_asm_h
#define __iop_dmc_in_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_dmc_in.r
* id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp
* last modfied: Mon Apr 11 16:08:45 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_in_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_in.r
* id: $Id: iop_dmc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_cfg, scope iop_dmc_in, type rw */
#define reg_iop_dmc_in_rw_cfg___sth_intr___lsb 0
#define reg_iop_dmc_in_rw_cfg___sth_intr___width 3
#define reg_iop_dmc_in_rw_cfg___last_dis_dif___lsb 3
#define reg_iop_dmc_in_rw_cfg___last_dis_dif___width 1
#define reg_iop_dmc_in_rw_cfg___last_dis_dif___bit 3
#define reg_iop_dmc_in_rw_cfg_offset 0
/* Register rw_ctrl, scope iop_dmc_in, type rw */
#define reg_iop_dmc_in_rw_ctrl___dif_en___lsb 0
#define reg_iop_dmc_in_rw_ctrl___dif_en___width 1
#define reg_iop_dmc_in_rw_ctrl___dif_en___bit 0
#define reg_iop_dmc_in_rw_ctrl___dif_dis___lsb 1
#define reg_iop_dmc_in_rw_ctrl___dif_dis___width 1
#define reg_iop_dmc_in_rw_ctrl___dif_dis___bit 1
#define reg_iop_dmc_in_rw_ctrl___stream_clr___lsb 2
#define reg_iop_dmc_in_rw_ctrl___stream_clr___width 1
#define reg_iop_dmc_in_rw_ctrl___stream_clr___bit 2
#define reg_iop_dmc_in_rw_ctrl_offset 4
/* Register r_stat, scope iop_dmc_in, type r */
#define reg_iop_dmc_in_r_stat___dif_en___lsb 0
#define reg_iop_dmc_in_r_stat___dif_en___width 1
#define reg_iop_dmc_in_r_stat___dif_en___bit 0
#define reg_iop_dmc_in_r_stat_offset 8
/* Register rw_stream_cmd, scope iop_dmc_in, type rw */
#define reg_iop_dmc_in_rw_stream_cmd___cmd___lsb 0
#define reg_iop_dmc_in_rw_stream_cmd___cmd___width 10
#define reg_iop_dmc_in_rw_stream_cmd___n___lsb 16
#define reg_iop_dmc_in_rw_stream_cmd___n___width 8
#define reg_iop_dmc_in_rw_stream_cmd_offset 12
/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */
#define reg_iop_dmc_in_rw_stream_wr_data_offset 16
/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */
#define reg_iop_dmc_in_rw_stream_wr_data_last_offset 20
/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */
#define reg_iop_dmc_in_rw_stream_ctrl___eop___lsb 0
#define reg_iop_dmc_in_rw_stream_ctrl___eop___width 1
#define reg_iop_dmc_in_rw_stream_ctrl___eop___bit 0
#define reg_iop_dmc_in_rw_stream_ctrl___wait___lsb 1
#define reg_iop_dmc_in_rw_stream_ctrl___wait___width 1
#define reg_iop_dmc_in_rw_stream_ctrl___wait___bit 1
#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___lsb 2
#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___width 1
#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___bit 2
#define reg_iop_dmc_in_rw_stream_ctrl___size___lsb 3
#define reg_iop_dmc_in_rw_stream_ctrl___size___width 3
#define reg_iop_dmc_in_rw_stream_ctrl_offset 24
/* Register r_stream_stat, scope iop_dmc_in, type r */
#define reg_iop_dmc_in_r_stream_stat___sth___lsb 0
#define reg_iop_dmc_in_r_stream_stat___sth___width 7
#define reg_iop_dmc_in_r_stream_stat___full___lsb 16
#define reg_iop_dmc_in_r_stream_stat___full___width 1
#define reg_iop_dmc_in_r_stream_stat___full___bit 16
#define reg_iop_dmc_in_r_stream_stat___last_pkt___lsb 17
#define reg_iop_dmc_in_r_stream_stat___last_pkt___width 1
#define reg_iop_dmc_in_r_stream_stat___last_pkt___bit 17
#define reg_iop_dmc_in_r_stream_stat___data_md_valid___lsb 18
#define reg_iop_dmc_in_r_stream_stat___data_md_valid___width 1
#define reg_iop_dmc_in_r_stream_stat___data_md_valid___bit 18
#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___lsb 19
#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___width 1
#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___bit 19
#define reg_iop_dmc_in_r_stream_stat___group_md_valid___lsb 20
#define reg_iop_dmc_in_r_stream_stat___group_md_valid___width 1
#define reg_iop_dmc_in_r_stream_stat___group_md_valid___bit 20
#define reg_iop_dmc_in_r_stream_stat___stream_busy___lsb 21
#define reg_iop_dmc_in_r_stream_stat___stream_busy___width 1
#define reg_iop_dmc_in_r_stream_stat___stream_busy___bit 21
#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___lsb 22
#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___width 1
#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___bit 22
#define reg_iop_dmc_in_r_stream_stat_offset 28
/* Register r_data_descr, scope iop_dmc_in, type r */
#define reg_iop_dmc_in_r_data_descr___ctrl___lsb 0
#define reg_iop_dmc_in_r_data_descr___ctrl___width 8
#define reg_iop_dmc_in_r_data_descr___stat___lsb 8
#define reg_iop_dmc_in_r_data_descr___stat___width 8
#define reg_iop_dmc_in_r_data_descr___md___lsb 16
#define reg_iop_dmc_in_r_data_descr___md___width 16
#define reg_iop_dmc_in_r_data_descr_offset 32
/* Register r_ctxt_descr, scope iop_dmc_in, type r */
#define reg_iop_dmc_in_r_ctxt_descr___ctrl___lsb 0
#define reg_iop_dmc_in_r_ctxt_descr___ctrl___width 8
#define reg_iop_dmc_in_r_ctxt_descr___stat___lsb 8
#define reg_iop_dmc_in_r_ctxt_descr___stat___width 8
#define reg_iop_dmc_in_r_ctxt_descr___md0___lsb 16
#define reg_iop_dmc_in_r_ctxt_descr___md0___width 16
#define reg_iop_dmc_in_r_ctxt_descr_offset 36
/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */
#define reg_iop_dmc_in_r_ctxt_descr_md1_offset 40
/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */
#define reg_iop_dmc_in_r_ctxt_descr_md2_offset 44
/* Register r_group_descr, scope iop_dmc_in, type r */
#define reg_iop_dmc_in_r_group_descr___ctrl___lsb 0
#define reg_iop_dmc_in_r_group_descr___ctrl___width 8
#define reg_iop_dmc_in_r_group_descr___stat___lsb 8
#define reg_iop_dmc_in_r_group_descr___stat___width 8
#define reg_iop_dmc_in_r_group_descr___md___lsb 16
#define reg_iop_dmc_in_r_group_descr___md___width 16
#define reg_iop_dmc_in_r_group_descr_offset 56
/* Register rw_data_descr, scope iop_dmc_in, type rw */
#define reg_iop_dmc_in_rw_data_descr___md___lsb 16
#define reg_iop_dmc_in_rw_data_descr___md___width 16
#define reg_iop_dmc_in_rw_data_descr_offset 60
/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */
#define reg_iop_dmc_in_rw_ctxt_descr___md0___lsb 16
#define reg_iop_dmc_in_rw_ctxt_descr___md0___width 16
#define reg_iop_dmc_in_rw_ctxt_descr_offset 64
/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */
#define reg_iop_dmc_in_rw_ctxt_descr_md1_offset 68
/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */
#define reg_iop_dmc_in_rw_ctxt_descr_md2_offset 72
/* Register rw_group_descr, scope iop_dmc_in, type rw */
#define reg_iop_dmc_in_rw_group_descr___md___lsb 16
#define reg_iop_dmc_in_rw_group_descr___md___width 16
#define reg_iop_dmc_in_rw_group_descr_offset 84
/* Register rw_intr_mask, scope iop_dmc_in, type rw */
#define reg_iop_dmc_in_rw_intr_mask___data_md___lsb 0
#define reg_iop_dmc_in_rw_intr_mask___data_md___width 1
#define reg_iop_dmc_in_rw_intr_mask___data_md___bit 0
#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___lsb 1
#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___width 1
#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___bit 1
#define reg_iop_dmc_in_rw_intr_mask___group_md___lsb 2
#define reg_iop_dmc_in_rw_intr_mask___group_md___width 1
#define reg_iop_dmc_in_rw_intr_mask___group_md___bit 2
#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___lsb 3
#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___width 1
#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___bit 3
#define reg_iop_dmc_in_rw_intr_mask___sth___lsb 4
#define reg_iop_dmc_in_rw_intr_mask___sth___width 1
#define reg_iop_dmc_in_rw_intr_mask___sth___bit 4
#define reg_iop_dmc_in_rw_intr_mask___full___lsb 5
#define reg_iop_dmc_in_rw_intr_mask___full___width 1
#define reg_iop_dmc_in_rw_intr_mask___full___bit 5
#define reg_iop_dmc_in_rw_intr_mask_offset 88
/* Register rw_ack_intr, scope iop_dmc_in, type rw */
#define reg_iop_dmc_in_rw_ack_intr___data_md___lsb 0
#define reg_iop_dmc_in_rw_ack_intr___data_md___width 1
#define reg_iop_dmc_in_rw_ack_intr___data_md___bit 0
#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___lsb 1
#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___width 1
#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___bit 1
#define reg_iop_dmc_in_rw_ack_intr___group_md___lsb 2
#define reg_iop_dmc_in_rw_ack_intr___group_md___width 1
#define reg_iop_dmc_in_rw_ack_intr___group_md___bit 2
#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___lsb 3
#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___width 1
#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___bit 3
#define reg_iop_dmc_in_rw_ack_intr___sth___lsb 4
#define reg_iop_dmc_in_rw_ack_intr___sth___width 1
#define reg_iop_dmc_in_rw_ack_intr___sth___bit 4
#define reg_iop_dmc_in_rw_ack_intr___full___lsb 5
#define reg_iop_dmc_in_rw_ack_intr___full___width 1
#define reg_iop_dmc_in_rw_ack_intr___full___bit 5
#define reg_iop_dmc_in_rw_ack_intr_offset 92
/* Register r_intr, scope iop_dmc_in, type r */
#define reg_iop_dmc_in_r_intr___data_md___lsb 0
#define reg_iop_dmc_in_r_intr___data_md___width 1
#define reg_iop_dmc_in_r_intr___data_md___bit 0
#define reg_iop_dmc_in_r_intr___ctxt_md___lsb 1
#define reg_iop_dmc_in_r_intr___ctxt_md___width 1
#define reg_iop_dmc_in_r_intr___ctxt_md___bit 1
#define reg_iop_dmc_in_r_intr___group_md___lsb 2
#define reg_iop_dmc_in_r_intr___group_md___width 1
#define reg_iop_dmc_in_r_intr___group_md___bit 2
#define reg_iop_dmc_in_r_intr___cmd_rdy___lsb 3
#define reg_iop_dmc_in_r_intr___cmd_rdy___width 1
#define reg_iop_dmc_in_r_intr___cmd_rdy___bit 3
#define reg_iop_dmc_in_r_intr___sth___lsb 4
#define reg_iop_dmc_in_r_intr___sth___width 1
#define reg_iop_dmc_in_r_intr___sth___bit 4
#define reg_iop_dmc_in_r_intr___full___lsb 5
#define reg_iop_dmc_in_r_intr___full___width 1
#define reg_iop_dmc_in_r_intr___full___bit 5
#define reg_iop_dmc_in_r_intr_offset 96
/* Register r_masked_intr, scope iop_dmc_in, type r */
#define reg_iop_dmc_in_r_masked_intr___data_md___lsb 0
#define reg_iop_dmc_in_r_masked_intr___data_md___width 1
#define reg_iop_dmc_in_r_masked_intr___data_md___bit 0
#define reg_iop_dmc_in_r_masked_intr___ctxt_md___lsb 1
#define reg_iop_dmc_in_r_masked_intr___ctxt_md___width 1
#define reg_iop_dmc_in_r_masked_intr___ctxt_md___bit 1
#define reg_iop_dmc_in_r_masked_intr___group_md___lsb 2
#define reg_iop_dmc_in_r_masked_intr___group_md___width 1
#define reg_iop_dmc_in_r_masked_intr___group_md___bit 2
#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___lsb 3
#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___width 1
#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___bit 3
#define reg_iop_dmc_in_r_masked_intr___sth___lsb 4
#define reg_iop_dmc_in_r_masked_intr___sth___width 1
#define reg_iop_dmc_in_r_masked_intr___sth___bit 4
#define reg_iop_dmc_in_r_masked_intr___full___lsb 5
#define reg_iop_dmc_in_r_masked_intr___full___width 1
#define reg_iop_dmc_in_r_masked_intr___full___bit 5
#define reg_iop_dmc_in_r_masked_intr_offset 100
/* Constants */
#define regk_iop_dmc_in_ack_pkt 0x00000100
#define regk_iop_dmc_in_array 0x00000008
#define regk_iop_dmc_in_burst 0x00000020
#define regk_iop_dmc_in_copy_next 0x00000010
#define regk_iop_dmc_in_copy_up 0x00000020
#define regk_iop_dmc_in_dis_c 0x00000010
#define regk_iop_dmc_in_dis_g 0x00000020
#define regk_iop_dmc_in_lim1 0x00000000
#define regk_iop_dmc_in_lim16 0x00000004
#define regk_iop_dmc_in_lim2 0x00000001
#define regk_iop_dmc_in_lim32 0x00000005
#define regk_iop_dmc_in_lim4 0x00000002
#define regk_iop_dmc_in_lim64 0x00000006
#define regk_iop_dmc_in_lim8 0x00000003
#define regk_iop_dmc_in_load_c 0x00000200
#define regk_iop_dmc_in_load_c_n 0x00000280
#define regk_iop_dmc_in_load_c_next 0x00000240
#define regk_iop_dmc_in_load_d 0x00000140
#define regk_iop_dmc_in_load_g 0x00000300
#define regk_iop_dmc_in_load_g_down 0x000003c0
#define regk_iop_dmc_in_load_g_next 0x00000340
#define regk_iop_dmc_in_load_g_up 0x00000380
#define regk_iop_dmc_in_next_en 0x00000010
#define regk_iop_dmc_in_next_pkt 0x00000010
#define regk_iop_dmc_in_no 0x00000000
#define regk_iop_dmc_in_restore 0x00000020
#define regk_iop_dmc_in_rw_cfg_default 0x00000000
#define regk_iop_dmc_in_rw_ctxt_descr_default 0x00000000
#define regk_iop_dmc_in_rw_ctxt_descr_md1_default 0x00000000
#define regk_iop_dmc_in_rw_ctxt_descr_md2_default 0x00000000
#define regk_iop_dmc_in_rw_data_descr_default 0x00000000
#define regk_iop_dmc_in_rw_group_descr_default 0x00000000
#define regk_iop_dmc_in_rw_intr_mask_default 0x00000000
#define regk_iop_dmc_in_rw_stream_ctrl_default 0x00000000
#define regk_iop_dmc_in_save_down 0x00000020
#define regk_iop_dmc_in_save_up 0x00000020
#define regk_iop_dmc_in_set_reg 0x00000050
#define regk_iop_dmc_in_set_w_size1 0x00000190
#define regk_iop_dmc_in_set_w_size2 0x000001a0
#define regk_iop_dmc_in_set_w_size4 0x000001c0
#define regk_iop_dmc_in_store_c 0x00000002
#define regk_iop_dmc_in_store_descr 0x00000000
#define regk_iop_dmc_in_store_g 0x00000004
#define regk_iop_dmc_in_store_md 0x00000001
#define regk_iop_dmc_in_update_down 0x00000020
#define regk_iop_dmc_in_yes 0x00000001
#endif /* __iop_dmc_in_defs_asm_h */

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#ifndef __iop_dmc_out_defs_asm_h
#define __iop_dmc_out_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_dmc_out.r
* id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp
* last modfied: Mon Apr 11 16:08:45 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r
* id: $Id: iop_dmc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_cfg, scope iop_dmc_out, type rw */
#define reg_iop_dmc_out_rw_cfg___trf_lim___lsb 0
#define reg_iop_dmc_out_rw_cfg___trf_lim___width 16
#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___lsb 16
#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___width 1
#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___bit 16
#define reg_iop_dmc_out_rw_cfg___dth_intr___lsb 17
#define reg_iop_dmc_out_rw_cfg___dth_intr___width 3
#define reg_iop_dmc_out_rw_cfg_offset 0
/* Register rw_ctrl, scope iop_dmc_out, type rw */
#define reg_iop_dmc_out_rw_ctrl___dif_en___lsb 0
#define reg_iop_dmc_out_rw_ctrl___dif_en___width 1
#define reg_iop_dmc_out_rw_ctrl___dif_en___bit 0
#define reg_iop_dmc_out_rw_ctrl___dif_dis___lsb 1
#define reg_iop_dmc_out_rw_ctrl___dif_dis___width 1
#define reg_iop_dmc_out_rw_ctrl___dif_dis___bit 1
#define reg_iop_dmc_out_rw_ctrl_offset 4
/* Register r_stat, scope iop_dmc_out, type r */
#define reg_iop_dmc_out_r_stat___dif_en___lsb 0
#define reg_iop_dmc_out_r_stat___dif_en___width 1
#define reg_iop_dmc_out_r_stat___dif_en___bit 0
#define reg_iop_dmc_out_r_stat_offset 8
/* Register rw_stream_cmd, scope iop_dmc_out, type rw */
#define reg_iop_dmc_out_rw_stream_cmd___cmd___lsb 0
#define reg_iop_dmc_out_rw_stream_cmd___cmd___width 10
#define reg_iop_dmc_out_rw_stream_cmd___n___lsb 16
#define reg_iop_dmc_out_rw_stream_cmd___n___width 8
#define reg_iop_dmc_out_rw_stream_cmd_offset 12
/* Register rs_stream_data, scope iop_dmc_out, type rs */
#define reg_iop_dmc_out_rs_stream_data_offset 16
/* Register r_stream_data, scope iop_dmc_out, type r */
#define reg_iop_dmc_out_r_stream_data_offset 20
/* Register r_stream_stat, scope iop_dmc_out, type r */
#define reg_iop_dmc_out_r_stream_stat___dth___lsb 0
#define reg_iop_dmc_out_r_stream_stat___dth___width 7
#define reg_iop_dmc_out_r_stream_stat___dv___lsb 16
#define reg_iop_dmc_out_r_stream_stat___dv___width 1
#define reg_iop_dmc_out_r_stream_stat___dv___bit 16
#define reg_iop_dmc_out_r_stream_stat___all_avail___lsb 17
#define reg_iop_dmc_out_r_stream_stat___all_avail___width 1
#define reg_iop_dmc_out_r_stream_stat___all_avail___bit 17
#define reg_iop_dmc_out_r_stream_stat___last___lsb 18
#define reg_iop_dmc_out_r_stream_stat___last___width 1
#define reg_iop_dmc_out_r_stream_stat___last___bit 18
#define reg_iop_dmc_out_r_stream_stat___size___lsb 19
#define reg_iop_dmc_out_r_stream_stat___size___width 3
#define reg_iop_dmc_out_r_stream_stat___data_md_valid___lsb 22
#define reg_iop_dmc_out_r_stream_stat___data_md_valid___width 1
#define reg_iop_dmc_out_r_stream_stat___data_md_valid___bit 22
#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___lsb 23
#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___width 1
#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___bit 23
#define reg_iop_dmc_out_r_stream_stat___group_md_valid___lsb 24
#define reg_iop_dmc_out_r_stream_stat___group_md_valid___width 1
#define reg_iop_dmc_out_r_stream_stat___group_md_valid___bit 24
#define reg_iop_dmc_out_r_stream_stat___stream_busy___lsb 25
#define reg_iop_dmc_out_r_stream_stat___stream_busy___width 1
#define reg_iop_dmc_out_r_stream_stat___stream_busy___bit 25
#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___lsb 26
#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___width 1
#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___bit 26
#define reg_iop_dmc_out_r_stream_stat___cmd_rq___lsb 27
#define reg_iop_dmc_out_r_stream_stat___cmd_rq___width 1
#define reg_iop_dmc_out_r_stream_stat___cmd_rq___bit 27
#define reg_iop_dmc_out_r_stream_stat_offset 24
/* Register r_data_descr, scope iop_dmc_out, type r */
#define reg_iop_dmc_out_r_data_descr___ctrl___lsb 0
#define reg_iop_dmc_out_r_data_descr___ctrl___width 8
#define reg_iop_dmc_out_r_data_descr___stat___lsb 8
#define reg_iop_dmc_out_r_data_descr___stat___width 8
#define reg_iop_dmc_out_r_data_descr___md___lsb 16
#define reg_iop_dmc_out_r_data_descr___md___width 16
#define reg_iop_dmc_out_r_data_descr_offset 28
/* Register r_ctxt_descr, scope iop_dmc_out, type r */
#define reg_iop_dmc_out_r_ctxt_descr___ctrl___lsb 0
#define reg_iop_dmc_out_r_ctxt_descr___ctrl___width 8
#define reg_iop_dmc_out_r_ctxt_descr___stat___lsb 8
#define reg_iop_dmc_out_r_ctxt_descr___stat___width 8
#define reg_iop_dmc_out_r_ctxt_descr___md0___lsb 16
#define reg_iop_dmc_out_r_ctxt_descr___md0___width 16
#define reg_iop_dmc_out_r_ctxt_descr_offset 32
/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */
#define reg_iop_dmc_out_r_ctxt_descr_md1_offset 36
/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */
#define reg_iop_dmc_out_r_ctxt_descr_md2_offset 40
/* Register r_group_descr, scope iop_dmc_out, type r */
#define reg_iop_dmc_out_r_group_descr___ctrl___lsb 0
#define reg_iop_dmc_out_r_group_descr___ctrl___width 8
#define reg_iop_dmc_out_r_group_descr___stat___lsb 8
#define reg_iop_dmc_out_r_group_descr___stat___width 8
#define reg_iop_dmc_out_r_group_descr___md___lsb 16
#define reg_iop_dmc_out_r_group_descr___md___width 16
#define reg_iop_dmc_out_r_group_descr_offset 52
/* Register rw_data_descr, scope iop_dmc_out, type rw */
#define reg_iop_dmc_out_rw_data_descr___md___lsb 16
#define reg_iop_dmc_out_rw_data_descr___md___width 16
#define reg_iop_dmc_out_rw_data_descr_offset 56
/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
#define reg_iop_dmc_out_rw_ctxt_descr___md0___lsb 16
#define reg_iop_dmc_out_rw_ctxt_descr___md0___width 16
#define reg_iop_dmc_out_rw_ctxt_descr_offset 60
/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
#define reg_iop_dmc_out_rw_ctxt_descr_md1_offset 64
/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
#define reg_iop_dmc_out_rw_ctxt_descr_md2_offset 68
/* Register rw_group_descr, scope iop_dmc_out, type rw */
#define reg_iop_dmc_out_rw_group_descr___md___lsb 16
#define reg_iop_dmc_out_rw_group_descr___md___width 16
#define reg_iop_dmc_out_rw_group_descr_offset 80
/* Register rw_intr_mask, scope iop_dmc_out, type rw */
#define reg_iop_dmc_out_rw_intr_mask___data_md___lsb 0
#define reg_iop_dmc_out_rw_intr_mask___data_md___width 1
#define reg_iop_dmc_out_rw_intr_mask___data_md___bit 0
#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___lsb 1
#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___width 1
#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___bit 1
#define reg_iop_dmc_out_rw_intr_mask___group_md___lsb 2
#define reg_iop_dmc_out_rw_intr_mask___group_md___width 1
#define reg_iop_dmc_out_rw_intr_mask___group_md___bit 2
#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___lsb 3
#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___width 1
#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___bit 3
#define reg_iop_dmc_out_rw_intr_mask___dth___lsb 4
#define reg_iop_dmc_out_rw_intr_mask___dth___width 1
#define reg_iop_dmc_out_rw_intr_mask___dth___bit 4
#define reg_iop_dmc_out_rw_intr_mask___dv___lsb 5
#define reg_iop_dmc_out_rw_intr_mask___dv___width 1
#define reg_iop_dmc_out_rw_intr_mask___dv___bit 5
#define reg_iop_dmc_out_rw_intr_mask___last_data___lsb 6
#define reg_iop_dmc_out_rw_intr_mask___last_data___width 1
#define reg_iop_dmc_out_rw_intr_mask___last_data___bit 6
#define reg_iop_dmc_out_rw_intr_mask___trf_lim___lsb 7
#define reg_iop_dmc_out_rw_intr_mask___trf_lim___width 1
#define reg_iop_dmc_out_rw_intr_mask___trf_lim___bit 7
#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___lsb 8
#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___width 1
#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___bit 8
#define reg_iop_dmc_out_rw_intr_mask_offset 84
/* Register rw_ack_intr, scope iop_dmc_out, type rw */
#define reg_iop_dmc_out_rw_ack_intr___data_md___lsb 0
#define reg_iop_dmc_out_rw_ack_intr___data_md___width 1
#define reg_iop_dmc_out_rw_ack_intr___data_md___bit 0
#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___lsb 1
#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___width 1
#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___bit 1
#define reg_iop_dmc_out_rw_ack_intr___group_md___lsb 2
#define reg_iop_dmc_out_rw_ack_intr___group_md___width 1
#define reg_iop_dmc_out_rw_ack_intr___group_md___bit 2
#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___lsb 3
#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___width 1
#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___bit 3
#define reg_iop_dmc_out_rw_ack_intr___dth___lsb 4
#define reg_iop_dmc_out_rw_ack_intr___dth___width 1
#define reg_iop_dmc_out_rw_ack_intr___dth___bit 4
#define reg_iop_dmc_out_rw_ack_intr___dv___lsb 5
#define reg_iop_dmc_out_rw_ack_intr___dv___width 1
#define reg_iop_dmc_out_rw_ack_intr___dv___bit 5
#define reg_iop_dmc_out_rw_ack_intr___last_data___lsb 6
#define reg_iop_dmc_out_rw_ack_intr___last_data___width 1
#define reg_iop_dmc_out_rw_ack_intr___last_data___bit 6
#define reg_iop_dmc_out_rw_ack_intr___trf_lim___lsb 7
#define reg_iop_dmc_out_rw_ack_intr___trf_lim___width 1
#define reg_iop_dmc_out_rw_ack_intr___trf_lim___bit 7
#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___lsb 8
#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___width 1
#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___bit 8
#define reg_iop_dmc_out_rw_ack_intr_offset 88
/* Register r_intr, scope iop_dmc_out, type r */
#define reg_iop_dmc_out_r_intr___data_md___lsb 0
#define reg_iop_dmc_out_r_intr___data_md___width 1
#define reg_iop_dmc_out_r_intr___data_md___bit 0
#define reg_iop_dmc_out_r_intr___ctxt_md___lsb 1
#define reg_iop_dmc_out_r_intr___ctxt_md___width 1
#define reg_iop_dmc_out_r_intr___ctxt_md___bit 1
#define reg_iop_dmc_out_r_intr___group_md___lsb 2
#define reg_iop_dmc_out_r_intr___group_md___width 1
#define reg_iop_dmc_out_r_intr___group_md___bit 2
#define reg_iop_dmc_out_r_intr___cmd_rdy___lsb 3
#define reg_iop_dmc_out_r_intr___cmd_rdy___width 1
#define reg_iop_dmc_out_r_intr___cmd_rdy___bit 3
#define reg_iop_dmc_out_r_intr___dth___lsb 4
#define reg_iop_dmc_out_r_intr___dth___width 1
#define reg_iop_dmc_out_r_intr___dth___bit 4
#define reg_iop_dmc_out_r_intr___dv___lsb 5
#define reg_iop_dmc_out_r_intr___dv___width 1
#define reg_iop_dmc_out_r_intr___dv___bit 5
#define reg_iop_dmc_out_r_intr___last_data___lsb 6
#define reg_iop_dmc_out_r_intr___last_data___width 1
#define reg_iop_dmc_out_r_intr___last_data___bit 6
#define reg_iop_dmc_out_r_intr___trf_lim___lsb 7
#define reg_iop_dmc_out_r_intr___trf_lim___width 1
#define reg_iop_dmc_out_r_intr___trf_lim___bit 7
#define reg_iop_dmc_out_r_intr___cmd_rq___lsb 8
#define reg_iop_dmc_out_r_intr___cmd_rq___width 1
#define reg_iop_dmc_out_r_intr___cmd_rq___bit 8
#define reg_iop_dmc_out_r_intr_offset 92
/* Register r_masked_intr, scope iop_dmc_out, type r */
#define reg_iop_dmc_out_r_masked_intr___data_md___lsb 0
#define reg_iop_dmc_out_r_masked_intr___data_md___width 1
#define reg_iop_dmc_out_r_masked_intr___data_md___bit 0
#define reg_iop_dmc_out_r_masked_intr___ctxt_md___lsb 1
#define reg_iop_dmc_out_r_masked_intr___ctxt_md___width 1
#define reg_iop_dmc_out_r_masked_intr___ctxt_md___bit 1
#define reg_iop_dmc_out_r_masked_intr___group_md___lsb 2
#define reg_iop_dmc_out_r_masked_intr___group_md___width 1
#define reg_iop_dmc_out_r_masked_intr___group_md___bit 2
#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___lsb 3
#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___width 1
#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___bit 3
#define reg_iop_dmc_out_r_masked_intr___dth___lsb 4
#define reg_iop_dmc_out_r_masked_intr___dth___width 1
#define reg_iop_dmc_out_r_masked_intr___dth___bit 4
#define reg_iop_dmc_out_r_masked_intr___dv___lsb 5
#define reg_iop_dmc_out_r_masked_intr___dv___width 1
#define reg_iop_dmc_out_r_masked_intr___dv___bit 5
#define reg_iop_dmc_out_r_masked_intr___last_data___lsb 6
#define reg_iop_dmc_out_r_masked_intr___last_data___width 1
#define reg_iop_dmc_out_r_masked_intr___last_data___bit 6
#define reg_iop_dmc_out_r_masked_intr___trf_lim___lsb 7
#define reg_iop_dmc_out_r_masked_intr___trf_lim___width 1
#define reg_iop_dmc_out_r_masked_intr___trf_lim___bit 7
#define reg_iop_dmc_out_r_masked_intr___cmd_rq___lsb 8
#define reg_iop_dmc_out_r_masked_intr___cmd_rq___width 1
#define reg_iop_dmc_out_r_masked_intr___cmd_rq___bit 8
#define reg_iop_dmc_out_r_masked_intr_offset 96
/* Constants */
#define regk_iop_dmc_out_ack_pkt 0x00000100
#define regk_iop_dmc_out_array 0x00000008
#define regk_iop_dmc_out_burst 0x00000020
#define regk_iop_dmc_out_copy_next 0x00000010
#define regk_iop_dmc_out_copy_up 0x00000020
#define regk_iop_dmc_out_dis_c 0x00000010
#define regk_iop_dmc_out_dis_g 0x00000020
#define regk_iop_dmc_out_lim1 0x00000000
#define regk_iop_dmc_out_lim16 0x00000004
#define regk_iop_dmc_out_lim2 0x00000001
#define regk_iop_dmc_out_lim32 0x00000005
#define regk_iop_dmc_out_lim4 0x00000002
#define regk_iop_dmc_out_lim64 0x00000006
#define regk_iop_dmc_out_lim8 0x00000003
#define regk_iop_dmc_out_load_c 0x00000200
#define regk_iop_dmc_out_load_c_n 0x00000280
#define regk_iop_dmc_out_load_c_next 0x00000240
#define regk_iop_dmc_out_load_d 0x00000140
#define regk_iop_dmc_out_load_g 0x00000300
#define regk_iop_dmc_out_load_g_down 0x000003c0
#define regk_iop_dmc_out_load_g_next 0x00000340
#define regk_iop_dmc_out_load_g_up 0x00000380
#define regk_iop_dmc_out_next_en 0x00000010
#define regk_iop_dmc_out_next_pkt 0x00000010
#define regk_iop_dmc_out_no 0x00000000
#define regk_iop_dmc_out_restore 0x00000020
#define regk_iop_dmc_out_rw_cfg_default 0x00000000
#define regk_iop_dmc_out_rw_ctxt_descr_default 0x00000000
#define regk_iop_dmc_out_rw_ctxt_descr_md1_default 0x00000000
#define regk_iop_dmc_out_rw_ctxt_descr_md2_default 0x00000000
#define regk_iop_dmc_out_rw_data_descr_default 0x00000000
#define regk_iop_dmc_out_rw_group_descr_default 0x00000000
#define regk_iop_dmc_out_rw_intr_mask_default 0x00000000
#define regk_iop_dmc_out_save_down 0x00000020
#define regk_iop_dmc_out_save_up 0x00000020
#define regk_iop_dmc_out_set_reg 0x00000050
#define regk_iop_dmc_out_set_w_size1 0x00000190
#define regk_iop_dmc_out_set_w_size2 0x000001a0
#define regk_iop_dmc_out_set_w_size4 0x000001c0
#define regk_iop_dmc_out_store_c 0x00000002
#define regk_iop_dmc_out_store_descr 0x00000000
#define regk_iop_dmc_out_store_g 0x00000004
#define regk_iop_dmc_out_store_md 0x00000001
#define regk_iop_dmc_out_update_down 0x00000020
#define regk_iop_dmc_out_yes 0x00000001
#endif /* __iop_dmc_out_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h Normal file
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#ifndef __iop_fifo_in_defs_asm_h
#define __iop_fifo_in_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_fifo_in.r
* id: <not found>
* last modfied: Mon Apr 11 16:10:07 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in.r
* id: $Id: iop_fifo_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_cfg, scope iop_fifo_in, type rw */
#define reg_iop_fifo_in_rw_cfg___avail_lim___lsb 0
#define reg_iop_fifo_in_rw_cfg___avail_lim___width 3
#define reg_iop_fifo_in_rw_cfg___byte_order___lsb 3
#define reg_iop_fifo_in_rw_cfg___byte_order___width 2
#define reg_iop_fifo_in_rw_cfg___trig___lsb 5
#define reg_iop_fifo_in_rw_cfg___trig___width 2
#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___lsb 7
#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___width 1
#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___bit 7
#define reg_iop_fifo_in_rw_cfg___mode___lsb 8
#define reg_iop_fifo_in_rw_cfg___mode___width 2
#define reg_iop_fifo_in_rw_cfg_offset 0
/* Register rw_ctrl, scope iop_fifo_in, type rw */
#define reg_iop_fifo_in_rw_ctrl___dif_in_en___lsb 0
#define reg_iop_fifo_in_rw_ctrl___dif_in_en___width 1
#define reg_iop_fifo_in_rw_ctrl___dif_in_en___bit 0
#define reg_iop_fifo_in_rw_ctrl___dif_out_en___lsb 1
#define reg_iop_fifo_in_rw_ctrl___dif_out_en___width 1
#define reg_iop_fifo_in_rw_ctrl___dif_out_en___bit 1
#define reg_iop_fifo_in_rw_ctrl_offset 4
/* Register r_stat, scope iop_fifo_in, type r */
#define reg_iop_fifo_in_r_stat___avail_bytes___lsb 0
#define reg_iop_fifo_in_r_stat___avail_bytes___width 4
#define reg_iop_fifo_in_r_stat___last___lsb 4
#define reg_iop_fifo_in_r_stat___last___width 8
#define reg_iop_fifo_in_r_stat___dif_in_en___lsb 12
#define reg_iop_fifo_in_r_stat___dif_in_en___width 1
#define reg_iop_fifo_in_r_stat___dif_in_en___bit 12
#define reg_iop_fifo_in_r_stat___dif_out_en___lsb 13
#define reg_iop_fifo_in_r_stat___dif_out_en___width 1
#define reg_iop_fifo_in_r_stat___dif_out_en___bit 13
#define reg_iop_fifo_in_r_stat_offset 8
/* Register rs_rd1byte, scope iop_fifo_in, type rs */
#define reg_iop_fifo_in_rs_rd1byte___data___lsb 0
#define reg_iop_fifo_in_rs_rd1byte___data___width 8
#define reg_iop_fifo_in_rs_rd1byte_offset 12
/* Register r_rd1byte, scope iop_fifo_in, type r */
#define reg_iop_fifo_in_r_rd1byte___data___lsb 0
#define reg_iop_fifo_in_r_rd1byte___data___width 8
#define reg_iop_fifo_in_r_rd1byte_offset 16
/* Register rs_rd2byte, scope iop_fifo_in, type rs */
#define reg_iop_fifo_in_rs_rd2byte___data___lsb 0
#define reg_iop_fifo_in_rs_rd2byte___data___width 16
#define reg_iop_fifo_in_rs_rd2byte_offset 20
/* Register r_rd2byte, scope iop_fifo_in, type r */
#define reg_iop_fifo_in_r_rd2byte___data___lsb 0
#define reg_iop_fifo_in_r_rd2byte___data___width 16
#define reg_iop_fifo_in_r_rd2byte_offset 24
/* Register rs_rd3byte, scope iop_fifo_in, type rs */
#define reg_iop_fifo_in_rs_rd3byte___data___lsb 0
#define reg_iop_fifo_in_rs_rd3byte___data___width 24
#define reg_iop_fifo_in_rs_rd3byte_offset 28
/* Register r_rd3byte, scope iop_fifo_in, type r */
#define reg_iop_fifo_in_r_rd3byte___data___lsb 0
#define reg_iop_fifo_in_r_rd3byte___data___width 24
#define reg_iop_fifo_in_r_rd3byte_offset 32
/* Register rs_rd4byte, scope iop_fifo_in, type rs */
#define reg_iop_fifo_in_rs_rd4byte___data___lsb 0
#define reg_iop_fifo_in_rs_rd4byte___data___width 32
#define reg_iop_fifo_in_rs_rd4byte_offset 36
/* Register r_rd4byte, scope iop_fifo_in, type r */
#define reg_iop_fifo_in_r_rd4byte___data___lsb 0
#define reg_iop_fifo_in_r_rd4byte___data___width 32
#define reg_iop_fifo_in_r_rd4byte_offset 40
/* Register rw_set_last, scope iop_fifo_in, type rw */
#define reg_iop_fifo_in_rw_set_last_offset 44
/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
#define reg_iop_fifo_in_rw_strb_dif_in___last___lsb 0
#define reg_iop_fifo_in_rw_strb_dif_in___last___width 2
#define reg_iop_fifo_in_rw_strb_dif_in_offset 48
/* Register rw_intr_mask, scope iop_fifo_in, type rw */
#define reg_iop_fifo_in_rw_intr_mask___urun___lsb 0
#define reg_iop_fifo_in_rw_intr_mask___urun___width 1
#define reg_iop_fifo_in_rw_intr_mask___urun___bit 0
#define reg_iop_fifo_in_rw_intr_mask___last_data___lsb 1
#define reg_iop_fifo_in_rw_intr_mask___last_data___width 1
#define reg_iop_fifo_in_rw_intr_mask___last_data___bit 1
#define reg_iop_fifo_in_rw_intr_mask___dav___lsb 2
#define reg_iop_fifo_in_rw_intr_mask___dav___width 1
#define reg_iop_fifo_in_rw_intr_mask___dav___bit 2
#define reg_iop_fifo_in_rw_intr_mask___avail___lsb 3
#define reg_iop_fifo_in_rw_intr_mask___avail___width 1
#define reg_iop_fifo_in_rw_intr_mask___avail___bit 3
#define reg_iop_fifo_in_rw_intr_mask___orun___lsb 4
#define reg_iop_fifo_in_rw_intr_mask___orun___width 1
#define reg_iop_fifo_in_rw_intr_mask___orun___bit 4
#define reg_iop_fifo_in_rw_intr_mask_offset 52
/* Register rw_ack_intr, scope iop_fifo_in, type rw */
#define reg_iop_fifo_in_rw_ack_intr___urun___lsb 0
#define reg_iop_fifo_in_rw_ack_intr___urun___width 1
#define reg_iop_fifo_in_rw_ack_intr___urun___bit 0
#define reg_iop_fifo_in_rw_ack_intr___last_data___lsb 1
#define reg_iop_fifo_in_rw_ack_intr___last_data___width 1
#define reg_iop_fifo_in_rw_ack_intr___last_data___bit 1
#define reg_iop_fifo_in_rw_ack_intr___dav___lsb 2
#define reg_iop_fifo_in_rw_ack_intr___dav___width 1
#define reg_iop_fifo_in_rw_ack_intr___dav___bit 2
#define reg_iop_fifo_in_rw_ack_intr___avail___lsb 3
#define reg_iop_fifo_in_rw_ack_intr___avail___width 1
#define reg_iop_fifo_in_rw_ack_intr___avail___bit 3
#define reg_iop_fifo_in_rw_ack_intr___orun___lsb 4
#define reg_iop_fifo_in_rw_ack_intr___orun___width 1
#define reg_iop_fifo_in_rw_ack_intr___orun___bit 4
#define reg_iop_fifo_in_rw_ack_intr_offset 56
/* Register r_intr, scope iop_fifo_in, type r */
#define reg_iop_fifo_in_r_intr___urun___lsb 0
#define reg_iop_fifo_in_r_intr___urun___width 1
#define reg_iop_fifo_in_r_intr___urun___bit 0
#define reg_iop_fifo_in_r_intr___last_data___lsb 1
#define reg_iop_fifo_in_r_intr___last_data___width 1
#define reg_iop_fifo_in_r_intr___last_data___bit 1
#define reg_iop_fifo_in_r_intr___dav___lsb 2
#define reg_iop_fifo_in_r_intr___dav___width 1
#define reg_iop_fifo_in_r_intr___dav___bit 2
#define reg_iop_fifo_in_r_intr___avail___lsb 3
#define reg_iop_fifo_in_r_intr___avail___width 1
#define reg_iop_fifo_in_r_intr___avail___bit 3
#define reg_iop_fifo_in_r_intr___orun___lsb 4
#define reg_iop_fifo_in_r_intr___orun___width 1
#define reg_iop_fifo_in_r_intr___orun___bit 4
#define reg_iop_fifo_in_r_intr_offset 60
/* Register r_masked_intr, scope iop_fifo_in, type r */
#define reg_iop_fifo_in_r_masked_intr___urun___lsb 0
#define reg_iop_fifo_in_r_masked_intr___urun___width 1
#define reg_iop_fifo_in_r_masked_intr___urun___bit 0
#define reg_iop_fifo_in_r_masked_intr___last_data___lsb 1
#define reg_iop_fifo_in_r_masked_intr___last_data___width 1
#define reg_iop_fifo_in_r_masked_intr___last_data___bit 1
#define reg_iop_fifo_in_r_masked_intr___dav___lsb 2
#define reg_iop_fifo_in_r_masked_intr___dav___width 1
#define reg_iop_fifo_in_r_masked_intr___dav___bit 2
#define reg_iop_fifo_in_r_masked_intr___avail___lsb 3
#define reg_iop_fifo_in_r_masked_intr___avail___width 1
#define reg_iop_fifo_in_r_masked_intr___avail___bit 3
#define reg_iop_fifo_in_r_masked_intr___orun___lsb 4
#define reg_iop_fifo_in_r_masked_intr___orun___width 1
#define reg_iop_fifo_in_r_masked_intr___orun___bit 4
#define reg_iop_fifo_in_r_masked_intr_offset 64
/* Constants */
#define regk_iop_fifo_in_dif_in 0x00000002
#define regk_iop_fifo_in_hi 0x00000000
#define regk_iop_fifo_in_neg 0x00000002
#define regk_iop_fifo_in_no 0x00000000
#define regk_iop_fifo_in_order16 0x00000001
#define regk_iop_fifo_in_order24 0x00000002
#define regk_iop_fifo_in_order32 0x00000003
#define regk_iop_fifo_in_order8 0x00000000
#define regk_iop_fifo_in_pos 0x00000001
#define regk_iop_fifo_in_pos_neg 0x00000003
#define regk_iop_fifo_in_rw_cfg_default 0x00000024
#define regk_iop_fifo_in_rw_ctrl_default 0x00000000
#define regk_iop_fifo_in_rw_intr_mask_default 0x00000000
#define regk_iop_fifo_in_rw_set_last_default 0x00000000
#define regk_iop_fifo_in_rw_strb_dif_in_default 0x00000000
#define regk_iop_fifo_in_size16 0x00000002
#define regk_iop_fifo_in_size24 0x00000001
#define regk_iop_fifo_in_size32 0x00000000
#define regk_iop_fifo_in_size8 0x00000003
#define regk_iop_fifo_in_yes 0x00000001
#endif /* __iop_fifo_in_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h Normal file
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#ifndef __iop_fifo_in_extra_defs_asm_h
#define __iop_fifo_in_extra_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r
* id: <not found>
* last modfied: Mon Apr 11 16:10:08 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r
* id: $Id: iop_fifo_in_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */
#define reg_iop_fifo_in_extra_rw_wr_data_offset 0
/* Register r_stat, scope iop_fifo_in_extra, type r */
#define reg_iop_fifo_in_extra_r_stat___avail_bytes___lsb 0
#define reg_iop_fifo_in_extra_r_stat___avail_bytes___width 4
#define reg_iop_fifo_in_extra_r_stat___last___lsb 4
#define reg_iop_fifo_in_extra_r_stat___last___width 8
#define reg_iop_fifo_in_extra_r_stat___dif_in_en___lsb 12
#define reg_iop_fifo_in_extra_r_stat___dif_in_en___width 1
#define reg_iop_fifo_in_extra_r_stat___dif_in_en___bit 12
#define reg_iop_fifo_in_extra_r_stat___dif_out_en___lsb 13
#define reg_iop_fifo_in_extra_r_stat___dif_out_en___width 1
#define reg_iop_fifo_in_extra_r_stat___dif_out_en___bit 13
#define reg_iop_fifo_in_extra_r_stat_offset 4
/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */
#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___lsb 0
#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___width 2
#define reg_iop_fifo_in_extra_rw_strb_dif_in_offset 8
/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */
#define reg_iop_fifo_in_extra_rw_intr_mask___urun___lsb 0
#define reg_iop_fifo_in_extra_rw_intr_mask___urun___width 1
#define reg_iop_fifo_in_extra_rw_intr_mask___urun___bit 0
#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___lsb 1
#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___width 1
#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___bit 1
#define reg_iop_fifo_in_extra_rw_intr_mask___dav___lsb 2
#define reg_iop_fifo_in_extra_rw_intr_mask___dav___width 1
#define reg_iop_fifo_in_extra_rw_intr_mask___dav___bit 2
#define reg_iop_fifo_in_extra_rw_intr_mask___avail___lsb 3
#define reg_iop_fifo_in_extra_rw_intr_mask___avail___width 1
#define reg_iop_fifo_in_extra_rw_intr_mask___avail___bit 3
#define reg_iop_fifo_in_extra_rw_intr_mask___orun___lsb 4
#define reg_iop_fifo_in_extra_rw_intr_mask___orun___width 1
#define reg_iop_fifo_in_extra_rw_intr_mask___orun___bit 4
#define reg_iop_fifo_in_extra_rw_intr_mask_offset 12
/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */
#define reg_iop_fifo_in_extra_rw_ack_intr___urun___lsb 0
#define reg_iop_fifo_in_extra_rw_ack_intr___urun___width 1
#define reg_iop_fifo_in_extra_rw_ack_intr___urun___bit 0
#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___lsb 1
#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___width 1
#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___bit 1
#define reg_iop_fifo_in_extra_rw_ack_intr___dav___lsb 2
#define reg_iop_fifo_in_extra_rw_ack_intr___dav___width 1
#define reg_iop_fifo_in_extra_rw_ack_intr___dav___bit 2
#define reg_iop_fifo_in_extra_rw_ack_intr___avail___lsb 3
#define reg_iop_fifo_in_extra_rw_ack_intr___avail___width 1
#define reg_iop_fifo_in_extra_rw_ack_intr___avail___bit 3
#define reg_iop_fifo_in_extra_rw_ack_intr___orun___lsb 4
#define reg_iop_fifo_in_extra_rw_ack_intr___orun___width 1
#define reg_iop_fifo_in_extra_rw_ack_intr___orun___bit 4
#define reg_iop_fifo_in_extra_rw_ack_intr_offset 16
/* Register r_intr, scope iop_fifo_in_extra, type r */
#define reg_iop_fifo_in_extra_r_intr___urun___lsb 0
#define reg_iop_fifo_in_extra_r_intr___urun___width 1
#define reg_iop_fifo_in_extra_r_intr___urun___bit 0
#define reg_iop_fifo_in_extra_r_intr___last_data___lsb 1
#define reg_iop_fifo_in_extra_r_intr___last_data___width 1
#define reg_iop_fifo_in_extra_r_intr___last_data___bit 1
#define reg_iop_fifo_in_extra_r_intr___dav___lsb 2
#define reg_iop_fifo_in_extra_r_intr___dav___width 1
#define reg_iop_fifo_in_extra_r_intr___dav___bit 2
#define reg_iop_fifo_in_extra_r_intr___avail___lsb 3
#define reg_iop_fifo_in_extra_r_intr___avail___width 1
#define reg_iop_fifo_in_extra_r_intr___avail___bit 3
#define reg_iop_fifo_in_extra_r_intr___orun___lsb 4
#define reg_iop_fifo_in_extra_r_intr___orun___width 1
#define reg_iop_fifo_in_extra_r_intr___orun___bit 4
#define reg_iop_fifo_in_extra_r_intr_offset 20
/* Register r_masked_intr, scope iop_fifo_in_extra, type r */
#define reg_iop_fifo_in_extra_r_masked_intr___urun___lsb 0
#define reg_iop_fifo_in_extra_r_masked_intr___urun___width 1
#define reg_iop_fifo_in_extra_r_masked_intr___urun___bit 0
#define reg_iop_fifo_in_extra_r_masked_intr___last_data___lsb 1
#define reg_iop_fifo_in_extra_r_masked_intr___last_data___width 1
#define reg_iop_fifo_in_extra_r_masked_intr___last_data___bit 1
#define reg_iop_fifo_in_extra_r_masked_intr___dav___lsb 2
#define reg_iop_fifo_in_extra_r_masked_intr___dav___width 1
#define reg_iop_fifo_in_extra_r_masked_intr___dav___bit 2
#define reg_iop_fifo_in_extra_r_masked_intr___avail___lsb 3
#define reg_iop_fifo_in_extra_r_masked_intr___avail___width 1
#define reg_iop_fifo_in_extra_r_masked_intr___avail___bit 3
#define reg_iop_fifo_in_extra_r_masked_intr___orun___lsb 4
#define reg_iop_fifo_in_extra_r_masked_intr___orun___width 1
#define reg_iop_fifo_in_extra_r_masked_intr___orun___bit 4
#define reg_iop_fifo_in_extra_r_masked_intr_offset 24
/* Constants */
#define regk_iop_fifo_in_extra_fifo_in 0x00000002
#define regk_iop_fifo_in_extra_no 0x00000000
#define regk_iop_fifo_in_extra_rw_intr_mask_default 0x00000000
#define regk_iop_fifo_in_extra_yes 0x00000001
#endif /* __iop_fifo_in_extra_defs_asm_h */

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#ifndef __iop_fifo_out_defs_asm_h
#define __iop_fifo_out_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_fifo_out.r
* id: <not found>
* last modfied: Mon Apr 11 16:10:09 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r
* id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_cfg, scope iop_fifo_out, type rw */
#define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0
#define reg_iop_fifo_out_rw_cfg___free_lim___width 3
#define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3
#define reg_iop_fifo_out_rw_cfg___byte_order___width 2
#define reg_iop_fifo_out_rw_cfg___trig___lsb 5
#define reg_iop_fifo_out_rw_cfg___trig___width 2
#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7
#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1
#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7
#define reg_iop_fifo_out_rw_cfg___mode___lsb 8
#define reg_iop_fifo_out_rw_cfg___mode___width 2
#define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10
#define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1
#define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10
#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11
#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1
#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11
#define reg_iop_fifo_out_rw_cfg_offset 0
/* Register rw_ctrl, scope iop_fifo_out, type rw */
#define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0
#define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1
#define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0
#define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1
#define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1
#define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1
#define reg_iop_fifo_out_rw_ctrl_offset 4
/* Register r_stat, scope iop_fifo_out, type r */
#define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0
#define reg_iop_fifo_out_r_stat___avail_bytes___width 4
#define reg_iop_fifo_out_r_stat___last___lsb 4
#define reg_iop_fifo_out_r_stat___last___width 8
#define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12
#define reg_iop_fifo_out_r_stat___dif_in_en___width 1
#define reg_iop_fifo_out_r_stat___dif_in_en___bit 12
#define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13
#define reg_iop_fifo_out_r_stat___dif_out_en___width 1
#define reg_iop_fifo_out_r_stat___dif_out_en___bit 13
#define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14
#define reg_iop_fifo_out_r_stat___zero_data_last___width 1
#define reg_iop_fifo_out_r_stat___zero_data_last___bit 14
#define reg_iop_fifo_out_r_stat_offset 8
/* Register rw_wr1byte, scope iop_fifo_out, type rw */
#define reg_iop_fifo_out_rw_wr1byte___data___lsb 0
#define reg_iop_fifo_out_rw_wr1byte___data___width 8
#define reg_iop_fifo_out_rw_wr1byte_offset 12
/* Register rw_wr2byte, scope iop_fifo_out, type rw */
#define reg_iop_fifo_out_rw_wr2byte___data___lsb 0
#define reg_iop_fifo_out_rw_wr2byte___data___width 16
#define reg_iop_fifo_out_rw_wr2byte_offset 16
/* Register rw_wr3byte, scope iop_fifo_out, type rw */
#define reg_iop_fifo_out_rw_wr3byte___data___lsb 0
#define reg_iop_fifo_out_rw_wr3byte___data___width 24
#define reg_iop_fifo_out_rw_wr3byte_offset 20
/* Register rw_wr4byte, scope iop_fifo_out, type rw */
#define reg_iop_fifo_out_rw_wr4byte___data___lsb 0
#define reg_iop_fifo_out_rw_wr4byte___data___width 32
#define reg_iop_fifo_out_rw_wr4byte_offset 24
/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
#define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0
#define reg_iop_fifo_out_rw_wr1byte_last___data___width 8
#define reg_iop_fifo_out_rw_wr1byte_last_offset 28
/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
#define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0
#define reg_iop_fifo_out_rw_wr2byte_last___data___width 16
#define reg_iop_fifo_out_rw_wr2byte_last_offset 32
/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
#define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0
#define reg_iop_fifo_out_rw_wr3byte_last___data___width 24
#define reg_iop_fifo_out_rw_wr3byte_last_offset 36
/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
#define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0
#define reg_iop_fifo_out_rw_wr4byte_last___data___width 32
#define reg_iop_fifo_out_rw_wr4byte_last_offset 40
/* Register rw_set_last, scope iop_fifo_out, type rw */
#define reg_iop_fifo_out_rw_set_last_offset 44
/* Register rs_rd_data, scope iop_fifo_out, type rs */
#define reg_iop_fifo_out_rs_rd_data_offset 48
/* Register r_rd_data, scope iop_fifo_out, type r */
#define reg_iop_fifo_out_r_rd_data_offset 52
/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
#define reg_iop_fifo_out_rw_strb_dif_out_offset 56
/* Register rw_intr_mask, scope iop_fifo_out, type rw */
#define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0
#define reg_iop_fifo_out_rw_intr_mask___urun___width 1
#define reg_iop_fifo_out_rw_intr_mask___urun___bit 0
#define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1
#define reg_iop_fifo_out_rw_intr_mask___last_data___width 1
#define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1
#define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2
#define reg_iop_fifo_out_rw_intr_mask___dav___width 1
#define reg_iop_fifo_out_rw_intr_mask___dav___bit 2
#define reg_iop_fifo_out_rw_intr_mask___free___lsb 3
#define reg_iop_fifo_out_rw_intr_mask___free___width 1
#define reg_iop_fifo_out_rw_intr_mask___free___bit 3
#define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4
#define reg_iop_fifo_out_rw_intr_mask___orun___width 1
#define reg_iop_fifo_out_rw_intr_mask___orun___bit 4
#define reg_iop_fifo_out_rw_intr_mask_offset 60
/* Register rw_ack_intr, scope iop_fifo_out, type rw */
#define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0
#define reg_iop_fifo_out_rw_ack_intr___urun___width 1
#define reg_iop_fifo_out_rw_ack_intr___urun___bit 0
#define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1
#define reg_iop_fifo_out_rw_ack_intr___last_data___width 1
#define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1
#define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2
#define reg_iop_fifo_out_rw_ack_intr___dav___width 1
#define reg_iop_fifo_out_rw_ack_intr___dav___bit 2
#define reg_iop_fifo_out_rw_ack_intr___free___lsb 3
#define reg_iop_fifo_out_rw_ack_intr___free___width 1
#define reg_iop_fifo_out_rw_ack_intr___free___bit 3
#define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4
#define reg_iop_fifo_out_rw_ack_intr___orun___width 1
#define reg_iop_fifo_out_rw_ack_intr___orun___bit 4
#define reg_iop_fifo_out_rw_ack_intr_offset 64
/* Register r_intr, scope iop_fifo_out, type r */
#define reg_iop_fifo_out_r_intr___urun___lsb 0
#define reg_iop_fifo_out_r_intr___urun___width 1
#define reg_iop_fifo_out_r_intr___urun___bit 0
#define reg_iop_fifo_out_r_intr___last_data___lsb 1
#define reg_iop_fifo_out_r_intr___last_data___width 1
#define reg_iop_fifo_out_r_intr___last_data___bit 1
#define reg_iop_fifo_out_r_intr___dav___lsb 2
#define reg_iop_fifo_out_r_intr___dav___width 1
#define reg_iop_fifo_out_r_intr___dav___bit 2
#define reg_iop_fifo_out_r_intr___free___lsb 3
#define reg_iop_fifo_out_r_intr___free___width 1
#define reg_iop_fifo_out_r_intr___free___bit 3
#define reg_iop_fifo_out_r_intr___orun___lsb 4
#define reg_iop_fifo_out_r_intr___orun___width 1
#define reg_iop_fifo_out_r_intr___orun___bit 4
#define reg_iop_fifo_out_r_intr_offset 68
/* Register r_masked_intr, scope iop_fifo_out, type r */
#define reg_iop_fifo_out_r_masked_intr___urun___lsb 0
#define reg_iop_fifo_out_r_masked_intr___urun___width 1
#define reg_iop_fifo_out_r_masked_intr___urun___bit 0
#define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1
#define reg_iop_fifo_out_r_masked_intr___last_data___width 1
#define reg_iop_fifo_out_r_masked_intr___last_data___bit 1
#define reg_iop_fifo_out_r_masked_intr___dav___lsb 2
#define reg_iop_fifo_out_r_masked_intr___dav___width 1
#define reg_iop_fifo_out_r_masked_intr___dav___bit 2
#define reg_iop_fifo_out_r_masked_intr___free___lsb 3
#define reg_iop_fifo_out_r_masked_intr___free___width 1
#define reg_iop_fifo_out_r_masked_intr___free___bit 3
#define reg_iop_fifo_out_r_masked_intr___orun___lsb 4
#define reg_iop_fifo_out_r_masked_intr___orun___width 1
#define reg_iop_fifo_out_r_masked_intr___orun___bit 4
#define reg_iop_fifo_out_r_masked_intr_offset 72
/* Constants */
#define regk_iop_fifo_out_hi 0x00000000
#define regk_iop_fifo_out_neg 0x00000002
#define regk_iop_fifo_out_no 0x00000000
#define regk_iop_fifo_out_order16 0x00000001
#define regk_iop_fifo_out_order24 0x00000002
#define regk_iop_fifo_out_order32 0x00000003
#define regk_iop_fifo_out_order8 0x00000000
#define regk_iop_fifo_out_pos 0x00000001
#define regk_iop_fifo_out_pos_neg 0x00000003
#define regk_iop_fifo_out_rw_cfg_default 0x00000024
#define regk_iop_fifo_out_rw_ctrl_default 0x00000000
#define regk_iop_fifo_out_rw_intr_mask_default 0x00000000
#define regk_iop_fifo_out_rw_set_last_default 0x00000000
#define regk_iop_fifo_out_rw_strb_dif_out_default 0x00000000
#define regk_iop_fifo_out_rw_wr1byte_default 0x00000000
#define regk_iop_fifo_out_rw_wr1byte_last_default 0x00000000
#define regk_iop_fifo_out_rw_wr2byte_default 0x00000000
#define regk_iop_fifo_out_rw_wr2byte_last_default 0x00000000
#define regk_iop_fifo_out_rw_wr3byte_default 0x00000000
#define regk_iop_fifo_out_rw_wr3byte_last_default 0x00000000
#define regk_iop_fifo_out_rw_wr4byte_default 0x00000000
#define regk_iop_fifo_out_rw_wr4byte_last_default 0x00000000
#define regk_iop_fifo_out_size16 0x00000002
#define regk_iop_fifo_out_size24 0x00000001
#define regk_iop_fifo_out_size32 0x00000000
#define regk_iop_fifo_out_size8 0x00000003
#define regk_iop_fifo_out_yes 0x00000001
#endif /* __iop_fifo_out_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h Normal file
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#ifndef __iop_fifo_out_extra_defs_asm_h
#define __iop_fifo_out_extra_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r
* id: <not found>
* last modfied: Mon Apr 11 16:10:10 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
* id: $Id: iop_fifo_out_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */
#define reg_iop_fifo_out_extra_rs_rd_data_offset 0
/* Register r_rd_data, scope iop_fifo_out_extra, type r */
#define reg_iop_fifo_out_extra_r_rd_data_offset 4
/* Register r_stat, scope iop_fifo_out_extra, type r */
#define reg_iop_fifo_out_extra_r_stat___avail_bytes___lsb 0
#define reg_iop_fifo_out_extra_r_stat___avail_bytes___width 4
#define reg_iop_fifo_out_extra_r_stat___last___lsb 4
#define reg_iop_fifo_out_extra_r_stat___last___width 8
#define reg_iop_fifo_out_extra_r_stat___dif_in_en___lsb 12
#define reg_iop_fifo_out_extra_r_stat___dif_in_en___width 1
#define reg_iop_fifo_out_extra_r_stat___dif_in_en___bit 12
#define reg_iop_fifo_out_extra_r_stat___dif_out_en___lsb 13
#define reg_iop_fifo_out_extra_r_stat___dif_out_en___width 1
#define reg_iop_fifo_out_extra_r_stat___dif_out_en___bit 13
#define reg_iop_fifo_out_extra_r_stat___zero_data_last___lsb 14
#define reg_iop_fifo_out_extra_r_stat___zero_data_last___width 1
#define reg_iop_fifo_out_extra_r_stat___zero_data_last___bit 14
#define reg_iop_fifo_out_extra_r_stat_offset 8
/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
#define reg_iop_fifo_out_extra_rw_strb_dif_out_offset 12
/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
#define reg_iop_fifo_out_extra_rw_intr_mask___urun___lsb 0
#define reg_iop_fifo_out_extra_rw_intr_mask___urun___width 1
#define reg_iop_fifo_out_extra_rw_intr_mask___urun___bit 0
#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___lsb 1
#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___width 1
#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___bit 1
#define reg_iop_fifo_out_extra_rw_intr_mask___dav___lsb 2
#define reg_iop_fifo_out_extra_rw_intr_mask___dav___width 1
#define reg_iop_fifo_out_extra_rw_intr_mask___dav___bit 2
#define reg_iop_fifo_out_extra_rw_intr_mask___free___lsb 3
#define reg_iop_fifo_out_extra_rw_intr_mask___free___width 1
#define reg_iop_fifo_out_extra_rw_intr_mask___free___bit 3
#define reg_iop_fifo_out_extra_rw_intr_mask___orun___lsb 4
#define reg_iop_fifo_out_extra_rw_intr_mask___orun___width 1
#define reg_iop_fifo_out_extra_rw_intr_mask___orun___bit 4
#define reg_iop_fifo_out_extra_rw_intr_mask_offset 16
/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
#define reg_iop_fifo_out_extra_rw_ack_intr___urun___lsb 0
#define reg_iop_fifo_out_extra_rw_ack_intr___urun___width 1
#define reg_iop_fifo_out_extra_rw_ack_intr___urun___bit 0
#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___lsb 1
#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___width 1
#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___bit 1
#define reg_iop_fifo_out_extra_rw_ack_intr___dav___lsb 2
#define reg_iop_fifo_out_extra_rw_ack_intr___dav___width 1
#define reg_iop_fifo_out_extra_rw_ack_intr___dav___bit 2
#define reg_iop_fifo_out_extra_rw_ack_intr___free___lsb 3
#define reg_iop_fifo_out_extra_rw_ack_intr___free___width 1
#define reg_iop_fifo_out_extra_rw_ack_intr___free___bit 3
#define reg_iop_fifo_out_extra_rw_ack_intr___orun___lsb 4
#define reg_iop_fifo_out_extra_rw_ack_intr___orun___width 1
#define reg_iop_fifo_out_extra_rw_ack_intr___orun___bit 4
#define reg_iop_fifo_out_extra_rw_ack_intr_offset 20
/* Register r_intr, scope iop_fifo_out_extra, type r */
#define reg_iop_fifo_out_extra_r_intr___urun___lsb 0
#define reg_iop_fifo_out_extra_r_intr___urun___width 1
#define reg_iop_fifo_out_extra_r_intr___urun___bit 0
#define reg_iop_fifo_out_extra_r_intr___last_data___lsb 1
#define reg_iop_fifo_out_extra_r_intr___last_data___width 1
#define reg_iop_fifo_out_extra_r_intr___last_data___bit 1
#define reg_iop_fifo_out_extra_r_intr___dav___lsb 2
#define reg_iop_fifo_out_extra_r_intr___dav___width 1
#define reg_iop_fifo_out_extra_r_intr___dav___bit 2
#define reg_iop_fifo_out_extra_r_intr___free___lsb 3
#define reg_iop_fifo_out_extra_r_intr___free___width 1
#define reg_iop_fifo_out_extra_r_intr___free___bit 3
#define reg_iop_fifo_out_extra_r_intr___orun___lsb 4
#define reg_iop_fifo_out_extra_r_intr___orun___width 1
#define reg_iop_fifo_out_extra_r_intr___orun___bit 4
#define reg_iop_fifo_out_extra_r_intr_offset 24
/* Register r_masked_intr, scope iop_fifo_out_extra, type r */
#define reg_iop_fifo_out_extra_r_masked_intr___urun___lsb 0
#define reg_iop_fifo_out_extra_r_masked_intr___urun___width 1
#define reg_iop_fifo_out_extra_r_masked_intr___urun___bit 0
#define reg_iop_fifo_out_extra_r_masked_intr___last_data___lsb 1
#define reg_iop_fifo_out_extra_r_masked_intr___last_data___width 1
#define reg_iop_fifo_out_extra_r_masked_intr___last_data___bit 1
#define reg_iop_fifo_out_extra_r_masked_intr___dav___lsb 2
#define reg_iop_fifo_out_extra_r_masked_intr___dav___width 1
#define reg_iop_fifo_out_extra_r_masked_intr___dav___bit 2
#define reg_iop_fifo_out_extra_r_masked_intr___free___lsb 3
#define reg_iop_fifo_out_extra_r_masked_intr___free___width 1
#define reg_iop_fifo_out_extra_r_masked_intr___free___bit 3
#define reg_iop_fifo_out_extra_r_masked_intr___orun___lsb 4
#define reg_iop_fifo_out_extra_r_masked_intr___orun___width 1
#define reg_iop_fifo_out_extra_r_masked_intr___orun___bit 4
#define reg_iop_fifo_out_extra_r_masked_intr_offset 28
/* Constants */
#define regk_iop_fifo_out_extra_no 0x00000000
#define regk_iop_fifo_out_extra_rw_intr_mask_default 0x00000000
#define regk_iop_fifo_out_extra_yes 0x00000001
#endif /* __iop_fifo_out_extra_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h Normal file
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#ifndef __iop_mpu_defs_asm_h
#define __iop_mpu_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_mpu.r
* id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp
* last modfied: Mon Apr 11 16:08:45 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r
* id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
#define STRIDE_iop_mpu_rw_r 4
/* Register rw_r, scope iop_mpu, type rw */
#define reg_iop_mpu_rw_r_offset 0
/* Register rw_ctrl, scope iop_mpu, type rw */
#define reg_iop_mpu_rw_ctrl___en___lsb 0
#define reg_iop_mpu_rw_ctrl___en___width 1
#define reg_iop_mpu_rw_ctrl___en___bit 0
#define reg_iop_mpu_rw_ctrl_offset 128
/* Register r_pc, scope iop_mpu, type r */
#define reg_iop_mpu_r_pc___addr___lsb 0
#define reg_iop_mpu_r_pc___addr___width 12
#define reg_iop_mpu_r_pc_offset 132
/* Register r_stat, scope iop_mpu, type r */
#define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0
#define reg_iop_mpu_r_stat___instr_reg_busy___width 1
#define reg_iop_mpu_r_stat___instr_reg_busy___bit 0
#define reg_iop_mpu_r_stat___intr_busy___lsb 1
#define reg_iop_mpu_r_stat___intr_busy___width 1
#define reg_iop_mpu_r_stat___intr_busy___bit 1
#define reg_iop_mpu_r_stat___intr_vect___lsb 2
#define reg_iop_mpu_r_stat___intr_vect___width 16
#define reg_iop_mpu_r_stat_offset 136
/* Register rw_instr, scope iop_mpu, type rw */
#define reg_iop_mpu_rw_instr_offset 140
/* Register rw_immediate, scope iop_mpu, type rw */
#define reg_iop_mpu_rw_immediate_offset 144
/* Register r_trace, scope iop_mpu, type r */
#define reg_iop_mpu_r_trace___intr_vect___lsb 0
#define reg_iop_mpu_r_trace___intr_vect___width 16
#define reg_iop_mpu_r_trace___pc___lsb 16
#define reg_iop_mpu_r_trace___pc___width 12
#define reg_iop_mpu_r_trace___en___lsb 28
#define reg_iop_mpu_r_trace___en___width 1
#define reg_iop_mpu_r_trace___en___bit 28
#define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29
#define reg_iop_mpu_r_trace___instr_reg_busy___width 1
#define reg_iop_mpu_r_trace___instr_reg_busy___bit 29
#define reg_iop_mpu_r_trace___intr_busy___lsb 30
#define reg_iop_mpu_r_trace___intr_busy___width 1
#define reg_iop_mpu_r_trace___intr_busy___bit 30
#define reg_iop_mpu_r_trace_offset 148
/* Register r_wr_stat, scope iop_mpu, type r */
#define reg_iop_mpu_r_wr_stat___r0___lsb 0
#define reg_iop_mpu_r_wr_stat___r0___width 1
#define reg_iop_mpu_r_wr_stat___r0___bit 0
#define reg_iop_mpu_r_wr_stat___r1___lsb 1
#define reg_iop_mpu_r_wr_stat___r1___width 1
#define reg_iop_mpu_r_wr_stat___r1___bit 1
#define reg_iop_mpu_r_wr_stat___r2___lsb 2
#define reg_iop_mpu_r_wr_stat___r2___width 1
#define reg_iop_mpu_r_wr_stat___r2___bit 2
#define reg_iop_mpu_r_wr_stat___r3___lsb 3
#define reg_iop_mpu_r_wr_stat___r3___width 1
#define reg_iop_mpu_r_wr_stat___r3___bit 3
#define reg_iop_mpu_r_wr_stat___r4___lsb 4
#define reg_iop_mpu_r_wr_stat___r4___width 1
#define reg_iop_mpu_r_wr_stat___r4___bit 4
#define reg_iop_mpu_r_wr_stat___r5___lsb 5
#define reg_iop_mpu_r_wr_stat___r5___width 1
#define reg_iop_mpu_r_wr_stat___r5___bit 5
#define reg_iop_mpu_r_wr_stat___r6___lsb 6
#define reg_iop_mpu_r_wr_stat___r6___width 1
#define reg_iop_mpu_r_wr_stat___r6___bit 6
#define reg_iop_mpu_r_wr_stat___r7___lsb 7
#define reg_iop_mpu_r_wr_stat___r7___width 1
#define reg_iop_mpu_r_wr_stat___r7___bit 7
#define reg_iop_mpu_r_wr_stat___r8___lsb 8
#define reg_iop_mpu_r_wr_stat___r8___width 1
#define reg_iop_mpu_r_wr_stat___r8___bit 8
#define reg_iop_mpu_r_wr_stat___r9___lsb 9
#define reg_iop_mpu_r_wr_stat___r9___width 1
#define reg_iop_mpu_r_wr_stat___r9___bit 9
#define reg_iop_mpu_r_wr_stat___r10___lsb 10
#define reg_iop_mpu_r_wr_stat___r10___width 1
#define reg_iop_mpu_r_wr_stat___r10___bit 10
#define reg_iop_mpu_r_wr_stat___r11___lsb 11
#define reg_iop_mpu_r_wr_stat___r11___width 1
#define reg_iop_mpu_r_wr_stat___r11___bit 11
#define reg_iop_mpu_r_wr_stat___r12___lsb 12
#define reg_iop_mpu_r_wr_stat___r12___width 1
#define reg_iop_mpu_r_wr_stat___r12___bit 12
#define reg_iop_mpu_r_wr_stat___r13___lsb 13
#define reg_iop_mpu_r_wr_stat___r13___width 1
#define reg_iop_mpu_r_wr_stat___r13___bit 13
#define reg_iop_mpu_r_wr_stat___r14___lsb 14
#define reg_iop_mpu_r_wr_stat___r14___width 1
#define reg_iop_mpu_r_wr_stat___r14___bit 14
#define reg_iop_mpu_r_wr_stat___r15___lsb 15
#define reg_iop_mpu_r_wr_stat___r15___width 1
#define reg_iop_mpu_r_wr_stat___r15___bit 15
#define reg_iop_mpu_r_wr_stat_offset 152
#define STRIDE_iop_mpu_rw_thread 4
/* Register rw_thread, scope iop_mpu, type rw */
#define reg_iop_mpu_rw_thread___addr___lsb 0
#define reg_iop_mpu_rw_thread___addr___width 12
#define reg_iop_mpu_rw_thread_offset 156
#define STRIDE_iop_mpu_rw_intr 4
/* Register rw_intr, scope iop_mpu, type rw */
#define reg_iop_mpu_rw_intr___addr___lsb 0
#define reg_iop_mpu_rw_intr___addr___width 12
#define reg_iop_mpu_rw_intr_offset 196
/* Constants */
#define regk_iop_mpu_no 0x00000000
#define regk_iop_mpu_r_pc_default 0x00000000
#define regk_iop_mpu_rw_ctrl_default 0x00000000
#define regk_iop_mpu_rw_intr_size 0x00000010
#define regk_iop_mpu_rw_r_size 0x00000010
#define regk_iop_mpu_rw_thread_default 0x00000000
#define regk_iop_mpu_rw_thread_size 0x00000004
#define regk_iop_mpu_yes 0x00000001
#endif /* __iop_mpu_defs_asm_h */

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/* Autogenerated Changes here will be lost!
* generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg
*/
#define iop_version 0
#define iop_fifo_in0_extra 64
#define iop_fifo_in1_extra 128
#define iop_fifo_out0_extra 192
#define iop_fifo_out1_extra 256
#define iop_trigger_grp0 320
#define iop_trigger_grp1 384
#define iop_trigger_grp2 448
#define iop_trigger_grp3 512
#define iop_trigger_grp4 576
#define iop_trigger_grp5 640
#define iop_trigger_grp6 704
#define iop_trigger_grp7 768
#define iop_crc_par0 896
#define iop_crc_par1 1024
#define iop_dmc_in0 1152
#define iop_dmc_in1 1280
#define iop_dmc_out0 1408
#define iop_dmc_out1 1536
#define iop_fifo_in0 1664
#define iop_fifo_in1 1792
#define iop_fifo_out0 1920
#define iop_fifo_out1 2048
#define iop_scrc_in0 2176
#define iop_scrc_in1 2304
#define iop_scrc_out0 2432
#define iop_scrc_out1 2560
#define iop_timer_grp0 2688
#define iop_timer_grp1 2816
#define iop_timer_grp2 2944
#define iop_timer_grp3 3072
#define iop_sap_in 3328
#define iop_sap_out 3584
#define iop_spu0 3840
#define iop_spu1 4096
#define iop_sw_cfg 4352
#define iop_sw_cpu 4608
#define iop_sw_mpu 4864
#define iop_sw_spu0 5120
#define iop_sw_spu1 5376
#define iop_mpu 5632

182
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#ifndef __iop_sap_in_defs_asm_h
#define __iop_sap_in_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_sap_in.r
* id: <not found>
* last modfied: Mon Apr 11 16:08:45 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r
* id: $Id: iop_sap_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_bus0_sync, scope iop_sap_in, type rw */
#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0
#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2
#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2
#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3
#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5
#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2
#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7
#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1
#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7
#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8
#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2
#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10
#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3
#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13
#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2
#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15
#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1
#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15
#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16
#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2
#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18
#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3
#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21
#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2
#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23
#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1
#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23
#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24
#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2
#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26
#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3
#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29
#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2
#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31
#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1
#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31
#define reg_iop_sap_in_rw_bus0_sync_offset 0
/* Register rw_bus1_sync, scope iop_sap_in, type rw */
#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0
#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2
#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2
#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3
#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5
#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2
#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7
#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1
#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7
#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8
#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2
#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10
#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3
#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13
#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2
#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15
#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1
#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15
#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16
#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2
#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18
#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3
#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21
#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2
#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23
#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1
#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23
#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24
#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2
#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26
#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3
#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29
#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2
#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31
#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1
#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31
#define reg_iop_sap_in_rw_bus1_sync_offset 4
#define STRIDE_iop_sap_in_rw_gio 4
/* Register rw_gio, scope iop_sap_in, type rw */
#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
#define reg_iop_sap_in_rw_gio___sync_sel___width 2
#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
#define reg_iop_sap_in_rw_gio___sync_edge___width 2
#define reg_iop_sap_in_rw_gio___delay___lsb 7
#define reg_iop_sap_in_rw_gio___delay___width 1
#define reg_iop_sap_in_rw_gio___delay___bit 7
#define reg_iop_sap_in_rw_gio___logic___lsb 8
#define reg_iop_sap_in_rw_gio___logic___width 2
#define reg_iop_sap_in_rw_gio_offset 8
/* Constants */
#define regk_iop_sap_in_and 0x00000002
#define regk_iop_sap_in_ext_clk200 0x00000003
#define regk_iop_sap_in_gio1 0x00000000
#define regk_iop_sap_in_gio13 0x00000005
#define regk_iop_sap_in_gio18 0x00000003
#define regk_iop_sap_in_gio19 0x00000004
#define regk_iop_sap_in_gio21 0x00000006
#define regk_iop_sap_in_gio23 0x00000005
#define regk_iop_sap_in_gio29 0x00000007
#define regk_iop_sap_in_gio5 0x00000004
#define regk_iop_sap_in_gio6 0x00000001
#define regk_iop_sap_in_gio7 0x00000002
#define regk_iop_sap_in_inv 0x00000001
#define regk_iop_sap_in_neg 0x00000002
#define regk_iop_sap_in_no 0x00000000
#define regk_iop_sap_in_no_del_ext_clk200 0x00000001
#define regk_iop_sap_in_none 0x00000000
#define regk_iop_sap_in_or 0x00000003
#define regk_iop_sap_in_pos 0x00000001
#define regk_iop_sap_in_pos_neg 0x00000003
#define regk_iop_sap_in_rw_bus0_sync_default 0x02020202
#define regk_iop_sap_in_rw_bus1_sync_default 0x02020202
#define regk_iop_sap_in_rw_gio_default 0x00000002
#define regk_iop_sap_in_rw_gio_size 0x00000020
#define regk_iop_sap_in_timer_grp0_tmr3 0x00000006
#define regk_iop_sap_in_timer_grp1_tmr3 0x00000004
#define regk_iop_sap_in_timer_grp2_tmr3 0x00000005
#define regk_iop_sap_in_timer_grp3_tmr3 0x00000007
#define regk_iop_sap_in_tmr_clk200 0x00000000
#define regk_iop_sap_in_two_clk200 0x00000002
#define regk_iop_sap_in_yes 0x00000001
#endif /* __iop_sap_in_defs_asm_h */

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#ifndef __iop_sap_out_defs_asm_h
#define __iop_sap_out_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_sap_out.r
* id: <not found>
* last modfied: Mon Apr 11 16:08:46 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r
* id: $Id: iop_sap_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_gen_gated, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0
#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2
#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2
#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2
#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4
#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3
#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7
#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2
#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9
#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2
#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11
#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3
#define reg_iop_sap_out_rw_gen_gated___clk2_src___lsb 14
#define reg_iop_sap_out_rw_gen_gated___clk2_src___width 2
#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___lsb 16
#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___width 2
#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___lsb 18
#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___width 3
#define reg_iop_sap_out_rw_gen_gated___clk3_src___lsb 21
#define reg_iop_sap_out_rw_gen_gated___clk3_src___width 2
#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___lsb 23
#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___width 2
#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___lsb 25
#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___width 3
#define reg_iop_sap_out_rw_gen_gated_offset 0
/* Register rw_bus0, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___lsb 0
#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___width 3
#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___lsb 3
#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___width 2
#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___lsb 5
#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___width 1
#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___bit 5
#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___lsb 6
#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___width 3
#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___lsb 9
#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___width 2
#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___lsb 11
#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___width 1
#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___bit 11
#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___lsb 12
#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___width 3
#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___lsb 15
#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___width 2
#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___lsb 17
#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___width 1
#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___bit 17
#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___lsb 18
#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___width 3
#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___lsb 21
#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___width 2
#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___lsb 23
#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___width 1
#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___bit 23
#define reg_iop_sap_out_rw_bus0_offset 4
/* Register rw_bus1, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___lsb 0
#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___width 3
#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___lsb 3
#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___width 2
#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___lsb 5
#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___width 1
#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___bit 5
#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___lsb 6
#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___width 3
#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___lsb 9
#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___width 2
#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___lsb 11
#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___width 1
#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___bit 11
#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___lsb 12
#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___width 3
#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___lsb 15
#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___width 2
#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___lsb 17
#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___width 1
#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___bit 17
#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___lsb 18
#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___width 3
#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___lsb 21
#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___width 2
#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___lsb 23
#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___width 1
#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___bit 23
#define reg_iop_sap_out_rw_bus1_offset 8
/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___lsb 0
#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___width 3
#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___lsb 3
#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___width 3
#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___lsb 6
#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___width 2
#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___lsb 8
#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___width 1
#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___bit 8
#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___lsb 9
#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___width 2
#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___lsb 11
#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___width 3
#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___lsb 14
#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___width 3
#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___lsb 17
#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___width 2
#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___lsb 19
#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___width 1
#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___bit 19
#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___lsb 20
#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___width 2
#define reg_iop_sap_out_rw_bus0_lo_oe_offset 12
/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___lsb 0
#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___width 3
#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___lsb 3
#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___width 3
#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___lsb 6
#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___width 2
#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___lsb 8
#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___width 1
#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___bit 8
#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___lsb 9
#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___width 2
#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___lsb 11
#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___width 3
#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___lsb 14
#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___width 3
#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___lsb 17
#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___width 2
#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___lsb 19
#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___width 1
#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___bit 19
#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___lsb 20
#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___width 2
#define reg_iop_sap_out_rw_bus0_hi_oe_offset 16
/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___lsb 0
#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___width 3
#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___lsb 3
#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___width 3
#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___lsb 6
#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___width 2
#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___lsb 8
#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___width 1
#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___bit 8
#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___lsb 9
#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___width 2
#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___lsb 11
#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___width 3
#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___lsb 14
#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___width 3
#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___lsb 17
#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___width 2
#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___lsb 19
#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___width 1
#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___bit 19
#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___lsb 20
#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___width 2
#define reg_iop_sap_out_rw_bus1_lo_oe_offset 20
/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___lsb 0
#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___width 3
#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___lsb 3
#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___width 3
#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___lsb 6
#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___width 2
#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___lsb 8
#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___width 1
#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___bit 8
#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___lsb 9
#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___width 2
#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___lsb 11
#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___width 3
#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___lsb 14
#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___width 3
#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___lsb 17
#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___width 2
#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___lsb 19
#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___width 1
#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___bit 19
#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___lsb 20
#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___width 2
#define reg_iop_sap_out_rw_bus1_hi_oe_offset 24
#define STRIDE_iop_sap_out_rw_gio 4
/* Register rw_gio, scope iop_sap_out, type rw */
#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0
#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3
#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3
#define reg_iop_sap_out_rw_gio___out_clk_ext___width 4
#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 7
#define reg_iop_sap_out_rw_gio___out_gated_clk___width 2
#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 9
#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1
#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 9
#define reg_iop_sap_out_rw_gio___out_logic___lsb 10
#define reg_iop_sap_out_rw_gio___out_logic___width 1
#define reg_iop_sap_out_rw_gio___out_logic___bit 10
#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 11
#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3
#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 14
#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 3
#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17
#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 2
#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 19
#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1
#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 19
#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20
#define reg_iop_sap_out_rw_gio___oe_logic___width 2
#define reg_iop_sap_out_rw_gio_offset 28
/* Constants */
#define regk_iop_sap_out_and 0x00000002
#define regk_iop_sap_out_clk0 0x00000000
#define regk_iop_sap_out_clk1 0x00000001
#define regk_iop_sap_out_clk12 0x00000002
#define regk_iop_sap_out_clk2 0x00000002
#define regk_iop_sap_out_clk200 0x00000001
#define regk_iop_sap_out_clk3 0x00000003
#define regk_iop_sap_out_ext 0x00000003
#define regk_iop_sap_out_gated 0x00000004
#define regk_iop_sap_out_gio1 0x00000000
#define regk_iop_sap_out_gio13 0x00000002
#define regk_iop_sap_out_gio13_clk 0x0000000c
#define regk_iop_sap_out_gio15 0x00000001
#define regk_iop_sap_out_gio18 0x00000003
#define regk_iop_sap_out_gio18_clk 0x0000000d
#define regk_iop_sap_out_gio1_clk 0x00000008
#define regk_iop_sap_out_gio21_clk 0x0000000e
#define regk_iop_sap_out_gio23 0x00000002
#define regk_iop_sap_out_gio29_clk 0x0000000f
#define regk_iop_sap_out_gio31 0x00000003
#define regk_iop_sap_out_gio5 0x00000001
#define regk_iop_sap_out_gio5_clk 0x00000009
#define regk_iop_sap_out_gio6_clk 0x0000000a
#define regk_iop_sap_out_gio7 0x00000000
#define regk_iop_sap_out_gio7_clk 0x0000000b
#define regk_iop_sap_out_gio_in13 0x00000001
#define regk_iop_sap_out_gio_in21 0x00000002
#define regk_iop_sap_out_gio_in29 0x00000003
#define regk_iop_sap_out_gio_in5 0x00000000
#define regk_iop_sap_out_inv 0x00000001
#define regk_iop_sap_out_nand 0x00000003
#define regk_iop_sap_out_no 0x00000000
#define regk_iop_sap_out_none 0x00000000
#define regk_iop_sap_out_rw_bus0_default 0x00000000
#define regk_iop_sap_out_rw_bus0_hi_oe_default 0x00000000
#define regk_iop_sap_out_rw_bus0_lo_oe_default 0x00000000
#define regk_iop_sap_out_rw_bus1_default 0x00000000
#define regk_iop_sap_out_rw_bus1_hi_oe_default 0x00000000
#define regk_iop_sap_out_rw_bus1_lo_oe_default 0x00000000
#define regk_iop_sap_out_rw_gen_gated_default 0x00000000
#define regk_iop_sap_out_rw_gio_default 0x00000000
#define regk_iop_sap_out_rw_gio_size 0x00000020
#define regk_iop_sap_out_spu0_gio0 0x00000002
#define regk_iop_sap_out_spu0_gio1 0x00000003
#define regk_iop_sap_out_spu0_gio12 0x00000004
#define regk_iop_sap_out_spu0_gio13 0x00000004
#define regk_iop_sap_out_spu0_gio14 0x00000004
#define regk_iop_sap_out_spu0_gio15 0x00000004
#define regk_iop_sap_out_spu0_gio2 0x00000002
#define regk_iop_sap_out_spu0_gio3 0x00000003
#define regk_iop_sap_out_spu0_gio4 0x00000002
#define regk_iop_sap_out_spu0_gio5 0x00000003
#define regk_iop_sap_out_spu0_gio6 0x00000002
#define regk_iop_sap_out_spu0_gio7 0x00000003
#define regk_iop_sap_out_spu1_gio0 0x00000005
#define regk_iop_sap_out_spu1_gio1 0x00000006
#define regk_iop_sap_out_spu1_gio12 0x00000007
#define regk_iop_sap_out_spu1_gio13 0x00000007
#define regk_iop_sap_out_spu1_gio14 0x00000007
#define regk_iop_sap_out_spu1_gio15 0x00000007
#define regk_iop_sap_out_spu1_gio2 0x00000005
#define regk_iop_sap_out_spu1_gio3 0x00000006
#define regk_iop_sap_out_spu1_gio4 0x00000005
#define regk_iop_sap_out_spu1_gio5 0x00000006
#define regk_iop_sap_out_spu1_gio6 0x00000005
#define regk_iop_sap_out_spu1_gio7 0x00000006
#define regk_iop_sap_out_timer_grp0_tmr2 0x00000004
#define regk_iop_sap_out_timer_grp1_tmr2 0x00000005
#define regk_iop_sap_out_timer_grp2_tmr2 0x00000006
#define regk_iop_sap_out_timer_grp3_tmr2 0x00000007
#define regk_iop_sap_out_tmr 0x00000005
#define regk_iop_sap_out_yes 0x00000001
#endif /* __iop_sap_out_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h Normal file
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#ifndef __iop_scrc_in_defs_asm_h
#define __iop_scrc_in_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_scrc_in.r
* id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp
* last modfied: Mon Apr 11 16:08:46 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r
* id: $Id: iop_scrc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_cfg, scope iop_scrc_in, type rw */
#define reg_iop_scrc_in_rw_cfg___trig___lsb 0
#define reg_iop_scrc_in_rw_cfg___trig___width 2
#define reg_iop_scrc_in_rw_cfg_offset 0
/* Register rw_ctrl, scope iop_scrc_in, type rw */
#define reg_iop_scrc_in_rw_ctrl___dif_in_en___lsb 0
#define reg_iop_scrc_in_rw_ctrl___dif_in_en___width 1
#define reg_iop_scrc_in_rw_ctrl___dif_in_en___bit 0
#define reg_iop_scrc_in_rw_ctrl_offset 4
/* Register r_stat, scope iop_scrc_in, type r */
#define reg_iop_scrc_in_r_stat___err___lsb 0
#define reg_iop_scrc_in_r_stat___err___width 1
#define reg_iop_scrc_in_r_stat___err___bit 0
#define reg_iop_scrc_in_r_stat_offset 8
/* Register rw_init_crc, scope iop_scrc_in, type rw */
#define reg_iop_scrc_in_rw_init_crc_offset 12
/* Register rs_computed_crc, scope iop_scrc_in, type rs */
#define reg_iop_scrc_in_rs_computed_crc_offset 16
/* Register r_computed_crc, scope iop_scrc_in, type r */
#define reg_iop_scrc_in_r_computed_crc_offset 20
/* Register rw_crc, scope iop_scrc_in, type rw */
#define reg_iop_scrc_in_rw_crc_offset 24
/* Register rw_correct_crc, scope iop_scrc_in, type rw */
#define reg_iop_scrc_in_rw_correct_crc_offset 28
/* Register rw_wr1bit, scope iop_scrc_in, type rw */
#define reg_iop_scrc_in_rw_wr1bit___data___lsb 0
#define reg_iop_scrc_in_rw_wr1bit___data___width 2
#define reg_iop_scrc_in_rw_wr1bit___last___lsb 2
#define reg_iop_scrc_in_rw_wr1bit___last___width 2
#define reg_iop_scrc_in_rw_wr1bit_offset 32
/* Constants */
#define regk_iop_scrc_in_dif_in 0x00000002
#define regk_iop_scrc_in_hi 0x00000000
#define regk_iop_scrc_in_neg 0x00000002
#define regk_iop_scrc_in_no 0x00000000
#define regk_iop_scrc_in_pos 0x00000001
#define regk_iop_scrc_in_pos_neg 0x00000003
#define regk_iop_scrc_in_r_computed_crc_default 0x00000000
#define regk_iop_scrc_in_rs_computed_crc_default 0x00000000
#define regk_iop_scrc_in_rw_cfg_default 0x00000000
#define regk_iop_scrc_in_rw_ctrl_default 0x00000000
#define regk_iop_scrc_in_rw_init_crc_default 0x00000000
#define regk_iop_scrc_in_set0 0x00000000
#define regk_iop_scrc_in_set1 0x00000001
#define regk_iop_scrc_in_yes 0x00000001
#endif /* __iop_scrc_in_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h Normal file
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#ifndef __iop_scrc_out_defs_asm_h
#define __iop_scrc_out_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_scrc_out.r
* id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp
* last modfied: Mon Apr 11 16:08:46 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_out_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_out.r
* id: $Id: iop_scrc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_cfg, scope iop_scrc_out, type rw */
#define reg_iop_scrc_out_rw_cfg___trig___lsb 0
#define reg_iop_scrc_out_rw_cfg___trig___width 2
#define reg_iop_scrc_out_rw_cfg___inv_crc___lsb 2
#define reg_iop_scrc_out_rw_cfg___inv_crc___width 1
#define reg_iop_scrc_out_rw_cfg___inv_crc___bit 2
#define reg_iop_scrc_out_rw_cfg_offset 0
/* Register rw_ctrl, scope iop_scrc_out, type rw */
#define reg_iop_scrc_out_rw_ctrl___strb_src___lsb 0
#define reg_iop_scrc_out_rw_ctrl___strb_src___width 1
#define reg_iop_scrc_out_rw_ctrl___strb_src___bit 0
#define reg_iop_scrc_out_rw_ctrl___out_src___lsb 1
#define reg_iop_scrc_out_rw_ctrl___out_src___width 1
#define reg_iop_scrc_out_rw_ctrl___out_src___bit 1
#define reg_iop_scrc_out_rw_ctrl_offset 4
/* Register rw_init_crc, scope iop_scrc_out, type rw */
#define reg_iop_scrc_out_rw_init_crc_offset 8
/* Register rw_crc, scope iop_scrc_out, type rw */
#define reg_iop_scrc_out_rw_crc_offset 12
/* Register rw_data, scope iop_scrc_out, type rw */
#define reg_iop_scrc_out_rw_data___val___lsb 0
#define reg_iop_scrc_out_rw_data___val___width 1
#define reg_iop_scrc_out_rw_data___val___bit 0
#define reg_iop_scrc_out_rw_data_offset 16
/* Register r_computed_crc, scope iop_scrc_out, type r */
#define reg_iop_scrc_out_r_computed_crc_offset 20
/* Constants */
#define regk_iop_scrc_out_crc 0x00000001
#define regk_iop_scrc_out_data 0x00000000
#define regk_iop_scrc_out_dif 0x00000001
#define regk_iop_scrc_out_hi 0x00000000
#define regk_iop_scrc_out_neg 0x00000002
#define regk_iop_scrc_out_no 0x00000000
#define regk_iop_scrc_out_pos 0x00000001
#define regk_iop_scrc_out_pos_neg 0x00000003
#define regk_iop_scrc_out_reg 0x00000000
#define regk_iop_scrc_out_rw_cfg_default 0x00000000
#define regk_iop_scrc_out_rw_crc_default 0x00000000
#define regk_iop_scrc_out_rw_ctrl_default 0x00000000
#define regk_iop_scrc_out_rw_data_default 0x00000000
#define regk_iop_scrc_out_rw_init_crc_default 0x00000000
#define regk_iop_scrc_out_yes 0x00000001
#endif /* __iop_scrc_out_defs_asm_h */

573
arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h Normal file
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#ifndef __iop_spu_defs_asm_h
#define __iop_spu_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_spu.r
* id: <not found>
* last modfied: Mon Apr 11 16:08:46 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r
* id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
#define STRIDE_iop_spu_rw_r 4
/* Register rw_r, scope iop_spu, type rw */
#define reg_iop_spu_rw_r_offset 0
/* Register rw_seq_pc, scope iop_spu, type rw */
#define reg_iop_spu_rw_seq_pc___addr___lsb 0
#define reg_iop_spu_rw_seq_pc___addr___width 12
#define reg_iop_spu_rw_seq_pc_offset 64
/* Register rw_fsm_pc, scope iop_spu, type rw */
#define reg_iop_spu_rw_fsm_pc___addr___lsb 0
#define reg_iop_spu_rw_fsm_pc___addr___width 12
#define reg_iop_spu_rw_fsm_pc_offset 68
/* Register rw_ctrl, scope iop_spu, type rw */
#define reg_iop_spu_rw_ctrl___fsm___lsb 0
#define reg_iop_spu_rw_ctrl___fsm___width 1
#define reg_iop_spu_rw_ctrl___fsm___bit 0
#define reg_iop_spu_rw_ctrl___en___lsb 1
#define reg_iop_spu_rw_ctrl___en___width 1
#define reg_iop_spu_rw_ctrl___en___bit 1
#define reg_iop_spu_rw_ctrl_offset 72
/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
#define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0
#define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5
#define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5
#define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3
#define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8
#define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5
#define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13
#define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3
#define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16
#define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5
#define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21
#define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3
#define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24
#define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5
#define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29
#define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3
#define reg_iop_spu_rw_fsm_inputs3_0_offset 76
/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
#define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0
#define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5
#define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5
#define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3
#define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8
#define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5
#define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13
#define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3
#define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16
#define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5
#define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21
#define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3
#define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24
#define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5
#define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29
#define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3
#define reg_iop_spu_rw_fsm_inputs7_4_offset 80
/* Register rw_gio_out, scope iop_spu, type rw */
#define reg_iop_spu_rw_gio_out_offset 84
/* Register rw_bus0_out, scope iop_spu, type rw */
#define reg_iop_spu_rw_bus0_out_offset 88
/* Register rw_bus1_out, scope iop_spu, type rw */
#define reg_iop_spu_rw_bus1_out_offset 92
/* Register r_gio_in, scope iop_spu, type r */
#define reg_iop_spu_r_gio_in_offset 96
/* Register r_bus0_in, scope iop_spu, type r */
#define reg_iop_spu_r_bus0_in_offset 100
/* Register r_bus1_in, scope iop_spu, type r */
#define reg_iop_spu_r_bus1_in_offset 104
/* Register rw_gio_out_set, scope iop_spu, type rw */
#define reg_iop_spu_rw_gio_out_set_offset 108
/* Register rw_gio_out_clr, scope iop_spu, type rw */
#define reg_iop_spu_rw_gio_out_clr_offset 112
/* Register rs_wr_stat, scope iop_spu, type rs */
#define reg_iop_spu_rs_wr_stat___r0___lsb 0
#define reg_iop_spu_rs_wr_stat___r0___width 1
#define reg_iop_spu_rs_wr_stat___r0___bit 0
#define reg_iop_spu_rs_wr_stat___r1___lsb 1
#define reg_iop_spu_rs_wr_stat___r1___width 1
#define reg_iop_spu_rs_wr_stat___r1___bit 1
#define reg_iop_spu_rs_wr_stat___r2___lsb 2
#define reg_iop_spu_rs_wr_stat___r2___width 1
#define reg_iop_spu_rs_wr_stat___r2___bit 2
#define reg_iop_spu_rs_wr_stat___r3___lsb 3
#define reg_iop_spu_rs_wr_stat___r3___width 1
#define reg_iop_spu_rs_wr_stat___r3___bit 3
#define reg_iop_spu_rs_wr_stat___r4___lsb 4
#define reg_iop_spu_rs_wr_stat___r4___width 1
#define reg_iop_spu_rs_wr_stat___r4___bit 4
#define reg_iop_spu_rs_wr_stat___r5___lsb 5
#define reg_iop_spu_rs_wr_stat___r5___width 1
#define reg_iop_spu_rs_wr_stat___r5___bit 5
#define reg_iop_spu_rs_wr_stat___r6___lsb 6
#define reg_iop_spu_rs_wr_stat___r6___width 1
#define reg_iop_spu_rs_wr_stat___r6___bit 6
#define reg_iop_spu_rs_wr_stat___r7___lsb 7
#define reg_iop_spu_rs_wr_stat___r7___width 1
#define reg_iop_spu_rs_wr_stat___r7___bit 7
#define reg_iop_spu_rs_wr_stat___r8___lsb 8
#define reg_iop_spu_rs_wr_stat___r8___width 1
#define reg_iop_spu_rs_wr_stat___r8___bit 8
#define reg_iop_spu_rs_wr_stat___r9___lsb 9
#define reg_iop_spu_rs_wr_stat___r9___width 1
#define reg_iop_spu_rs_wr_stat___r9___bit 9
#define reg_iop_spu_rs_wr_stat___r10___lsb 10
#define reg_iop_spu_rs_wr_stat___r10___width 1
#define reg_iop_spu_rs_wr_stat___r10___bit 10
#define reg_iop_spu_rs_wr_stat___r11___lsb 11
#define reg_iop_spu_rs_wr_stat___r11___width 1
#define reg_iop_spu_rs_wr_stat___r11___bit 11
#define reg_iop_spu_rs_wr_stat___r12___lsb 12
#define reg_iop_spu_rs_wr_stat___r12___width 1
#define reg_iop_spu_rs_wr_stat___r12___bit 12
#define reg_iop_spu_rs_wr_stat___r13___lsb 13
#define reg_iop_spu_rs_wr_stat___r13___width 1
#define reg_iop_spu_rs_wr_stat___r13___bit 13
#define reg_iop_spu_rs_wr_stat___r14___lsb 14
#define reg_iop_spu_rs_wr_stat___r14___width 1
#define reg_iop_spu_rs_wr_stat___r14___bit 14
#define reg_iop_spu_rs_wr_stat___r15___lsb 15
#define reg_iop_spu_rs_wr_stat___r15___width 1
#define reg_iop_spu_rs_wr_stat___r15___bit 15
#define reg_iop_spu_rs_wr_stat_offset 116
/* Register r_wr_stat, scope iop_spu, type r */
#define reg_iop_spu_r_wr_stat___r0___lsb 0
#define reg_iop_spu_r_wr_stat___r0___width 1
#define reg_iop_spu_r_wr_stat___r0___bit 0
#define reg_iop_spu_r_wr_stat___r1___lsb 1
#define reg_iop_spu_r_wr_stat___r1___width 1
#define reg_iop_spu_r_wr_stat___r1___bit 1
#define reg_iop_spu_r_wr_stat___r2___lsb 2
#define reg_iop_spu_r_wr_stat___r2___width 1
#define reg_iop_spu_r_wr_stat___r2___bit 2
#define reg_iop_spu_r_wr_stat___r3___lsb 3
#define reg_iop_spu_r_wr_stat___r3___width 1
#define reg_iop_spu_r_wr_stat___r3___bit 3
#define reg_iop_spu_r_wr_stat___r4___lsb 4
#define reg_iop_spu_r_wr_stat___r4___width 1
#define reg_iop_spu_r_wr_stat___r4___bit 4
#define reg_iop_spu_r_wr_stat___r5___lsb 5
#define reg_iop_spu_r_wr_stat___r5___width 1
#define reg_iop_spu_r_wr_stat___r5___bit 5
#define reg_iop_spu_r_wr_stat___r6___lsb 6
#define reg_iop_spu_r_wr_stat___r6___width 1
#define reg_iop_spu_r_wr_stat___r6___bit 6
#define reg_iop_spu_r_wr_stat___r7___lsb 7
#define reg_iop_spu_r_wr_stat___r7___width 1
#define reg_iop_spu_r_wr_stat___r7___bit 7
#define reg_iop_spu_r_wr_stat___r8___lsb 8
#define reg_iop_spu_r_wr_stat___r8___width 1
#define reg_iop_spu_r_wr_stat___r8___bit 8
#define reg_iop_spu_r_wr_stat___r9___lsb 9
#define reg_iop_spu_r_wr_stat___r9___width 1
#define reg_iop_spu_r_wr_stat___r9___bit 9
#define reg_iop_spu_r_wr_stat___r10___lsb 10
#define reg_iop_spu_r_wr_stat___r10___width 1
#define reg_iop_spu_r_wr_stat___r10___bit 10
#define reg_iop_spu_r_wr_stat___r11___lsb 11
#define reg_iop_spu_r_wr_stat___r11___width 1
#define reg_iop_spu_r_wr_stat___r11___bit 11
#define reg_iop_spu_r_wr_stat___r12___lsb 12
#define reg_iop_spu_r_wr_stat___r12___width 1
#define reg_iop_spu_r_wr_stat___r12___bit 12
#define reg_iop_spu_r_wr_stat___r13___lsb 13
#define reg_iop_spu_r_wr_stat___r13___width 1
#define reg_iop_spu_r_wr_stat___r13___bit 13
#define reg_iop_spu_r_wr_stat___r14___lsb 14
#define reg_iop_spu_r_wr_stat___r14___width 1
#define reg_iop_spu_r_wr_stat___r14___bit 14
#define reg_iop_spu_r_wr_stat___r15___lsb 15
#define reg_iop_spu_r_wr_stat___r15___width 1
#define reg_iop_spu_r_wr_stat___r15___bit 15
#define reg_iop_spu_r_wr_stat_offset 120
/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */
#define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124
/* Register r_stat_in, scope iop_spu, type r */
#define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0
#define reg_iop_spu_r_stat_in___timer_grp_lo___width 4
#define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4
#define reg_iop_spu_r_stat_in___fifo_out_last___width 1
#define reg_iop_spu_r_stat_in___fifo_out_last___bit 4
#define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5
#define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1
#define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5
#define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6
#define reg_iop_spu_r_stat_in___fifo_out_all___width 1
#define reg_iop_spu_r_stat_in___fifo_out_all___bit 6
#define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7
#define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1
#define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7
#define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8
#define reg_iop_spu_r_stat_in___dmc_out_all___width 1
#define reg_iop_spu_r_stat_in___dmc_out_all___bit 8
#define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9
#define reg_iop_spu_r_stat_in___dmc_out_dth___width 1
#define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9
#define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10
#define reg_iop_spu_r_stat_in___dmc_out_eop___width 1
#define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10
#define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11
#define reg_iop_spu_r_stat_in___dmc_out_dv___width 1
#define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11
#define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12
#define reg_iop_spu_r_stat_in___dmc_out_last___width 1
#define reg_iop_spu_r_stat_in___dmc_out_last___bit 12
#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13
#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1
#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13
#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14
#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1
#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14
#define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15
#define reg_iop_spu_r_stat_in___pcrc_correct___width 1
#define reg_iop_spu_r_stat_in___pcrc_correct___bit 15
#define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16
#define reg_iop_spu_r_stat_in___timer_grp_hi___width 4
#define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20
#define reg_iop_spu_r_stat_in___dmc_in_sth___width 1
#define reg_iop_spu_r_stat_in___dmc_in_sth___bit 20
#define reg_iop_spu_r_stat_in___dmc_in_full___lsb 21
#define reg_iop_spu_r_stat_in___dmc_in_full___width 1
#define reg_iop_spu_r_stat_in___dmc_in_full___bit 21
#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___lsb 22
#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___width 1
#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___bit 22
#define reg_iop_spu_r_stat_in___spu_gio_out___lsb 23
#define reg_iop_spu_r_stat_in___spu_gio_out___width 4
#define reg_iop_spu_r_stat_in___sync_clk12___lsb 27
#define reg_iop_spu_r_stat_in___sync_clk12___width 1
#define reg_iop_spu_r_stat_in___sync_clk12___bit 27
#define reg_iop_spu_r_stat_in___scrc_out_data___lsb 28
#define reg_iop_spu_r_stat_in___scrc_out_data___width 1
#define reg_iop_spu_r_stat_in___scrc_out_data___bit 28
#define reg_iop_spu_r_stat_in___scrc_in_err___lsb 29
#define reg_iop_spu_r_stat_in___scrc_in_err___width 1
#define reg_iop_spu_r_stat_in___scrc_in_err___bit 29
#define reg_iop_spu_r_stat_in___mc_busy___lsb 30
#define reg_iop_spu_r_stat_in___mc_busy___width 1
#define reg_iop_spu_r_stat_in___mc_busy___bit 30
#define reg_iop_spu_r_stat_in___mc_owned___lsb 31
#define reg_iop_spu_r_stat_in___mc_owned___width 1
#define reg_iop_spu_r_stat_in___mc_owned___bit 31
#define reg_iop_spu_r_stat_in_offset 128
/* Register r_trigger_in, scope iop_spu, type r */
#define reg_iop_spu_r_trigger_in_offset 132
/* Register r_special_stat, scope iop_spu, type r */
#define reg_iop_spu_r_special_stat___c_flag___lsb 0
#define reg_iop_spu_r_special_stat___c_flag___width 1
#define reg_iop_spu_r_special_stat___c_flag___bit 0
#define reg_iop_spu_r_special_stat___v_flag___lsb 1
#define reg_iop_spu_r_special_stat___v_flag___width 1
#define reg_iop_spu_r_special_stat___v_flag___bit 1
#define reg_iop_spu_r_special_stat___z_flag___lsb 2
#define reg_iop_spu_r_special_stat___z_flag___width 1
#define reg_iop_spu_r_special_stat___z_flag___bit 2
#define reg_iop_spu_r_special_stat___n_flag___lsb 3
#define reg_iop_spu_r_special_stat___n_flag___width 1
#define reg_iop_spu_r_special_stat___n_flag___bit 3
#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___lsb 4
#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___width 1
#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___bit 4
#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___lsb 5
#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___width 1
#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___bit 5
#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___lsb 6
#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___width 1
#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___bit 6
#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___lsb 7
#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___width 1
#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___bit 7
#define reg_iop_spu_r_special_stat___fsm_in0___lsb 8
#define reg_iop_spu_r_special_stat___fsm_in0___width 1
#define reg_iop_spu_r_special_stat___fsm_in0___bit 8
#define reg_iop_spu_r_special_stat___fsm_in1___lsb 9
#define reg_iop_spu_r_special_stat___fsm_in1___width 1
#define reg_iop_spu_r_special_stat___fsm_in1___bit 9
#define reg_iop_spu_r_special_stat___fsm_in2___lsb 10
#define reg_iop_spu_r_special_stat___fsm_in2___width 1
#define reg_iop_spu_r_special_stat___fsm_in2___bit 10
#define reg_iop_spu_r_special_stat___fsm_in3___lsb 11
#define reg_iop_spu_r_special_stat___fsm_in3___width 1
#define reg_iop_spu_r_special_stat___fsm_in3___bit 11
#define reg_iop_spu_r_special_stat___fsm_in4___lsb 12
#define reg_iop_spu_r_special_stat___fsm_in4___width 1
#define reg_iop_spu_r_special_stat___fsm_in4___bit 12
#define reg_iop_spu_r_special_stat___fsm_in5___lsb 13
#define reg_iop_spu_r_special_stat___fsm_in5___width 1
#define reg_iop_spu_r_special_stat___fsm_in5___bit 13
#define reg_iop_spu_r_special_stat___fsm_in6___lsb 14
#define reg_iop_spu_r_special_stat___fsm_in6___width 1
#define reg_iop_spu_r_special_stat___fsm_in6___bit 14
#define reg_iop_spu_r_special_stat___fsm_in7___lsb 15
#define reg_iop_spu_r_special_stat___fsm_in7___width 1
#define reg_iop_spu_r_special_stat___fsm_in7___bit 15
#define reg_iop_spu_r_special_stat___event0___lsb 16
#define reg_iop_spu_r_special_stat___event0___width 1
#define reg_iop_spu_r_special_stat___event0___bit 16
#define reg_iop_spu_r_special_stat___event1___lsb 17
#define reg_iop_spu_r_special_stat___event1___width 1
#define reg_iop_spu_r_special_stat___event1___bit 17
#define reg_iop_spu_r_special_stat___event2___lsb 18
#define reg_iop_spu_r_special_stat___event2___width 1
#define reg_iop_spu_r_special_stat___event2___bit 18
#define reg_iop_spu_r_special_stat___event3___lsb 19
#define reg_iop_spu_r_special_stat___event3___width 1
#define reg_iop_spu_r_special_stat___event3___bit 19
#define reg_iop_spu_r_special_stat_offset 136
/* Register rw_reg_access, scope iop_spu, type rw */
#define reg_iop_spu_rw_reg_access___addr___lsb 0
#define reg_iop_spu_rw_reg_access___addr___width 13
#define reg_iop_spu_rw_reg_access___imm_hi___lsb 16
#define reg_iop_spu_rw_reg_access___imm_hi___width 16
#define reg_iop_spu_rw_reg_access_offset 140
#define STRIDE_iop_spu_rw_event_cfg 4
/* Register rw_event_cfg, scope iop_spu, type rw */
#define reg_iop_spu_rw_event_cfg___addr___lsb 0
#define reg_iop_spu_rw_event_cfg___addr___width 12
#define reg_iop_spu_rw_event_cfg___src___lsb 12
#define reg_iop_spu_rw_event_cfg___src___width 2
#define reg_iop_spu_rw_event_cfg___eq_en___lsb 14
#define reg_iop_spu_rw_event_cfg___eq_en___width 1
#define reg_iop_spu_rw_event_cfg___eq_en___bit 14
#define reg_iop_spu_rw_event_cfg___eq_inv___lsb 15
#define reg_iop_spu_rw_event_cfg___eq_inv___width 1
#define reg_iop_spu_rw_event_cfg___eq_inv___bit 15
#define reg_iop_spu_rw_event_cfg___gt_en___lsb 16
#define reg_iop_spu_rw_event_cfg___gt_en___width 1
#define reg_iop_spu_rw_event_cfg___gt_en___bit 16
#define reg_iop_spu_rw_event_cfg___gt_inv___lsb 17
#define reg_iop_spu_rw_event_cfg___gt_inv___width 1
#define reg_iop_spu_rw_event_cfg___gt_inv___bit 17
#define reg_iop_spu_rw_event_cfg_offset 144
#define STRIDE_iop_spu_rw_event_mask 4
/* Register rw_event_mask, scope iop_spu, type rw */
#define reg_iop_spu_rw_event_mask_offset 160
#define STRIDE_iop_spu_rw_event_val 4
/* Register rw_event_val, scope iop_spu, type rw */
#define reg_iop_spu_rw_event_val_offset 176
/* Register rw_event_ret, scope iop_spu, type rw */
#define reg_iop_spu_rw_event_ret___addr___lsb 0
#define reg_iop_spu_rw_event_ret___addr___width 12
#define reg_iop_spu_rw_event_ret_offset 192
/* Register r_trace, scope iop_spu, type r */
#define reg_iop_spu_r_trace___fsm___lsb 0
#define reg_iop_spu_r_trace___fsm___width 1
#define reg_iop_spu_r_trace___fsm___bit 0
#define reg_iop_spu_r_trace___en___lsb 1
#define reg_iop_spu_r_trace___en___width 1
#define reg_iop_spu_r_trace___en___bit 1
#define reg_iop_spu_r_trace___c_flag___lsb 2
#define reg_iop_spu_r_trace___c_flag___width 1
#define reg_iop_spu_r_trace___c_flag___bit 2
#define reg_iop_spu_r_trace___v_flag___lsb 3
#define reg_iop_spu_r_trace___v_flag___width 1
#define reg_iop_spu_r_trace___v_flag___bit 3
#define reg_iop_spu_r_trace___z_flag___lsb 4
#define reg_iop_spu_r_trace___z_flag___width 1
#define reg_iop_spu_r_trace___z_flag___bit 4
#define reg_iop_spu_r_trace___n_flag___lsb 5
#define reg_iop_spu_r_trace___n_flag___width 1
#define reg_iop_spu_r_trace___n_flag___bit 5
#define reg_iop_spu_r_trace___seq_addr___lsb 6
#define reg_iop_spu_r_trace___seq_addr___width 12
#define reg_iop_spu_r_trace___fsm_addr___lsb 20
#define reg_iop_spu_r_trace___fsm_addr___width 12
#define reg_iop_spu_r_trace_offset 196
/* Register r_fsm_trace, scope iop_spu, type r */
#define reg_iop_spu_r_fsm_trace___fsm___lsb 0
#define reg_iop_spu_r_fsm_trace___fsm___width 1
#define reg_iop_spu_r_fsm_trace___fsm___bit 0
#define reg_iop_spu_r_fsm_trace___en___lsb 1
#define reg_iop_spu_r_fsm_trace___en___width 1
#define reg_iop_spu_r_fsm_trace___en___bit 1
#define reg_iop_spu_r_fsm_trace___tmr_done___lsb 2
#define reg_iop_spu_r_fsm_trace___tmr_done___width 1
#define reg_iop_spu_r_fsm_trace___tmr_done___bit 2
#define reg_iop_spu_r_fsm_trace___inp0___lsb 3
#define reg_iop_spu_r_fsm_trace___inp0___width 1
#define reg_iop_spu_r_fsm_trace___inp0___bit 3
#define reg_iop_spu_r_fsm_trace___inp1___lsb 4
#define reg_iop_spu_r_fsm_trace___inp1___width 1
#define reg_iop_spu_r_fsm_trace___inp1___bit 4
#define reg_iop_spu_r_fsm_trace___inp2___lsb 5
#define reg_iop_spu_r_fsm_trace___inp2___width 1
#define reg_iop_spu_r_fsm_trace___inp2___bit 5
#define reg_iop_spu_r_fsm_trace___inp3___lsb 6
#define reg_iop_spu_r_fsm_trace___inp3___width 1
#define reg_iop_spu_r_fsm_trace___inp3___bit 6
#define reg_iop_spu_r_fsm_trace___event0___lsb 7
#define reg_iop_spu_r_fsm_trace___event0___width 1
#define reg_iop_spu_r_fsm_trace___event0___bit 7
#define reg_iop_spu_r_fsm_trace___event1___lsb 8
#define reg_iop_spu_r_fsm_trace___event1___width 1
#define reg_iop_spu_r_fsm_trace___event1___bit 8
#define reg_iop_spu_r_fsm_trace___event2___lsb 9
#define reg_iop_spu_r_fsm_trace___event2___width 1
#define reg_iop_spu_r_fsm_trace___event2___bit 9
#define reg_iop_spu_r_fsm_trace___event3___lsb 10
#define reg_iop_spu_r_fsm_trace___event3___width 1
#define reg_iop_spu_r_fsm_trace___event3___bit 10
#define reg_iop_spu_r_fsm_trace___gio_out___lsb 11
#define reg_iop_spu_r_fsm_trace___gio_out___width 8
#define reg_iop_spu_r_fsm_trace___fsm_addr___lsb 20
#define reg_iop_spu_r_fsm_trace___fsm_addr___width 12
#define reg_iop_spu_r_fsm_trace_offset 200
#define STRIDE_iop_spu_rw_brp 4
/* Register rw_brp, scope iop_spu, type rw */
#define reg_iop_spu_rw_brp___addr___lsb 0
#define reg_iop_spu_rw_brp___addr___width 12
#define reg_iop_spu_rw_brp___fsm___lsb 12
#define reg_iop_spu_rw_brp___fsm___width 1
#define reg_iop_spu_rw_brp___fsm___bit 12
#define reg_iop_spu_rw_brp___en___lsb 13
#define reg_iop_spu_rw_brp___en___width 1
#define reg_iop_spu_rw_brp___en___bit 13
#define reg_iop_spu_rw_brp_offset 204
/* Constants */
#define regk_iop_spu_attn_hi 0x00000005
#define regk_iop_spu_attn_lo 0x00000005
#define regk_iop_spu_attn_r0 0x00000000
#define regk_iop_spu_attn_r1 0x00000001
#define regk_iop_spu_attn_r10 0x00000002
#define regk_iop_spu_attn_r11 0x00000003
#define regk_iop_spu_attn_r12 0x00000004
#define regk_iop_spu_attn_r13 0x00000005
#define regk_iop_spu_attn_r14 0x00000006
#define regk_iop_spu_attn_r15 0x00000007
#define regk_iop_spu_attn_r2 0x00000002
#define regk_iop_spu_attn_r3 0x00000003
#define regk_iop_spu_attn_r4 0x00000004
#define regk_iop_spu_attn_r5 0x00000005
#define regk_iop_spu_attn_r6 0x00000006
#define regk_iop_spu_attn_r7 0x00000007
#define regk_iop_spu_attn_r8 0x00000000
#define regk_iop_spu_attn_r9 0x00000001
#define regk_iop_spu_c 0x00000000
#define regk_iop_spu_flag 0x00000002
#define regk_iop_spu_gio_in 0x00000000
#define regk_iop_spu_gio_out 0x00000005
#define regk_iop_spu_gio_out0 0x00000008
#define regk_iop_spu_gio_out1 0x00000009
#define regk_iop_spu_gio_out2 0x0000000a
#define regk_iop_spu_gio_out3 0x0000000b
#define regk_iop_spu_gio_out4 0x0000000c
#define regk_iop_spu_gio_out5 0x0000000d
#define regk_iop_spu_gio_out6 0x0000000e
#define regk_iop_spu_gio_out7 0x0000000f
#define regk_iop_spu_n 0x00000003
#define regk_iop_spu_no 0x00000000
#define regk_iop_spu_r0 0x00000008
#define regk_iop_spu_r1 0x00000009
#define regk_iop_spu_r10 0x0000000a
#define regk_iop_spu_r11 0x0000000b
#define regk_iop_spu_r12 0x0000000c
#define regk_iop_spu_r13 0x0000000d
#define regk_iop_spu_r14 0x0000000e
#define regk_iop_spu_r15 0x0000000f
#define regk_iop_spu_r2 0x0000000a
#define regk_iop_spu_r3 0x0000000b
#define regk_iop_spu_r4 0x0000000c
#define regk_iop_spu_r5 0x0000000d
#define regk_iop_spu_r6 0x0000000e
#define regk_iop_spu_r7 0x0000000f
#define regk_iop_spu_r8 0x00000008
#define regk_iop_spu_r9 0x00000009
#define regk_iop_spu_reg_hi 0x00000002
#define regk_iop_spu_reg_lo 0x00000002
#define regk_iop_spu_rw_brp_default 0x00000000
#define regk_iop_spu_rw_brp_size 0x00000004
#define regk_iop_spu_rw_ctrl_default 0x00000000
#define regk_iop_spu_rw_event_cfg_size 0x00000004
#define regk_iop_spu_rw_event_mask_size 0x00000004
#define regk_iop_spu_rw_event_val_size 0x00000004
#define regk_iop_spu_rw_gio_out_default 0x00000000
#define regk_iop_spu_rw_r_size 0x00000010
#define regk_iop_spu_rw_reg_access_default 0x00000000
#define regk_iop_spu_stat_in 0x00000002
#define regk_iop_spu_statin_hi 0x00000004
#define regk_iop_spu_statin_lo 0x00000004
#define regk_iop_spu_trig 0x00000003
#define regk_iop_spu_trigger 0x00000006
#define regk_iop_spu_v 0x00000001
#define regk_iop_spu_wsts_gioout_spec 0x00000001
#define regk_iop_spu_xor 0x00000003
#define regk_iop_spu_xor_bus0_r2_0 0x00000000
#define regk_iop_spu_xor_bus0m_r2_0 0x00000002
#define regk_iop_spu_xor_bus1_r3_0 0x00000001
#define regk_iop_spu_xor_bus1m_r3_0 0x00000003
#define regk_iop_spu_yes 0x00000001
#define regk_iop_spu_z 0x00000002
#endif /* __iop_spu_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h Normal file
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arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h Normal file
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arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h Normal file
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arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h Normal file
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#ifndef __iop_sw_spu_defs_asm_h
#define __iop_sw_spu_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
* id: <not found>
* last modfied: Mon Apr 11 16:10:19 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_spu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
* id: $Id: iop_sw_spu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0
#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1
#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0
#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1
#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2
#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3
#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3
#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___lsb 6
#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___width 1
#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___bit 6
#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___lsb 7
#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___width 1
#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___bit 7
#define reg_iop_sw_spu_rw_mc_ctrl_offset 0
/* Register rw_mc_data, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_mc_data___val___lsb 0
#define reg_iop_sw_spu_rw_mc_data___val___width 32
#define reg_iop_sw_spu_rw_mc_data_offset 4
/* Register rw_mc_addr, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_mc_addr_offset 8
/* Register rs_mc_data, scope iop_sw_spu, type rs */
#define reg_iop_sw_spu_rs_mc_data_offset 12
/* Register r_mc_data, scope iop_sw_spu, type r */
#define reg_iop_sw_spu_r_mc_data_offset 16
/* Register r_mc_stat, scope iop_sw_spu, type r */
#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0
#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1
#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0
#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1
#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1
#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1
#define reg_iop_sw_spu_r_mc_stat___busy_spu0___lsb 2
#define reg_iop_sw_spu_r_mc_stat___busy_spu0___width 1
#define reg_iop_sw_spu_r_mc_stat___busy_spu0___bit 2
#define reg_iop_sw_spu_r_mc_stat___busy_spu1___lsb 3
#define reg_iop_sw_spu_r_mc_stat___busy_spu1___width 1
#define reg_iop_sw_spu_r_mc_stat___busy_spu1___bit 3
#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 4
#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1
#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 4
#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 5
#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1
#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 5
#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___lsb 6
#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___width 1
#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___bit 6
#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___lsb 7
#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___width 1
#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___bit 7
#define reg_iop_sw_spu_r_mc_stat_offset 20
/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___width 8
#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___lsb 8
#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___width 8
#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___lsb 16
#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___width 8
#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___lsb 24
#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___width 8
#define reg_iop_sw_spu_rw_bus0_clr_mask_offset 24
/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___width 8
#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___lsb 8
#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___width 8
#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___lsb 16
#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___width 8
#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___lsb 24
#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___width 8
#define reg_iop_sw_spu_rw_bus0_set_mask_offset 28
/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___width 1
#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___bit 0
#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___lsb 1
#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___width 1
#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___bit 1
#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___lsb 2
#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___width 1
#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___bit 2
#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___lsb 3
#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___width 1
#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___bit 3
#define reg_iop_sw_spu_rw_bus0_oe_clr_mask_offset 32
/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___width 1
#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___bit 0
#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___lsb 1
#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___width 1
#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___bit 1
#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___lsb 2
#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___width 1
#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___bit 2
#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___lsb 3
#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___width 1
#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___bit 3
#define reg_iop_sw_spu_rw_bus0_oe_set_mask_offset 36
/* Register r_bus0_in, scope iop_sw_spu, type r */
#define reg_iop_sw_spu_r_bus0_in_offset 40
/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___width 8
#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___lsb 8
#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___width 8
#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___lsb 16
#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___width 8
#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___lsb 24
#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___width 8
#define reg_iop_sw_spu_rw_bus1_clr_mask_offset 44
/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___width 8
#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___lsb 8
#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___width 8
#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___lsb 16
#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___width 8
#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___lsb 24
#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___width 8
#define reg_iop_sw_spu_rw_bus1_set_mask_offset 48
/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___width 1
#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___bit 0
#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___lsb 1
#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___width 1
#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___bit 1
#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___lsb 2
#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___width 1
#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___bit 2
#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___lsb 3
#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___width 1
#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___bit 3
#define reg_iop_sw_spu_rw_bus1_oe_clr_mask_offset 52
/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___width 1
#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___bit 0
#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___lsb 1
#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___width 1
#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___bit 1
#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___lsb 2
#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___width 1
#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___bit 2
#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___lsb 3
#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___width 1
#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___bit 3
#define reg_iop_sw_spu_rw_bus1_oe_set_mask_offset 56
/* Register r_bus1_in, scope iop_sw_spu, type r */
#define reg_iop_sw_spu_r_bus1_in_offset 60
/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0
#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32
#define reg_iop_sw_spu_rw_gio_clr_mask_offset 64
/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0
#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32
#define reg_iop_sw_spu_rw_gio_set_mask_offset 68
/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0
#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32
#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 72
/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0
#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32
#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 76
/* Register r_gio_in, scope iop_sw_spu, type r */
#define reg_iop_sw_spu_r_gio_in_offset 80
/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___width 8
#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___lsb 8
#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___width 8
#define reg_iop_sw_spu_rw_bus0_clr_mask_lo_offset 84
/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___lsb 0
#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___width 8
#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___lsb 8
#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___width 8
#define reg_iop_sw_spu_rw_bus0_clr_mask_hi_offset 88
/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___width 8
#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___lsb 8
#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___width 8
#define reg_iop_sw_spu_rw_bus0_set_mask_lo_offset 92
/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___lsb 0
#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___width 8
#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___lsb 8
#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___width 8
#define reg_iop_sw_spu_rw_bus0_set_mask_hi_offset 96
/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___width 8
#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___lsb 8
#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___width 8
#define reg_iop_sw_spu_rw_bus1_clr_mask_lo_offset 100
/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___lsb 0
#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___width 8
#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___lsb 8
#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___width 8
#define reg_iop_sw_spu_rw_bus1_clr_mask_hi_offset 104
/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___lsb 0
#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___width 8
#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___lsb 8
#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___width 8
#define reg_iop_sw_spu_rw_bus1_set_mask_lo_offset 108
/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___lsb 0
#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___width 8
#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___lsb 8
#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___width 8
#define reg_iop_sw_spu_rw_bus1_set_mask_hi_offset 112
/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0
#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16
#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 116
/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0
#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16
#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120
/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0
#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16
#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 124
/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0
#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16
#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 128
/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0
#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16
#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 132
/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0
#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16
#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 136
/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0
#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16
#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 140
/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0
#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16
#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 144
/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0
#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0
#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1
#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1
#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2
#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2
#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3
#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3
#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4
#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4
#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5
#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5
#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6
#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6
#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7
#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7
#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8
#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8
#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9
#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9
#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10
#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10
#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11
#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11
#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12
#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12
#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13
#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13
#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14
#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14
#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15
#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1
#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15
#define reg_iop_sw_spu_rw_cpu_intr_offset 148
/* Register r_cpu_intr, scope iop_sw_spu, type r */
#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0
#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0
#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1
#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1
#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2
#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2
#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3
#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3
#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4
#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4
#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5
#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5
#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6
#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6
#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7
#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7
#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8
#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8
#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9
#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9
#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10
#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10
#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11
#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11
#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12
#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12
#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13
#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13
#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14
#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14
#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15
#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1
#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15
#define reg_iop_sw_spu_r_cpu_intr_offset 152
/* Register r_hw_intr, scope iop_sw_spu, type r */
#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0
#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0
#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2
#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2
#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3
#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3
#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4
#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4
#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5
#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5
#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6
#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6
#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7
#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1
#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7
#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8
#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1
#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8
#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9
#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1
#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9
#define reg_iop_sw_spu_r_hw_intr___timer_grp2___lsb 10
#define reg_iop_sw_spu_r_hw_intr___timer_grp2___width 1
#define reg_iop_sw_spu_r_hw_intr___timer_grp2___bit 10
#define reg_iop_sw_spu_r_hw_intr___timer_grp3___lsb 11
#define reg_iop_sw_spu_r_hw_intr___timer_grp3___width 1
#define reg_iop_sw_spu_r_hw_intr___timer_grp3___bit 11
#define reg_iop_sw_spu_r_hw_intr___fifo_out0___lsb 12
#define reg_iop_sw_spu_r_hw_intr___fifo_out0___width 1
#define reg_iop_sw_spu_r_hw_intr___fifo_out0___bit 12
#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___lsb 13
#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___width 1
#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___bit 13
#define reg_iop_sw_spu_r_hw_intr___fifo_in0___lsb 14
#define reg_iop_sw_spu_r_hw_intr___fifo_in0___width 1
#define reg_iop_sw_spu_r_hw_intr___fifo_in0___bit 14
#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___lsb 15
#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___width 1
#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___bit 15
#define reg_iop_sw_spu_r_hw_intr___fifo_out1___lsb 16
#define reg_iop_sw_spu_r_hw_intr___fifo_out1___width 1
#define reg_iop_sw_spu_r_hw_intr___fifo_out1___bit 16
#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___lsb 17
#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___width 1
#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___bit 17
#define reg_iop_sw_spu_r_hw_intr___fifo_in1___lsb 18
#define reg_iop_sw_spu_r_hw_intr___fifo_in1___width 1
#define reg_iop_sw_spu_r_hw_intr___fifo_in1___bit 18
#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___lsb 19
#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___width 1
#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___bit 19
#define reg_iop_sw_spu_r_hw_intr___dmc_out0___lsb 20
#define reg_iop_sw_spu_r_hw_intr___dmc_out0___width 1
#define reg_iop_sw_spu_r_hw_intr___dmc_out0___bit 20
#define reg_iop_sw_spu_r_hw_intr___dmc_in0___lsb 21
#define reg_iop_sw_spu_r_hw_intr___dmc_in0___width 1
#define reg_iop_sw_spu_r_hw_intr___dmc_in0___bit 21
#define reg_iop_sw_spu_r_hw_intr___dmc_out1___lsb 22
#define reg_iop_sw_spu_r_hw_intr___dmc_out1___width 1
#define reg_iop_sw_spu_r_hw_intr___dmc_out1___bit 22
#define reg_iop_sw_spu_r_hw_intr___dmc_in1___lsb 23
#define reg_iop_sw_spu_r_hw_intr___dmc_in1___width 1
#define reg_iop_sw_spu_r_hw_intr___dmc_in1___bit 23
#define reg_iop_sw_spu_r_hw_intr_offset 156
/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0
#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0
#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1
#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1
#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2
#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2
#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3
#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3
#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4
#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4
#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5
#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5
#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6
#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6
#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7
#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7
#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8
#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8
#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9
#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9
#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10
#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10
#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11
#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11
#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12
#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12
#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13
#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13
#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14
#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14
#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15
#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1
#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15
#define reg_iop_sw_spu_rw_mpu_intr_offset 160
/* Register r_mpu_intr, scope iop_sw_spu, type r */
#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0
#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0
#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1
#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1
#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2
#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2
#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3
#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3
#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4
#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4
#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5
#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5
#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6
#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6
#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7
#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7
#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8
#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8
#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9
#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9
#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10
#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10
#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11
#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11
#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12
#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12
#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13
#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13
#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14
#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14
#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15
#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1
#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___lsb 16
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___width 1
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___bit 16
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___lsb 17
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___width 1
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___bit 17
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___lsb 18
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___width 1
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___bit 18
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___lsb 19
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___width 1
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___bit 19
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___lsb 20
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___width 1
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___bit 20
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___lsb 21
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___width 1
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___bit 21
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___lsb 22
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___width 1
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___bit 22
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___lsb 23
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___width 1
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___bit 23
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___lsb 24
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___width 1
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___bit 24
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___lsb 25
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___width 1
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___bit 25
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___lsb 26
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___width 1
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___bit 26
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___lsb 27
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___width 1
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___bit 27
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___lsb 28
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___width 1
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___bit 28
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___lsb 29
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___width 1
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___bit 29
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___lsb 30
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___width 1
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___bit 30
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___lsb 31
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___width 1
#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___bit 31
#define reg_iop_sw_spu_r_mpu_intr_offset 164
/* Constants */
#define regk_iop_sw_spu_copy 0x00000000
#define regk_iop_sw_spu_no 0x00000000
#define regk_iop_sw_spu_nop 0x00000000
#define regk_iop_sw_spu_rd 0x00000002
#define regk_iop_sw_spu_reg_copy 0x00000001
#define regk_iop_sw_spu_rw_bus0_clr_mask_default 0x00000000
#define regk_iop_sw_spu_rw_bus0_oe_clr_mask_default 0x00000000
#define regk_iop_sw_spu_rw_bus0_oe_set_mask_default 0x00000000
#define regk_iop_sw_spu_rw_bus0_set_mask_default 0x00000000
#define regk_iop_sw_spu_rw_bus1_clr_mask_default 0x00000000
#define regk_iop_sw_spu_rw_bus1_oe_clr_mask_default 0x00000000
#define regk_iop_sw_spu_rw_bus1_oe_set_mask_default 0x00000000
#define regk_iop_sw_spu_rw_bus1_set_mask_default 0x00000000
#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000
#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000
#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000
#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000
#define regk_iop_sw_spu_set 0x00000001
#define regk_iop_sw_spu_wr 0x00000003
#define regk_iop_sw_spu_yes 0x00000001
#endif /* __iop_sw_spu_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h Normal file
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#ifndef __iop_timer_grp_defs_asm_h
#define __iop_timer_grp_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_timer_grp.r
* id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
* last modfied: Mon Apr 11 16:08:46 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r
* id: $Id: iop_timer_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_cfg, scope iop_timer_grp, type rw */
#define reg_iop_timer_grp_rw_cfg___clk_src___lsb 0
#define reg_iop_timer_grp_rw_cfg___clk_src___width 1
#define reg_iop_timer_grp_rw_cfg___clk_src___bit 0
#define reg_iop_timer_grp_rw_cfg___trig___lsb 1
#define reg_iop_timer_grp_rw_cfg___trig___width 2
#define reg_iop_timer_grp_rw_cfg___clk_gen_div___lsb 3
#define reg_iop_timer_grp_rw_cfg___clk_gen_div___width 8
#define reg_iop_timer_grp_rw_cfg___clk_div___lsb 11
#define reg_iop_timer_grp_rw_cfg___clk_div___width 8
#define reg_iop_timer_grp_rw_cfg_offset 0
/* Register rw_half_period, scope iop_timer_grp, type rw */
#define reg_iop_timer_grp_rw_half_period___quota_lo___lsb 0
#define reg_iop_timer_grp_rw_half_period___quota_lo___width 15
#define reg_iop_timer_grp_rw_half_period___quota_hi___lsb 15
#define reg_iop_timer_grp_rw_half_period___quota_hi___width 15
#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___lsb 30
#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___width 1
#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___bit 30
#define reg_iop_timer_grp_rw_half_period_offset 4
/* Register rw_half_period_len, scope iop_timer_grp, type rw */
#define reg_iop_timer_grp_rw_half_period_len_offset 8
#define STRIDE_iop_timer_grp_rw_tmr_cfg 4
/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___lsb 0
#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___width 3
#define reg_iop_timer_grp_rw_tmr_cfg___strb___lsb 3
#define reg_iop_timer_grp_rw_tmr_cfg___strb___width 2
#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___lsb 5
#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___width 2
#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___lsb 7
#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___width 1
#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___bit 7
#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___lsb 8
#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___width 2
#define reg_iop_timer_grp_rw_tmr_cfg___inv___lsb 10
#define reg_iop_timer_grp_rw_tmr_cfg___inv___width 1
#define reg_iop_timer_grp_rw_tmr_cfg___inv___bit 10
#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___lsb 11
#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___width 2
#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___lsb 13
#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___width 2
#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___lsb 15
#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___width 1
#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___bit 15
#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___lsb 16
#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___width 1
#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___bit 16
#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___lsb 17
#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___width 1
#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___bit 17
#define reg_iop_timer_grp_rw_tmr_cfg_offset 12
#define STRIDE_iop_timer_grp_rw_tmr_len 4
/* Register rw_tmr_len, scope iop_timer_grp, type rw */
#define reg_iop_timer_grp_rw_tmr_len___val___lsb 0
#define reg_iop_timer_grp_rw_tmr_len___val___width 16
#define reg_iop_timer_grp_rw_tmr_len_offset 44
/* Register rw_cmd, scope iop_timer_grp, type rw */
#define reg_iop_timer_grp_rw_cmd___rst___lsb 0
#define reg_iop_timer_grp_rw_cmd___rst___width 4
#define reg_iop_timer_grp_rw_cmd___en___lsb 4
#define reg_iop_timer_grp_rw_cmd___en___width 4
#define reg_iop_timer_grp_rw_cmd___dis___lsb 8
#define reg_iop_timer_grp_rw_cmd___dis___width 4
#define reg_iop_timer_grp_rw_cmd___strb___lsb 12
#define reg_iop_timer_grp_rw_cmd___strb___width 4
#define reg_iop_timer_grp_rw_cmd_offset 60
/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
#define reg_iop_timer_grp_r_clk_gen_cnt_offset 64
#define STRIDE_iop_timer_grp_rs_tmr_cnt 8
/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
#define reg_iop_timer_grp_rs_tmr_cnt___val___lsb 0
#define reg_iop_timer_grp_rs_tmr_cnt___val___width 16
#define reg_iop_timer_grp_rs_tmr_cnt_offset 68
#define STRIDE_iop_timer_grp_r_tmr_cnt 8
/* Register r_tmr_cnt, scope iop_timer_grp, type r */
#define reg_iop_timer_grp_r_tmr_cnt___val___lsb 0
#define reg_iop_timer_grp_r_tmr_cnt___val___width 16
#define reg_iop_timer_grp_r_tmr_cnt_offset 72
/* Register rw_intr_mask, scope iop_timer_grp, type rw */
#define reg_iop_timer_grp_rw_intr_mask___tmr0___lsb 0
#define reg_iop_timer_grp_rw_intr_mask___tmr0___width 1
#define reg_iop_timer_grp_rw_intr_mask___tmr0___bit 0
#define reg_iop_timer_grp_rw_intr_mask___tmr1___lsb 1
#define reg_iop_timer_grp_rw_intr_mask___tmr1___width 1
#define reg_iop_timer_grp_rw_intr_mask___tmr1___bit 1
#define reg_iop_timer_grp_rw_intr_mask___tmr2___lsb 2
#define reg_iop_timer_grp_rw_intr_mask___tmr2___width 1
#define reg_iop_timer_grp_rw_intr_mask___tmr2___bit 2
#define reg_iop_timer_grp_rw_intr_mask___tmr3___lsb 3
#define reg_iop_timer_grp_rw_intr_mask___tmr3___width 1
#define reg_iop_timer_grp_rw_intr_mask___tmr3___bit 3
#define reg_iop_timer_grp_rw_intr_mask_offset 100
/* Register rw_ack_intr, scope iop_timer_grp, type rw */
#define reg_iop_timer_grp_rw_ack_intr___tmr0___lsb 0
#define reg_iop_timer_grp_rw_ack_intr___tmr0___width 1
#define reg_iop_timer_grp_rw_ack_intr___tmr0___bit 0
#define reg_iop_timer_grp_rw_ack_intr___tmr1___lsb 1
#define reg_iop_timer_grp_rw_ack_intr___tmr1___width 1
#define reg_iop_timer_grp_rw_ack_intr___tmr1___bit 1
#define reg_iop_timer_grp_rw_ack_intr___tmr2___lsb 2
#define reg_iop_timer_grp_rw_ack_intr___tmr2___width 1
#define reg_iop_timer_grp_rw_ack_intr___tmr2___bit 2
#define reg_iop_timer_grp_rw_ack_intr___tmr3___lsb 3
#define reg_iop_timer_grp_rw_ack_intr___tmr3___width 1
#define reg_iop_timer_grp_rw_ack_intr___tmr3___bit 3
#define reg_iop_timer_grp_rw_ack_intr_offset 104
/* Register r_intr, scope iop_timer_grp, type r */
#define reg_iop_timer_grp_r_intr___tmr0___lsb 0
#define reg_iop_timer_grp_r_intr___tmr0___width 1
#define reg_iop_timer_grp_r_intr___tmr0___bit 0
#define reg_iop_timer_grp_r_intr___tmr1___lsb 1
#define reg_iop_timer_grp_r_intr___tmr1___width 1
#define reg_iop_timer_grp_r_intr___tmr1___bit 1
#define reg_iop_timer_grp_r_intr___tmr2___lsb 2
#define reg_iop_timer_grp_r_intr___tmr2___width 1
#define reg_iop_timer_grp_r_intr___tmr2___bit 2
#define reg_iop_timer_grp_r_intr___tmr3___lsb 3
#define reg_iop_timer_grp_r_intr___tmr3___width 1
#define reg_iop_timer_grp_r_intr___tmr3___bit 3
#define reg_iop_timer_grp_r_intr_offset 108
/* Register r_masked_intr, scope iop_timer_grp, type r */
#define reg_iop_timer_grp_r_masked_intr___tmr0___lsb 0
#define reg_iop_timer_grp_r_masked_intr___tmr0___width 1
#define reg_iop_timer_grp_r_masked_intr___tmr0___bit 0
#define reg_iop_timer_grp_r_masked_intr___tmr1___lsb 1
#define reg_iop_timer_grp_r_masked_intr___tmr1___width 1
#define reg_iop_timer_grp_r_masked_intr___tmr1___bit 1
#define reg_iop_timer_grp_r_masked_intr___tmr2___lsb 2
#define reg_iop_timer_grp_r_masked_intr___tmr2___width 1
#define reg_iop_timer_grp_r_masked_intr___tmr2___bit 2
#define reg_iop_timer_grp_r_masked_intr___tmr3___lsb 3
#define reg_iop_timer_grp_r_masked_intr___tmr3___width 1
#define reg_iop_timer_grp_r_masked_intr___tmr3___bit 3
#define reg_iop_timer_grp_r_masked_intr_offset 112
/* Constants */
#define regk_iop_timer_grp_clk200 0x00000000
#define regk_iop_timer_grp_clk_gen 0x00000002
#define regk_iop_timer_grp_complete 0x00000002
#define regk_iop_timer_grp_div_clk200 0x00000001
#define regk_iop_timer_grp_div_clk_gen 0x00000003
#define regk_iop_timer_grp_ext 0x00000001
#define regk_iop_timer_grp_hi 0x00000000
#define regk_iop_timer_grp_long_period 0x00000001
#define regk_iop_timer_grp_neg 0x00000002
#define regk_iop_timer_grp_no 0x00000000
#define regk_iop_timer_grp_once 0x00000003
#define regk_iop_timer_grp_pause 0x00000001
#define regk_iop_timer_grp_pos 0x00000001
#define regk_iop_timer_grp_pos_neg 0x00000003
#define regk_iop_timer_grp_pulse 0x00000000
#define regk_iop_timer_grp_r_tmr_cnt_size 0x00000004
#define regk_iop_timer_grp_rs_tmr_cnt_size 0x00000004
#define regk_iop_timer_grp_rw_cfg_default 0x00000002
#define regk_iop_timer_grp_rw_intr_mask_default 0x00000000
#define regk_iop_timer_grp_rw_tmr_cfg_default0 0x00018000
#define regk_iop_timer_grp_rw_tmr_cfg_default1 0x0001a900
#define regk_iop_timer_grp_rw_tmr_cfg_default2 0x0001d200
#define regk_iop_timer_grp_rw_tmr_cfg_default3 0x0001fb00
#define regk_iop_timer_grp_rw_tmr_cfg_size 0x00000004
#define regk_iop_timer_grp_rw_tmr_len_default 0x00000000
#define regk_iop_timer_grp_rw_tmr_len_size 0x00000004
#define regk_iop_timer_grp_short_period 0x00000000
#define regk_iop_timer_grp_stop 0x00000000
#define regk_iop_timer_grp_tmr 0x00000004
#define regk_iop_timer_grp_toggle 0x00000001
#define regk_iop_timer_grp_yes 0x00000001
#endif /* __iop_timer_grp_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h Normal file
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#ifndef __iop_trigger_grp_defs_asm_h
#define __iop_trigger_grp_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_trigger_grp.r
* id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp
* last modfied: Mon Apr 11 16:08:46 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r
* id: $Id: iop_trigger_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
#define STRIDE_iop_trigger_grp_rw_cfg 4
/* Register rw_cfg, scope iop_trigger_grp, type rw */
#define reg_iop_trigger_grp_rw_cfg___action___lsb 0
#define reg_iop_trigger_grp_rw_cfg___action___width 2
#define reg_iop_trigger_grp_rw_cfg___once___lsb 2
#define reg_iop_trigger_grp_rw_cfg___once___width 1
#define reg_iop_trigger_grp_rw_cfg___once___bit 2
#define reg_iop_trigger_grp_rw_cfg___trig___lsb 3
#define reg_iop_trigger_grp_rw_cfg___trig___width 3
#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6
#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1
#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6
#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7
#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1
#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7
#define reg_iop_trigger_grp_rw_cfg_offset 0
/* Register rw_cmd, scope iop_trigger_grp, type rw */
#define reg_iop_trigger_grp_rw_cmd___dis___lsb 0
#define reg_iop_trigger_grp_rw_cmd___dis___width 4
#define reg_iop_trigger_grp_rw_cmd___en___lsb 4
#define reg_iop_trigger_grp_rw_cmd___en___width 4
#define reg_iop_trigger_grp_rw_cmd_offset 16
/* Register rw_intr_mask, scope iop_trigger_grp, type rw */
#define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0
#define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1
#define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0
#define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1
#define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1
#define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1
#define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2
#define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1
#define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2
#define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3
#define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1
#define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3
#define reg_iop_trigger_grp_rw_intr_mask_offset 20
/* Register rw_ack_intr, scope iop_trigger_grp, type rw */
#define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0
#define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1
#define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0
#define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1
#define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1
#define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1
#define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2
#define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1
#define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2
#define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3
#define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1
#define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3
#define reg_iop_trigger_grp_rw_ack_intr_offset 24
/* Register r_intr, scope iop_trigger_grp, type r */
#define reg_iop_trigger_grp_r_intr___trig0___lsb 0
#define reg_iop_trigger_grp_r_intr___trig0___width 1
#define reg_iop_trigger_grp_r_intr___trig0___bit 0
#define reg_iop_trigger_grp_r_intr___trig1___lsb 1
#define reg_iop_trigger_grp_r_intr___trig1___width 1
#define reg_iop_trigger_grp_r_intr___trig1___bit 1
#define reg_iop_trigger_grp_r_intr___trig2___lsb 2
#define reg_iop_trigger_grp_r_intr___trig2___width 1
#define reg_iop_trigger_grp_r_intr___trig2___bit 2
#define reg_iop_trigger_grp_r_intr___trig3___lsb 3
#define reg_iop_trigger_grp_r_intr___trig3___width 1
#define reg_iop_trigger_grp_r_intr___trig3___bit 3
#define reg_iop_trigger_grp_r_intr_offset 28
/* Register r_masked_intr, scope iop_trigger_grp, type r */
#define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0
#define reg_iop_trigger_grp_r_masked_intr___trig0___width 1
#define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0
#define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1
#define reg_iop_trigger_grp_r_masked_intr___trig1___width 1
#define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1
#define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2
#define reg_iop_trigger_grp_r_masked_intr___trig2___width 1
#define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2
#define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3
#define reg_iop_trigger_grp_r_masked_intr___trig3___width 1
#define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3
#define reg_iop_trigger_grp_r_masked_intr_offset 32
/* Constants */
#define regk_iop_trigger_grp_fall 0x00000002
#define regk_iop_trigger_grp_fall_lo 0x00000006
#define regk_iop_trigger_grp_no 0x00000000
#define regk_iop_trigger_grp_off 0x00000000
#define regk_iop_trigger_grp_pulse 0x00000000
#define regk_iop_trigger_grp_rise 0x00000001
#define regk_iop_trigger_grp_rise_fall 0x00000003
#define regk_iop_trigger_grp_rise_fall_hi 0x00000007
#define regk_iop_trigger_grp_rise_fall_lo 0x00000004
#define regk_iop_trigger_grp_rise_hi 0x00000005
#define regk_iop_trigger_grp_rw_cfg_default 0x000000c0
#define regk_iop_trigger_grp_rw_cfg_size 0x00000004
#define regk_iop_trigger_grp_rw_intr_mask_default 0x00000000
#define regk_iop_trigger_grp_toggle 0x00000003
#define regk_iop_trigger_grp_yes 0x00000001
#endif /* __iop_trigger_grp_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h Normal file
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#ifndef __iop_version_defs_asm_h
#define __iop_version_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/guinness/iop_version.r
* id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp
* last modfied: Mon Apr 11 16:08:44 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_version_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_version.r
* id: $Id: iop_version_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register r_version, scope iop_version, type r */
#define reg_iop_version_r_version___nr___lsb 0
#define reg_iop_version_r_version___nr___width 8
#define reg_iop_version_r_version_offset 0
/* Constants */
#define regk_iop_version_v1_0 0x00000001
#endif /* __iop_version_defs_asm_h */

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arch/cris/include/arch-v32/arch/hwregs/iop/iop_crc_par_defs.h Normal file
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#ifndef __iop_crc_par_defs_h
#define __iop_crc_par_defs_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_crc_par.r
* id: <not found>
* last modfied: Mon Apr 11 16:08:45 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r
* id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope iop_crc_par */
/* Register rw_cfg, scope iop_crc_par, type rw */
typedef struct {
unsigned int mode : 1;
unsigned int crc_out : 1;
unsigned int rev_out : 1;
unsigned int inv_out : 1;
unsigned int trig : 2;
unsigned int poly : 3;
unsigned int dummy1 : 23;
} reg_iop_crc_par_rw_cfg;
#define REG_RD_ADDR_iop_crc_par_rw_cfg 0
#define REG_WR_ADDR_iop_crc_par_rw_cfg 0
/* Register rw_init_crc, scope iop_crc_par, type rw */
typedef unsigned int reg_iop_crc_par_rw_init_crc;
#define REG_RD_ADDR_iop_crc_par_rw_init_crc 4
#define REG_WR_ADDR_iop_crc_par_rw_init_crc 4
/* Register rw_correct_crc, scope iop_crc_par, type rw */
typedef unsigned int reg_iop_crc_par_rw_correct_crc;
#define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8
#define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8
/* Register rw_ctrl, scope iop_crc_par, type rw */
typedef struct {
unsigned int en : 1;
unsigned int dummy1 : 31;
} reg_iop_crc_par_rw_ctrl;
#define REG_RD_ADDR_iop_crc_par_rw_ctrl 12
#define REG_WR_ADDR_iop_crc_par_rw_ctrl 12
/* Register rw_set_last, scope iop_crc_par, type rw */
typedef struct {
unsigned int tr_dif : 1;
unsigned int dummy1 : 31;
} reg_iop_crc_par_rw_set_last;
#define REG_RD_ADDR_iop_crc_par_rw_set_last 16
#define REG_WR_ADDR_iop_crc_par_rw_set_last 16
/* Register rw_wr1byte, scope iop_crc_par, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_iop_crc_par_rw_wr1byte;
#define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20
#define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20
/* Register rw_wr2byte, scope iop_crc_par, type rw */
typedef struct {
unsigned int data : 16;
unsigned int dummy1 : 16;
} reg_iop_crc_par_rw_wr2byte;
#define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24
#define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24
/* Register rw_wr3byte, scope iop_crc_par, type rw */
typedef struct {
unsigned int data : 24;
unsigned int dummy1 : 8;
} reg_iop_crc_par_rw_wr3byte;
#define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28
#define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28
/* Register rw_wr4byte, scope iop_crc_par, type rw */
typedef struct {
unsigned int data : 32;
} reg_iop_crc_par_rw_wr4byte;
#define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32
#define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32
/* Register rw_wr1byte_last, scope iop_crc_par, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_iop_crc_par_rw_wr1byte_last;
#define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36
#define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36
/* Register rw_wr2byte_last, scope iop_crc_par, type rw */
typedef struct {
unsigned int data : 16;
unsigned int dummy1 : 16;
} reg_iop_crc_par_rw_wr2byte_last;
#define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40
#define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40
/* Register rw_wr3byte_last, scope iop_crc_par, type rw */
typedef struct {
unsigned int data : 24;
unsigned int dummy1 : 8;
} reg_iop_crc_par_rw_wr3byte_last;
#define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44
#define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44
/* Register rw_wr4byte_last, scope iop_crc_par, type rw */
typedef struct {
unsigned int data : 32;
} reg_iop_crc_par_rw_wr4byte_last;
#define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48
#define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48
/* Register r_stat, scope iop_crc_par, type r */
typedef struct {
unsigned int err : 1;
unsigned int busy : 1;
unsigned int dummy1 : 30;
} reg_iop_crc_par_r_stat;
#define REG_RD_ADDR_iop_crc_par_r_stat 52
/* Register r_sh_reg, scope iop_crc_par, type r */
typedef unsigned int reg_iop_crc_par_r_sh_reg;
#define REG_RD_ADDR_iop_crc_par_r_sh_reg 56
/* Register r_crc, scope iop_crc_par, type r */
typedef unsigned int reg_iop_crc_par_r_crc;
#define REG_RD_ADDR_iop_crc_par_r_crc 60
/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
typedef struct {
unsigned int last : 2;
unsigned int dummy1 : 30;
} reg_iop_crc_par_rw_strb_rec_dif_in;
#define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
#define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
/* Constants */
enum {
regk_iop_crc_par_calc = 0x00000001,
regk_iop_crc_par_ccitt = 0x00000002,
regk_iop_crc_par_check = 0x00000000,
regk_iop_crc_par_crc16 = 0x00000001,
regk_iop_crc_par_crc32 = 0x00000000,
regk_iop_crc_par_crc5 = 0x00000003,
regk_iop_crc_par_crc5_11 = 0x00000004,
regk_iop_crc_par_dif_in = 0x00000002,
regk_iop_crc_par_hi = 0x00000000,
regk_iop_crc_par_neg = 0x00000002,
regk_iop_crc_par_no = 0x00000000,
regk_iop_crc_par_pos = 0x00000001,
regk_iop_crc_par_pos_neg = 0x00000003,
regk_iop_crc_par_rw_cfg_default = 0x00000000,
regk_iop_crc_par_rw_ctrl_default = 0x00000000,
regk_iop_crc_par_yes = 0x00000001
};
#endif /* __iop_crc_par_defs_h */

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arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_in_defs.h Normal file
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#ifndef __iop_dmc_in_defs_h
#define __iop_dmc_in_defs_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_dmc_in.r
* id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp
* last modfied: Mon Apr 11 16:08:45 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_in_defs.h ../../inst/io_proc/rtl/iop_dmc_in.r
* id: $Id: iop_dmc_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope iop_dmc_in */
/* Register rw_cfg, scope iop_dmc_in, type rw */
typedef struct {
unsigned int sth_intr : 3;
unsigned int last_dis_dif : 1;
unsigned int dummy1 : 28;
} reg_iop_dmc_in_rw_cfg;
#define REG_RD_ADDR_iop_dmc_in_rw_cfg 0
#define REG_WR_ADDR_iop_dmc_in_rw_cfg 0
/* Register rw_ctrl, scope iop_dmc_in, type rw */
typedef struct {
unsigned int dif_en : 1;
unsigned int dif_dis : 1;
unsigned int stream_clr : 1;
unsigned int dummy1 : 29;
} reg_iop_dmc_in_rw_ctrl;
#define REG_RD_ADDR_iop_dmc_in_rw_ctrl 4
#define REG_WR_ADDR_iop_dmc_in_rw_ctrl 4
/* Register r_stat, scope iop_dmc_in, type r */
typedef struct {
unsigned int dif_en : 1;
unsigned int dummy1 : 31;
} reg_iop_dmc_in_r_stat;
#define REG_RD_ADDR_iop_dmc_in_r_stat 8
/* Register rw_stream_cmd, scope iop_dmc_in, type rw */
typedef struct {
unsigned int cmd : 10;
unsigned int dummy1 : 6;
unsigned int n : 8;
unsigned int dummy2 : 8;
} reg_iop_dmc_in_rw_stream_cmd;
#define REG_RD_ADDR_iop_dmc_in_rw_stream_cmd 12
#define REG_WR_ADDR_iop_dmc_in_rw_stream_cmd 12
/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */
typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data;
#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data 16
#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data 16
/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */
typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data_last;
#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data_last 20
#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data_last 20
/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */
typedef struct {
unsigned int eop : 1;
unsigned int wait : 1;
unsigned int keep_md : 1;
unsigned int size : 3;
unsigned int dummy1 : 26;
} reg_iop_dmc_in_rw_stream_ctrl;
#define REG_RD_ADDR_iop_dmc_in_rw_stream_ctrl 24
#define REG_WR_ADDR_iop_dmc_in_rw_stream_ctrl 24
/* Register r_stream_stat, scope iop_dmc_in, type r */
typedef struct {
unsigned int sth : 7;
unsigned int dummy1 : 9;
unsigned int full : 1;
unsigned int last_pkt : 1;
unsigned int data_md_valid : 1;
unsigned int ctxt_md_valid : 1;
unsigned int group_md_valid : 1;
unsigned int stream_busy : 1;
unsigned int cmd_rdy : 1;
unsigned int dummy2 : 9;
} reg_iop_dmc_in_r_stream_stat;
#define REG_RD_ADDR_iop_dmc_in_r_stream_stat 28
/* Register r_data_descr, scope iop_dmc_in, type r */
typedef struct {
unsigned int ctrl : 8;
unsigned int stat : 8;
unsigned int md : 16;
} reg_iop_dmc_in_r_data_descr;
#define REG_RD_ADDR_iop_dmc_in_r_data_descr 32
/* Register r_ctxt_descr, scope iop_dmc_in, type r */
typedef struct {
unsigned int ctrl : 8;
unsigned int stat : 8;
unsigned int md0 : 16;
} reg_iop_dmc_in_r_ctxt_descr;
#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr 36
/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */
typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md1;
#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md1 40
/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */
typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md2;
#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md2 44
/* Register r_group_descr, scope iop_dmc_in, type r */
typedef struct {
unsigned int ctrl : 8;
unsigned int stat : 8;
unsigned int md : 16;
} reg_iop_dmc_in_r_group_descr;
#define REG_RD_ADDR_iop_dmc_in_r_group_descr 56
/* Register rw_data_descr, scope iop_dmc_in, type rw */
typedef struct {
unsigned int dummy1 : 16;
unsigned int md : 16;
} reg_iop_dmc_in_rw_data_descr;
#define REG_RD_ADDR_iop_dmc_in_rw_data_descr 60
#define REG_WR_ADDR_iop_dmc_in_rw_data_descr 60
/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */
typedef struct {
unsigned int dummy1 : 16;
unsigned int md0 : 16;
} reg_iop_dmc_in_rw_ctxt_descr;
#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr 64
#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr 64
/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */
typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md1;
#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68
#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68
/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */
typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md2;
#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72
#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72
/* Register rw_group_descr, scope iop_dmc_in, type rw */
typedef struct {
unsigned int dummy1 : 16;
unsigned int md : 16;
} reg_iop_dmc_in_rw_group_descr;
#define REG_RD_ADDR_iop_dmc_in_rw_group_descr 84
#define REG_WR_ADDR_iop_dmc_in_rw_group_descr 84
/* Register rw_intr_mask, scope iop_dmc_in, type rw */
typedef struct {
unsigned int data_md : 1;
unsigned int ctxt_md : 1;
unsigned int group_md : 1;
unsigned int cmd_rdy : 1;
unsigned int sth : 1;
unsigned int full : 1;
unsigned int dummy1 : 26;
} reg_iop_dmc_in_rw_intr_mask;
#define REG_RD_ADDR_iop_dmc_in_rw_intr_mask 88
#define REG_WR_ADDR_iop_dmc_in_rw_intr_mask 88
/* Register rw_ack_intr, scope iop_dmc_in, type rw */
typedef struct {
unsigned int data_md : 1;
unsigned int ctxt_md : 1;
unsigned int group_md : 1;
unsigned int cmd_rdy : 1;
unsigned int sth : 1;
unsigned int full : 1;
unsigned int dummy1 : 26;
} reg_iop_dmc_in_rw_ack_intr;
#define REG_RD_ADDR_iop_dmc_in_rw_ack_intr 92
#define REG_WR_ADDR_iop_dmc_in_rw_ack_intr 92
/* Register r_intr, scope iop_dmc_in, type r */
typedef struct {
unsigned int data_md : 1;
unsigned int ctxt_md : 1;
unsigned int group_md : 1;
unsigned int cmd_rdy : 1;
unsigned int sth : 1;
unsigned int full : 1;
unsigned int dummy1 : 26;
} reg_iop_dmc_in_r_intr;
#define REG_RD_ADDR_iop_dmc_in_r_intr 96
/* Register r_masked_intr, scope iop_dmc_in, type r */
typedef struct {
unsigned int data_md : 1;
unsigned int ctxt_md : 1;
unsigned int group_md : 1;
unsigned int cmd_rdy : 1;
unsigned int sth : 1;
unsigned int full : 1;
unsigned int dummy1 : 26;
} reg_iop_dmc_in_r_masked_intr;
#define REG_RD_ADDR_iop_dmc_in_r_masked_intr 100
/* Constants */
enum {
regk_iop_dmc_in_ack_pkt = 0x00000100,
regk_iop_dmc_in_array = 0x00000008,
regk_iop_dmc_in_burst = 0x00000020,
regk_iop_dmc_in_copy_next = 0x00000010,
regk_iop_dmc_in_copy_up = 0x00000020,
regk_iop_dmc_in_dis_c = 0x00000010,
regk_iop_dmc_in_dis_g = 0x00000020,
regk_iop_dmc_in_lim1 = 0x00000000,
regk_iop_dmc_in_lim16 = 0x00000004,
regk_iop_dmc_in_lim2 = 0x00000001,
regk_iop_dmc_in_lim32 = 0x00000005,
regk_iop_dmc_in_lim4 = 0x00000002,
regk_iop_dmc_in_lim64 = 0x00000006,
regk_iop_dmc_in_lim8 = 0x00000003,
regk_iop_dmc_in_load_c = 0x00000200,
regk_iop_dmc_in_load_c_n = 0x00000280,
regk_iop_dmc_in_load_c_next = 0x00000240,
regk_iop_dmc_in_load_d = 0x00000140,
regk_iop_dmc_in_load_g = 0x00000300,
regk_iop_dmc_in_load_g_down = 0x000003c0,
regk_iop_dmc_in_load_g_next = 0x00000340,
regk_iop_dmc_in_load_g_up = 0x00000380,
regk_iop_dmc_in_next_en = 0x00000010,
regk_iop_dmc_in_next_pkt = 0x00000010,
regk_iop_dmc_in_no = 0x00000000,
regk_iop_dmc_in_restore = 0x00000020,
regk_iop_dmc_in_rw_cfg_default = 0x00000000,
regk_iop_dmc_in_rw_ctxt_descr_default = 0x00000000,
regk_iop_dmc_in_rw_ctxt_descr_md1_default = 0x00000000,
regk_iop_dmc_in_rw_ctxt_descr_md2_default = 0x00000000,
regk_iop_dmc_in_rw_data_descr_default = 0x00000000,
regk_iop_dmc_in_rw_group_descr_default = 0x00000000,
regk_iop_dmc_in_rw_intr_mask_default = 0x00000000,
regk_iop_dmc_in_rw_stream_ctrl_default = 0x00000000,
regk_iop_dmc_in_save_down = 0x00000020,
regk_iop_dmc_in_save_up = 0x00000020,
regk_iop_dmc_in_set_reg = 0x00000050,
regk_iop_dmc_in_set_w_size1 = 0x00000190,
regk_iop_dmc_in_set_w_size2 = 0x000001a0,
regk_iop_dmc_in_set_w_size4 = 0x000001c0,
regk_iop_dmc_in_store_c = 0x00000002,
regk_iop_dmc_in_store_descr = 0x00000000,
regk_iop_dmc_in_store_g = 0x00000004,
regk_iop_dmc_in_store_md = 0x00000001,
regk_iop_dmc_in_update_down = 0x00000020,
regk_iop_dmc_in_yes = 0x00000001
};
#endif /* __iop_dmc_in_defs_h */

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#ifndef __iop_dmc_out_defs_h
#define __iop_dmc_out_defs_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_dmc_out.r
* id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp
* last modfied: Mon Apr 11 16:08:45 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r
* id: $Id: iop_dmc_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope iop_dmc_out */
/* Register rw_cfg, scope iop_dmc_out, type rw */
typedef struct {
unsigned int trf_lim : 16;
unsigned int last_at_trf_lim : 1;
unsigned int dth_intr : 3;
unsigned int dummy1 : 12;
} reg_iop_dmc_out_rw_cfg;
#define REG_RD_ADDR_iop_dmc_out_rw_cfg 0
#define REG_WR_ADDR_iop_dmc_out_rw_cfg 0
/* Register rw_ctrl, scope iop_dmc_out, type rw */
typedef struct {
unsigned int dif_en : 1;
unsigned int dif_dis : 1;
unsigned int dummy1 : 30;
} reg_iop_dmc_out_rw_ctrl;
#define REG_RD_ADDR_iop_dmc_out_rw_ctrl 4
#define REG_WR_ADDR_iop_dmc_out_rw_ctrl 4
/* Register r_stat, scope iop_dmc_out, type r */
typedef struct {
unsigned int dif_en : 1;
unsigned int dummy1 : 31;
} reg_iop_dmc_out_r_stat;
#define REG_RD_ADDR_iop_dmc_out_r_stat 8
/* Register rw_stream_cmd, scope iop_dmc_out, type rw */
typedef struct {
unsigned int cmd : 10;
unsigned int dummy1 : 6;
unsigned int n : 8;
unsigned int dummy2 : 8;
} reg_iop_dmc_out_rw_stream_cmd;
#define REG_RD_ADDR_iop_dmc_out_rw_stream_cmd 12
#define REG_WR_ADDR_iop_dmc_out_rw_stream_cmd 12
/* Register rs_stream_data, scope iop_dmc_out, type rs */
typedef unsigned int reg_iop_dmc_out_rs_stream_data;
#define REG_RD_ADDR_iop_dmc_out_rs_stream_data 16
/* Register r_stream_data, scope iop_dmc_out, type r */
typedef unsigned int reg_iop_dmc_out_r_stream_data;
#define REG_RD_ADDR_iop_dmc_out_r_stream_data 20
/* Register r_stream_stat, scope iop_dmc_out, type r */
typedef struct {
unsigned int dth : 7;
unsigned int dummy1 : 9;
unsigned int dv : 1;
unsigned int all_avail : 1;
unsigned int last : 1;
unsigned int size : 3;
unsigned int data_md_valid : 1;
unsigned int ctxt_md_valid : 1;
unsigned int group_md_valid : 1;
unsigned int stream_busy : 1;
unsigned int cmd_rdy : 1;
unsigned int cmd_rq : 1;
unsigned int dummy2 : 4;
} reg_iop_dmc_out_r_stream_stat;
#define REG_RD_ADDR_iop_dmc_out_r_stream_stat 24
/* Register r_data_descr, scope iop_dmc_out, type r */
typedef struct {
unsigned int ctrl : 8;
unsigned int stat : 8;
unsigned int md : 16;
} reg_iop_dmc_out_r_data_descr;
#define REG_RD_ADDR_iop_dmc_out_r_data_descr 28
/* Register r_ctxt_descr, scope iop_dmc_out, type r */
typedef struct {
unsigned int ctrl : 8;
unsigned int stat : 8;
unsigned int md0 : 16;
} reg_iop_dmc_out_r_ctxt_descr;
#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr 32
/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */
typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md1;
#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md1 36
/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */
typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md2;
#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md2 40
/* Register r_group_descr, scope iop_dmc_out, type r */
typedef struct {
unsigned int ctrl : 8;
unsigned int stat : 8;
unsigned int md : 16;
} reg_iop_dmc_out_r_group_descr;
#define REG_RD_ADDR_iop_dmc_out_r_group_descr 52
/* Register rw_data_descr, scope iop_dmc_out, type rw */
typedef struct {
unsigned int dummy1 : 16;
unsigned int md : 16;
} reg_iop_dmc_out_rw_data_descr;
#define REG_RD_ADDR_iop_dmc_out_rw_data_descr 56
#define REG_WR_ADDR_iop_dmc_out_rw_data_descr 56
/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
typedef struct {
unsigned int dummy1 : 16;
unsigned int md0 : 16;
} reg_iop_dmc_out_rw_ctxt_descr;
#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr 60
#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr 60
/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md1;
#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md2;
#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
/* Register rw_group_descr, scope iop_dmc_out, type rw */
typedef struct {
unsigned int dummy1 : 16;
unsigned int md : 16;
} reg_iop_dmc_out_rw_group_descr;
#define REG_RD_ADDR_iop_dmc_out_rw_group_descr 80
#define REG_WR_ADDR_iop_dmc_out_rw_group_descr 80
/* Register rw_intr_mask, scope iop_dmc_out, type rw */
typedef struct {
unsigned int data_md : 1;
unsigned int ctxt_md : 1;
unsigned int group_md : 1;
unsigned int cmd_rdy : 1;
unsigned int dth : 1;
unsigned int dv : 1;
unsigned int last_data : 1;
unsigned int trf_lim : 1;
unsigned int cmd_rq : 1;
unsigned int dummy1 : 23;
} reg_iop_dmc_out_rw_intr_mask;
#define REG_RD_ADDR_iop_dmc_out_rw_intr_mask 84
#define REG_WR_ADDR_iop_dmc_out_rw_intr_mask 84
/* Register rw_ack_intr, scope iop_dmc_out, type rw */
typedef struct {
unsigned int data_md : 1;
unsigned int ctxt_md : 1;
unsigned int group_md : 1;
unsigned int cmd_rdy : 1;
unsigned int dth : 1;
unsigned int dv : 1;
unsigned int last_data : 1;
unsigned int trf_lim : 1;
unsigned int cmd_rq : 1;
unsigned int dummy1 : 23;
} reg_iop_dmc_out_rw_ack_intr;
#define REG_RD_ADDR_iop_dmc_out_rw_ack_intr 88
#define REG_WR_ADDR_iop_dmc_out_rw_ack_intr 88
/* Register r_intr, scope iop_dmc_out, type r */
typedef struct {
unsigned int data_md : 1;
unsigned int ctxt_md : 1;
unsigned int group_md : 1;
unsigned int cmd_rdy : 1;
unsigned int dth : 1;
unsigned int dv : 1;
unsigned int last_data : 1;
unsigned int trf_lim : 1;
unsigned int cmd_rq : 1;
unsigned int dummy1 : 23;
} reg_iop_dmc_out_r_intr;
#define REG_RD_ADDR_iop_dmc_out_r_intr 92
/* Register r_masked_intr, scope iop_dmc_out, type r */
typedef struct {
unsigned int data_md : 1;
unsigned int ctxt_md : 1;
unsigned int group_md : 1;
unsigned int cmd_rdy : 1;
unsigned int dth : 1;
unsigned int dv : 1;
unsigned int last_data : 1;
unsigned int trf_lim : 1;
unsigned int cmd_rq : 1;
unsigned int dummy1 : 23;
} reg_iop_dmc_out_r_masked_intr;
#define REG_RD_ADDR_iop_dmc_out_r_masked_intr 96
/* Constants */
enum {
regk_iop_dmc_out_ack_pkt = 0x00000100,
regk_iop_dmc_out_array = 0x00000008,
regk_iop_dmc_out_burst = 0x00000020,
regk_iop_dmc_out_copy_next = 0x00000010,
regk_iop_dmc_out_copy_up = 0x00000020,
regk_iop_dmc_out_dis_c = 0x00000010,
regk_iop_dmc_out_dis_g = 0x00000020,
regk_iop_dmc_out_lim1 = 0x00000000,
regk_iop_dmc_out_lim16 = 0x00000004,
regk_iop_dmc_out_lim2 = 0x00000001,
regk_iop_dmc_out_lim32 = 0x00000005,
regk_iop_dmc_out_lim4 = 0x00000002,
regk_iop_dmc_out_lim64 = 0x00000006,
regk_iop_dmc_out_lim8 = 0x00000003,
regk_iop_dmc_out_load_c = 0x00000200,
regk_iop_dmc_out_load_c_n = 0x00000280,
regk_iop_dmc_out_load_c_next = 0x00000240,
regk_iop_dmc_out_load_d = 0x00000140,
regk_iop_dmc_out_load_g = 0x00000300,
regk_iop_dmc_out_load_g_down = 0x000003c0,
regk_iop_dmc_out_load_g_next = 0x00000340,
regk_iop_dmc_out_load_g_up = 0x00000380,
regk_iop_dmc_out_next_en = 0x00000010,
regk_iop_dmc_out_next_pkt = 0x00000010,
regk_iop_dmc_out_no = 0x00000000,
regk_iop_dmc_out_restore = 0x00000020,
regk_iop_dmc_out_rw_cfg_default = 0x00000000,
regk_iop_dmc_out_rw_ctxt_descr_default = 0x00000000,
regk_iop_dmc_out_rw_ctxt_descr_md1_default = 0x00000000,
regk_iop_dmc_out_rw_ctxt_descr_md2_default = 0x00000000,
regk_iop_dmc_out_rw_data_descr_default = 0x00000000,
regk_iop_dmc_out_rw_group_descr_default = 0x00000000,
regk_iop_dmc_out_rw_intr_mask_default = 0x00000000,
regk_iop_dmc_out_save_down = 0x00000020,
regk_iop_dmc_out_save_up = 0x00000020,
regk_iop_dmc_out_set_reg = 0x00000050,
regk_iop_dmc_out_set_w_size1 = 0x00000190,
regk_iop_dmc_out_set_w_size2 = 0x000001a0,
regk_iop_dmc_out_set_w_size4 = 0x000001c0,
regk_iop_dmc_out_store_c = 0x00000002,
regk_iop_dmc_out_store_descr = 0x00000000,
regk_iop_dmc_out_store_g = 0x00000004,
regk_iop_dmc_out_store_md = 0x00000001,
regk_iop_dmc_out_update_down = 0x00000020,
regk_iop_dmc_out_yes = 0x00000001
};
#endif /* __iop_dmc_out_defs_h */

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arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_defs.h Normal file
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#ifndef __iop_fifo_in_defs_h
#define __iop_fifo_in_defs_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_fifo_in.r
* id: <not found>
* last modfied: Mon Apr 11 16:10:07 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r
* id: $Id: iop_fifo_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope iop_fifo_in */
/* Register rw_cfg, scope iop_fifo_in, type rw */
typedef struct {
unsigned int avail_lim : 3;
unsigned int byte_order : 2;
unsigned int trig : 2;
unsigned int last_dis_dif_in : 1;
unsigned int mode : 2;
unsigned int dummy1 : 22;
} reg_iop_fifo_in_rw_cfg;
#define REG_RD_ADDR_iop_fifo_in_rw_cfg 0
#define REG_WR_ADDR_iop_fifo_in_rw_cfg 0
/* Register rw_ctrl, scope iop_fifo_in, type rw */
typedef struct {
unsigned int dif_in_en : 1;
unsigned int dif_out_en : 1;
unsigned int dummy1 : 30;
} reg_iop_fifo_in_rw_ctrl;
#define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4
#define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4
/* Register r_stat, scope iop_fifo_in, type r */
typedef struct {
unsigned int avail_bytes : 4;
unsigned int last : 8;
unsigned int dif_in_en : 1;
unsigned int dif_out_en : 1;
unsigned int dummy1 : 18;
} reg_iop_fifo_in_r_stat;
#define REG_RD_ADDR_iop_fifo_in_r_stat 8
/* Register rs_rd1byte, scope iop_fifo_in, type rs */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_iop_fifo_in_rs_rd1byte;
#define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12
/* Register r_rd1byte, scope iop_fifo_in, type r */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_iop_fifo_in_r_rd1byte;
#define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16
/* Register rs_rd2byte, scope iop_fifo_in, type rs */
typedef struct {
unsigned int data : 16;
unsigned int dummy1 : 16;
} reg_iop_fifo_in_rs_rd2byte;
#define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20
/* Register r_rd2byte, scope iop_fifo_in, type r */
typedef struct {
unsigned int data : 16;
unsigned int dummy1 : 16;
} reg_iop_fifo_in_r_rd2byte;
#define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24
/* Register rs_rd3byte, scope iop_fifo_in, type rs */
typedef struct {
unsigned int data : 24;
unsigned int dummy1 : 8;
} reg_iop_fifo_in_rs_rd3byte;
#define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28
/* Register r_rd3byte, scope iop_fifo_in, type r */
typedef struct {
unsigned int data : 24;
unsigned int dummy1 : 8;
} reg_iop_fifo_in_r_rd3byte;
#define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32
/* Register rs_rd4byte, scope iop_fifo_in, type rs */
typedef struct {
unsigned int data : 32;
} reg_iop_fifo_in_rs_rd4byte;
#define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36
/* Register r_rd4byte, scope iop_fifo_in, type r */
typedef struct {
unsigned int data : 32;
} reg_iop_fifo_in_r_rd4byte;
#define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40
/* Register rw_set_last, scope iop_fifo_in, type rw */
typedef unsigned int reg_iop_fifo_in_rw_set_last;
#define REG_RD_ADDR_iop_fifo_in_rw_set_last 44
#define REG_WR_ADDR_iop_fifo_in_rw_set_last 44
/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
typedef struct {
unsigned int last : 2;
unsigned int dummy1 : 30;
} reg_iop_fifo_in_rw_strb_dif_in;
#define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48
#define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48
/* Register rw_intr_mask, scope iop_fifo_in, type rw */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int avail : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_in_rw_intr_mask;
#define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52
#define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52
/* Register rw_ack_intr, scope iop_fifo_in, type rw */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int avail : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_in_rw_ack_intr;
#define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56
#define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56
/* Register r_intr, scope iop_fifo_in, type r */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int avail : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_in_r_intr;
#define REG_RD_ADDR_iop_fifo_in_r_intr 60
/* Register r_masked_intr, scope iop_fifo_in, type r */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int avail : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_in_r_masked_intr;
#define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64
/* Constants */
enum {
regk_iop_fifo_in_dif_in = 0x00000002,
regk_iop_fifo_in_hi = 0x00000000,
regk_iop_fifo_in_neg = 0x00000002,
regk_iop_fifo_in_no = 0x00000000,
regk_iop_fifo_in_order16 = 0x00000001,
regk_iop_fifo_in_order24 = 0x00000002,
regk_iop_fifo_in_order32 = 0x00000003,
regk_iop_fifo_in_order8 = 0x00000000,
regk_iop_fifo_in_pos = 0x00000001,
regk_iop_fifo_in_pos_neg = 0x00000003,
regk_iop_fifo_in_rw_cfg_default = 0x00000024,
regk_iop_fifo_in_rw_ctrl_default = 0x00000000,
regk_iop_fifo_in_rw_intr_mask_default = 0x00000000,
regk_iop_fifo_in_rw_set_last_default = 0x00000000,
regk_iop_fifo_in_rw_strb_dif_in_default = 0x00000000,
regk_iop_fifo_in_size16 = 0x00000002,
regk_iop_fifo_in_size24 = 0x00000001,
regk_iop_fifo_in_size32 = 0x00000000,
regk_iop_fifo_in_size8 = 0x00000003,
regk_iop_fifo_in_yes = 0x00000001
};
#endif /* __iop_fifo_in_defs_h */

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#ifndef __iop_fifo_in_extra_defs_h
#define __iop_fifo_in_extra_defs_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r
* id: <not found>
* last modfied: Mon Apr 11 16:10:08 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r
* id: $Id: iop_fifo_in_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope iop_fifo_in_extra */
/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */
typedef unsigned int reg_iop_fifo_in_extra_rw_wr_data;
#define REG_RD_ADDR_iop_fifo_in_extra_rw_wr_data 0
#define REG_WR_ADDR_iop_fifo_in_extra_rw_wr_data 0
/* Register r_stat, scope iop_fifo_in_extra, type r */
typedef struct {
unsigned int avail_bytes : 4;
unsigned int last : 8;
unsigned int dif_in_en : 1;
unsigned int dif_out_en : 1;
unsigned int dummy1 : 18;
} reg_iop_fifo_in_extra_r_stat;
#define REG_RD_ADDR_iop_fifo_in_extra_r_stat 4
/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */
typedef struct {
unsigned int last : 2;
unsigned int dummy1 : 30;
} reg_iop_fifo_in_extra_rw_strb_dif_in;
#define REG_RD_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8
#define REG_WR_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8
/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int avail : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_in_extra_rw_intr_mask;
#define REG_RD_ADDR_iop_fifo_in_extra_rw_intr_mask 12
#define REG_WR_ADDR_iop_fifo_in_extra_rw_intr_mask 12
/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int avail : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_in_extra_rw_ack_intr;
#define REG_RD_ADDR_iop_fifo_in_extra_rw_ack_intr 16
#define REG_WR_ADDR_iop_fifo_in_extra_rw_ack_intr 16
/* Register r_intr, scope iop_fifo_in_extra, type r */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int avail : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_in_extra_r_intr;
#define REG_RD_ADDR_iop_fifo_in_extra_r_intr 20
/* Register r_masked_intr, scope iop_fifo_in_extra, type r */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int avail : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_in_extra_r_masked_intr;
#define REG_RD_ADDR_iop_fifo_in_extra_r_masked_intr 24
/* Constants */
enum {
regk_iop_fifo_in_extra_fifo_in = 0x00000002,
regk_iop_fifo_in_extra_no = 0x00000000,
regk_iop_fifo_in_extra_rw_intr_mask_default = 0x00000000,
regk_iop_fifo_in_extra_yes = 0x00000001
};
#endif /* __iop_fifo_in_extra_defs_h */

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#ifndef __iop_fifo_out_defs_h
#define __iop_fifo_out_defs_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_fifo_out.r
* id: <not found>
* last modfied: Mon Apr 11 16:10:09 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r
* id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope iop_fifo_out */
/* Register rw_cfg, scope iop_fifo_out, type rw */
typedef struct {
unsigned int free_lim : 3;
unsigned int byte_order : 2;
unsigned int trig : 2;
unsigned int last_dis_dif_in : 1;
unsigned int mode : 2;
unsigned int delay_out_last : 1;
unsigned int last_dis_dif_out : 1;
unsigned int dummy1 : 20;
} reg_iop_fifo_out_rw_cfg;
#define REG_RD_ADDR_iop_fifo_out_rw_cfg 0
#define REG_WR_ADDR_iop_fifo_out_rw_cfg 0
/* Register rw_ctrl, scope iop_fifo_out, type rw */
typedef struct {
unsigned int dif_in_en : 1;
unsigned int dif_out_en : 1;
unsigned int dummy1 : 30;
} reg_iop_fifo_out_rw_ctrl;
#define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4
#define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4
/* Register r_stat, scope iop_fifo_out, type r */
typedef struct {
unsigned int avail_bytes : 4;
unsigned int last : 8;
unsigned int dif_in_en : 1;
unsigned int dif_out_en : 1;
unsigned int zero_data_last : 1;
unsigned int dummy1 : 17;
} reg_iop_fifo_out_r_stat;
#define REG_RD_ADDR_iop_fifo_out_r_stat 8
/* Register rw_wr1byte, scope iop_fifo_out, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_iop_fifo_out_rw_wr1byte;
#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12
#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12
/* Register rw_wr2byte, scope iop_fifo_out, type rw */
typedef struct {
unsigned int data : 16;
unsigned int dummy1 : 16;
} reg_iop_fifo_out_rw_wr2byte;
#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16
#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16
/* Register rw_wr3byte, scope iop_fifo_out, type rw */
typedef struct {
unsigned int data : 24;
unsigned int dummy1 : 8;
} reg_iop_fifo_out_rw_wr3byte;
#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20
#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20
/* Register rw_wr4byte, scope iop_fifo_out, type rw */
typedef struct {
unsigned int data : 32;
} reg_iop_fifo_out_rw_wr4byte;
#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24
#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24
/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_iop_fifo_out_rw_wr1byte_last;
#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28
#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28
/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
typedef struct {
unsigned int data : 16;
unsigned int dummy1 : 16;
} reg_iop_fifo_out_rw_wr2byte_last;
#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32
#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32
/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
typedef struct {
unsigned int data : 24;
unsigned int dummy1 : 8;
} reg_iop_fifo_out_rw_wr3byte_last;
#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36
#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36
/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
typedef struct {
unsigned int data : 32;
} reg_iop_fifo_out_rw_wr4byte_last;
#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40
#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40
/* Register rw_set_last, scope iop_fifo_out, type rw */
typedef unsigned int reg_iop_fifo_out_rw_set_last;
#define REG_RD_ADDR_iop_fifo_out_rw_set_last 44
#define REG_WR_ADDR_iop_fifo_out_rw_set_last 44
/* Register rs_rd_data, scope iop_fifo_out, type rs */
typedef unsigned int reg_iop_fifo_out_rs_rd_data;
#define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48
/* Register r_rd_data, scope iop_fifo_out, type r */
typedef unsigned int reg_iop_fifo_out_r_rd_data;
#define REG_RD_ADDR_iop_fifo_out_r_rd_data 52
/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out;
#define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56
#define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56
/* Register rw_intr_mask, scope iop_fifo_out, type rw */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int free : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_out_rw_intr_mask;
#define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60
#define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60
/* Register rw_ack_intr, scope iop_fifo_out, type rw */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int free : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_out_rw_ack_intr;
#define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64
#define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64
/* Register r_intr, scope iop_fifo_out, type r */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int free : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_out_r_intr;
#define REG_RD_ADDR_iop_fifo_out_r_intr 68
/* Register r_masked_intr, scope iop_fifo_out, type r */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int free : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_out_r_masked_intr;
#define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72
/* Constants */
enum {
regk_iop_fifo_out_hi = 0x00000000,
regk_iop_fifo_out_neg = 0x00000002,
regk_iop_fifo_out_no = 0x00000000,
regk_iop_fifo_out_order16 = 0x00000001,
regk_iop_fifo_out_order24 = 0x00000002,
regk_iop_fifo_out_order32 = 0x00000003,
regk_iop_fifo_out_order8 = 0x00000000,
regk_iop_fifo_out_pos = 0x00000001,
regk_iop_fifo_out_pos_neg = 0x00000003,
regk_iop_fifo_out_rw_cfg_default = 0x00000024,
regk_iop_fifo_out_rw_ctrl_default = 0x00000000,
regk_iop_fifo_out_rw_intr_mask_default = 0x00000000,
regk_iop_fifo_out_rw_set_last_default = 0x00000000,
regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000,
regk_iop_fifo_out_rw_wr1byte_default = 0x00000000,
regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000,
regk_iop_fifo_out_rw_wr2byte_default = 0x00000000,
regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000,
regk_iop_fifo_out_rw_wr3byte_default = 0x00000000,
regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000,
regk_iop_fifo_out_rw_wr4byte_default = 0x00000000,
regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000,
regk_iop_fifo_out_size16 = 0x00000002,
regk_iop_fifo_out_size24 = 0x00000001,
regk_iop_fifo_out_size32 = 0x00000000,
regk_iop_fifo_out_size8 = 0x00000003,
regk_iop_fifo_out_yes = 0x00000001
};
#endif /* __iop_fifo_out_defs_h */

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#ifndef __iop_fifo_out_extra_defs_h
#define __iop_fifo_out_extra_defs_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r
* id: <not found>
* last modfied: Mon Apr 11 16:10:10 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
* id: $Id: iop_fifo_out_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope iop_fifo_out_extra */
/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */
typedef unsigned int reg_iop_fifo_out_extra_rs_rd_data;
#define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0
/* Register r_rd_data, scope iop_fifo_out_extra, type r */
typedef unsigned int reg_iop_fifo_out_extra_r_rd_data;
#define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4
/* Register r_stat, scope iop_fifo_out_extra, type r */
typedef struct {
unsigned int avail_bytes : 4;
unsigned int last : 8;
unsigned int dif_in_en : 1;
unsigned int dif_out_en : 1;
unsigned int zero_data_last : 1;
unsigned int dummy1 : 17;
} reg_iop_fifo_out_extra_r_stat;
#define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8
/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
typedef unsigned int reg_iop_fifo_out_extra_rw_strb_dif_out;
#define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
#define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int free : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_out_extra_rw_intr_mask;
#define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16
#define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16
/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int free : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_out_extra_rw_ack_intr;
#define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20
#define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20
/* Register r_intr, scope iop_fifo_out_extra, type r */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int free : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_out_extra_r_intr;
#define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24
/* Register r_masked_intr, scope iop_fifo_out_extra, type r */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int free : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_out_extra_r_masked_intr;
#define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28
/* Constants */
enum {
regk_iop_fifo_out_extra_no = 0x00000000,
regk_iop_fifo_out_extra_rw_intr_mask_default = 0x00000000,
regk_iop_fifo_out_extra_yes = 0x00000001
};
#endif /* __iop_fifo_out_extra_defs_h */

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