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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-01 00:28:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
238
arch/ia64/sn/kernel/msi_sn.c
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238
arch/ia64/sn/kernel/msi_sn.c
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 Silicon Graphics, Inc. All Rights Reserved.
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*/
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#include <linux/types.h>
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#include <linux/irq.h>
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#include <linux/pci.h>
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#include <linux/cpumask.h>
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#include <linux/msi.h>
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#include <linux/slab.h>
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#include <asm/sn/addrs.h>
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#include <asm/sn/intr.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/pcidev.h>
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#include <asm/sn/nodepda.h>
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struct sn_msi_info {
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u64 pci_addr;
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struct sn_irq_info *sn_irq_info;
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};
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static struct sn_msi_info sn_msi_info[NR_IRQS];
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static struct irq_chip sn_msi_chip;
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void sn_teardown_msi_irq(unsigned int irq)
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{
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nasid_t nasid;
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int widget;
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struct pci_dev *pdev;
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struct pcidev_info *sn_pdev;
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struct sn_irq_info *sn_irq_info;
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struct pcibus_bussoft *bussoft;
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struct sn_pcibus_provider *provider;
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sn_irq_info = sn_msi_info[irq].sn_irq_info;
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if (sn_irq_info == NULL || sn_irq_info->irq_int_bit >= 0)
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return;
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sn_pdev = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
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pdev = sn_pdev->pdi_linux_pcidev;
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provider = SN_PCIDEV_BUSPROVIDER(pdev);
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(*provider->dma_unmap)(pdev,
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sn_msi_info[irq].pci_addr,
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PCI_DMA_FROMDEVICE);
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sn_msi_info[irq].pci_addr = 0;
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bussoft = SN_PCIDEV_BUSSOFT(pdev);
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nasid = NASID_GET(bussoft->bs_base);
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widget = (nasid & 1) ?
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TIO_SWIN_WIDGETNUM(bussoft->bs_base) :
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SWIN_WIDGETNUM(bussoft->bs_base);
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sn_intr_free(nasid, widget, sn_irq_info);
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sn_msi_info[irq].sn_irq_info = NULL;
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destroy_irq(irq);
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}
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int sn_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *entry)
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{
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struct msi_msg msg;
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int widget;
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int status;
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nasid_t nasid;
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u64 bus_addr;
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struct sn_irq_info *sn_irq_info;
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struct pcibus_bussoft *bussoft = SN_PCIDEV_BUSSOFT(pdev);
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struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
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int irq;
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if (!entry->msi_attrib.is_64)
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return -EINVAL;
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if (bussoft == NULL)
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return -EINVAL;
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if (provider == NULL || provider->dma_map_consistent == NULL)
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return -EINVAL;
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irq = create_irq();
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if (irq < 0)
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return irq;
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/*
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* Set up the vector plumbing. Let the prom (via sn_intr_alloc)
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* decide which cpu to direct this msi at by default.
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*/
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nasid = NASID_GET(bussoft->bs_base);
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widget = (nasid & 1) ?
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TIO_SWIN_WIDGETNUM(bussoft->bs_base) :
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SWIN_WIDGETNUM(bussoft->bs_base);
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sn_irq_info = kzalloc(sizeof(struct sn_irq_info), GFP_KERNEL);
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if (! sn_irq_info) {
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destroy_irq(irq);
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return -ENOMEM;
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}
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status = sn_intr_alloc(nasid, widget, sn_irq_info, irq, -1, -1);
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if (status) {
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kfree(sn_irq_info);
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destroy_irq(irq);
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return -ENOMEM;
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}
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sn_irq_info->irq_int_bit = -1; /* mark this as an MSI irq */
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sn_irq_fixup(pdev, sn_irq_info);
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/* Prom probably should fill these in, but doesn't ... */
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sn_irq_info->irq_bridge_type = bussoft->bs_asic_type;
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sn_irq_info->irq_bridge = (void *)bussoft->bs_base;
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/*
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* Map the xio address into bus space
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*/
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bus_addr = (*provider->dma_map_consistent)(pdev,
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sn_irq_info->irq_xtalkaddr,
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sizeof(sn_irq_info->irq_xtalkaddr),
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SN_DMA_MSI|SN_DMA_ADDR_XIO);
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if (! bus_addr) {
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sn_intr_free(nasid, widget, sn_irq_info);
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kfree(sn_irq_info);
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destroy_irq(irq);
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return -ENOMEM;
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}
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sn_msi_info[irq].sn_irq_info = sn_irq_info;
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sn_msi_info[irq].pci_addr = bus_addr;
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msg.address_hi = (u32)(bus_addr >> 32);
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msg.address_lo = (u32)(bus_addr & 0x00000000ffffffff);
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/*
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* In the SN platform, bit 16 is a "send vector" bit which
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* must be present in order to move the vector through the system.
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*/
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msg.data = 0x100 + irq;
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irq_set_msi_desc(irq, entry);
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write_msi_msg(irq, &msg);
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irq_set_chip_and_handler(irq, &sn_msi_chip, handle_edge_irq);
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return 0;
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}
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#ifdef CONFIG_SMP
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static int sn_set_msi_irq_affinity(struct irq_data *data,
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const struct cpumask *cpu_mask, bool force)
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{
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struct msi_msg msg;
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int slice;
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nasid_t nasid;
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u64 bus_addr;
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struct pci_dev *pdev;
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struct pcidev_info *sn_pdev;
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struct sn_irq_info *sn_irq_info;
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struct sn_irq_info *new_irq_info;
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struct sn_pcibus_provider *provider;
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unsigned int cpu, irq = data->irq;
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cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
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sn_irq_info = sn_msi_info[irq].sn_irq_info;
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if (sn_irq_info == NULL || sn_irq_info->irq_int_bit >= 0)
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return -1;
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/*
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* Release XIO resources for the old MSI PCI address
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*/
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__get_cached_msi_msg(data->msi_desc, &msg);
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sn_pdev = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
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pdev = sn_pdev->pdi_linux_pcidev;
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provider = SN_PCIDEV_BUSPROVIDER(pdev);
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bus_addr = (u64)(msg.address_hi) << 32 | (u64)(msg.address_lo);
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(*provider->dma_unmap)(pdev, bus_addr, PCI_DMA_FROMDEVICE);
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sn_msi_info[irq].pci_addr = 0;
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nasid = cpuid_to_nasid(cpu);
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slice = cpuid_to_slice(cpu);
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new_irq_info = sn_retarget_vector(sn_irq_info, nasid, slice);
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sn_msi_info[irq].sn_irq_info = new_irq_info;
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if (new_irq_info == NULL)
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return -1;
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/*
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* Map the xio address into bus space
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*/
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bus_addr = (*provider->dma_map_consistent)(pdev,
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new_irq_info->irq_xtalkaddr,
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sizeof(new_irq_info->irq_xtalkaddr),
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SN_DMA_MSI|SN_DMA_ADDR_XIO);
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sn_msi_info[irq].pci_addr = bus_addr;
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msg.address_hi = (u32)(bus_addr >> 32);
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msg.address_lo = (u32)(bus_addr & 0x00000000ffffffff);
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write_msi_msg(irq, &msg);
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cpumask_copy(data->affinity, cpu_mask);
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return 0;
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}
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#endif /* CONFIG_SMP */
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static void sn_ack_msi_irq(struct irq_data *data)
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{
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irq_move_irq(data);
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ia64_eoi();
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}
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static int sn_msi_retrigger_irq(struct irq_data *data)
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{
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unsigned int vector = data->irq;
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ia64_resend_irq(vector);
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return 1;
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}
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static struct irq_chip sn_msi_chip = {
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.name = "PCI-MSI",
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.irq_mask = mask_msi_irq,
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.irq_unmask = unmask_msi_irq,
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.irq_ack = sn_ack_msi_irq,
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#ifdef CONFIG_SMP
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.irq_set_affinity = sn_set_msi_irq_affinity,
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#endif
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.irq_retrigger = sn_msi_retrigger_irq,
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};
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