mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-30 07:38:52 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
1
arch/m32r/platforms/oaks32r/Makefile
Normal file
1
arch/m32r/platforms/oaks32r/Makefile
Normal file
|
|
@ -0,0 +1 @@
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|||
obj-y := setup.o io.o
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154
arch/m32r/platforms/oaks32r/dot.gdbinit.nommu
Normal file
154
arch/m32r/platforms/oaks32r/dot.gdbinit.nommu
Normal file
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@ -0,0 +1,154 @@
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# .gdbinit file
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# $Id: dot.gdbinit.oaks32r,v 1.4 2004/10/20 02:24:37 takata Exp $
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#-----
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# NOTE: this file is generated by a script, "gen_gdbinit.pl".
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# (Please type "gen_gdbinit.pl --help" and check the help message).
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# $ Id: gen_gdbinit.pl,v 1.12 2004/07/26 09:56:10 takata Exp $
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#-----
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# target platform: oaks32r
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# setting
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set width 0d70
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set radix 0d16
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# clk xin:cpu:bus=16:66:33
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define clock_init
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set *(unsigned long *)0x00ef4008 = 1
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shell sleep 0.1
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set *(unsigned long *)0x00ef4000 = 0x00020100
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end
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# Initialize programmable ports
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define port_init
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set *(unsigned long *)0x00ef1000 = 0x1
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set *(unsigned long *)0x00ef1060 = 0x01400001
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set *(unsigned long *)0x00ef1064 = 0x00015555
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set *(unsigned long *)0x00ef1068 = 0x55555050
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set *(unsigned long *)0x00ef106c = 0x05150040
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end
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# Initialize SDRAM controller
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define sdram_init
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set *(unsigned long *)0x00ef6008 = 0x00000182
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set *(unsigned long *)0x00ef600c = 0x00000001
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shell sleep 0.1
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set *(unsigned long *)0x00ef602c = 0x00000010
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set *(unsigned long *)0x00ef6028 = 0x00000300
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set *(unsigned long *)0x00ef6048 = 0x00000001
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set *(unsigned long *)0x00ef6020 = 0x01000041
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set *(unsigned long *)0x00ef6004 = 0x00010117
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set *(unsigned long *)0x00ef6010 = 0x00000001
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set *(unsigned long *)0x00ef6024 = 0x00000001
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end
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document sdram_init
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SDRAM controller initialization
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0x01000000 - 0x017fffff (8MB)
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end
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|
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# Initialize LAN controller
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define lanc_init
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set *(unsigned long *)0x00ef5008 = 0x03031303
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#RST DRV (P64)
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set *(unsigned char *)0x00ef1046 = 0x08
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set *(unsigned char *)0x00ef1026 = 0xff
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set *(unsigned char *)0x00ef1026 = 0x00
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set *(unsigned short *)0x02000630 = 0xffff
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end
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|
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# Show current task structure
|
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define show_current
|
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set $current = $spi & 0xffffe000
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printf "$current=0x%08lX\n",$current
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print *(struct task_struct *)$current
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end
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|
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# Show user assigned task structure
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define show_task
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set = $arg0 & 0xffffe000
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printf "$task=0x%08lX\n",$task
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print *(struct task_struct *)$task
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end
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document show_task
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Show user assigned task structure
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arg0 : task structure address
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end
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|
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# Show M32R registers
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define show_regs
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printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
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printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
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printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
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printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
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printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
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printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
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end
|
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|
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# Setup all
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define setup
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use_mon_code
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set *(unsigned int)0xfffffffc=0x60
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shell sleep 0.1
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clock_init
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shell sleep 0.1
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port_init
|
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sdram_init
|
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lanc_init
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end
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|
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# Load modules
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define load_modules
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use_debug_dma
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load
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end
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|
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# Set kernel parameters
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define set_kernel_parameters
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set $param = (void*)0x01001000
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# INITRD_START
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# set *(unsigned long *)($param + 0x0010) = 0x00000000
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# INITRD_SIZE
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# set *(unsigned long *)($param + 0x0014) = 0x00000000
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# M32R_CPUCLK
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set *(unsigned long *)($param + 0x0018) = 0d66666667
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# M32R_BUSCLK
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set *(unsigned long *)($param + 0x001c) = 0d33333333
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# M32R_TIMER_DIVIDE
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set *(unsigned long *)($param + 0x0020) = 0d128
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set {char[0x200]}($param + 0x100) = "console=ttyS0,115200n8x root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/rootfs nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 \0"
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end
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# Boot
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define boot
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set_kernel_parameters
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set $fp = 0
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set $pc = 0x01002000
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si
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c
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end
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# Set breakpoints
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define set_breakpoints
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b *0x00000020
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b *0x00000030
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end
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|
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# Restart
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define restart
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sdireset
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sdireset
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setup
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load_modules
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boot
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end
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sdireset
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sdireset
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file vmlinux
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target m32rsdi
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setup
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#load_modules
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#set_breakpoints
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#boot
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228
arch/m32r/platforms/oaks32r/io.c
Normal file
228
arch/m32r/platforms/oaks32r/io.c
Normal file
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@ -0,0 +1,228 @@
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/*
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* linux/arch/m32r/platforms/oaks32r/io.c
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*
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* Typical I/O routines for OAKS32R board.
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*
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* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
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* Hitoshi Yamamoto, Mamoru Sakugawa
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*/
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#include <asm/m32r.h>
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#include <asm/page.h>
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#include <asm/io.h>
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#define PORT2ADDR(port) _port2addr(port)
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static inline void *_port2addr(unsigned long port)
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{
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return (void *)(port | NONCACHE_OFFSET);
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}
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static inline void *_port2addr_ne(unsigned long port)
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{
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return (void *)((port<<1) + NONCACHE_OFFSET + 0x02000000);
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}
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static inline void delay(void)
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{
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__asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
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}
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|
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/*
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* NIC I/O function
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*/
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#define PORT2ADDR_NE(port) _port2addr_ne(port)
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static inline unsigned char _ne_inb(void *portp)
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{
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return *(volatile unsigned char *)(portp+1);
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}
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static inline unsigned short _ne_inw(void *portp)
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{
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unsigned short tmp;
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tmp = *(unsigned short *)(portp) & 0xff;
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tmp |= *(unsigned short *)(portp+2) << 8;
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return tmp;
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}
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static inline void _ne_insb(void *portp, void *addr, unsigned long count)
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{
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unsigned char *buf = addr;
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while (count--)
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*buf++ = *(volatile unsigned char *)(portp+1);
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}
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static inline void _ne_outb(unsigned char b, void *portp)
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{
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*(volatile unsigned char *)(portp+1) = b;
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}
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static inline void _ne_outw(unsigned short w, void *portp)
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{
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*(volatile unsigned short *)portp = (w >> 8);
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*(volatile unsigned short *)(portp+2) = (w & 0xff);
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}
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unsigned char _inb(unsigned long port)
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{
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if (port >= 0x300 && port < 0x320)
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return _ne_inb(PORT2ADDR_NE(port));
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return *(volatile unsigned char *)PORT2ADDR(port);
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}
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unsigned short _inw(unsigned long port)
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{
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if (port >= 0x300 && port < 0x320)
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return _ne_inw(PORT2ADDR_NE(port));
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return *(volatile unsigned short *)PORT2ADDR(port);
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}
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unsigned long _inl(unsigned long port)
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{
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return *(volatile unsigned long *)PORT2ADDR(port);
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}
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unsigned char _inb_p(unsigned long port)
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{
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unsigned char v = _inb(port);
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delay();
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return (v);
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}
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unsigned short _inw_p(unsigned long port)
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{
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unsigned short v = _inw(port);
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delay();
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return (v);
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}
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unsigned long _inl_p(unsigned long port)
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{
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unsigned long v = _inl(port);
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delay();
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return (v);
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}
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void _outb(unsigned char b, unsigned long port)
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{
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if (port >= 0x300 && port < 0x320)
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_ne_outb(b, PORT2ADDR_NE(port));
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else
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*(volatile unsigned char *)PORT2ADDR(port) = b;
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}
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void _outw(unsigned short w, unsigned long port)
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{
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if (port >= 0x300 && port < 0x320)
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_ne_outw(w, PORT2ADDR_NE(port));
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else
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*(volatile unsigned short *)PORT2ADDR(port) = w;
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}
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void _outl(unsigned long l, unsigned long port)
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{
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*(volatile unsigned long *)PORT2ADDR(port) = l;
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}
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void _outb_p(unsigned char b, unsigned long port)
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{
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_outb(b, port);
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delay();
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}
|
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|
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void _outw_p(unsigned short w, unsigned long port)
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{
|
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_outw(w, port);
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delay();
|
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}
|
||||
|
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void _outl_p(unsigned long l, unsigned long port)
|
||||
{
|
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_outl(l, port);
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delay();
|
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}
|
||||
|
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void _insb(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
if (port >= 0x300 && port < 0x320)
|
||||
_ne_insb(PORT2ADDR_NE(port), addr, count);
|
||||
else {
|
||||
unsigned char *buf = addr;
|
||||
unsigned char *portp = PORT2ADDR(port);
|
||||
while (count--)
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*buf++ = *(volatile unsigned char *)portp;
|
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}
|
||||
}
|
||||
|
||||
void _insw(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= 0x300 && port < 0x320) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
*buf++ = _ne_inw(portp);
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
}
|
||||
}
|
||||
|
||||
void _insl(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
unsigned long *buf = addr;
|
||||
unsigned long *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned long *)portp;
|
||||
}
|
||||
|
||||
void _outsb(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned char *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
if (port >= 0x300 && port < 0x320) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
_ne_outb(*buf++, portp);
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned char *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsw(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= 0x300 && port < 0x320) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
_ne_outw(*buf++, portp);
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsl(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned long *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned long *)portp = *buf++;
|
||||
}
|
||||
113
arch/m32r/platforms/oaks32r/setup.c
Normal file
113
arch/m32r/platforms/oaks32r/setup.c
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* linux/arch/m32r/platforms/oaks32r/setup.c
|
||||
*
|
||||
* Setup routines for OAKS32R Board
|
||||
*
|
||||
* Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
|
||||
* Hitoshi Yamamoto, Mamoru Sakugawa
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
|
||||
|
||||
icu_data_t icu_data[NR_IRQS];
|
||||
|
||||
static void disable_oaks32r_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void enable_oaks32r_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void mask_oaks32r(struct irq_data *data)
|
||||
{
|
||||
disable_oaks32r_irq(data->irq);
|
||||
}
|
||||
|
||||
static void unmask_oaks32r(struct irq_data *data)
|
||||
{
|
||||
enable_oaks32r_irq(data->irq);
|
||||
}
|
||||
|
||||
static void shutdown_oaks32r(struct irq_data *data)
|
||||
{
|
||||
unsigned long port;
|
||||
|
||||
port = irq2port(data->irq);
|
||||
outl(M32R_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct irq_chip oaks32r_irq_type =
|
||||
{
|
||||
.name = "OAKS32R-IRQ",
|
||||
.irq_shutdown = shutdown_oaks32r,
|
||||
.irq_mask = mask_oaks32r,
|
||||
.irq_unmask = unmask_oaks32r,
|
||||
};
|
||||
|
||||
void __init init_IRQ(void)
|
||||
{
|
||||
static int once = 0;
|
||||
|
||||
if (once)
|
||||
return;
|
||||
else
|
||||
once++;
|
||||
|
||||
#ifdef CONFIG_NE2000
|
||||
/* INT3 : LAN controller (RTL8019AS) */
|
||||
irq_set_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type,
|
||||
handle_level_irq);
|
||||
icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
|
||||
disable_oaks32r_irq(M32R_IRQ_INT3);
|
||||
#endif /* CONFIG_M32R_NE2000 */
|
||||
|
||||
/* MFT2 : system timer */
|
||||
irq_set_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type,
|
||||
handle_level_irq);
|
||||
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
|
||||
disable_oaks32r_irq(M32R_IRQ_MFT2);
|
||||
|
||||
#ifdef CONFIG_SERIAL_M32R_SIO
|
||||
/* SIO0_R : uart receive data */
|
||||
irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type,
|
||||
handle_level_irq);
|
||||
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
|
||||
disable_oaks32r_irq(M32R_IRQ_SIO0_R);
|
||||
|
||||
/* SIO0_S : uart send data */
|
||||
irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type,
|
||||
handle_level_irq);
|
||||
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
|
||||
disable_oaks32r_irq(M32R_IRQ_SIO0_S);
|
||||
|
||||
/* SIO1_R : uart receive data */
|
||||
irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type,
|
||||
handle_level_irq);
|
||||
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
|
||||
disable_oaks32r_irq(M32R_IRQ_SIO1_R);
|
||||
|
||||
/* SIO1_S : uart send data */
|
||||
irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type,
|
||||
handle_level_irq);
|
||||
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
|
||||
disable_oaks32r_irq(M32R_IRQ_SIO1_S);
|
||||
#endif /* CONFIG_SERIAL_M32R_SIO */
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue