mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-30 23:58:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
1
arch/m32r/platforms/opsput/Makefile
Normal file
1
arch/m32r/platforms/opsput/Makefile
Normal file
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@ -0,0 +1 @@
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obj-y := setup.o io.o
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218
arch/m32r/platforms/opsput/dot.gdbinit
Normal file
218
arch/m32r/platforms/opsput/dot.gdbinit
Normal file
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@ -0,0 +1,218 @@
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# .gdbinit file
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# $Id: dot.gdbinit,v 1.1 2004/07/27 06:54:20 sakugawa Exp $
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# setting
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set width 0d70
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set radix 0d16
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set height 0
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debug_chaos
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# clk xin:cpu:bus=1:8:1
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define clock_init_on_181
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set *(unsigned long *)0x00ef400c = 0x2
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set *(unsigned long *)0x00ef4004 = 0x1
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shell sleep 0.1
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set *(unsigned long *)0x00ef4000 = 0x101
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end
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# clk xin:cpu:bus=1:8:2
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define clock_init_on_182
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set *(unsigned long *)0x00ef400c = 0x1
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set *(unsigned long *)0x00ef4004 = 0x1
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shell sleep 0.1
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set *(unsigned long *)0x00ef4000 = 0x101
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end
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# clk xin:cpu:bus=1:8:4
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define clock_init_on_184
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set *(unsigned long *)0x00ef400c = 0x0
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set *(unsigned long *)0x00ef4004 = 0x1
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shell sleep 0.1
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set *(unsigned long *)0x00ef4000 = 0x101
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end
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# clk xin:cpu:bus=1:1:1
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define clock_init_off
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shell sleep 0.1
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set *(unsigned long *)0x00ef4000 = 0x0
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shell sleep 0.1
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set *(unsigned long *)0x00ef4004 = 0x0
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shell sleep 0.1
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set *(unsigned long *)0x00ef400c = 0x0
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end
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define tlb_init
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set $tlbbase = 0xfe000000
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set *(unsigned long *)($tlbbase + 0x04) = 0x0
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set *(unsigned long *)($tlbbase + 0x0c) = 0x0
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set *(unsigned long *)($tlbbase + 0x14) = 0x0
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set *(unsigned long *)($tlbbase + 0x1c) = 0x0
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set *(unsigned long *)($tlbbase + 0x24) = 0x0
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set *(unsigned long *)($tlbbase + 0x2c) = 0x0
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set *(unsigned long *)($tlbbase + 0x34) = 0x0
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set *(unsigned long *)($tlbbase + 0x3c) = 0x0
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set *(unsigned long *)($tlbbase + 0x44) = 0x0
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set *(unsigned long *)($tlbbase + 0x4c) = 0x0
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set *(unsigned long *)($tlbbase + 0x54) = 0x0
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set *(unsigned long *)($tlbbase + 0x5c) = 0x0
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set *(unsigned long *)($tlbbase + 0x64) = 0x0
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set *(unsigned long *)($tlbbase + 0x6c) = 0x0
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set *(unsigned long *)($tlbbase + 0x74) = 0x0
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set *(unsigned long *)($tlbbase + 0x7c) = 0x0
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set *(unsigned long *)($tlbbase + 0x84) = 0x0
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set *(unsigned long *)($tlbbase + 0x8c) = 0x0
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set *(unsigned long *)($tlbbase + 0x94) = 0x0
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set *(unsigned long *)($tlbbase + 0x9c) = 0x0
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set *(unsigned long *)($tlbbase + 0xa4) = 0x0
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set *(unsigned long *)($tlbbase + 0xac) = 0x0
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set *(unsigned long *)($tlbbase + 0xb4) = 0x0
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set *(unsigned long *)($tlbbase + 0xbc) = 0x0
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set *(unsigned long *)($tlbbase + 0xc4) = 0x0
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set *(unsigned long *)($tlbbase + 0xcc) = 0x0
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set *(unsigned long *)($tlbbase + 0xd4) = 0x0
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set *(unsigned long *)($tlbbase + 0xdc) = 0x0
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set *(unsigned long *)($tlbbase + 0xe4) = 0x0
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set *(unsigned long *)($tlbbase + 0xec) = 0x0
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set *(unsigned long *)($tlbbase + 0xf4) = 0x0
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set *(unsigned long *)($tlbbase + 0xfc) = 0x0
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set $tlbbase = 0xfe000800
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set *(unsigned long *)($tlbbase + 0x04) = 0x0
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set *(unsigned long *)($tlbbase + 0x0c) = 0x0
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set *(unsigned long *)($tlbbase + 0x14) = 0x0
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set *(unsigned long *)($tlbbase + 0x1c) = 0x0
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set *(unsigned long *)($tlbbase + 0x24) = 0x0
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set *(unsigned long *)($tlbbase + 0x2c) = 0x0
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set *(unsigned long *)($tlbbase + 0x34) = 0x0
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set *(unsigned long *)($tlbbase + 0x3c) = 0x0
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set *(unsigned long *)($tlbbase + 0x44) = 0x0
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set *(unsigned long *)($tlbbase + 0x4c) = 0x0
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set *(unsigned long *)($tlbbase + 0x54) = 0x0
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set *(unsigned long *)($tlbbase + 0x5c) = 0x0
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set *(unsigned long *)($tlbbase + 0x64) = 0x0
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set *(unsigned long *)($tlbbase + 0x6c) = 0x0
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set *(unsigned long *)($tlbbase + 0x74) = 0x0
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set *(unsigned long *)($tlbbase + 0x7c) = 0x0
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set *(unsigned long *)($tlbbase + 0x84) = 0x0
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set *(unsigned long *)($tlbbase + 0x8c) = 0x0
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set *(unsigned long *)($tlbbase + 0x94) = 0x0
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set *(unsigned long *)($tlbbase + 0x9c) = 0x0
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set *(unsigned long *)($tlbbase + 0xa4) = 0x0
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set *(unsigned long *)($tlbbase + 0xac) = 0x0
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set *(unsigned long *)($tlbbase + 0xb4) = 0x0
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set *(unsigned long *)($tlbbase + 0xbc) = 0x0
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set *(unsigned long *)($tlbbase + 0xc4) = 0x0
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set *(unsigned long *)($tlbbase + 0xcc) = 0x0
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set *(unsigned long *)($tlbbase + 0xd4) = 0x0
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set *(unsigned long *)($tlbbase + 0xdc) = 0x0
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set *(unsigned long *)($tlbbase + 0xe4) = 0x0
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set *(unsigned long *)($tlbbase + 0xec) = 0x0
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set *(unsigned long *)($tlbbase + 0xf4) = 0x0
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set *(unsigned long *)($tlbbase + 0xfc) = 0x0
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end
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define load_modules
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use_debug_dma
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load
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end
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# Set kernel parameters
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define set_kernel_parameters
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set $param = (void*)0x88001000
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# INITRD_START
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# set *(unsigned long *)($param + 0x0010) = 0x08300000
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# INITRD_SIZE
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# set *(unsigned long *)($param + 0x0014) = 0x00400000
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# M32R_CPUCLK
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set *(unsigned long *)($param + 0x0018) = 0d200000000
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# M32R_BUSCLK
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set *(unsigned long *)($param + 0x001c) = 0d50000000
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# set *(unsigned long *)($param + 0x001c) = 0d25000000
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# M32R_TIMER_DIVIDE
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set *(unsigned long *)($param + 0x0020) = 0d128
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set {char[0x200]}($param + 0x100) = "console=ttyS0,115200n8x console=tty1 \
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root=/dev/nfsroot \
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nfsroot=192.168.0.1:/project/m32r-linux/export/root.2.6 \
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nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 \
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mem=16m \0"
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end
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define boot
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set_kernel_parameters
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set $pc=0x88002000
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set $fp=0
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set $evb=0x88000000
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si
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c
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end
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# Show TLB entries
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define show_tlb_entries
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set $i = 0
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set $addr = $arg0
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use_mon_code
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while ($i < 0d32 )
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set $tlb_tag = *(unsigned long*)$addr
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set $tlb_data = *(unsigned long*)($addr + 4)
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printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
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set $i = $i + 1
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set $addr = $addr + 8
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end
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# use_debug_dma
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end
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define itlb
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set $itlb=0xfe000000
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show_tlb_entries $itlb
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end
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define dtlb
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set $dtlb=0xfe000800
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show_tlb_entries $dtlb
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end
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define show_regs
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printf " R0[%08lx] R1[%08lx] R2[%08lx] R3[%08lx]\n",$r0,$r1,$r2,$r3
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printf " R4[%08lx] R5[%08lx] R6[%08lx] R7[%08lx]\n",$r4,$r5,$r6,$r7
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printf " R8[%08lx] R9[%08lx] R10[%08lx] R11[%08lx]\n",$r8,$r9,$r10,$r11
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printf "R12[%08lx] FP[%08lx] LR[%08lx] SP[%08lx]\n",$r12,$fp,$lr,$sp
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printf "PSW[%08lx] CBR[%08lx] SPI[%08lx] SPU[%08lx]\n",$psw,$cbr,$spi,$spu
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printf "BPC[%08lx] PC[%08lx] ACCL[%08lx] ACCH[%08lx]\n",$bpc,$pc,$accl,$acch
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printf "EVB[%08lx]\n",$evb
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end
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define restart
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sdireset
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sdireset
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en 1
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set $pc=0x0
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c
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tlb_init
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setup
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load_modules
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boot
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end
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define setup
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debug_chaos
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# Clock
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# shell sleep 0.1
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# clock_init_off
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# shell sleep 1
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# clock_init_on_182
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# shell sleep 0.1
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# SDRAM
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set *(unsigned long *)0xa0ef6004 = 0x0001053f
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set *(unsigned long *)0xa0ef6028 = 0x00031102
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end
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sdireset
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sdireset
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file vmlinux
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target m32rsdi
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set $pc=0x0
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b *0x30000
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c
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dis 1
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setup
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tlb_init
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load_modules
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boot
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395
arch/m32r/platforms/opsput/io.c
Normal file
395
arch/m32r/platforms/opsput/io.c
Normal file
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@ -0,0 +1,395 @@
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/*
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* linux/arch/m32r/platforms/opsput/io.c
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*
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* Typical I/O routines for OPSPUT board.
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*
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* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
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* Hitoshi Yamamoto, Takeo Takahashi
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*
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* This file is subject to the terms and conditions of the GNU General
|
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* Public License. See the file "COPYING" in the main directory of this
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* archive for more details.
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*/
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#include <asm/m32r.h>
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#include <asm/page.h>
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#include <asm/io.h>
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#include <asm/byteorder.h>
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#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
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#include <linux/types.h>
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#define M32R_PCC_IOMAP_SIZE 0x1000
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#define M32R_PCC_IOSTART0 0x1000
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#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
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extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
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extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
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extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
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extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
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#endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */
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#define PORT2ADDR(port) _port2addr(port)
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#define PORT2ADDR_USB(port) _port2addr_usb(port)
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static inline void *_port2addr(unsigned long port)
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{
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return (void *)(port | NONCACHE_OFFSET);
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}
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|
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#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
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static inline void *__port2addr_ata(unsigned long port)
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{
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static int dummy_reg;
|
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|
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switch (port) {
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case 0x1f0: return (void *)(0x0c002000 | NONCACHE_OFFSET);
|
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case 0x1f1: return (void *)(0x0c012800 | NONCACHE_OFFSET);
|
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case 0x1f2: return (void *)(0x0c012002 | NONCACHE_OFFSET);
|
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case 0x1f3: return (void *)(0x0c012802 | NONCACHE_OFFSET);
|
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case 0x1f4: return (void *)(0x0c012004 | NONCACHE_OFFSET);
|
||||
case 0x1f5: return (void *)(0x0c012804 | NONCACHE_OFFSET);
|
||||
case 0x1f6: return (void *)(0x0c012006 | NONCACHE_OFFSET);
|
||||
case 0x1f7: return (void *)(0x0c012806 | NONCACHE_OFFSET);
|
||||
case 0x3f6: return (void *)(0x0c01200e | NONCACHE_OFFSET);
|
||||
default: return (void *)&dummy_reg;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* OPSPUT-LAN is located in the extended bus space
|
||||
* from 0x10000000 to 0x13ffffff on physical address.
|
||||
* The base address of LAN controller(LAN91C111) is 0x300.
|
||||
*/
|
||||
#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
|
||||
#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
|
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static inline void *_port2addr_ne(unsigned long port)
|
||||
{
|
||||
return (void *)(port + 0x10000000);
|
||||
}
|
||||
static inline void *_port2addr_usb(unsigned long port)
|
||||
{
|
||||
return (void *)((port & 0x0f) + NONCACHE_OFFSET + 0x10303000);
|
||||
}
|
||||
|
||||
static inline void delay(void)
|
||||
{
|
||||
__asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
|
||||
}
|
||||
|
||||
/*
|
||||
* NIC I/O function
|
||||
*/
|
||||
|
||||
#define PORT2ADDR_NE(port) _port2addr_ne(port)
|
||||
|
||||
static inline unsigned char _ne_inb(void *portp)
|
||||
{
|
||||
return *(volatile unsigned char *)portp;
|
||||
}
|
||||
|
||||
static inline unsigned short _ne_inw(void *portp)
|
||||
{
|
||||
return (unsigned short)le16_to_cpu(*(volatile unsigned short *)portp);
|
||||
}
|
||||
|
||||
static inline void _ne_insb(void *portp, void *addr, unsigned long count)
|
||||
{
|
||||
unsigned char *buf = (unsigned char *)addr;
|
||||
|
||||
while (count--)
|
||||
*buf++ = _ne_inb(portp);
|
||||
}
|
||||
|
||||
static inline void _ne_outb(unsigned char b, void *portp)
|
||||
{
|
||||
*(volatile unsigned char *)portp = b;
|
||||
}
|
||||
|
||||
static inline void _ne_outw(unsigned short w, void *portp)
|
||||
{
|
||||
*(volatile unsigned short *)portp = cpu_to_le16(w);
|
||||
}
|
||||
|
||||
unsigned char _inb(unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
return _ne_inb(PORT2ADDR_NE(port));
|
||||
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
return *(volatile unsigned char *)__port2addr_ata(port);
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned char b;
|
||||
pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
|
||||
return b;
|
||||
} else
|
||||
#endif
|
||||
|
||||
return *(volatile unsigned char *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned short _inw(unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
return _ne_inw(PORT2ADDR_NE(port));
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
return *(volatile unsigned short *)__port2addr_ata(port);
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_USB)
|
||||
else if(port >= 0x340 && port < 0x3a0)
|
||||
return *(volatile unsigned short *)PORT2ADDR_USB(port);
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned short w;
|
||||
pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
|
||||
return w;
|
||||
} else
|
||||
#endif
|
||||
return *(volatile unsigned short *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned long _inl(unsigned long port)
|
||||
{
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
unsigned long l;
|
||||
pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
|
||||
return l;
|
||||
} else
|
||||
#endif
|
||||
return *(volatile unsigned long *)PORT2ADDR(port);
|
||||
}
|
||||
|
||||
unsigned char _inb_p(unsigned long port)
|
||||
{
|
||||
unsigned char v = _inb(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
unsigned short _inw_p(unsigned long port)
|
||||
{
|
||||
unsigned short v = _inw(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
unsigned long _inl_p(unsigned long port)
|
||||
{
|
||||
unsigned long v = _inl(port);
|
||||
delay();
|
||||
return (v);
|
||||
}
|
||||
|
||||
void _outb(unsigned char b, unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
_ne_outb(b, PORT2ADDR_NE(port));
|
||||
else
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
*(volatile unsigned char *)__port2addr_ata(port) = b;
|
||||
} else
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned char *)PORT2ADDR(port) = b;
|
||||
}
|
||||
|
||||
void _outw(unsigned short w, unsigned long port)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
_ne_outw(w, PORT2ADDR_NE(port));
|
||||
else
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
*(volatile unsigned short *)__port2addr_ata(port) = w;
|
||||
} else
|
||||
#endif
|
||||
#if defined(CONFIG_USB)
|
||||
if(port >= 0x340 && port < 0x3a0)
|
||||
*(volatile unsigned short *)PORT2ADDR_USB(port) = w;
|
||||
else
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned short *)PORT2ADDR(port) = w;
|
||||
}
|
||||
|
||||
void _outl(unsigned long l, unsigned long port)
|
||||
{
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
|
||||
} else
|
||||
#endif
|
||||
*(volatile unsigned long *)PORT2ADDR(port) = l;
|
||||
}
|
||||
|
||||
void _outb_p(unsigned char b, unsigned long port)
|
||||
{
|
||||
_outb(b, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _outw_p(unsigned short w, unsigned long port)
|
||||
{
|
||||
_outw(w, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _outl_p(unsigned long l, unsigned long port)
|
||||
{
|
||||
_outl(l, port);
|
||||
delay();
|
||||
}
|
||||
|
||||
void _insb(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND)
|
||||
_ne_insb(PORT2ADDR_NE(port), addr, count);
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
unsigned char *buf = addr;
|
||||
unsigned char *portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned char *)portp;
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_ioread_byte(0, port, (void *)addr, sizeof(unsigned char),
|
||||
count, 1);
|
||||
}
|
||||
#endif
|
||||
else {
|
||||
unsigned char *buf = addr;
|
||||
unsigned char *portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned char *)portp;
|
||||
}
|
||||
}
|
||||
|
||||
void _insw(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND) {
|
||||
/*
|
||||
* This portion is only used by smc91111.c to read data
|
||||
* from the DATA_REG. Do not swap the data.
|
||||
*/
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short),
|
||||
count, 1);
|
||||
#endif
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
} else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned short *)portp;
|
||||
}
|
||||
}
|
||||
|
||||
void _insl(unsigned int port, void *addr, unsigned long count)
|
||||
{
|
||||
unsigned long *buf = addr;
|
||||
unsigned long *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*buf++ = *(volatile unsigned long *)portp;
|
||||
}
|
||||
|
||||
void _outsb(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned char *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND) {
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
_ne_outb(*buf++, portp);
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
} else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*(volatile unsigned char *)portp = *buf++;
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char),
|
||||
count, 1);
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned char *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsw(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned short *buf = addr;
|
||||
unsigned short *portp;
|
||||
|
||||
if (port >= LAN_IOSTART && port < LAN_IOEND) {
|
||||
/*
|
||||
* This portion is only used by smc91111.c to write data
|
||||
* into the DATA_REG. Do not swap the data.
|
||||
*/
|
||||
portp = PORT2ADDR_NE(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
|
||||
} else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
|
||||
portp = __port2addr_ata(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
#endif
|
||||
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
|
||||
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
|
||||
pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short),
|
||||
count, 1);
|
||||
#endif
|
||||
} else {
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned short *)portp = *buf++;
|
||||
}
|
||||
}
|
||||
|
||||
void _outsl(unsigned int port, const void *addr, unsigned long count)
|
||||
{
|
||||
const unsigned long *buf = addr;
|
||||
unsigned char *portp;
|
||||
|
||||
portp = PORT2ADDR(port);
|
||||
while (count--)
|
||||
*(volatile unsigned long *)portp = *buf++;
|
||||
}
|
||||
448
arch/m32r/platforms/opsput/setup.c
Normal file
448
arch/m32r/platforms/opsput/setup.c
Normal file
|
|
@ -0,0 +1,448 @@
|
|||
/*
|
||||
* linux/arch/m32r/platforms/opsput/setup.c
|
||||
*
|
||||
* Setup routines for Renesas OPSPUT Board
|
||||
*
|
||||
* Copyright (c) 2002-2005
|
||||
* Hiroyuki Kondo, Hirokazu Takata,
|
||||
* Hitoshi Yamamoto, Takeo Takahashi, Mamoru Sakugawa
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General
|
||||
* Public License. See the file "COPYING" in the main directory of this
|
||||
* archive for more details.
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
/*
|
||||
* OPSP Interrupt Control Unit (Level 1)
|
||||
*/
|
||||
#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
|
||||
|
||||
icu_data_t icu_data[OPSPUT_NUM_CPU_IRQ];
|
||||
|
||||
static void disable_opsput_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void enable_opsput_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
|
||||
port = irq2port(irq);
|
||||
data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
|
||||
outl(data, port);
|
||||
}
|
||||
|
||||
static void mask_opsput(struct irq_data *data)
|
||||
{
|
||||
disable_opsput_irq(data->irq);
|
||||
}
|
||||
|
||||
static void unmask_opsput(struct irq_data *data)
|
||||
{
|
||||
enable_opsput_irq(data->irq);
|
||||
}
|
||||
|
||||
static void shutdown_opsput(struct irq_data *data)
|
||||
{
|
||||
unsigned long port;
|
||||
|
||||
port = irq2port(data->irq);
|
||||
outl(M32R_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct irq_chip opsput_irq_type =
|
||||
{
|
||||
.name = "OPSPUT-IRQ",
|
||||
.irq_shutdown = shutdown_opsput,
|
||||
.irq_mask = mask_opsput,
|
||||
.irq_unmask = unmask_opsput,
|
||||
};
|
||||
|
||||
/*
|
||||
* Interrupt Control Unit of PLD on OPSPUT (Level 2)
|
||||
*/
|
||||
#define irq2pldirq(x) ((x) - OPSPUT_PLD_IRQ_BASE)
|
||||
#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
|
||||
(((x) - 1) * sizeof(unsigned short)))
|
||||
|
||||
typedef struct {
|
||||
unsigned short icucr; /* ICU Control Register */
|
||||
} pld_icu_data_t;
|
||||
|
||||
static pld_icu_data_t pld_icu_data[OPSPUT_NUM_PLD_IRQ];
|
||||
|
||||
static void disable_opsput_pld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2pldirq(irq);
|
||||
port = pldirq2port(pldirq);
|
||||
data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void enable_opsput_pld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2pldirq(irq);
|
||||
port = pldirq2port(pldirq);
|
||||
data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void mask_opsput_pld(struct irq_data *data)
|
||||
{
|
||||
disable_opsput_pld_irq(data->irq);
|
||||
}
|
||||
|
||||
static void unmask_opsput_pld(struct irq_data *data)
|
||||
{
|
||||
enable_opsput_pld_irq(data->irq);
|
||||
enable_opsput_irq(M32R_IRQ_INT1);
|
||||
}
|
||||
|
||||
static void shutdown_opsput_pld(struct irq_data *data)
|
||||
{
|
||||
unsigned long port;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2pldirq(data->irq);
|
||||
port = pldirq2port(pldirq);
|
||||
outw(PLD_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct irq_chip opsput_pld_irq_type =
|
||||
{
|
||||
.name = "OPSPUT-PLD-IRQ",
|
||||
.irq_shutdown = shutdown_opsput_pld,
|
||||
.irq_mask = mask_opsput_pld,
|
||||
.irq_unmask = unmask_opsput_pld,
|
||||
};
|
||||
|
||||
/*
|
||||
* Interrupt Control Unit of PLD on OPSPUT-LAN (Level 2)
|
||||
*/
|
||||
#define irq2lanpldirq(x) ((x) - OPSPUT_LAN_PLD_IRQ_BASE)
|
||||
#define lanpldirq2port(x) (unsigned long)((int)OPSPUT_LAN_ICUCR1 + \
|
||||
(((x) - 1) * sizeof(unsigned short)))
|
||||
|
||||
static pld_icu_data_t lanpld_icu_data[OPSPUT_NUM_LAN_PLD_IRQ];
|
||||
|
||||
static void disable_opsput_lanpld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lanpldirq(irq);
|
||||
port = lanpldirq2port(pldirq);
|
||||
data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void enable_opsput_lanpld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lanpldirq(irq);
|
||||
port = lanpldirq2port(pldirq);
|
||||
data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void mask_opsput_lanpld(struct irq_data *data)
|
||||
{
|
||||
disable_opsput_lanpld_irq(data->irq);
|
||||
}
|
||||
|
||||
static void unmask_opsput_lanpld(struct irq_data *data)
|
||||
{
|
||||
enable_opsput_lanpld_irq(data->irq);
|
||||
enable_opsput_irq(M32R_IRQ_INT0);
|
||||
}
|
||||
|
||||
static void shutdown_opsput_lanpld(struct irq_data *data)
|
||||
{
|
||||
unsigned long port;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lanpldirq(data->irq);
|
||||
port = lanpldirq2port(pldirq);
|
||||
outw(PLD_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct irq_chip opsput_lanpld_irq_type =
|
||||
{
|
||||
.name = "OPSPUT-PLD-LAN-IRQ",
|
||||
.irq_shutdown = shutdown_opsput_lanpld,
|
||||
.irq_mask = mask_opsput_lanpld,
|
||||
.irq_unmask = unmask_opsput_lanpld,
|
||||
};
|
||||
|
||||
/*
|
||||
* Interrupt Control Unit of PLD on OPSPUT-LCD (Level 2)
|
||||
*/
|
||||
#define irq2lcdpldirq(x) ((x) - OPSPUT_LCD_PLD_IRQ_BASE)
|
||||
#define lcdpldirq2port(x) (unsigned long)((int)OPSPUT_LCD_ICUCR1 + \
|
||||
(((x) - 1) * sizeof(unsigned short)))
|
||||
|
||||
static pld_icu_data_t lcdpld_icu_data[OPSPUT_NUM_LCD_PLD_IRQ];
|
||||
|
||||
static void disable_opsput_lcdpld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lcdpldirq(irq);
|
||||
port = lcdpldirq2port(pldirq);
|
||||
data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void enable_opsput_lcdpld_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long port, data;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lcdpldirq(irq);
|
||||
port = lcdpldirq2port(pldirq);
|
||||
data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
|
||||
outw(data, port);
|
||||
}
|
||||
|
||||
static void mask_opsput_lcdpld(struct irq_data *data)
|
||||
{
|
||||
disable_opsput_lcdpld_irq(data->irq);
|
||||
}
|
||||
|
||||
static void unmask_opsput_lcdpld(struct irq_data *data)
|
||||
{
|
||||
enable_opsput_lcdpld_irq(data->irq);
|
||||
enable_opsput_irq(M32R_IRQ_INT2);
|
||||
}
|
||||
|
||||
static void shutdown_opsput_lcdpld(struct irq_data *data)
|
||||
{
|
||||
unsigned long port;
|
||||
unsigned int pldirq;
|
||||
|
||||
pldirq = irq2lcdpldirq(data->irq);
|
||||
port = lcdpldirq2port(pldirq);
|
||||
outw(PLD_ICUCR_ILEVEL7, port);
|
||||
}
|
||||
|
||||
static struct irq_chip opsput_lcdpld_irq_type = {
|
||||
.name = "OPSPUT-PLD-LCD-IRQ",
|
||||
.irq_shutdown = shutdown_opsput_lcdpld,
|
||||
.irq_mask = mask_opsput_lcdpld,
|
||||
.irq_unmask = unmask_opsput_lcdpld,
|
||||
};
|
||||
|
||||
void __init init_IRQ(void)
|
||||
{
|
||||
#if defined(CONFIG_SMC91X)
|
||||
/* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
|
||||
irq_set_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type,
|
||||
handle_level_irq);
|
||||
lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
|
||||
disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
|
||||
#endif /* CONFIG_SMC91X */
|
||||
|
||||
/* MFT2 : system timer */
|
||||
irq_set_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type,
|
||||
handle_level_irq);
|
||||
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
|
||||
disable_opsput_irq(M32R_IRQ_MFT2);
|
||||
|
||||
/* SIO0 : receive */
|
||||
irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type,
|
||||
handle_level_irq);
|
||||
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
|
||||
disable_opsput_irq(M32R_IRQ_SIO0_R);
|
||||
|
||||
/* SIO0 : send */
|
||||
irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type,
|
||||
handle_level_irq);
|
||||
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
|
||||
disable_opsput_irq(M32R_IRQ_SIO0_S);
|
||||
|
||||
/* SIO1 : receive */
|
||||
irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type,
|
||||
handle_level_irq);
|
||||
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
|
||||
disable_opsput_irq(M32R_IRQ_SIO1_R);
|
||||
|
||||
/* SIO1 : send */
|
||||
irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type,
|
||||
handle_level_irq);
|
||||
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
|
||||
disable_opsput_irq(M32R_IRQ_SIO1_S);
|
||||
|
||||
/* DMA1 : */
|
||||
irq_set_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type,
|
||||
handle_level_irq);
|
||||
icu_data[M32R_IRQ_DMA1].icucr = 0;
|
||||
disable_opsput_irq(M32R_IRQ_DMA1);
|
||||
|
||||
#ifdef CONFIG_SERIAL_M32R_PLDSIO
|
||||
/* INT#1: SIO0 Receive on PLD */
|
||||
irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type,
|
||||
handle_level_irq);
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
|
||||
disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
|
||||
|
||||
/* INT#1: SIO0 Send on PLD */
|
||||
irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type,
|
||||
handle_level_irq);
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
|
||||
disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
|
||||
#endif /* CONFIG_SERIAL_M32R_PLDSIO */
|
||||
|
||||
/* INT#1: CFC IREQ on PLD */
|
||||
irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type,
|
||||
handle_level_irq);
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
|
||||
disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
|
||||
|
||||
/* INT#1: CFC Insert on PLD */
|
||||
irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type,
|
||||
handle_level_irq);
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
|
||||
disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
|
||||
|
||||
/* INT#1: CFC Eject on PLD */
|
||||
irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type,
|
||||
handle_level_irq);
|
||||
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
|
||||
disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
|
||||
|
||||
/*
|
||||
* INT0# is used for LAN, DIO
|
||||
* We enable it here.
|
||||
*/
|
||||
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
|
||||
enable_opsput_irq(M32R_IRQ_INT0);
|
||||
|
||||
/*
|
||||
* INT1# is used for UART, MMC, CF Controller in FPGA.
|
||||
* We enable it here.
|
||||
*/
|
||||
icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
|
||||
enable_opsput_irq(M32R_IRQ_INT1);
|
||||
|
||||
#if defined(CONFIG_USB)
|
||||
outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
|
||||
irq_set_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1,
|
||||
&opsput_lcdpld_irq_type, handle_level_irq);
|
||||
lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
|
||||
disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
|
||||
#endif
|
||||
/*
|
||||
* INT2# is used for BAT, USB, AUDIO
|
||||
* We enable it here.
|
||||
*/
|
||||
icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
|
||||
enable_opsput_irq(M32R_IRQ_INT2);
|
||||
|
||||
#if defined(CONFIG_VIDEO_M32R_AR)
|
||||
/*
|
||||
* INT3# is used for AR
|
||||
*/
|
||||
irq_set_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type,
|
||||
handle_level_irq);
|
||||
icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
|
||||
disable_opsput_irq(M32R_IRQ_INT3);
|
||||
#endif /* CONFIG_VIDEO_M32R_AR */
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SMC91X)
|
||||
|
||||
#define LAN_IOSTART 0x300
|
||||
#define LAN_IOEND 0x320
|
||||
static struct resource smc91x_resources[] = {
|
||||
[0] = {
|
||||
.start = (LAN_IOSTART),
|
||||
.end = (LAN_IOEND),
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = OPSPUT_LAN_IRQ_LAN,
|
||||
.end = OPSPUT_LAN_IRQ_LAN,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FB_S1D13XXX)
|
||||
|
||||
#include <video/s1d13xxxfb.h>
|
||||
#include <asm/s1d13806.h>
|
||||
|
||||
static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
|
||||
.initregs = s1d13xxxfb_initregs,
|
||||
.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
|
||||
.platform_init_video = NULL,
|
||||
#ifdef CONFIG_PM
|
||||
.platform_suspend_video = NULL,
|
||||
.platform_resume_video = NULL,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct resource s1d13xxxfb_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x10600000UL,
|
||||
.end = 0x1073FFFFUL,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 0x10400000UL,
|
||||
.end = 0x104001FFUL,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device s1d13xxxfb_device = {
|
||||
.name = S1D_DEVICENAME,
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &s1d13xxxfb_data,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
|
||||
.resource = s1d13xxxfb_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
static int __init platform_init(void)
|
||||
{
|
||||
#if defined(CONFIG_SMC91X)
|
||||
platform_device_register(&smc91x_device);
|
||||
#endif
|
||||
#if defined(CONFIG_FB_S1D13XXX)
|
||||
platform_device_register(&s1d13xxxfb_device);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(platform_init);
|
||||
Loading…
Add table
Add a link
Reference in a new issue